CPC7701 16-Channel High Voltage Analog Switch with Integrated Bleed Resistors INTEGRATED CIRCUITS DIVISION Features Description • Processed with BCDMOS on SOI (Silicon on Insulator) • Flexible High Voltage Supplies up to VPP-VNN=200V • Internal Output Bleed Resistors • DC to 10MHz Analog Signal Frequency • 60dB Minimum Output-Off Isolation at 5MHz • Low Quiescent Power Dissipation (< 1A Typical) • Low Output On-Resistance • Surface Mount Package The CPC7701 is a low charge injection 16-channel high-voltage analog switch integrated circuit (IC) for use in applications requiring high voltage switching. Bleed resistors are incorporated into both terminals of each output switch. Control of the high voltage switching is via low voltage CMOS logic level inputs for direct connectivity to the system controller. Applications • • • • Ultrasound Imaging Printers Industrial Controls and Measurement Piezoelectric Transducer Drivers Because the CPC7701 is capable of switching high load voltages and has a flexible load voltage range, e.g. VPP/VNN: +40V/160V or +100V/100V, it is well suited for many medical and industrial applications such as medical ultrasound imaging, printers, and industrial measurement equipment. The bleed resistors enable the discharge of capacitive loads, such as piezoelectric transducers, connected to the output switches of the CPC7701. Figure 1. Block Diagram LATCHES LEVEL SHIFTERS VDD DIN OUTPUT SWITCHES VPP D LE CL SW0 D LE CL SW1 D LE CL SW2 DOUT 16 BIT SHIFT REGISTER CLK Switch manipulation is managed by an 16-bit serial to parallel shift register whose outputs are buffered and stored by a 16-bit transparent latch. Level shifters buffer the latch outputs and operate the high voltage switches. Construction of the high voltage switches using IXYS Integrated Circuits Division's reliable SOI BCDMOS process technology allows the switches to be organized as solid state switches with direct gate drive. Ordering Information Part Number Description D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW15 CPC7701K CPC7701KTR Pb CL LE VNN DS-CPC7701-R03 48-Pin LQFP in Trays (250/Tray) 48-Pin LQFP Tape & Reel (2000/Reel) RGND www.ixysic.com e3 1 CPC7701 INTEGRATED CIRCUITS DIVISION 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Board Wash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 www.ixysic.com R03 CPC7701 INTEGRATED CIRCUITS DIVISION 1. Specifications 1.1 Package Pinout 48 47 46 45 44 43 42 41 40 39 38 37 1.2 Pin Description 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 R03 Pin Name 3 4 5 6 7 8 9 10 11 12 13 SW4 SW4 SW3 SW3 SW2 SW2 SW1 SW1 SW0 SW0 VNN SW4 Output SW4 Output SW3 Output SW3 Output SW2 Output SW2 Output SW1 Output SW1 Output SW0 Output SW0 Output Switch Negative High Voltage Supply 15 17 18 VPP GND VDD Switch Positive High Voltage Supply Ground: All Voltages are Referenced to Ground Logic Positive Supply Voltage 19 20 21 CLK LE 22 CL DIN 23 DOUT 24 25 26 27 28 29 30 31 32 33 34 37 38 39 40 41 42 43 44 45 46 47 48 1, 2, 14, 16, 35, 36 RGND www.ixysic.com SW15 SW15 SW14 SW14 SW13 SW13 SW12 SW12 SW11 SW11 SW10 SW10 SW9 SW9 SW8 SW8 SW7 SW7 SW6 SW6 SW5 SW5 N/C Description Serial Data Input Clock Input, Positive Edge Trigger Latch Enable, Active Low Latch Clear, Active High, Asynchronously Clears Latches and Opens Switches Serial Data Output Ground for Bleed Resistors, Connect to GND SW15 Output SW15 Output SW14 Output SW14 Output SW13 Output SW13 Output SW12 Output SW12 Output SW11 Output SW11 Output SW10 Output SW10 Output SW9 Output SW9 Output SW8 Output SW8 Output SW7 Output SW7 Output SW6 Output SW6 Output SW5 Output SW5 Output No Connection 3 INTEGRATED CIRCUITS DIVISION CPC7701 1.3 Absolute Maximum Ratings Electrical Absolute Maximum ratings are at 25°C. All voltages are referenced from ground (GND). Parameter Min Max Units -0.5 7 V - 220 V VPP Positive High Voltage Supply -0.5 VNN+200 V VNN Negative High Voltage Supply -0.5 VPP-200 V RGND-GND Differential -0.3 +0.3 V Logic input voltages -0.5 VDD+0.3 V Analog signal range VNN VPP V VDD Logic Power Supply Voltage VPP - VNN Supply Voltage Peak analog signal current per channel - 1 A Power dissipation - 2.3 W - 65 +150 C Storage temperature Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. 1.4 Operating Conditions Parameter Symbol Value Logic power supply voltage 1 VDD 3V to 5.5V Positive high voltage supply 1 VPP 40V to VNN + 200V Negative high voltage supply 1 VNN -40V to -160V Analog signal voltage, peak-to-peak 2 VSW VNN+10V to VPP-10V TA 0°C to 70°C Operating temperature 1 Power up/down sequence is arbitrary except that GND must be powered-up first and powered-down last. 2 VSW must be VNN VSW VPP or floating during power up/down transition. 4 www.ixysic.com R03 CPC7701 INTEGRATED CIRCUITS DIVISION 1.5 Electrical Characteristics 1.5.1 Switch Characteristics (Over recommended operating conditions unless otherwise noted.) 0°C Parameter Symbol Units min max min typ max min max ISW=5mA - 30 - 27 35 - 48 - 26 - 22 29 - 40 ISW=5mA - 30 - 27 35 - 48 ISW=200mA - 26 - 22 29 - 40 ISW=5mA - 30 - 27 35 - 48 ISW=200mA - 26 - 22 29 - 40 RONS VPP=100V, VNN=-100V, ISW=5mA - 20 - 4 20 - 20 % RONS VPP=100V, VNN=-100V VPP=160V, VNN=-40V Switch on-resistance matching, Small signal +70°C ISW=200mA VPP=40V, VNN=-160V Switch on-resistance, Small signal +25°C Test Conditions Switch on-resistance, Large signal RONL VSW=VPP-10V, ISW=1A - - - 15 - - - Output bleed resistors RINT Output switch to RGND, IRINT=0.5mA - - 20 28 50 - - k Switch off leakage, per switch* ISOL VSW=VPP-10V and VNN+10V - 5 - 0.4 10 - 15 A DC offset, switch off VOS No Load - 300 - - 300 - 300 DC offset, switch on VOS No Load - 500 - - 500 - 500 Switch output peak current ISW VSW duty cycle = 0.1% - - - - 1 - - A Output switch frequency fSW Duty cycle = 50% - - - - 50 - - kHz - 20 - - 20 - 20 V/ns f=5MHz, ZL=1k || 15pF load 30 - 30 - - 30 - f=5MHz, RL=50 load 58 - 58 - - 58 - f=5MHz, RL=50 load -60 - -60 - - -60 - dB - 300 - - 300 - 300 mA mV VPP=160V, VNN=-40V Maximum VSW slew rate dV/dt VPP=100V, VNN=-100V VPP=40V, VNN=-160V Off isolation KO Switch crosstalk KCR Output switch isolation diode current IID 300ns pulse width, 2.0% duty cycle Off capacitance, SW to GND CSG(OFF) VSW=0V, f=1MHz 5 17 5 - 17 5 17 On capacitance, SW to GND CSG(ON) VSW=0V, f=1MHz 25 50 20 - 50 25 50 VPP=40V, VNN=-160V - - - - 150 - - VPP=100V, VNN=-100V RL=50 - - - - 150 - - VPP=160V, VNN=-40V - - - - 150 - - - 820 - +VSPK -VSPK Output voltage spike +VSPK -VSPK +VSPK -VSPK Charge injection Q VPP=100V, VNN=-100V, VSW=0V dB pF mV pC * Does not include the leakage current contribution due to the bleed resistors. R03 www.ixysic.com 5 INTEGRATED CIRCUITS DIVISION CPC7701 1.5.2 Logic Timing Characteristics (Over recommended operating conditions unless otherwise noted.) 0°C Parameter Symbol Time width of LE min typ max min max - 150 - 150 - - 150 - VDD=3V 56 - 56 - - 56 - VDD=5V 12 - 12 - - 12 - VDD=3V 10 100 10 - 100 10 100 VDD=5V 5 45 5 - 45 5 45 - 55 - 55 - - 55 - VDD=3V 21 - - 21 - 21 - VDD=5V 7 - - 7 - 7 - - 2 - 2 - - 2 - 50% duty cycle, fDATA= ½ fCLK, VDD=3V - 8 - - 8 - 8 50% duty cycle, fDATA= ½ fCLK, VDD=5V - 20 - - 20 - 20 - - 50 - - 50 - 50 ns VSW=VPP-10V, RL=10k - 5 - - 5 - 5 s tDO tWCL Time width of CL Setup time, data to clock tsu th Hold time, data from clock Clock frequency fCLK Clock rise and fall times tr , tf Turn-on time ton Turn-off time toff Units max tWLE Clock delay time to Data Out 70°C min tSD Setup time before LE rises +25°C Test Conditions ns MHz 1.5.3 Logic Timing Waveforms DN-1 DN DIN 50% LE 50% DN+1 50% 50% tWLE tSD tsu tDO DOUT VOUT 50% 50% CLK th 50% toff OFF ton 90% 10% ON CL 50% 50% tWCL 6 www.ixysic.com R03 CPC7701 INTEGRATED CIRCUITS DIVISION 1.5.4 Logic DC Characteristics (Over recommended operating conditions unless otherwise noted.) 0°C Parameter Symbol +25°C +70°C Test Conditions Units min max min typ max min max DOUT source capability VOH IOUT= -400A - - VDD-0.7 VDD-0.1 - - - DOUT sink capability VOL IOUT= +400A - - - 0.04 0.7 - - Input (Logic) capacitance CIN - - 10 - - 10 - 10 Input, Logic high VIH - 0.9 VDD - 0.9 VDD - - 0.9 VDD - Input, Logic low VIL - - 0.1 VDD - - 0.1 VDD - 0.1 VDD V pF V 1.5.5 Supply DC Characteristics (Over recommended operating conditions unless otherwise noted.) 0°C Parameter Symbol VPP quiescent supply current IPPQ VNN quiescent supply current INNQ All switches off All switches on, ISW=5mA All switches off IPP IDD VDD quiescent supply current IDDQ min typ max min max - - - 0.1 50 - A -0.1 - 50 - - - 6.5 - - 7 - 8 - 4 - - 5.5 - 5.5 - 4 - - 5 - 5.5 - 6.5 - - 7 - 8 - 4 - - 5.5 - 5.5 - 4 - - 5 - 5.5 - 4 - - 4 - 4 mA - - 10 - 0.03 10 - 10 A Conditions Symbol Minimum Typical Maximum Units Free Air RJA - - 53 °C/W 50kHz output switching frequency with no load VPP=100V, VNN=-100V 50kHz output switching frequency with no load VPP=100V, VNN=-100V VPP=160V, VNN=-40V VDD average supply current max - VPP=40V, VNN=-160V INN Units min - VPP=160V, VNN=-40V VNN operating supply current +70°C - All switches on, ISW=5mA VPP=40V, VNN=-160V VPP operating supply current +25°C Test Conditions fCLK=5MHz, VDD=5V mA mA 1.5.6 Thermal Characteristics Parameter Thermal Resistance (Junction to Ambient) R03 www.ixysic.com 7 INTEGRATED CIRCUITS DIVISION CPC7701 2. Functional Description The CPC7701 takes a serial stream of input data along with a synchronous clock signal. As the clock transits from low to high, the data at the input of each shift register is shifted through from SR(n) to SR(n+1). A high data bit, a “1,” represents an ON switch; a low data bit, a “0,” represents an OFF switch. Data is input and shifted through the internal shift register until all sixteen shift register positions, SR0 through SR15, are in the desired state. VPP and VNN: Voltage inputs to the level shifters for each switch channel that translate the voltage level of the latch output signals to an appropriate level for the voltages being switched. DIN: The data-in line presents data bits to the CPC7701 to be shifted through the internal shift register. The last bit into the shift register is the SW0 control bit. Two or more CPC7701 devices can be cascaded to form an n-switch arrangement. The DOUT pin of the first is connected to the DIN pin of the next in the series. All devices are connected to the same clock (CLK) signal. LE of all devices would normally be connected, as would CL, but this is not necessary. CLK: The clock signal's rising edge is associated only with shifting data into and through the shift register. CL: The clear line overrides all other inputs. When CL is high, the shift register is asynchronously cleared to all 0s and all latches are set low, which causes all output switches to be turned OFF immediately. When CL is low, all output switches remain in whatever state they are in, ON or OFF, in response to CLK, latch inputs, and the LE signal. The high-voltage output switches are turned on and off in response to the data sent into the latches from the shift register: data 0 turns a switch OFF, data 1 turns a switch ON. The first data bit applied to DIN of the CPC7701, whether it's a single device or several cascaded devices, ripples through to the last switch output in line after the application of a full clocking sequence of 16 clock pulses. Setting the serial I/O device to output the most significant bit (MSB) first, results in the MSB appearing on SW15 of the last device in line after a full clocking sequence. LE: latch enable controls the state of the latches and the state of the sixteen switches. If LE is high, then the latches do not change states, but retain their most recent status: either ON or OFF. With LE high, input data and CLK have no effect on the state of the output switches. If LE is low, then all latch outputs and their switch states follow the inputs from the shift register. LE is overridden by CL: no matter what state LE is in, CL clears the latches. See “Truth Table” on page 9. Note that holding LE active while clocking in new data will cause the outputs to toggle with the shifting data. DOUT: The data-out pin is the output of SR15. After sixteen clock pulses, the first bit of sixteen shifted input data bits is output at SR15, and appears on DOUT. SW0 - SW15: The CPC7701 provides sixteen high-voltage SPST output switches with a nominal small signal on-resistance of 25. The two connections of each switch are not polarity-sensitive. As can be seen in “Block Diagram” on page 1, integrated bleed resistors are provided to facilitate charge dissipation for capacitive load applications. DIN DIN CLK CLK SW0 CPC7701 CL CL LE LE SW15 DOUT DIN CLK SW0 CPC7701 CL LE SW15 DOUT DIN CLK SW0 CPC7701 CL LE DOUT 8 www.ixysic.com SW15 R03 R03 D4 D5 D6 D8 D9 D10 D11 D12 D13 D14 D15 LE www.ixysic.com X X X X X X X X X X X X X H L L L H H L L L X L L H X L L L X L L H X L L L X L L H X L L L X L L H OFF OFF OFF OFF OFF OFF ON OFF 5. Shift register clocking has no effect on the switch states if LE is H. X X L L L ON OFF 6. The clear input overrides all other inputs. X X L L H ON OFF 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low, the shift register data flows through the latch. X X L L L ON OFF 4. DOUT is high when switch SW15 is on. X X L L H ON OFF 2. Serial data is clocked in on the rising edge of the CLK signal. X X X L L L L H L L L L L L ON OFF ON OFF ON OFF ON OFF OFF OFF OFF OFF HOLD PREVIOUS STATE ON OFF OFF ON OFF OFF ON OFF OFF ON OFF OFF ON OFF OFF ON OFF OFF ON OFF SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11 SW12 SW13 SW14 SW15 1. The sixteen switches operate independently. X X H L L L H L L L L L H L L L L L H L L L L L H L L L L L H L L L L L CL L L L H L L L L D7 L D3 H D2 L D1 L D0 INTEGRATED CIRCUITS DIVISION CPC7701 2.1 Truth Table 9 INTEGRATED CIRCUITS DIVISION CPC7701 3. Manufacturing Information 3.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Rating CPC7701K MSL 3 3.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 3.3 Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed. Device Maximum Temperature x Time CPC7701K 260°C for 30 seconds 3.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used. Pb 10 e3 www.ixysic.com R03 CPC7701 INTEGRATED CIRCUITS DIVISION 3.5 Mechanical Dimensions 9.00 ± 0.20 (0.354 ± 0.008) 7.00 ± 0.10 (0.276 ± 0.004) PCB Land Pattern 8.40 (0.331) 1.60 Max (0.063Max) 7.00 ± 0.10 (0.276 ± 0.004) 9.00 ± 0.20 (0.354 ± 0.008) 0.50 (0.020) 8.40 (0.331) Pin 48 Pin 1 0.22 ± 0.05 (0.009 ± 0.002) 1.40 ± 0.05 (0.055 ± 0.002) 0.05 Min / 0.15 Max (0.002 Min - 0.006 Max) 0.60, +0.15/-0.10 (0.024, +0.006/-0.004) 0.50 (0.020) Dimensions mm (inches) 0.30 (0.012) 1.50 (0.059) 3.6 Tape and Reel Specifications 330.2 DIA. (13.00 DIA.) Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) 16.0±0.3 (0.63±0.012) B0=9.30 (0.366) K0=2.20 (0.087) A0=9.30 (0.366) K1=1.60 (0.063) 12.00 (0.472) Dimensions mm (inches) Embossed Carrier Embossment NOTE: Unless otherwise specified, tolerance ±0.1 (0.004) For additional information please visit www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7701-R03 © Copyright 2012, IXYS Integrated Circuits Division All rights reserved. Printed in USA. 12/18/2012 R03 www.ixysic.com 11