TI DRV8840PWP Dc motor driver ic Datasheet

DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
DC MOTOR DRIVER IC
Check for Samples: DRV8840
FEATURES
1
•
2
•
•
•
Single H-Bridge Current-Control Motor Driver
– Drives One DC Motor
– Brake Mode
– Five-Bit Winding Current Control Allows Up
to 32 Current Levels
– Low MOSFET On-Resistance
5-A Maximum Drive Current at 24 V, 25°C
Built-In 3.3-V Reference Output
Industry-Standard Parallel Digital Control
Interface
•
•
8.2-V to 45-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
APPLICATIONS
•
•
•
•
•
•
Printers
Scanners
Office Automation Machines
Gaming Machines
Factory Automation
Robotics
DESCRIPTION
The DRV8840 provides an integrated motor driver solution for printers, scanners, and other automated
equipment applications. The device has one H-bridge driver, and is intended to drive one DC motor. The output
driver block for each consists of N-channel power MOSFET’s configured as full H-bridges to drive the motor
windings. The DRV8840 can supply up to 5-A peak or 3.5-A output current (with proper heatsinking at 24 V and
25°C).
A simple parallel digital control interface is compatible with industry-standard devices. Decay mode is
programmable to allow braking or coasting of the motor when disabled.
Internal shutdown functions are provided for over current protection, short circuit protection, under voltage
lockout and overtemperature.
TheDRV8840 is available in a 28-pin HTSSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br).
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
(2)
PACKAGE (2)
PowerPAD™ (HTSSOP) - PWP
Reel of 2000
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
DRV8840PWPR
8840
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
DEVICE INFORMATION
Functional Block Diagram
VM
VM
Internal
Reference &
Regs
Int. VCC
CP1
LS Gate
Drive
0.01mF
Charge
Pump
V3P3OUT
3.3V
CP2
VM
3.3V
VCP
Thermal
Shut down
0.1mF
HS Gate
Drive
VM
VREF
VM
VREF
VM
PHASE
OUT1
ENABLE
OUT1
I0
I1
DCM
I2
I3
I4
Motor
Driver
Control
Logic
OUT2
OUT2
DECAY
nRESET
ISEN
nSLEEP
ISEN
nFAULT
GND
2
GND
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
Table 1. TERMINAL FUNCTIONS
NAME
PIN
I/O (1)
EXTERNAL COMPONENTS
OR CONNECTIONS
DESCRIPTION
POWER AND GROUND
GND
14, 28
-
Device ground
VM
4, 11
-
Bridge A power supply
Connect to motor supply (8.2 - 45 V). Both
pins must be connected to same supply.
V3P3OUT
15
O
3.3-V regulator output
Bypass to GND with a 0.47-μF, 6.3-V ceramic
capacitor. Can be used to supply VREF.
CP1
1
IO
Charge pump flying capacitor
CP2
2
IO
Charge pump flying capacitor
VCP
3
IO
High-side gate drive voltage
Connect a 0.1-μF 16-V ceramic capacitor to
VM.
PHASE
20
I
Bridge phase (direction)
Logic high sets OUT1 high, OUT2 low.
Internal pulldown.
ENBL
21
I
Bridge enable
Logic high to enable H-bridge. Internal
pulldown.
I0
23
I
I1
24
I
I2
25
I
Current set inputs
Sets winding current as a percentage of
full-scale. Internal pulldown.
I3
26
I
I4
27
I
DECAY
19
I
Decay (brake) mode
Low = brake (slow decay), high = coast (fast
decay). Internal pulldown and pullup.
nRESET
16
I
Reset input
Active-low reset input initializes the logic and
disables the H-bridge outputs. Internal
pulldown.
nSLEEP
17
I
Sleep mode input
Logic high to enable device, logic low to enter
low-power sleep mode. Internal pulldown.
12,13
I
Current set reference input
Reference voltage for winding current set.
Both pins must be connected together on the
PCB.
18
OD
Fault
Logic low when in fault condition (overtemp,
overcurrent)
ISEN
6, 9
IO
Bridge ground / Isense
Connect to current sense resistor. Both pins
must be connected together on the PCB.
OUT1
5, 10
O
Bridge output 1
Connect to motor winding. Both pins must be
connected together on the PCB.
OUT2
7, 8
O
Bridge output 2
Connect to motor winding. Both pins must be
connected together on the PCB.
Connect a 0.01-μF 50-V capacitor between
CP1 and CP2.
CONTROL
VREF
STATUS
nFAULT
OUTPUT
(1)
Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
Copyright © 2010–2011, Texas Instruments Incorporated
3
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
PWP PACKAGE
(TOP VIEW)
CP1
CP2
VCP
VM
OUT1
ISEN
OUT2
OUT2
ISEN
OUT1
VM
VREF
VREF
GND
1
2
3
28
27
26
4
25
5
24
6
7
8
23
GND
(PPAD)
22
21
9
20
10
19
11
18
12
13
17
16
14
15
GND
I4
I3
I2
I1
I0
NC
ENBL
PHASE
DECAY
nFAULT
nSLEEP
nRESET
V3P3OUT
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VMx
VREF
(1) (2)
VALUE
UNIT
Power supply voltage range
–0.3 to 47
V
Digital pin voltage range
–0.5 to 7
V
Input voltage
ISENSEx pin voltage
Peak motor drive output current, t < 1 μS
Continuous motor drive output current
(3)
Continuous total power dissipation
–0.3 to 4
V
–0.3 to 0.8
V
Internally limited
A
5
A
See Dissipation Ratings table
TJ
Operating virtual junction temperature range
–40 to 150
°C
TA
Operating ambient temperature range
–40 to 85
°C
Tstg
Storage temperature range
–60 to 150
°C
(1)
(2)
(3)
4
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed.
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
THERMAL INFORMATION
DRV8840
THERMAL METRIC (1)
PWP
UNITS
28 PINS
Junction-to-ambient thermal resistance (2)
θJA
31.6
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
5.6
ψJT
Junction-to-top characterization parameter (5)
0.2
ψJB
Junction-to-board characterization parameter (6)
5.5
θJCbot
Junction-to-case (bottom) thermal resistance (7)
1.4
(1)
(2)
(3)
(4)
(5)
(6)
(7)
15.9
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VM
Motor power supply voltage range (1)
VREF
NOM
MAX
UNIT
8.2
45
V
VREF input voltage (2)
1
3.5
V
IV3P3
V3P3OUT load current
0
1
mA
fPWM
Externally applied PWM frequency
0
100
kHz
(1)
(2)
All VM pins must be connected to the same supply voltage.
Operational at VREF between 0 V and 1 V, but accuracy is degraded.
Copyright © 2010–2011, Texas Instruments Incorporated
5
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V, fPWM < 50 kHz
5
8
mA
IVMQ
VM sleep mode supply current
VM = 24 V
10
20
μA
VUVLO
VM undervoltage lockout voltage
VM rising
7.8
8.2
V
3.3
3.4
V
V3P3OUT REGULATOR
V3P3
V3P3OUT voltage
IOUT = 0 to 1 mA
3.2
LOGIC-LEVEL INPUTS
VIL
Input low voltage
VIH
Input high voltage
2.2
0.6
VHYS
Input hysteresis
0.3
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Internal pulldown resistance
0.7
V
5.25
V
0.45
0.6
V
20
μA
33
100
μA
–20
100
kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
0.5
V
1
μA
0.8
V
±40
μA
DECAY INPUT
VIL
Input low threshold voltage
For slow decay (brake) mode
0
VIH
Input high threshold voltage
For fast decay (coast) mode
2
IIN
Input current
RPU
Internal pullup resistance
RPD
Internal pulldown resistance
V
130
kΩ
80
kΩ
H-BRIDGE FETS
RDS(ON)
HS FET on resistance
RDS(ON)
LS FET on resistance
IOFF
Off-state leakage current
VM = 24 V, IO = 1 A, TJ = 25°C
0.1
VM = 24 V, IO = 1 A, TJ = 85°C
0.13
VM = 24 V, IO = 1 A, TJ = 25°C
0.1
VM = 24 V, IO = 1 A, TJ = 85°C
0.13
–40
0.16
0.16
40
Ω
Ω
μA
MOTOR DRIVER
fPWM
Internal current control PWM
frequency
tBLANK
Current sense blanking time
tR
Rise time
30
200
ns
tF
Fall time
30
200
ns
160
180
°C
3
μA
660
685
mV
50
kHz
μs
3.75
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tTSD
Thermal shutdown temperature
6
Die temperature
150
A
CURRENT CONTROL
–3
IREF
VREF input current
VREF = 3.3 V
VTRIP
ISENSE trip voltage
VREF = 3.3 V, 100% current setting
635
VREF = 3.3 V, 5% current setting
–25
25
VREF = 3.3 V, 10% - 34% current setting
–15
15
VREF = 3.3 V, 38% - 67% current setting
–10
10
VREF = 3.3 V, 71% - 100% current setting
–5
5
ΔITRIP
Current trip accuracy
(relative to programmed value)
AISENSE Current sense amplifier gain
6
Reference only
5
%
V/V
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
FUNCTIONAL DESCRIPTION
PWM Motor Driver
The DRV8840 contains one H-bridge motor driver with current-control PWM circuitry. A block diagram of the
motor control circuitry is shown in Figure 1.
VM
OCP
VM
VCP, VGD
OUT1
Predrive
DCM
OUT2
ENBL
PHASE
PWM
DECAY
OCP
ISEN
+
I[4:0]
A =5
DAC
5
VREF
Figure 1. Motor Control Circuitry
Note that there are multiple VM, ISEN, OUT, and VREF pins. All like-named pins must be connected together on
the PCB.
Bridge Control
The PHASE input pin controls the direction of current flow through the H-bridge, and hence the direction of
rotation of a DC motor. The ENBL input pin enables the H-bridge outputs when active high, and can also be
used for PWM speed control of the motor. Note that the state of the DECAY pin selects the behavior of the
bridge when ENBL = 0, allowing the selection of slow decay (brake) or fast decay (coast). Table 2 shows the
logic.
Table 2. H-Bridge Logic
DECAY
ENBL
PHASE
OUT1
OUT2
0
0
X
L
L
Z
1
0
X
Z
X
1
1
H
L
X
1
0
L
H
The control inputs have internal pulldown resistors of approximately 100 kΩ.
Copyright © 2010–2011, Texas Instruments Incorporated
7
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
Current Regulation
The maximum current through the motor winding is regulated by a fixed-frequency PWM current regulation, or
current chopping. When the H-bridge is enabled, current rises through the winding at a rate dependent on the
DC voltage and inductance of the winding. Once the current hits the current chopping threshold, the bridge
disables the current until the beginning of the next PWM cycle.
For DC motors, current regulation is used to limit the start-up and stall current of the motor. Speed control is
typically performed by providing an external PWM signal to the ENBLx input pins.
If the current regulation feature is not needed, it can be disabled by connecting the ISENSE pins directly to
ground and the VREF pins to V3P3.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the ISEN pin, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the VREF pin, and is scaled by a 5-bit DAC that allows current settings of zero to 100% in an approximately
sinusoidal sequence.
The full-scale (100%) chopping current is calculated in Equation 1.
VREFX
ICHOP = 5¾
· RISENSE
(1)
Example:
If a 0.25-Ω sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current will be
2.5 V / (5 x 0.25 Ω) = 2 A.
Five input pins (I0 - I4) are used to scale the current in the bridge as a percentage of the full-scale current set by
the VREF input pin and sense resistance. The I0 - I4 pins have internal pulldown resistors of approximately
100 kΩ. The function of the pins is shown in Table 3.
Table 3. Pin Functions
8
I[4..0]
RELATIVE CURRENT
(% FULL-SCALE CHOPPING CURRENT)
0x00h
0%
0x01h
5%
0x02h
10%
0x03h
15%
0x04h
20%
0x05h
24%
0x06h
29%
0x07h
34%
0x08h
38%
0x09h
43%
0x0Ah
47%
0x0Bh
51%
0x0Ch
56%
0x0Dh
60%
0x0Eh
63%
0x0Fh
67%
0x10h
71%
0x11h
74%
0x12h
77%
0x13h
80%
0x14h
83%
0x15h
86%
0x16h
88%
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
Table 3. Pin Functions (continued)
I[4..0]
RELATIVE CURRENT
(% FULL-SCALE CHOPPING CURRENT)
0x17h
90%
0x18h
92%
0x19h
94%
0x1Ah
96%
0x1Bh
97%
0x1Ch
98%
0x1Dh
99%
0x1Eh
100%
0x1Fh
100%
Decay Mode and Braking
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. This is shown in Figure 2 as case 1. The current flow direction shown
indicates the state when the xENBL pin is high.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 2 as case 2.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 2 as case 3.
Figure 2. Decay Mode
Copyright © 2010–2011, Texas Instruments Incorporated
9
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
The DRV8840 supports fast decay and slow decay mode. Slow or fast decay mode is selected by the state of
the DECAY pin - logic low selects slow decay, and logic high sets fast decay mode. The DECAY pin has both an
internal pullup resistor of approximately 130 kΩ and an internal pulldown resistor of approximately 80 kΩ. This
sets the mixed decay mode if the pin is left open or undriven.
DECAY mode also affects the operation of the bridge when it is disabled (by taking the ENBL pin inactive). This
applies if the ENABLE input is being used for PWM speed control of the motor, or if it is simply being used to
start and stop motor rotation.
If the DECAY pin is high (fast decay), when the bridge is disabled fast decay mode will be entered until the
current through the bridge reaches zero. Once the current is at zero, the bridge is disabled to prevent the motor
from reversing direction. This allows the motor to coast to a stop.
If the DECAY pin is low (slow decay), both low-side FETs will be turned on when ENBL is made inactive. This
essentially shorts out the back EMF of the motor, causing the motor to brake, and stop quickly. The low-side
FETs will stay in the ON state even after the current reaches zero.
Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.
nRESET and nSLEEP Operation
The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge driver. All inputs
are ignored while nRESET is active.
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before the motor driver becomes fully operational. Note that nRESET and
nSLEEP have internal pulldown resistors of approximately 100 kΩ. These signals need to be driven to logic high
for device operation.
Protection Circuits
The DRV8840 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is
removed and re-applied.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
10
Copyright © 2010–2011, Texas Instruments Incorporated
DRV8840
SLVSAB7B – MAY 2010 – REVISED MAY 2011
www.ti.com
THERMAL INFORMATION
Thermal Protection
The DRV8840 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
Power Dissipation
Average power dissipation in the DRV8840 when running a DC motor can be roughly estimated by: Equation 2.
P = 2 · RDS(ON) · (IOUT)2
(2)
where P is the power dissipation of one H-bridge, RDS(ON) is the resistance of each FET, and IOUT is the RMS
output current being applied to each winding. IOUT is equal to the average current drawn by the DC motor. Note
that at start-up and fault conditions this current is much higher than normal running current; these peak currents
and their duration also need to be taken into consideration. The factor of 2 comes from the fact that at any
instant two FETs are conducting winding current (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally
Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
Copyright © 2010–2011, Texas Instruments Incorporated
11
PACKAGE OPTION ADDENDUM
www.ti.com
20-May-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
DRV8840PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
DRV8840PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8840PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8840PWPR
HTSSOP
PWP
28
2000
346.0
346.0
33.0
Pack Materials-Page 2
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