Micron MT4LSDT1664AIY-133 Sdram unbuffered dimm (udimm) Datasheet

32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Features
SDRAM Unbuffered DIMM (UDIMM)
MT4LSDT464A – 32MB
MT4LSDT864A(I) – 64MB
MT4LSDT1664A(I) – 128MB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Figure 1:
168-pin, dual in-line memory module (DIMM)
PC100- and PC133-compliant
Unbuffered
32MB (4 Meg x 64)2, 64MB (8 Meg x 64),
128MB (16 Meg x 64)
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal SDRAM banks for hiding row access/
precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes CONCURRENT AUTO
PRECHARGE and auto refresh modes
Self refresh mode: 64ms, 4,096-cycle refresh
for 32MB and 64MB; 64ms, 8,192-cycle refresh
for 128MB
LVTTL-compatible inputs and outputs
Serial presence-detect (SPD)
Gold edge contacts
168-Pin DIMM (MO-161)
Standard 25.4mm (1.0in)
Options
Marking
• Package
– 168-pin DIMM (standard)
– 168-pin DIMM (Pb-free)
• Operating temperature range
– Commercial (0°C to +65°C)
– Industrial (–40°C to +85°C)1, 3
• Frequency/CAS Latency
– 7.5ns (133 MHz)/CL = 2
– 7.5ns (133 MHz)/CL = 3
– 8ns (100 MHz)/CL = 22
• PCB
– Standard 25.40mm (1.0in)
G
Y
None
I
-13E
-133
-10E
Notes: 1. Contact Micron for product availability.
2. Not recommended for new designs.
3. Industrial temperature option available in
-133 MHz only.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency
Access Time
Speed Grade
Industry
Nomenclature
CL = 2
CL = 3
Setup Time
Hold Time
-13E
-133
-10E2
PC133
PC133
PC100
5.4ns
–
9ns
–
5.4ns
7.5ns
-13E
-133
-10E
133 MHz
133 MHz
100 MHz
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Features
Table 2:
Addressing
Refresh count
Device banks
Device configuration
Row addressing
Column addressing
Module ranks
Table 3:
32MB
64MB
128MB
4K
4 (BA0, BA1)
64Mb (4 Meg x 16)
4K (A0–A11)
256 (A0–A7)
1 (S0#, S2#)
4K
4 (BA0, BA1)
128Mb (8 Meg x 16)
4K (A0–A11)
512 (A0–A8)
1 (S0#, S2#)
8K
4 (BA0, BA1)
256Mb (16 Meg x 16)
8K (A0–A12)
512 (A0–A8)
1 (S0#, S2#)
Part Numbers and Timing Parameters
Part Number3
MT4LSDT464AG-13E_1
MT4LSDT464AY-13E_2
MT4LSDT464AG-133_2
MT4LSDT464AY-133_2
MT4LSDT464AG-10E_2
MT4LSDT464AY-10E_1
MT4LSDT864AG-13E_1
MT4LSDT864AY-13E_
MT4LSDT864AIG-133_1
MT4LSDT864AG-133_1
MT4LSDT864AIY-133_1
MT4LSDT864AY-133_
MT4LSDT864AG-10E_2
MT4LSDT864AY-10E_1
MT4LSDT1664AG-13E_
MT4LSDT1664AY-13E_
MT4LSDT1664AIG-133_1
MT4LSDT1664AG-133_
MT4LSDT1664AIY-133_1
MT4LSDT1664AY-133_
MT4LSDT1664AG-10E_2
MT4LSDT1664AY-10E_2
Notes:
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
Module Density
Configuration
System Bus Speed
32MB
32MB
32MB
32MB
32MB
32MB
64MB
64MB
64MB
64MB
64MB
64MB
64MB
64MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
128MB
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
1. Contact Micron for product availability.
2. Not recommended for new designs.
3. The designators for component and PCB revision are the last two characters of each part
number. Consult factory for current revision codes. Example: MT4LSDT464AG-133G1
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignments
168-Pin DIMM Front
Pin Symbol Pin
168-Pin DIMM Back
Symbol
Pin
Symbol
Pin
Symbol
Pin Symbol Pin Symbol
Pin
Symbol
Pin
Symbol
1
VSS
22
DNU
43
VSS
64
VSS
85
VSS
106
DNU
127
VSS
148
VSS
2
DQ0
23
VSS
44
NC
65
DQ21
86
DQ32
107
VSS
128
CKE0
149
DQ53
3
DQ1
24
NC
45
S2#
66
DQ22
87
DQ33
108
NC
129
DNU
150
DQ54
4
DQ2
25
NC
46
DQM2
67
DQ23
88
DQ34
109
NC
130
DQM6
151
DQ55
5
DQ3
26
VDD
47
DQM3
68
VSS
89
DQ35
110
VDD
131
DQM7
152
VSS
6
VDD
27
WE#
48
NC
69
DQ24
90
VDD
111
CAS#
132
DNU
153
DQ56
7
DQ4
28
DQM0
49
VDD
70
DQ25
91
DQ36
112
DQM4
133
VDD
154
DQ57
8
DQ5
29
DQM1
50
NC
71
DQ26
92
DQ37
113
DQM5
134
NC
155
DQ58
9
DQ6
30
S0#
51
NC
72
DQ27
93
DQ38
114
DNU
135
NC
156
DQ59
10
DQ7
31
NC
52
DNU
73
VDD
94
DQ39
115
RAS#
136
DNU
157
VDD
11
DQ8
32
VSS
53
DNU
74
DQ28
95
DQ40
116
VSS
137
DNU
158
DQ60
12
VSS
33
A0
54
VSS
75
DQ29
96
VSS
117
A1
138
VSS
159
DQ61
13
DQ9
34
A2
55
DQ16
76
DQ30
97
DQ41
118
A3
139
DQ48
160
DQ62
14
DQ10
35
A4
56
DQ17
77
DQ31
98
DQ42
119
A5
140
DQ49
161
DQ63
15
DQ11
36
A6
57
DQ18
78
VSS
99
DQ43
120
A7
141
DQ50
162
VSS
16
DQ12
37
A8
58
DQ19
79
CK2
100
DQ44
121
A9
142
DQ51
163
DNU
17
DQ13
38
A10
59
VDD
80
NC
101
DQ45
122
BA0
143
VDD
164
NC
18
VDD
39
BA1
60
DQ20
81
NC
102
VDD
123
A11
144
DQ52
165
SA0
19
DQ14
40
VDD
61
NC
82
SDA
103
DQ46
124
VDD
145
NC
166
SA1
20
DQ15
41
VDD
62
NC
83
SCL
104
DQ47
125
DNU
146
NC
167
SA2
126
NC/A121
147
NC
168
VDD
21
DNU
42
CK0
Notes:
Figure 2:
63
NC
84
VDD
105
DNU
1. Pin 126 is NC for 32MB and 64MB modules, or A12 for the 128MB module.
Pin Locations (168-Pin DIMM)
Front View
U1
U4
U2
U5
U6
PIN 1
PIN 84
Back View
No components on this side of module
PIN 168
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
PIN 85
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pins may not correlate with symbols; refer to Table 4 on page 3 for more information
Pin Numbers
Symbol
Type
Description
27, 111, 115
Input
42, 79
RAS#, CAS#,
WE#
CK0, CK2
Input
128
CKE0
Input
30, 45
S0#, S2#
Input
28, 29, 46, 47, 112, 113,
130, 131
DQMB0–
DQMB7
Input
39, 122
BA0, BA1
Input
33–38, 117–121, 123,
126 (128MB)
A0–A11
(32MB, 64MB)
A0–A12
(128MB)
Input
83
SCL
Input
165–167
SA0–SA2
Input
82
SDA
Input/Output
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95,
97–101, 103–104, 139–
142, 144, 149–151, 153–
156, 158–161
DQ0–DQ63
Input/Output
Command inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW)
the CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in progress).
CKE is synchronous except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers, including
CK, are disabled during power-down and self refresh modes,
providing low standby power.
Chip select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input/output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (twoclock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial clock for presence-detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-detect address inputs: These pins are used to
configure the presence-detect device.
Serial presence-detect data: SDA is a bidirectional pin used
to transfer addresses and data into and out of the presencedetect portion of the module.
Data I/Os: Data bus.
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions (Continued)
Pins may not correlate with symbols; refer to Table 4 on page 3 for more information
Pin Numbers
Symbol
Type
6, 18, 26, 40, 41, 49, 59,
73, 84, 90, 102, 110, 124,
133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
21, 22, 52, 53, 105, 106,
114, 125, 129, 132, 163
24, 25, 31, 44, 48, 50, 51,
61, 62, 63, 80, 81, 108,
109, 126 (32MB, 64MB),
134, 135, 145–147, 164
VDD
Supply
Power supply: +3.3V ±0.3V.
VSS
Supply
Ground.
DNU
–
NC
–
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
Description
Do not use: These pins are not used on these modules, but
are assigned pins on other modules in this product family.
Not connected: These pins are not connected on these
modules.
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 3:
Functional Block Diagram
S0#
DQMB4
DQMB5
DQML CS#
DQ
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB1
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
S2#
DQMB6
DQMB7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB2
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQML CS#
DQ
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RAS#
RAS#: SDRAMs
CAS#
CAS#: SDRAMs
CKE0
CKE: SDRAMs
WE#
WE#: SDRAMs
A0–A11 (32MB/64MB)
A0–A11: SDRAMs
A0–A12 (128MB)
A0–A12: SDRAMs
BA0–BA1
Notes:
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
DQML CS#
DQ
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM3
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
U1
CK0
DQML CS#
DQ
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U4
CK2
U2
11.2pF
13.6pF
U5
CK1, CK3
10pF
SPD EEPROM
SCL
WP
BA0–BA1: SDRAMs
A0
U6
A1
A2
SDA
VDD
SDRAMs
VSS
SDRAMs
SA0 SA1 SA2
1. All resistor values are 10Ω unless otherwise specified.
2. Per industry standard, Micron modules use various component speed grades as referenced
in the module part numbering guide found on Micron’s Web site:
www.micron.com/support.
3. Standard modules use the following SDRAM devices: MT48LC4M16A2TG(IT) (32MB);
MT48LC8M16A2TG(IT) (64MB); MT48LC16M16A2TG(IT) (128MB).
4. Pb-free modules use the following SDRAM devices: MT48LC4M16A2P(IT) (32MB);
MT48LC8M16A2P(IT) (64MB); MT48LC16M16A2P(IT) (128MB).
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
General Description
General Description
The Micron MT4LSDT464A, MT4LSDT864A(I), and MT4LSDT1664A(I) are high-speed
CMOS, dynamic random access, 32MB, 64MB, and 128MB memory modules organized
in a x64 configuration. These modules use SDRAM devices which are internally configured as quad-bank DRAMs with a synchronous interface (all signals are registered on the
positive edge of the clock signals CK).
Read and write accesses to the SDRAM module are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank, A0–A11 for 32MB and 64MB; A0–A12 for 128MB select the device
row). The address bits registered coincident with the READ or WRITE command (A0–A7
for 32MB; A0–A8 for 64MB and 128MB) are used to select the starting device column
location for the burst access.
These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8
locations, or the full page with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence. These modules use an internal pipelined architecture to achieve highspeed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve
a high-speed, fully random access. Precharging one device bank while accessing one of
the other three device banks will hide the PRECHARGE cycles and provide seamless,
high-speed, random access operation.
These modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs,
outputs, and clocks are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks in order to hide
precharge time, and the capability to randomly change column addresses on each clock
cycle during a burst access. For more information regarding SDRAM operation, refer to
the 64Mb, 128Mb, or 256Mb SDRAM component data sheets.
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM’s SCL (clock) and SDA (data) signals. Write protect (WP) is tied to
ground on the module, permanently disabling hardware write protect.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Once power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Mode Register Definition
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All device
banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
Mode Register Definition
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode, and a write burst mode, as shown in Figure 4 on page 10. The mode register
is programmed via the LOAD MODE REGISTER command and will retain the stored
information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future
use. For the 128MB module, address A12 (M12) is undefined but should be driven LOW
during loading of the mode register.
The mode register must be loaded when all device banks are idle, and the controller
must wait the specified time before initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 4 on page 10. The burst length determines the
maximum number of column locations that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and
the interleaved burst types, and a full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached, as shown in
Table 6 on page 11. The block is uniquely selected by A1–Ai when BL = 2, A2–Ai when BL
= 4, and A3–Ai when BL = 8. See note 8 of Table 6 on page 11 for Ai values. The remaining
(least significant) address bit(s) is (are) used to select the starting location within the
block. Full-page bursts wrap within the page if the boundary is reached, as shown in
Table 6 on page 11.
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Mode Register Definition
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address, as shown in Table 6 on page 11.
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Mode Register Definition
Figure 4:
Mode Register Definition Diagram
32MB and 64MB Modules
A11 A10
11
A9
9
10
A8
8
A6
A7
6
7
Reserved1 WB Op Mode
A5
5
A4
A3
4
3
CAS Latency
1
2
BT
A1
A2
Address Bus
A0
0
Mode Register (Mx)
Burst Length
128MB Module
A12 A11 A10
12
11
Reserved2
10
A9
9
A8
8
A6
A7
6
7
WB Op Mode
A5
5
A4
A3
4
CAS Latency
3
1
2
BT
A1
A2
Address Bus
A0
0
Mode Register (Mx)
Burst Length
Burst Length
M2 M1 M0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full page
Reserved
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
Notes:
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
M3 = 1
0
M3
M9
M3 = 0
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6–M0
Operating Mode
0
0
Defined
Standard operation
–
–
–
All other states reserved
Write Burst Mode
0
Programmed BL
1
Single location access
1. M11 and M10 should be programmed = “0, 0” to ensure compatibility with future devices.
2. M12, M11, and M10 should be programmed = “0, 0, 0” to ensure compatibility with future
devices.
10
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©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Mode Register Definition
Table 6:
Burst Definition Table
Order of Accesses Within a Burst
Burst Length
Starting Column Address
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
A0
0
1
2
4
8
Type = Sequential
A2
0
0
0
0
1
1
1
1
Full page (y)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
A1
A0
0
0
1
1
A1
0
0
1
1
0
0
1
1
n = A0–Ai
(location
0–y)
0
1
0
1
A0
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Not supported
Cn, Cn + 1,
Cn + 2, Cn + 3,
Cn + 4. . . Cn - 1,
Cn . . .
For full-page accesses: y = 256 (32MB); y = 512 (64MB/128MB).
For BL = 2, A1–Ai select the block-of-two burst; A0 selects the starting column within the
block.
For BL = 4, A2–Ai select the block-of-four burst; A0–A1 select the starting column within the
block.
For BL = 8, A3–Ai select the block-of-eight burst; A0–A2 select the starting column within
the block.
For a full-page burst, the full row is selected and A0–Ai select the starting column.
Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
For BL = 1, A0–Ai select the unique column to be accessed, and mode register bit M3 is
ignored.
i = 7 for 32MB; i = 8 for 64MB and 128MB.
11
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©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Mode Register Definition
Figure 5:
CAS Latency Diagram
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 3
Don’t Care
Undefined
CAS Latency (CL)
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 5. Table 7 on page 13 indicates the operating
frequencies at which each CL setting can be used.
Reserved states should not be used because unknown operation or incompatibility with
future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed BL applies to READ bursts, but write accesses are singlelocation (nonburst) accesses.
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
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©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Mode Register Definition
Table 7:
CAS Latency Table
Allowable Operating Clock Frequency (MHz)
Speed
CL = 2
CL = 3
-13E
-133
-10E
≤133
≤100
≤100
≤143
≤133
n/a
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
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©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Commands
Commands
This truth table provides a general reference of available commands. For a more detailed
description of commands and operations, refer to the 64Mb, 128Mb, or 256Mb SDRAM
component data sheet.
Table 8:
Truth Table – Commands and DQMB Operation
Notes appear below; CKE is HIGH for all commands shown except SELF REFRESH
Name (Function)
CS#
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ
burst)
WRITE (select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Notes:
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
RAS# CAS# WE# DQMB
Address
DQs
Notes
H
L
L
L
X
H
L
H
X
H
H
L
X
H
H
H
X
X
X
L/H7
X
X
Bank/row
Bank/col
X
X
X
X
1
3
L
H
L
L
L/H7
Bank/col
Valid
3
L
L
L
H
L
L
H
H
L
L
L
H
X
X
X
X
Code
X
Active
X
X
4
5, 6
L
–
–
L
–
–
L
–
–
L
–
–
X
L
H
Op-code
–
–
X
Active
High-Z
1
7
7
1. A0–A11 define the op-code written to the mode register, and for the 128MB module, A12
should be driven LOW.
2. A0–A11 (32MB and 64MB) or A0–A12 (128MB) provide device row address, and BA0, BA1
determine which device bank is made active.
3. A0–A7 (32MB) or A0–A8 (64MB and 128MB) provide device column address; A10 HIGH
enables the auto precharge feature (nonpersistent) while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.
4. A10 LOW: BA0, BA1 determine the device bank being precharged. A10 HIGH: All device
banks precharged and BA0, BA1 are “Don’t Care.”
5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care”
except for CKE.
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
delay).
14
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©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings
Table 9:
Absolute Maximum Ratings
Parameter
Symbol
Voltage on VDD, VDDQ supply relative to VSS
Voltage on inputs, NC or I/O pins relative to VSS
Operating temperature TOPR (commercial - ambient)
Operating temperature TOPR (industrial - ambient)
Storage temperature (plastic)
Min
Max
Units
–1.0
–1.0
0
–40
–55
+4.6
+4.6
+65
+85
+150
V
V
°C
°C
°C
Capacitance
Table 10:
Capacitance
Notes 1, 2; notes appear on page 20
Parameter
Input capacitance: Address and command
Input capacitance: S#
Input capacitance: CK0
Input capacitance: CK2
Input capacitance: DQMB
Input/output capacitance: DQ
Symbol
Min
Max
Units
CI1
CI2
CI3a
CI3b
CI4
CIO
10
5
16.2
18.6
2.5
4
15.2
7.6
18.2
20.6
3.8
6
pF
pF
pF
pF
pF
pF
Timing and Operating Conditions
Table 11:
AC Functional Characteristics
Notes: 5, 6, 8, 9, 11, 31; notes appear on page 20
Parameter
Symbol
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
15
t
CCD
t
CKED
tPED
tDQD
tDQM
t
DQZ
t
DWD
tDAL
tDPL
tBDL
tCDL
t
RDL
tMRD
-13E
-133
-10E
1
1
1
0
0
2
0
4
2
1
1
2
2
1
1
1
0
0
2
0
5
2
1
1
2
2
1
1
1
0
0
2
0
4
2
1
1
2
2
Units
t
CK
t
CK
tCK
tCK
tCK
t
CK
t
CK
tCK
tCK
tCK
tCK
t
CK
tCK
Notes
17
14
14
17
17
17
17
15, 21
16, 21
17
17
16, 21
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©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Electrical Specifications
Table 11:
AC Functional Characteristics (Continued)
Notes: 5, 6, 8, 9, 11, 31; notes appear on page 20
Parameter
Symbol
Data-out to high-impedance from PRECHARGE
command
t
Table 12:
CL = 3
CL = 2
-13E
ROH(3)
ROH(2)
3
2
t
-133
-10E
3
2
Units
3
2
t
CK
CK
t
Notes
17
17
Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11, 31; notes appear on page 20; VDD, VDDQ = +3.3V ±0.3V
AC Characteristics
-13E
Parameter
Access time from CLK
(positive edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
Symbol
CL = 3
CL = 2
AC(3)
tAC(2)
t
AH
tAS
tCH
tCL
CL = 3
CL = 2
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time CL = 3
CL = 2
Data-out low-impedance time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8,192 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b
command
Transition time
WRITE recovery time
Exit SELF REFRESH to ACTIVE command
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
t
tCK(3)
tCK(2)
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ(3)
tHZ(2)
tLZ
tOH
tOH
N
tRAS
tRC
tRCD
t
REF
tRFC
tRP
tRRD
tT
tWR
t
XSR
-133
-10E
Min
Max
Min
Max
Min
Max
Units
Notes
–
–
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
1.5
0.8
1.5
–
–
1
3
1.8
37
60
15
–
66
15
14
5.4
5.4
–
–
–
–
–
–
–
–
–
–
–
–
5.4
5.4
–
–
–
120,000
–
–
64
–
–
–
–
–
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
0.8
1.5
–
–
1
3
1.8
44
66
20
–
66
20
15
5.4
6
–
–
–
–
–
–
–
–
–
–
–
–
5.4
6
–
–
–
120,000
–
–
64
–
–
–
–
–
1
2
3
3
8
10
1
2
1
2
1
2
–
–
1
3
1.8
50
70
20
–
70
20
20
–
6
–
–
–
–
–
–
–
–
–
–
–
–
6
6
–
–
–
120,000
–
–
64
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
27
0.3
1 CLK +
7ns
14
67
1.2
–
0.3
1 CLK +
7.5ns
15
75
1.2
–
0.3
1 CLK +
7ns
15
80
1.2
–
ns
ns
7
24
–
–
ns
ns
25
20
–
–
16
–
–
23
23
10
10
28
32
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©2002 Micron Technology, Inc. All rights reserved.
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Electrical Specifications
Table 13:
DC Electrical Characteristics and Operating Conditions
Notes: 1, 5, 6; notes appear on page 20; VDD, VDDQ = +3.3V ±0.3V
Parameter/Condition
Symbol
Min
Max
Units
Notes
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Input leakage current: Any input 0V ≤ VIN ≤ VDD
(all other pins not under test = 0V)
VDD, VDDQ
VIH
VIL
II
22
22
33
IOZ
3.6
VDD + 0.3
0.8
20
10
5
5
V
V
V
µA
Output leakage current: DQs are disabled;
0V ≤ VOUT ≤ VDDQ
Output levels: Output high voltage (IOUT = –4mA)
Output low voltage: (IOUT = 4mA)
3
2
–0.3
–20
–10
–5
–5
µA
33
VOH
VOL
2.4
–
–
0.4
V
V
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Electrical Specifications
IDD Specifications
Table 14:
IDD Specifications and Conditions – 32MB
Notes: 1, 5, 6, 11, 13; notes appear on page 20; VDD, VDDQ = +3.3V ±0.3V; DRAM components only
Max
Parameter/Condition
Symbol
-13E
-133
-10E
Units
Notes
IDD1
500
460
380
mA
IDD2
8
8
8
mA
3, 18, 19,
29
29
IDD3
180
180
140
mA
IDD4
600
560
480
mA
IDD5
IDD6
IDD7
920
12
4
840
12
4
760
12
4
mA
mA
mA
Operating current: Active mode; Burst = 2; READ or WRITE;
RC = tRC (MIN)
Standby current: Power-down mode; All device banks idle;
CKE = LOW
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All
device banks active after tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or
WRITE; All device banks active
tRFC = tRFC (MIN)
Auto refresh current: CS# = HIGH;
tRFC = 15.62µs
CKE = HIGH
Self refresh current: CKE ≤ 0.2V
t
Table 15:
3, 12, 19,
29
3, 18, 19,
29
3, 12, 18,
19, 29, 30
4
IDD Specifications and Conditions – 64MB
Notes: 1, 5, 6, 11, 13; notes appear on page 20; VDD, VDDQ = +3.3V ±0.3V; DRAM components only
Max
Parameter/Condition
Symbol
-13E
-133
-10E
Units
Notes
IDD1
640
600
560
mA
3, 18, 19, 29
IDD2
8
8
8
mA
29
IDD3
200
200
160
mA
3, 12, 19, 29
IDD4
660
600
560
mA
3, 18, 19, 29
mA
mA
mA
3, 12, 18,
19, 29, 30
Operating current: Active mode; Burst = 2; READ or WRITE;
= tRC (MIN)
Standby current: Power-down mode; All device banks idle;
CKE = LOW
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All
device banks active after tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or
WRITE; All device banks active
tRFC = tRFC (MIN)
Auto refresh current: CS# = HIGH;
t
CKE = HIGH
RFC = 15.62µs
Self refresh current: CKE ≤ 0.2V
tRC
Table 16:
IDD5
IDD6
IDD7
1,320 1,240 1,080
12
12
12
8
8
8
4
IDD Specifications and Conditions – 128MB
Notes: 1, 5, 6, 11, 13; notes appear on page 20; VDD, VDDQ = +3.3V ±0.3V; DRAM components only
Max
Parameter/Condition
Operating current: Active mode; burst = 2; READ or WRITE;
= tRC (MIN)
Standby current: Power-down mode; All device banks idle;
CKE = LOW
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All
device banks active after tRCD met; No accesses in progress
Operating current: Burst mode; Continuous burst; READ or
WRITE; All device banks active
Symbol
-13E
-133
-10E
Units
Notes
IDD1
540
500
500
mA
3, 18, 19, 29
IDD2
8
8
8
mA
29
IDD3
160
160
160
mA
3, 12, 19, 29
IDD4
540
540
540
mA
3, 18, 19, 29
tRC
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Electrical Specifications
Table 16:
IDD Specifications and Conditions – 128MB (Continued)
Notes: 1, 5, 6, 11, 13; notes appear on page 20; VDD, VDDQ = +3.3V ±0.3V; DRAM components only
Max
Parameter/Condition
Auto refresh current: CS# = HIGH;
CKE = HIGH
Symbol
t
t
RFC = RFC (MIN)
RFC = 7.81µs
t
Self refresh current: CKE ≤ 0.2V
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
19
IDD5
IDD6
IDD7
-13E
-133
-10E
1,140 1,080 1,080
14
14
14
10
10
10
Units
Notes
mA
mA
mA
3, 12, 18,
19, 29, 30
4
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Notes
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V;
f = 1 MHz; TA = 25°C; pin under test biased at 1.4V.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over the full temperature range is
ensured (0°C ≤ TA ≤ +70°C for commercial, –40°C ≤ TA ≤ +85°C for industrial).
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated anytime the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the ISV crossover point.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 10ns for -10E; tCK = 7.5ns for -133 and -13E.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤3ns, and the pulse width
cannot be greater than one-third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤3ns.
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20
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Notes
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR and PRECHARGE commands). CKE may be used
to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -13E;
7.5ns for -133; and 7ns for -10E after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For -13E, CL = 2 and tCK = 7.5ns; for -133, CL = 3 and tCK = 7.5ns; for -10E, CL = 2 and
t
CK = 10ns.
30. CKE is HIGH during refresh command period tRFC (MIN), else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
31. Refer to device data sheet for timing waveforms.
32. The value of tRAS used in -13E speed grade modules is calculated from tRC - tRP.
33. Leakage number reflects the worst-case leakage possible through the module pin, not
what each memory device contributes.
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21
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Serial Presence-Detect
Serial Presence-Detect
SPD Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions, as indicated in Figure 6
on page 22 and Figure 7 on page 23.
SPD Start Condition
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data, as indicated in Figure 8 on page 23.
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each
subsequent eight-bit word. In the read mode, the SPD device will transmit eight bits of
data, release the SDA line, and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
Figure 6:
Data Validity
SCL
SDA
DATA STABLE
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
DATA
CHANGE
22
DATA STABLE
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Serial Presence-Detect
Figure 7:
Definition of Start and Stop
SCL
SDA
START
BIT
Figure 8:
STOP
BIT
Acknowledge Response from Receiver
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Table 17:
EEPROM Device Select Code
The most significant bit (b7) is sent first
Device Type Identifier
Memory area select code (two arrays)
Protection register select code
Table 18:
Chip Enable
RW#
b7
b6
b5
b4
b3
b2
b1
b0
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW#
RW#
EEPROM Operating Modes
Mode
Current address read
Random address read
Sequential read
Byte write
Page write
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
RW# Bit
W#C
Bytes
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
VIL
1
1
1
≥1
1
≤16
23
Initial Sequence
Start, device select, RW# = ‘1’
Start, device select, RW# = ‘0’, address
Restart, device select, RW# = ‘1’
Similar to current or random address read
Start, device select, RW# = ‘0’
Start, device select, RW# = ‘0’
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Serial Presence-Detect
Figure 9:
SPD EEPROM Timing Diagram
tF
t HIGH
tR
t LOW
SCL
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
t DH
t AA
t BUF
SDA OUT
Undefined
Table 19:
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
Symbol
Min
Max
Units
VDD
VIH
VIL
VOL
ILI
ILO
ISB
3
VDD x 0.7
–1
–
–
–
–
3.6
VDD + 0.5
VDD x 0.3
0.4
10
10
30
V
V
V
V
µA
µA
µA
IDD
–
2
mA
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUTL = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = GND or
3.3V ±10%
Power supply current: SCL clock frequency = 100 KHz
Table 20:
Serial Presence-Detect EEPROM AC Operating Conditions
Notes appear below; All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
Symbol
Min
Max
Units
Notes
tAA
0.2
1.3
200
–
0
0.6
0.6
–
1.3
–
–
100
0.6
0.6
0.9
–
–
300
–
–
–
50
–
0.3
400
–
–
–
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
1
tBUF
t
DH
t
F
tHD:DAT
tHD:STA
tHIGH
t
I
tLOW
tR
fSCL
tSU:DAT
t
SU:STA
tSU:STO
24
2
2
3
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Serial Presence-Detect
Table 20:
Serial Presence-Detect EEPROM AC Operating Conditions (Continued)
Notes appear below; All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
Symbol
Min
Max
Units
Notes
t
WRITE cycle time
Notes:
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
WRC
–
10
ms
4
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle,
the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and
the EEPROM does not respond to its slave address.
25
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Serial Presence-Detect
Table 21:
Serial Presence-Detect Matrix
“1”/”0”: Serial data, “driven to HIGH”/”driven to LOW.”
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Description
Entry (Version)
128
256
SDRAM
12 or 13
8 or 9
1
64
0
LVTTL
7ns (-13E)
7.5ns (-133)
8ns (-10E)
5.4ns (-13E/-133)
SDRAM access from clock, tAC
6ns (-10E)
(CL = 3)
None
Module configuration type
(80) 15.6µs/SELF
Refresh rate/type
(82) 7.81µs/SELF
16
SDRAM width (primary SDRAM)
None
Error-checking SDRAM data width
1
Minimum clock delay, tCCD
1, 2, 4, 8, page
Burst lengths supported
4
Number of internal banks on SDRAM device
2, 3
CAS latencies supported
0
CS latency
0
WE latency
Unbuffered
SDRAM module attributes
0E
SDRAM device attributes: general
tCK (CL = 2)
7.5ns (-13E)
SDRAM cycle time,
10ns (-133/-10E)
5.4ns (-13E)
SDRAM access from CK, tAC (CL = 2)
6ns (-133/-10E)
–
SDRAM cycle time, tCK (CL = 1)
–
SDRAM access from CK, tAC (CL = 1)
15ns (-13E)
Minimum row precharge time, tRP
20ns (-133/-10E)
14ns (-13E)
Minimum row active to row active, tRRD
15ns (-133)
20ns (-10E)
15ns (-13E)
Minimum RAS# to CAS# delay, tRCD
20ns (-133/-10E)
45ns (-13E)
Minimum RAS# pulse width, tRAS
44ns (-133)
(see note 1)
50ns (-10E)
32MB, 64MB, or 128MB
Module rank density
1.5ns (-13E/-133)
Command and address setup time
2ns (-10E)
Number of bytes used by Micron
Total number of SPD memory bytes
Memory type
Number of row addresses
Number of column addresses
Number of banks
Module data width
Module data width (continued)
Module voltage interface levels
SDRAM cycle time, tCK (CL = 3)
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
26
32MB
64MB
128MB
80
08
04
0C
08
01
40
00
01
70
75
80
54
60
00
80
80
08
04
0C
09
01
40
00
01
70
75
80
54
60
00
80
80
08
04
0D
09
01
40
00
01
70
75
80
54
60
00
82
10
00
01
8F
04
06
01
01
00
0E
75
A0
54
60
00
00
0F
14
0E
0F
14
0F
14
2D
2C
32
08
15
20
10
00
01
8F
04
06
01
01
00
0E
75
A0
54
60
00
00
0F
14
0E
0F
14
0F
14
2D
2C
32
10
15
20
10
00
01
8F
04
06
01
01
00
0E
75
A0
54
60
00
00
0F
14
0E
0F
14
0F
14
2D
2C
32
20
15
20
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Serial Presence-Detect
Table 21:
Serial Presence-Detect Matrix (Continued)
“1”/”0”: Serial data, “driven to HIGH”/”driven to LOW.”
Byte
Description
33
Command and address hold time
34
Data Signal input setup time
35
Data signal input hold time
36–61 Reserved
41
Device minimum active/auto-refresh time,
t
RC
42–61 Reserved
62
SPD revision
63
Checksum for bytes 0–62
64
65–71
72
73–90
91
92
93
94
95–98
99–125
126
127
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code (continued)
Manufacturing location
Module part number (ASCII)
PCB identification code
Identification code (continued)
Year of manufacture in BCD
Week of manufacture in BCD
Module serial number
Manufacturer-specific data (reserved)
System frequency
SDRAM component and clock detail
Notes:
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SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
Entry (Version)
32MB
64MB
128MB
0.8ns (-13E/-133)
1ns (-10E)
1.5ns (-13E/-133)
2ns (-10E)
0.8ns (-13E/-133)
1ns (-10E)
08
10
15
20
08
10
00
3C
42
46
00
02
82
CE
1A
2C
FF
01–0C
Variable data
01–09
00
Variable data
Variable data
Variable data
Variable data
64
AF
08
10
15
20
08
10
00
3C
42
46
00
02
8B
D7
23
2C
FF
01–0C
Variable data
01–09
00
Variable data
Variable data
Variable data
Variable data
64
AF
08
10
15
20
08
10
00
3C
42
46
00
02
9E
EA
36
2C
FF
01–0C
Variable data
01–09
00
Variable data
Variable data
Variable data
Variable data
64
AF
60ns (-13E)
66ns (-133)
70ns (10E)
2
-13E
-133
-10E
MICRON
1–12
1–9
0
100/133 MHz
1. The value of tRAS used for the -13E part is calculated from tRC - tRP. Actual device specification value is 37ns.
27
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32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Module Dimensions
Module Dimensions
Figure 10:
168-Pin DIMM
FRONT VIEW
3.18 (0.125)
MAX
133.05 (5.256)
133.20 (5.244)
2.00 (0.079) R
(2X)
U1
U4
U2
U5
U6
3.00 (0.118)
(2X)
25.53 (1.005)
17.78 (0.700) 25.27 (0.995)
TYP
3.00 (0.118) TYP
6.35 (0.250) TYP
3.00 (0.118)
TYP
42.18 (1.661)
1.00 (0.039) R
(2X)
66.68 (2.625)
PIN 1 (PIN 85 ON BACKSIDE)
3.25 (0.128)
(2X)
3.00 (0.118)
1.00 (0.039)
TYP
1.27 (0.050)
TYP
1.37 (0.054)
1.17 (0.046)
PIN 84 (PIN 168 ON BACKSIDE)
115.57 (4.550)
Notes:
1. All dimensions in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for complete design dimensions.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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