Freescale Semiconductor Technical Data 900 MHz Low Voltage LVPECL Clock Synthesizer The MPC9239 is a 3.3 V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 3.125 MHz to 900 MHz and the support of differential LVPECL output signals the device meets the needs of the most demanding clock applications. MPC9239 Rev. 3, 08/2005 MPC9239 900 MHz LOW VOLTAGE CLOCK SYNTHESIZER Features • • • • • • • • • • • • • • • 3.125 MHz to 900 MHz synthesized clock output signal Differential LVPECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference input 3.3 V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 28 PLCC and 32 LQFP packaging 28-lead and 32-lead Pb-free package available SiGe Technology Ambient temperature range 0°C to + 70°C Pin and function compatible to the MC12439 Functional Description FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 EI SUFFIX 28-LEAD PLCC PACKAGE Pb-FREE PACKAGE CASE 776-02 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 Ω to VCC – 2.0 V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. Refer to the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the fOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the fOUT input will step back up to its programmed frequency in four discrete increments. © Freescale Semiconductor, Inc., 2005. All rights reserved. XTAL_IN XTAL_OUT XTAL 1 10 – 20 MHz Ref ÷2 PLL 800 – 1800 MHz 0 fREF_EXT ÷1 ÷2 ÷4 ÷8 ÷2 VCO VCC 11 00 01 10 1 ÷16 fOUT fOUT OE 0 FB ÷0 TO ÷127 7-BIT M-DIVIDER XTAL_SEL ÷2 2 9 VCC TEST TEST M-LATCH 3 N-LATCH T-LATCH LE P_LOAD S_LOAD P/S 0 1 S_DATA S_CLOCK 0 1 BITS 0-2 BITS 3-4 BITS 11-5 12-BIT SHIFT REGISTER VCC M[0:6] N[1:0] PWR_DOWN OE 16 NC VCC 27 14 M[2] 15 XTAL_SEL VCC 28 13 M[1] GND 29 12 M[0] fOUT 30 11 P_LOAD fOUT 31 10 OE VCC 32 9 M[3] 3 4 5 6 7 8 XTAL_IN M[2] 2 fREF_EXT M[1] 1 PWR_DOWN M[0] Figure 2. MPC9239 28-Lead PLCC Pinout (Top View) MPC9239 VCC_PLL 12 P_LOAD M[4] M[3] M[4] OE M[5] 15 4 XTAL_OUT M[6] 26 XTAL_IN 11 XTAL_SEL TEST M[5] 10 17 N[0] 13 9 18 17 3 8 19 NC fREF_EXT 7 20 16 M[6] 6 21 25 14 5 22 GND 2 MPC9239 23 N[1] PWR_DOWN S_LOAD 24 18 VCC_PLL S_DATA NC 19 VCC_PLL 20 N[0] GND 21 S_LOAD TEST 22 N[1] VCC 23 S_DATA GND 24 NC fOUT 25 2 6 2 7 2 8 1 S_CLOCK fOUT S_CLOCK VCC Figure 1. MPC9239 Logic Diagram XTAL_OUT Figure 3. MPC9239 32-Lead LQFP Pinout (Top View) MPC9239 2 Advanced Clock Drivers Devices Freescale Semiconductor Table 1. Pin Configurations Pin I/O Default Type Input 0 LVCMOS Alternative PLL reference input. XTAL_IN, XTAL_OUT fREF_EXT Analog Function Crystal oscillator interface. fOUT, fOUT Output LVPECL Differential clock output. TEST Output LVCMOS Test and device diagnosis output. XTAL_SEL Input 1 LVCMOS PLL reference select input. PWR_DOWN Input 0 LVCMOS Configuration input for power down mode. Assertion (deassertion) of power down will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps. PWR_DOWN assertion (deassertion) is synchronous to the input reference clock. S_LOAD Input 0 LVCMOS Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. P_LOAD Input 1 LVCMOS Parallel configuration control input. this input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive. S_DATA Input 0 LVCMOS Serial configuration data input. S_CLOCK Input 0 LVCMOS Serial configuration clock input. M[0:6] Input 1 LVCMOS Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. N[1:0] Input 1 LVCMOS Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD. OE Input 1 LVCMOS Output enable (active high). The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the fOUT output. OE = L low stops fOUT in the logic low stat (fOUT = L, fOUT = H). GND Supply Ground VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. VCC_PLL Supply VCC PLL positive power supply (analog power supply). NC Negative power supply (GND). Do not connect. Table 2. Output Frequency Range and PLL Post-Divider N N 1 0 VCO Output Frequency Division fOUT Frequency Range 0 0 0 2 200 – 450 MHz 0 0 1 4 100 – 225 MHz 0 1 0 8 50 – 112.5 MHz 0 1 1 1 400 – 900 MHz 1 0 0 32 12.5 – 28.125 MHz 1 0 1 64 6.25 – 14.0625 MHz 1 1 0 128 3.125 – 7.03125 MHz 1 1 1 16 25 – 56.25 MHz PWR_DOWN MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 3 Table 3. Function Table Input 0 1 XTAL_SEL fREF_EXT XTAL interface OE Outputs disabled. fOUT is stopped in the logic low state (fOUT = L, fOUT = H) Outputs enabled PWR_DOWN Output divider ÷ 1 Output divider ÷ 16 Table 4. General Specifications Symbol Characteristics Min Typ Max Unit VTT Output Termination Voltage VCC – 2 MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V 200 LU Latch-Up Immunity CIN Input Capacitance θJA LQFP 32 Thermal Resistance Junction to Ambient JESD 51-3, single layer test board θJC mA 4.0 JESD 51-6, 2S2P multilayer test board LQFP 32 Thermal Resistance Junction to Case Condition V pF Inputs 83.1 73.3 68.9 63.8 57.4 86.0 75.4 70.9 65.3 59.6 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0 54.4 52.5 50.4 47.8 60.6 55.7 53.8 51.5 48.8 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 23.0 26.3 °C/W MIL-SPEC 883E Method 1012.1 Table 5. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC + 0.3 V DC Output Voltage –0.3 VCC + 0.3 V ±20 mA ±50 mA 125 °C VOUT IIN IOUT TS DC Input Current DC Output Current Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. MPC9239 4 Advanced Clock Drivers Devices Freescale Semiconductor Table 6. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C) Symbol Characteristics Min Typ Max Unit Condition LVCMOS Control Inputs (fREF_EXT, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE) VIH Input High Voltage VIL Input Low Voltage IIN Input 2.0 Current(1) Differential Clock Output fOUT VCC + 0.3 V LVCMOS 0.8 V LVCMOS ±200 µA VIN = VCC or GND (2) VOH Output High Voltage(3) VCC–1.02 VCC–0.74 V LVPECL VOL Voltage(3) VCC–1.95 VCC–1.60 V LVPECL Output Low Test and Diagnosis Output TEST VOH Output High Voltage(3) VOL Output Low Voltage(3) 2.0 V IOH = –0.8 mA 0.55 V IOL = 0.8 mA 20 mA VCC_PLL Pins 100 mA All VCC Pins Supply Current ICC_PLL ICC Maximum PLL Supply Current Maximum Supply Current 62 1. Inputs have pull-down resistors affecting the input current. 2. Outputs terminated 50 Ω to VTT = VCC – 2 V. 3. The MPC9239 TEST output levels are compatible to the MC12429 output levels. The MPC9239 is capable of driving 25 Ω loads. Table 7. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1) Symbol fXTAL Characteristics Max Unit 10 20 MHz 800 1800 MHz 400 300 100 50 900 450 225 112.5 MHz MHz MHz MHz Serial Interface Programming Clock Frequency(3) 0 10 MHz Minimum Pulse Width 50 Crystal Interface Frequency Range Range(2) fVCO VCO Frequency fMAX Output Frequency fS_CLOCK tP,MIN Min DC Output Duty Cycle tr, tf Output Rise/Fall Time N = 11 (÷ 1) N = 00 (÷ 2) N = 01 (÷ 4) N = 10 (÷ 8) (S_LOAD, P_LOAD) 45 0.05 Typ 50 55 % 0.3 ns Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD 20 20 20 ns ns ns tS Hold Time S_DATA to S_CLOCK M, N to P_LOAD 20 20 ns ns tJIT(CC) Cycle-to-Cycle Jitter N = 11 (÷ 1) N = 00 (÷ 2) N = 01 (÷ 4) N = 10 (÷ 8) 60 90 120 160 ps ps ps ps tJIT(PER) Period Jitter N = 11 (÷ 1) N = 00 (÷ 2) N = 01 (÷ 4) N = 10 (÷ 8) 40 65 90 120 ps ps ps ps 10 ms Maximum PLL Lock Time PWR_DOWN = 0 ns tS tLOCK Condition 20% to 80% 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL ⋅ 2 ⋅ M. 3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. Refer to the application section for more details. MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 5 Table 8. MPC9239 Frequency Operating Range (in MHz) VCO frequency for a crystal interface frequency of M M[6:0] 20 0010100 800 21 0010101 840 22 0010110 23 0010111 24 0011000 864 960 25 0011001 800 900 26 0011010 832 27 0011011 28 0011100 29 0011101 30 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz Output frequency for fXTAL = 16 MHz and for N = 1 2 4 8 1000 400 200 100 50 936 1040 416 208 104 52 864 972 1080 432 216 108 54 812 896 1008 1120 448 224 112 56 840 928 1044 1160 464 232 116 58 0011110 875 960 1080 1200 480 240 120 60 31 0011111 868 992 1116 1240 496 248 124 62 32 0100000 896 1024 1152 1280 512 256 128 64 33 0100001 924 1056 1188 1320 528 264 132 66 34 0100010 816 952 1088 1224 1360 544 272 136 68 35 0100011 840 980 1120 1260 1400 560 280 140 70 36 0100100 864 1008 1152 1296 1440 576 288 144 72 37 0100101 888 1036 1184 1332 1480 592 296 148 74 38 0100110 912 1064 1216 1368 1520 608 304 152 76 39 0100111 936 1092 1248 1404 1560 624 312 156 78 40 0101000 800 960 1120 1280 1440 1600 640 320 160 80 41 0101001 820 984 1148 1312 1476 1640 656 328 164 82 42 0101010 840 1008 1176 1344 1512 1680 672 336 168 84 43 0101011 860 1032 1204 1376 1548 1720 688 344 172 86 44 0101100 880 1056 1232 1408 1584 1760 704 352 176 88 45 0101101 900 1080 1260 1440 1620 1800 720 360 180 90 46 0101110 920 1104 1288 1472 1656 736 368 184 92 47 0101111 940 1128 1316 1504 1692 752 376 188 94 48 0110000 960 1152 1344 1536 1728 768 384 192 96 49 0110001 980 1176 1372 1568 1764 784 392 196 98 50 0110010 1000 1200 1400 1600 1800 800 400 200 100 51 0110011 1020 1224 1428 1632 816 408 204 102 52 0110100 1040 1248 1456 1664 832 416 208 104 53 0110101 1060 1272 1484 1696 848 424 212 106 54 0110110 1080 1296 1512 1728 864 432 216 108 55 0110111 1100 1320 1540 1760 880 440 220 110 56 0111000 1120 1344 1568 1792 896 448 224 112 57 0111001 1140 1368 1596 58 0111010 1160 1392 1624 59 0111011 1180 1416 1652 60 0111100 1200 1440 1680 61 0111101 1220 1488 1736 62 0111110 1260 1512 1764 63 0111111 1260 1512 1764 64 1000000 1280 1536 1792 ... ... ... ... 10 MHz 880 828 920 MPC9239 6 Advanced Clock Drivers Devices Freescale Semiconductor Programming the MPC9239 Programming the MPC9239 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: (1) fOUT = (fXTAL ÷ 2) ⋅ (M ⋅ 4) ÷ (N ⋅ 2) or (2) fOUT = fXTAL ⋅ M ÷ N where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to match the VCO frequency range of 800 to 1800 MHz in order to achieve stable PLL operation: (3) MMIN = fVCO,MIN ÷ (2 ⋅ fXTAL) and (4) MMAX = fVCO,MAX ÷ (2 ⋅ fXTAL) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 25 and M = 56. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: fOUT = 16 M ÷ N Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 10 MHz N fOUT fOUT Range fOUT Step 2 8⋅M 200–450 MHz 8 MHz 1 4 4⋅M 100–225 MHz 4 MHz 0 8 2⋅M 50–112.5 MHz 2 MHz 1 1 16⋅M 400–900 MHz 16 MHz 1 0 Value 0 0 0 1 1 Example Calculation for an 16 MHz Input Frequency For example, if an output frequency of 384 MHz was desired, the following steps would be taken to identify the appropriate M and N values. 384 MHz falls within the frequency range set by an N value of 2, so N[1:0]=00. For N = 2, fOUT = 8⋅M, and M = fOUT ÷ 8. Therefore, M = 384 ÷ 8 = 48, so M[6:0] = 0110000. Following this procedure a user can generate any whole frequency between 50 MHz and 900 MHz. The size of the programmable frequency steps will be equal to: fSTEP = fXTAL ÷ N Using the Parallel and Serial Interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[6:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[6:0] and N[1:0] inputs will affect the fOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 12 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1, and M6). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MPC9239 synthesizer. M[6:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the Test and Diagnosis Output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents fOUT, the LVCMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1, and T0 control bits are preset to ‘000' when P_LOAD is LOW so that the PECL fOUT outputs are as jitterfree as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC9239 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC9239 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the fOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving fOUT directly gives the user more control on the test clocks sent through the clock tree shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the fOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 7 Table 11. Debug Configuration for PLL Bypass(1) Table 10. Test and Debug Configuration for TEST T[2:0] Output TEST Output T2 T1 T0 0 0 0 12-bit shift register out(1) 0 0 1 Logic 1 0 1 0 fXTAL ÷ 2 0 1 1 M-Counter out 1 0 0 fOUT 1 0 1 Logic 0 1 1 0 M-Counter out in PLL-bypass mode 1 1 1 fOUT ÷ 4 Configuration fOUT S_CLOCK ÷ N TEST M-Counter out(2) 1. T[2:0] = 110. AC specifications do not apply in PLL bypass mode. 2. Clocked out at the rate of S_CLOCK ÷ (2 ⋅ N) 1. Clocked out at the rate of S_CLOCK. S_CLOCK T2 S_DATA T0 N1 N0 M6 M5 M4 M3 M2 M1 M0 First Bit S_LOAD M[6:0] N[1:0] T1 Last Bit M, N P_LOAD Figure 4. Serial Interface Timing Diagram Power Supply Filtering The MPC9239 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The MPC9239 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC9239. Figure 5 illustrates a typical power supply filter scheme. The MPC9239 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC9239 pin of the MPC9239. From the data sheet, the VCC_PLLcurrent (the current sourced through the VCC_PLL pin) is maximum 20 mA, assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. The resistor shown in Figure 5 must have a resistance of 10-15 Ω to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 µH choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than 15 Ω). VCC RF = 10-15 Ω CF = 22 µF VCC_PLL C2 MPC9239 VCC C1, C2 = 0.01...0.1 µF C1 Figure 5. VCC_PLL Power Supply Filter MPC9239 8 Advanced Clock Drivers Devices Freescale Semiconductor Layout Recommendations The MPC9239 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representative board layout for the MPC9239. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC9239 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on—board oscillator. Although the MPC9239 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. C1 C1 Using the On-Board Crystal Oscillator The MPC9239 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC9239 as possible to avoid any board level parasitics. To facilitate colocation surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the XTAL terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1KΩ. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MPC9239 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 12 below specifies the performance requirements of the crystals to be used with the MPC9239. Table 12. Recommended Crystal Specifications Parameter 1 CF C2 XTAL = VCC = GND Value Crystal Cut Fundamental AT Cut Resonance Series Resonance* Frequency Tolerance ±75 ppm at 25°C Frequency/Temperature Stability ±150 pm 0 to 70°C Operating Range 0 to 70°C Shunt Capacitance 5-7 pF Equivalent Series Resistance (ESR) 50 to 80 Ω Correlation Drive Level 100 µW Aging 5ppm/Yr (First 3 Years) * See accompanying text for series versus parallel resonant discussion. = Via Figure 6. PCB Board Layout Recommendation for the PLCC28 Package MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 9 PACKAGE DIMENSIONS 0.007 (0.180) B M T L-M S N S Y BRK -N- 0.007 (0.180) U M T L-M S N S D Z -M- -L- W 28 D X V 1 G1 0.010 (0.250) S T L-M N S S VIEW D-D A 0.007 (0.180) R 0.007 (0.180) M T L-M S N S N S C M T L-M S 0.007 (0.180) H Z M T L-M N S S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) -T- T L-M S N S 0.007 (0.180) M T L-M S N S VIEW S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXISTS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DEMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASITC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MILLIMETERS MAX MAX MIN MIN 12.57 0.485 0.495 12.32 12.57 0.485 0.495 12.32 4.20 4.57 0.165 0.180 2.29 2.79 0.090 0.110 0.33 0.48 0.013 0.019 0.050 BSC 1.27 BSC 0.032 0.66 0.81 0.026 --0.020 --0.51 --0.025 --0.64 0.450 0.456 11.43 11.58 11.58 0.450 0.456 11.43 0.042 0.048 1.07 1.21 1.07 1.21 0.042 0.048 1.42 0.042 0.056 1.07 0.020 --0.50 --2˚ 10˚ 2˚ 10˚ 0.410 0.430 10.42 10.92 --1.02 --0.040 CASE 776-02 ISSUE D 28-LEAD PLCC PACKAGE MPC9239 10 Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS PAGE 1 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 11 PACKAGE DIMENSIONS PAGE 2 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE MPC9239 12 Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS PAGE 3 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE MPC9239 Advanced Clock Drivers Devices Freescale Semiconductor 13 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 [email protected] MPC9239 Rev. 3 08/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005. All rights reserved.