HI-8685, HI-8686 PIN CONFIGURATIONS (Top View) DESCRIPTION The HI-8685 and HI-8686 are system components for interfacing incoming ARINC 429 signals to 16-bit parallel data using proven +5V analog/digital CMOS technology. Both products incorporate the digital logic and analog line receiver circuitry in a single device. The receivers on the HI-8685 and the HI-8686 connect directly to the ARINC 429 Bus and translate the incoming signals to normal CMOS levels. Internal comparator levels are set just below the standard 6.5 volt minimum data threshold and just above the standard 2.5 volt maximum null threshold. The -10 version of the HI-8685 allows the incorporation of an external 10KW resistance in series with each ARINC input for lightning protection without affecting ARINC level detection. Both products offer high speed 16-bit parallel bus interface, a 32-bit buffer, and error detection for word length and parity. A reset pin is also provided for power-on initialization. DATARDY 1 28 Vcc D15 2 27 GAPCLK D14 3 26 TESTA D13 4 25 TESTB D12 5 24 RESET D11 6 D10 7 D9 8 D8 9 HI-8685PSI 23 HI-8685PST 22 & 21 HI-8685PSI-10 HI-8685PST-10 20 D7 10 19 READ D6 11 18 D0 D5 12 17 D1 D4 13 16 D2 GND 14 15 D3 RINA (-10) ERROR PARITY ENB 26 - TESTA 25 - TESTB Error detection - word length and parity 30 - D15 32 - D13 High speed parallel 16-bit data bus 31 - D14 561 data to 16-bit parallel data 28 - Vcc ! Automatic conversion of serial ARINC 429, 575 & 27 - GAPCLK FEATURES ! ! ! ! ! ! ! RINB (-10) HI-8685 28-Pin Plastic SOIC - WB Package 29 - DATARDY December 2008 ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 16-Bit Parallel Data Reset input for power-on initialization On-chip line receiver Input hysteresis of at least 2 volts N/C - 1 24 - RESET D12 - 2 23 - RINB-10 D11 - 3 Test lnputs bypass analog inputs 22 - RINB HI-8686PQI HI-8686PQT D10 - 4 D9 - 5 21 - RINA 20 - RINA-10 ! Industrial and extended temperature ranges APPLICATIONS ! Avionics data communication D0 - 15 D5 - 9 SOIC, PQFP and PLCC READ - 16 17 - N/C D2 - 13 ! Small, surface mount, plastic package options: D1 - 14 18 - PARITY ENB D6 - 8 D3 - 12 19 - ERROR D7 - 7 GND - 11 D8 - 6 D4 - 10 Simplified lightning protection with the ability to add 10 Kohm external series resistors HI-8686 32-Pin Plastic PQFP Package ! Serial to parallel conversion ! Parallel to serial conversion (DS8685 Rev. N) (See page 8 for additional pin configurations) HOLT INTEGRATED CIRCUITS www.holtic.com 12/08 HI-8685, HI-8686 PIN DESCRIPTIONS SIGNAL FUNCTION DESCRIPTION DATA RDY OUTPUT Receiver data ready flag. A high level indicates data is available in the receive buffer. Flag goes low when the first 16-bit byte is read. D0 to D15 OUTPUT 16-bit parallel data bus (tri-state) GND POWER 0V READ INPUT Read strobe. A low level transfers receive buffer data to the data bus PARITY ENB INPUT Parity Enable - A high level activates odd parity checking which replaces the 32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged ERROR OUTPUT RINA/RINA-10 INPUT Positive direct ARINC serial data input (both RINA and RINA-10 on HI-8686) RINB/RINB-10 INPUT Negative direct ARINC serial data input (both RINB and RINB-10 on HI-8686) RESET INPUT Internal logic states are initialized with a low level TESTA INPUT Used in conjunction with the TESTB input to bypass the built-in analog line receiver circuitry TESTB INPUT Used in conjunction with the TESTA input to bypass the built-in analog line receiver circuitry GAPCLK INPUT Gap Clock. Determines the minimum time required between ARINC words for detection. The minimum word gap time is between 16 and 17 clock cycles of this signal. Vcc POWER Error Flag. A high level indicates a bit count error (number of ARINC bits was less than or greater than 32) and/or a parity error if parity detection was enabled (PARITY ENB high) +5V ±5% supply FUNCTIONAL DESCRIPTION The HI-8685 and HI-8686 are serial to 16-bit parallel converters. The incoming data stream is serially shifted into an input register, checked for errors, and then transferred in parallel to a 32-bit receive buffer. The receive data can be accessed using two 16-bit parallel read operations while the next serial data steam is being received. translation, the buffered inputs drive a differential amplifier. The differential signal is compared to levels derived from a divider between VCC and GND. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. A valid ARINC One/Zero input sets a latch and a Null input resets the latch. RECEIVER INPUTS HI-8685-10 ARINC INPUTS (RINA-10 & RINB-10) The block diagram for both the HI-8685 and HI-8685-10 products is found in Figure 1. Both have built-in receivers eliminating the need for additional external ARINC level detection circuitry. The only difference between the two products is the amount of internal resistance in series with each ARINC input. Since any added external series resistance will affect the voltage translation, the HI-8685-10 product has only 25KW of the 35KW series resistance required for proper ARINC 429 level detection. The remaining 10KW required is available to the user for incorporation in external circuitry such as for lightning protection. HI-8685 ARINC INPUTS (RINA & RINB) HI-8686 ARINC INPUTS Internal 35KW resistors are in series with both the RINA and RINB ARINC 429 inputs. They connect to level translators whose resistance to GND is typically 10KW. After level The HI-8686 has both sets of ARINC inputs, RINA/RINA-10 and RINB/RINB-10 available to the user. HOLT INTEGRATED CIRCUITS 2 HI-8685, HI-8686 PARITY ENB ERROR ERROR DETECT CLK PARITY DETECT 10KW 25KW RINA RINB 10KW 25KW ESD PROTECTION & LINE RECEIVER RXA CLOCK & DATA DETECT RXB BIT 32 BIT 32 DATA RINA-10 32-BIT SHIFT REG. BIT COUNT 32 32-BIT RECEIVE 32 BUFFER 32-BIT TO 16-BIT 16 MUX D0 - D15 RINB-10 TESTA TESTB BYTE COUNT GAP DETECT DATA RDY GAPCLK RESET READ Figure 1. Block Diagram FUNCTIONAL DESCRIPTION (cont.) PROTOCOL DETECTION GAP DETECTION The ARINC clock and One/Zero data that are derived from the digital outputs of the built-in line receiver is illustrated in Figure 3. The resulting steam of digital data is shifted into a 32-bit input register. The end of a data word is detected by an internal counter that times out when a data One or Zero is not received for a period equal to 16 cycles of the GAPCLK signal. The gap detection time may vary between 16 and 17 cycles of the GAPCLK signal since the incoming data and GAPCLK are not usually synchronous inputs. The required frequency of GAPCLK is a function of the mininum gap time specified for the type of ARINC data being received. Table 1 indicates typical frequencies that may be used for the various data rates normally encountered. The ARINC clock and One/Zero data can also be created from the TESTA and TESTB inputs as shown in Figure 4. When either test input is high, the built-in analog line driver is disabled. For ARINC 561 operation, the TESTA and TESTB digital input data streams must be derived from the ARINC 561 data, clock and sync with external logic. DATABUS TYPE BIT PERIOD (µs) MINIMUM GAP (µs) GAP CLOCK MHz GAP DETECTION TIME (µs) 429 10 45 0.75 1.0 1.5 21.3 - 22.7 16 - 17 10.7 - 11.3 429 69 - 133 310 - 599 0.1 160 - 170 575 69 - 133 310 - 599 0.1 160 - 170 561 69 - 133 103 - 200 0.2 80 - 85 Table 1 - Typical Gap Detection Times HOLT INTEGRATED CIRCUITS 3 HI-8685, HI-8686 FUNCTIONAL DESCRIPTION (cont.) ERROR CHECKING Once a word gap is detected, the data word in the input register is transferred to the receive buffer and checked for errors. When parity detection is enabled (PARITY ENB high), the received word is checked for odd parity. If there is a parity error, the 32nd bit of the received data word is set high. If parity checking is disabled (PARITY ENB low) the 32nd bit of the data word is always the 32nd ARINC bit received. The ERROR flag output is set high upon receipt of a word gap and the number of bits received since the previous word gap is less than or greater than 32. The ERROR flag is reset low when the next valid ARINC word is written into the receive buffer or when RESET is pulsed low. READING RECEIVE BUFFER When the data word is transferred to the receive buffer, the DATA RDY pin goes high. The data word can then be read in two 16-bit bytes by pulsing the READ input low as indicated in Figure 5. The first read cycle resets DATARDY low and increments an internal counter to the second 16-bit byte. The relationship between each bit of an ARINC word received and each bit of the two 16-bit data bus bytes is specified in Figure 2. When a new ARINC word is received it always overwrites the receive buffer. If the first byte of the previous word has not been read, then previous data is lost and the receive buffer will contain the new ARINC word. However, if the DATARDY pin goes high between the reading of the first and second bytes, the first byte is no longer valid because the corresponding second byte has been overwritten by the new ARINC word. Also, the next read will be of the first byte of the new ARINC word since the internal byte counter is always reset to the first byte when new data is transferred to the receive buffer. Read Byte Data Bus Bits ARINC Bits 1st Byte 1 D0 - D15 ARINC 1 - ARINC 16 2nd Byte 2 D0 - D15 ARINC 17 - ARINC 32 FIGURE 2. ORDER OF RECEIVED DATA RESET A low on the RESET input sets a flip-flop which initializes the internal logic. When RESET goes high, the internal logic remains in the initialized state until the first word gap is detected preventing reception of a partial word. TEST MODE The built-in differential line receiver can be disabled allowing the data and clock detection circuitry to be driven directly with digital signals. The logical OR function of the TESTA and TESTB is defined in Truth Table 1. The two inputs can be used for testing the receiver logic and for inputting ARINC 429 type data derived from another source / protocol. See Figure 4 for typical test input timing. The device should always be initialized with RESET immediately after entering the test mode to clear a partial word that may have been received since the last word gap. Otherwise, an ERROR condition may occur and the first 32 bits of data on the test inputs may not be properly received. Also, when entering the test mode, both TESTA and TESTB should be set high and held in that state for at least one word gap period (17 gap clocks) after RESET goes high. When exiting the test mode, both test inputs should be held low and the device initialized with RESET. TRUTH TABLE 1. RINA (-10) RINB (-10) TESTA TESTB RXA RXB -1.50V to +1.50V -1.50V to +1.50V 0 0 0 0 -3.25V to -6.50V +3.25V to +6.50V 0 0 0 1 +3.25V to +6.50V -3.25V to -6.50V 0 0 1 0 X X 0 1 0 1 X X 1 0 1 0 X X 1 1 0 0 X = don't care HOLT INTEGRATED CIRCUITS 4 HI-8685, HI-8686 TIMING DIAGRAMS ARINC Data Bits 29 30 31 28 Word Gap 4 Bit Periods Min. 32 1 2 +10V VDIFF RINA - RINB 0V -10V DERIVED DATA DERIVED CLOCK FIGURE 3 - RECEIVER INPUT TIMING FOR ARINC 429 ARINC Data Bits 29 30 31 28 Word Gap 4 Bit Periods Min. 32 1 2 +5V TESTA 0V +5V TESTB 0V DERIVED DATA DERIVED CLOCK FIGURE 4 - TEST INPUT TIMING FOR ARINC 429 DERIVED DATA 32nd ARINC bit tDRDY tRDYCLR DATA RDY tRDPW 1st 16-bits READ tRD D0 - D15 tRR 2nd 16-bits tFD VALID VALID FIGURE 5 - RECEIVER PARALLEL DATABUS TIMING HOLT INTEGRATED CIRCUITS 5 HI-8685, HI-8686 RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND Supply voltages VCC ....................................................... +7.0V Supply Voltages VCC ...................................................+5V ± 5% Voltage on inputs RINA (-10) to RINB (-10) ......... +29V to - 29V All other input pins..................-0.3 to Vcc +0.3 Temperature Range Industrial ................................ -40°C to +85°C Hi-Temp ............................... -55°C to +125°C DC current per input pin ....................... +10mA Junction Temperature, Tj ................... £+175°C Power dissipation at 25°C plastic 28-pin SO..... 1.8W, derate 14.1mW/°C plastic 28-pin PLCC .2.3W, derate 18.2mW/°C plastic 32-pin SO......1.6W, derate 15.4mW/°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. Solder Temperature Leads ............................. +280°C for 10 sec Package body ..................................+220°C Storage Temperature ............. -65°C to +150°C DC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 10.0 13.0 2.75 5.0 ARINC Bus Inputs (RINA, RINB, RINA-10 & RINB-10) Differential input voltage one or zero null common mode VDIN VNIN VCOM differential voltage " " " " with respect to GND 6.5 - Input resistance RINA (-10) to RINB(-10) RINA (-10) or RINB(-10) to GND or VCC RDIFF RSUP supplies floating " " " ' 30 19 75 40 - Kohm Kohm Input capacitance (Guaranteed but not tested) differential to GND to VCC CDIFF CG CH RINA (-10) to RINB (-10) - - 20 20 20 pF pF pF 2.0 0.0 - VCC 0.8 volts volts -1.0 - 1.0 - µA µA - - 8.0 pF volts volts volts Digital Inputs (RESET, GAPCLK, READ & PARITY ENB) Input voltage high low VIH VIL Input current source sink IIH IIL Input capacitance CI VIN = 5.0V VIN = 0.0V HOLT INTEGRATED CIRCUITS 6 HI-8685, HI-8686 DC ELECTRICAL CHARACTERISTICS (cont.) Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 2.4 0.0 - VCC 0.8 volts volts -1.0 110 - - µA µA - - 8.0 pF IOH = -1.0 mA IOL = 1.6 mA 2.7 - - 0.4 volts volts VOH = 5.0V VOL = 0.0V -1.0 - 1.0 - µA µA - - 15 pF - - 6.5 mA MIN TYP Digital Inputs (TESTA & TESTB) Input voltage high low VIH VIL Input current source sink IIH IIL Input capacitance CI VIN = 5.0V VIN = 0.0V Outputs (D0 to D15, ERROR & DATA RDY) Output voltage high low VOH VOL Output tri-state current (D0 - D15 only) IIH IIL Output capacitance CO Operating Supply Current VCC ICC VIN = 0.0V, outputs open AC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS READ pulse width SYMBOL TEST CONDITIONS tRDPW MAX UNITS 50 ns Data delay from READ tRD 40 ns READ to data floating tFD 20 ns tRDYCLR 35 ns READ to DATA RDY clear READ pulse to next READ pulse tRR GAPCLK frequency fGC 32nd ARINC bit to DATA RDY tDRDY HOLT INTEGRATED CIRCUITS 7 25 ns 1 16 MHz 17 clocks HI-8685, HI-8686 ADDITIONAL HI-8685 PIN CONFIGURATION 9 D7 10 D6 11 DATA RDY VCC GAPCLK TESTA D14 D15 26 HI-8685PJI HI-8685PJT & HI-8685PJI-10 HI-8685PJT-10 12 13 14 15 16 17 25 TESTB 24 RESET 23 RINB (RINB-10) 22 RINA (RINA-10) 21 ERROR 20 PARITY ENB 19 READ 18 D0 D8 27 D2 8 28 D1 7 D9 1 D3 D10 2 D4 6 3 GND 5 D11 4 D5 D12 D13 (See page 1 for additional pin configurations) HI-8685 28-Pin Plastic PLCC ORDERING INFORMATION HI - 8685xx x x - xx PART NUMBER INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY No dash number 35 Kohm 0 -10 25 Kohm 10 Kohm PART NUMBER Blank F PART NUMBER LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No T -55°C TO +125°C T No PART NUMBER PACKAGE DESCRIPTION BUILT-IN LINE RECV’R 8685PJ 28 PIN PLASTIC PLCC (28J) Yes 8685PS 28 PIN PLASTIC WIDE SOIC (28HW) Yes For HI-8686PQ please see next page HOLT INTEGRATED CIRCUITS 8 HI-8685, HI-8686 ORDERING INFORMATION HI - 8686PQ x x LEAD FINISH PART NUMBER Tin / Lead (Sn / Pb) Solder Blank 100% Matte Tin (Pb-free, RoHS compliant) F PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No T -55°C TO +125°C T No PART NUMBER PACKAGE DESCRIPTION 8686PQ 32 PIN PLASTIC PQFP (32PQS) (1) RINA / RINB and RINA-10 / RINB-10 are both available For HI-8685 please see previous page HOLT INTEGRATED CIRCUITS 9 BUILT-IN LINE RECV’R Yes EXT. 10KW REQUIRED Optional (1) HI-8685, HI-8686 REVISION HISTORY Revision Date Description of Change DS8685, Rev. N 12/15/08 Replaced 18-pin SOIC Package Dimension drawing with correct 28-pin drawing, corrected dimensions for PQFP package to reflect current package vendor, and clarified temperature ranges. HOLT INTEGRATED CIRCUITS 10 HI-8685, HI-8686 PACKAGE DIMENSIONS 28-PIN PLASTIC PLCC inches (millimeters) Package Type: 28J PIN NO. 1 PIN NO. 1 IDENT .045 x 45° .050 (1.27) BSC .045 x 45° .453 ± .003 (11.506 ±.076) SQ. .490 ± .005 (12.446 ±.127) SQ. .031 ±.005 (.787 ±.127) .017 ±.004 (.432 ±.102) See Detail A .010 ± .001 (.254 ± .03) .173 ±.008 (4.394 ±.203) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .020 (.508) min .410 ±.020 (10.414 ±.508) DETAIL A R 28-PIN PLASTIC SMALL OUTLINE (SOIC) - WB (Wide Body) .035 .889 inches (millimeters) Package Type: 28HW .706 ± .004 (17.92 ± .11) .0105 ± .0015 (.2667 ± .0381) .294 ± .002 (7.486 ± .05) .407 ± .013 (10.325 ± .32) See Detail A .018 typ (.457) .095 ± .005 (2.413 ± .127) .050 BSC (1.27) 0° to 8° .0075 ± .0035 (.191 ± .089) .033 ± .017 (.838 ± .432) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Detail A HOLT INTEGRATED CIRCUITS 11 HI-8685, HI-8686 PACKAGE DIMENSIONS 32 PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: 32PQS .006 ± .002 (0.152 ± .06) .354 BSC SQ (9.00) .0315 BSC (0.80) .276 BSC SQ (7.00) .015 ± .003 (0.375 ± .075) .024 ± .006 (0.60 ± .15) .039 ± .002 (1.0 ± .05) .006 R ref (0.15) See Detail A 0° £ Q £ 7° .047 max (1.20) .004 ± .002 (0.10 ± .05) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 12 .004 R ref (.10) Detail A