Dallas DS1689S 3-volt/5-volt serialized real-time clock with nv ram control Datasheet

DS1689/DS1693
3-Volt/5-Volt Serialized Real-Time Clock
with NV RAM Control
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
Incorporates industry standard DS1287 PC clock
plus enhanced features:
§ +3- or +5V operation
§ 64-bit silicon serial number
§ 64-bit customer specific ROM or additional
serial number available
§ Power control circuitry supports system
power-on from date/time alarm or key closure
§ Automatic battery backup and write
protection to external SRAM
§ Crystal select bit allows RTC to operate with
6 pF or 12.5 pF crystal
§ 114 bytes user NV RAM
§ Auxiliary battery input
§ RAM clear input
§ Century register
§ 32 kHz output for power management
§ 32-bit VCC powered elapsed time counter
§ 32-bit VBAT powered elapsed time counter
§ 16-bit power cycle counter
§ Compatible with existing BIOS for original
DS1287 functions
§ Available as IC (DS1689) or standalone
module with embedded battery and crystal
(DS1693)
§ IC is available in industrial temperature
version
§ Timekeeping algorithm includes leap year
compensation valid up to 2100
ORDERING INFORMATION
PART #
DS1689S
DS1689SN
DS1693
DESCRIPTION
RTC IC, 28-pin SOIC
RTC IC, 28-pin SOIC IND
RTC Module; 28-pin DIP
VBAUX
NC
NC
RCLR
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PWR
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CEI
CEO
VCCI
VCCO
SQW
NC
IRQ
PSEL
RD
NC
WR
ALE
CS
KS
VBAUX
X1
X2
RCLR
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PWR
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CEI
CEO
VCCI
VCCO
SQW
VBAT
IRQ
PSEL
RD
GND
WR
ALE
CS
KS
DS1693 28-Pin Encapsulated Package DS1689S 28-Pin SOIC
(740-mil)
(330-mil)
PIN DESCRIPTION
X1
X2
RCLR
AD0-AD7
PWR
KS
CS
ALE
WR
RD
VCCO
IRQ
SQW
VCCI
GND
VBAT
VBAUX
PSEL
CEI
CEO
1 of 32
- Crystal Input
- Crystal Output
- RAM Clear Input
- Mux’ed Address/Data Bus
- Power-on Interrupt Output
(Open drain)
- Kickstart Input
- RTC Chip Select Input
- RTC Address Strobe
- RTC Write Data Strobe
- RTC Read Data Strobe
- RAM Power Supply Output
- Interrupt Request Output
(Open drain)
- Square Wave Output
- +3- or +5V Main Supply
- Ground
- Battery + Supply
- Auxiliary Battery Supply
- +3- or +5V Power Select
- RAM Chip Enable In
- RAM Chip Enable Out
092800
DS1689/DS1693
DESCRIPTION
The DS1689/DS1693 is a real time clock (RTC) designed as a successor to the industry standard DS1285,
DS1385, DS1485, and DS1585 PC real time clocks. This device provides the industry standard DS1285
clock function with the new feature of either +3.0- or +5.0 volt operation and automatic backup and write
protection to an external SRAM. The DS1689 also incorporates a number of enhanced features including
a silicon serial number, power-on/off control circuitry, and 114 bytes of user NVSRAM, power-on
elapsed timer, and power cycle counter.
Each DS1689/DS1693 is individually manufactured with a unique 64-bit serial number as well as an
additional 64-bit customer specific ROM or serial number. The serial number is programmed and tested
at Dallas to insure that no two devices are alike. The serial number can be used to electronically identify a
system for purposes such as establishment of a network node address or for maintenance tracking. Blocks
of available numbers from Dallas Semiconductor can be reserved by the customer.
The serialized RTCs also incorporate power control circuitry, which allows the system to be powered on
via an external stimulus, such as a keyboard or by a time and date (wake-up) alarm. The PWR output pin
can be triggered by one or either of these events, and can be used to turn on an external power supply.
The PWR pin is under software control, so that when a task is complete, the system power can then be
shut down.
The DS1689/DS1693 incorporates a power-on elapsed time counter, a power-on cycle counter, and a
battery powered continuous counter. These three counters provide valuable information for maintenance
and warranty requirements.
Automatic backup and write protection for an external SRAM is provided through the VCCO and CEO
pins. The lithium energy source used to permanently power the real time clock is also used to retain RAM
data in the absence of VCC power through the VCCO pin. The chip enable output to RAM ( CEO ) is
controlled during power transients to prevent data corruption.
The DS1689 is a clock/calendar chip with the features described above. An external crystal and battery
are the only components required to maintain time-of-day and memory status in the absence of power.
The DS1693 incorporates the DS1689 chip, a 32.768 kHz crystal, and a lithium battery in a complete,
self-contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a
minimum of 10 years of timekeeping and data retention in the absence of VCC is guaranteed.
OPERATION
The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS1689/DS1693. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, VCCI - DC power is provided to the device on these pins. VCCI is the +3-volt or +5-volt input.
Five-volt operation is selected when the PSEL pin is at a logic 1. If PSEL is floated or at a logic 0, the
device will be in auto-sense mode and will determine the correct operating voltage based on the VCCI
voltage level.
PSEL (Power Select Input) - This pin selects whether 3-volt operation or 5-volt operation will be used.
When PSEL is a logic 1, 5-volt operation is selected. When PSEL is a logic 0 or is floated, the device will
be in auto-sense mode and will determine the correct mode of operation based on the voltage on VCCI.
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DS1689/DS1693
VCCO (External SRAM Power Supply Output) - This pin will be internally connected to VCCI when
VCCI is within nominal limits. However, during power fail, VCCO will be internally connected to the VBAT
or VBAUX (whichever is larger). For 5-volt operation, switch over from VCCI to the backup supply occurs
when VCCI drops below the larger of VBAT and VBAUX. For 3-volt operation, switch over from VCCI to the
backup supply occurs at VPF if VPF is less than VBAT and VBAUX. If VPF is greater than VBAT and VBAUX,
the switch from VCCI to the backup supply occurs when VCCI drops below the larger of VBAT and VBAUX.
DS1689/DS1693 BLOCK DIAGRAM Figure 1
SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15
internal divider stages of the real time clock. The frequency of the SQW pin can be changed by
programming Register A as shown in Table 2. The SQW signal can be turned on and off using the SQWE
bit in Register B. A 32 kHz SQW signal is output when SQWE=1, the Enable 32 kHz (E32K) bit in
extended register 04BH is a logic 1, and VCC is above VPF. A 32 kHz square wave is also available when
VCC is less than VPF if E32K=1, ABE=1, and voltage is applied to VBAUX.
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DS1689/DS1693
AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because
address information and data information time-share the same signal paths. The addresses are present
during the first portion of the bus cycle and the same pins and signal paths are used for data in the second
portion of the cycle. Address/data multiplexing does not slow the access time of the DS1689 since the bus
change from address to data occurs during the internal RAM access time. Addresses must be valid prior
to the latter portion of ALE, at which time the DS1689/DS1693 latches the address. Valid write data must
be present and held stable during the latter portion of the WR pulse. In a read cycle the DS1689/DS1693
outputs 8 bits of data during the latter portion of the RD pulse. The read cycle is terminated and the bus
returns to a high impedance state as RD transitions high. The address/data bus also serves as a bidirectional data path for the external extended RAM.
ALE (RTC Address Strobe Input; active high) - A pulse on the address strobe pin serves to
demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the
DS1689/DS1693.
(RTC Read Input; active low) - RD identifies the time period when the DS1689/DS1693 drives the
bus with RTC read data. The RD signal is an enable signal for the output buffers of the clock.
RD
WR (RTC Write Input; active low) - The WR signal is an active low signal. The WR signal defines
the time period during which data is written to the addressed register.
CS (RTC Chip Select Input; active low) - The Chip Select signal must be asserted low during a bus
cycle for the RTC portion of the DS1689/DS1693 to be accessed. CS must be kept in the active state
during RD and WR timing. Bus cycles, which take place with ALE asserted but without asserting, CS
will latch addresses. However, no data transfer will occur.
(Interrupt Request Output; open drain, active low) - The IRQ pin is an active low output of the
DS1689/DS1693 that can be tied to the interrupt input of a processor. The IRQ output remains low as
long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To
clear the IRQ pin, the application software must clear all enabled flag bits contributing to IRQ ’s active
state.
IRQ
When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple
interrupting devices can be connected to an IRQ bus. The IRQ pin is an open drain output and requires an
external pull-up resistor.
CEI
(RAM Chip Enable Input; active low) - CEI should be driven low to enable the external RAM.
(RAM Chip Enable Output; active low) - When power is valid, CEO will equal CEI . When
power is not valid, CEO will be driven high regardless of CEI .
CEO
(Power-on Output; open drain, active low) - The PWR pin is intended for use as an on/off
control for the system power. With VCC voltage removed from the DS1689/DS1693, PWR may be
automatically activated from a Kickstart input via the KS pin or from a Wake-up interrupt. Once the
system is powered on, the state of PWR can be controlled via bits in the Dallas registers.
PWR
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DS1689/DS1693
(Kickstart Input; active low) - When VCC is removed from the DS1689/DS1693, the system can be
powered on in response to an active low transition on the KS pin, as might be generated from a key
closure. VBAUX must be present and Auxiliary Battery Enable bit (ABE) must be set to 1 if the kickstart
function is used, and the KS pin must be pulled up to the VBAUX supply. While VCC is applied, the KS pin
can be used as an interrupt input.
KS
(RAM Clear Input; active low) - If enabled by software, taking RCLR low will result in the
clearing of the 114 bytes of user RAM. When enabled, RCLR can be activated whether or not VCC is
present.
RCLR
VBAUX - Auxiliary battery input required for kickstart and wake-up features. This input also supports
clock/calendar and External NVRAM if VBAT is at lower voltage or is not present. A standard +3-volt
lithium cell or other energy source can be used. Battery voltage must be held between +2.5 and +3.7 volts
for proper operation. If VBAUX is not going to be used it should be grounded and auxiliary battery enable
bit bank 1, register 4BH, should=0.
DS1689 ONLY
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. For greatest accuracy, the DS1689 must
be used with a crystal that has a specified load capacitance of either 6 pF or 12.5 pF. The Crystal Select
(CS) bit in Extended Control Register 4B is used to select operation with a 6 pF or 12.5 pF crystal. The
crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors.
Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal by guardringed with ground and that high frequency signals be kept away from the crystal area.
For more information on crystal selection and crystal layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real Time Clocks.” The DS1689 can also be driven by an
external 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator
signal and the X2 pin is floated.
VBAT - Battery input for any standard 3-Volt lithium cell or other energy source. Battery voltage must be
held between 2.5 and 3.7 volts for proper operation.
POWER-DOWN/POWER-UP CONSIDERATIONS
The real-time clock function will continue to operate and all of the RAM, time, calendar, and alarm
memory locations remain nonvolatile regardless of the level of the VCCI input. When VCCI is applied to
the DS1689/DS1693 and reaches a level of greater than VPF (power fail trip point), the device becomes
accessible after tREC, provided that the oscillator is running and the oscillator countdown chain is not in
reset (see Register A). This time period allows the system to stabilize after power is applied.
When PSEL is floating or logic 0, the DS1689 is in autosense mode and 3-volt or 5-volt operation is
determined based on the voltage on VCCI. Selection of 5-volt operation is automatically invoked when
VCCI rises above 4.5 volts for a minimum of tREC. However, 3-volt operation is automatically selected if
VCCI does not rise above the level of 4.25 volts. Selection of the power supply input levels requires
150 ms of input stability before operation can commence.
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DS1689/DS1693
When 5-volt operation is selected, the device is fully accessible and data can be written and read only
when VCCI is greater than 4.5 volts. When VCCI is below 4.5 volts, read and writes are inhibited. However,
the timekeeping function continues unaffected by the lower input voltage. As VCC falls below the greater
of VBAT and VBAUX, the RAM and timekeeper are switched over to a lithium battery connected either to
the VBAT pin or VBAUX pin.
When 3-volt operation is selected and applied within normal limits, the device is fully accessible and data
can be written or read. When VCCI falls below VPF, access to the device is inhibited. If VPF is less than
VBAT and VBAUX, the power supply is switched from VCCI to the backup supply (the greater of VBAT and
VBAUX) when VCCI drops below VPF. If VPF is greater than VBAT and VBAUX, the power supply is switched
from VCCI to the backup supply when VCCI drops below the larger of VBAT and VBAUX.
When VCC falls below VPF, the chip is write-protected. With the possible exception of the KS , PWR , and
SQW pins, all inputs are ignored and all outputs are in a high impedance state.
RTC ADDRESS MAP
The address map for the RTC registers of the DS1689/DS1693 is shown in Figure 2. The address map
consists of the 14-clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and
four bytes are used for control and status. All registers can be directly written or read except for the
following:
1. Registers C and D are read-only.
2. Bit 7 of Register A is read-only.
3. The high order bit of the seconds byte is read-only.
DS1689 REAL TIME CLOCK ADDRESS MAP Figure 2
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DS1689/DS1693
TIME, CALENDAR AND ALARM LOCATIONS
The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1.
The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents
of the time, calendar, and alarm registers can be either Binary or Binary-Coded Decimal (BCD) format.
Table 1 shows the binary and BCD formats of the twelve time, calendar, and alarm locations that reside in
both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and bank 1
switching will be explained later in this text).
Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written
to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data
format (binary or BCD) should be set via the data mode bit (DM) of Register B. All time, calendar, and
alarm registers must use the same data mode. The set bit in Register B should be cleared after the data
mode bit has been written to allow the real-time clock to update the time and calendar bytes.
Once initialized, the real-time clock makes all updates in the selected mode. The data mode cannot be
changed without reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializing
the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents
PM when it is a logic 1. The time, calendar, and alarm bytes are always accessible because they are
double-buffered. Once per second the 10 bytes are advanced by one second and checked for an alarm
condition. If a read of the time and calendar data occurs during an update, a problem exists where
seconds, minutes, hours, etc. may not correlate. The probability of reading incorrect time and calendar
data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later
in this text.
The 4 alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours,
minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the
alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of the 4
alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The 2 most significant bits
of each byte set the “don’t care” condition when at logic 1. An alarm will be generated each hour when
the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with “don’t
care” codes in the hours and minute alarm bytes. The “don’t care” codes in all 3-alarm bytes create an
interrupt every second. The 3 alarm bytes may be used in conjunction with the date alarm as described in
the Wakeup/Kickstart section. The century counter will be discussed later in this text.
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DS1689/DS1693
TIME, CALENDAR AND ALARM DATA MODES Table 1
ADDRESS
LOCATION
FUNCTION
00H
01H
02H
03H
04H
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours 12-hr Mode
Hours 24-hr Mode
05H
Hours Alarm 12-hr
Mode
Hours Alarm 24-hr
Mode
06H
Day of Week
Sunday=1
07H
Date of Month
08H
Month
09H
Year
BANK1, 48H Century
BANK 1, 49H Date Alarm
DECIMAL
RANGE
0-59
0-59
0-59
0-59
1-12
0-23
1-12
RANGE
BINARY DATA
BCD DATA
MODE
MODE
00-3B
00-59
00-3B
00-59
00-3B
00-59
00-3B
00-59
01-0C AM, 81-8C PM 01-12 AM, 81-92 PM
00-17
00-23
01-0C AM, 81-8C PM 01-12 AM, 81-92 PM
0-23
00-17
00-23
1-7
01-07
01-07
1-31
1-12
0-99
0-99
1-31
01-1F
01-0C
00-63
00-63
01-1F
01-31
01-12
00-99
00-99
01-31
CONTROL REGISTERS
The four control registers; A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible
at all times, even during the update cycle.
NONVOLATILE RAM - RTC
The 114 general-purpose nonvolatile RAM bytes are not dedicated to any special function within the
DS1689/DS1693. They can be used by the application program as nonvolatile memory and are fully
available during the update cycle. This memory is directly accessible when bank 0 is selected.
INTERRUPT CONTROL
The DS1689/DS1693 includes six separate, fully automatic sources of interrupt for a processor:
1.
2.
3.
4.
5.
6.
Alarm interrupt
Periodic interrupt
Update-ended interrupt
Wake-up interrupt
Kickstart interrupt
RAM clear interrupt
The conditions, which generate each of these independent interrupt conditions, are described in greater
detail elsewhere in this data sheet. This section describes the overall control of the interrupts.
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DS1689/DS1693
The application software can select which interrupts, if any are to be used. There are a total of 6 bits
including 3 bits in Register B and 3 bits in Extended Register B which enable the interrupts. The extended
register locations are described later. Writing a logic 1 to an interrupt enable bit permits that interrupt to
be initiated when the event occurs. A logic 0 in the interrupt enable bit prohibits the IRQ . pin from being
asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ
will immediately be set at an active level, even though the event initiating the interrupt condition may
have occurred much earlier. As a result, there are cases where the software should clear these earlier
generated interrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended
Register A. These flag bits are set regardless of the setting of the corresponding enable bit located either
in Register B or in Extended Register B. The flag bits can be used in a polling mode without enabling the
corresponding enable bits.
However, care should be taken when using the flag bits of Register C as they are automatically cleared to
0 immediately after they are read. Double latching is implemented on these bits so that bits which are set
remain stable throughout the read cycle. All bits which were set are cleared when read and new interrupts
which are pending during the read cycle are held until after the cycle is completed. One, 2, or 3 bits can
be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no
interrupts are lost.
The flag bits in Extended Register A are not automatically cleared following a read. Instead, each flag bit
can be cleared to 0 only by writing 0 to that bit.
When using the flag bits with fully enabled interrupts, the IRQ line will be driven low when an interrupt
flag bit is set and its corresponding enable bit is also set. IRQ will be held low as long as at least one of
the six possible interrupt sources has it s flag and enable bits both set. The IRQF bit in Register C is a 1
whenever the IRQ pin is being driven low as a result of one of the six possible active sources. Therefore,
determination that the DS1689/DS1693 initiated an interrupt is accomplished by reading Register C and
finding IRQF=1. IRQF will remain set until all enabled interrupt flag bits are cleared to 0.
SQUARE WAVE OUTPUT SELECTION
The SQW pin can be programmed to output a variety of frequencies divided down from the 32.768 kHz
crystal tied to X1 and X2. The square wave output is enabled and disabled via the SQWE bit in Register
B. If the square wave is enabled (SQWE=1), then the output frequency will be determined by the settings
of the E32K bit in Extended Register B and by the RS3-0 bits in Register A. If the E32K = 1, then a
32.768 kHz square wave will be output on the SQW pin regardless of the settings of RS3-0.
If E32K = 0, then the square wave output frequency is determined by the RS3-0 bits. These bits control a
1-of-15 decoder, which selects one of 13 taps that divide the 32.768 kHz frequency. The RS3-0 bits
establish the SQW output frequency as shown in Table 2. In addition, RS3-0 bits control the periodic
interrupt selection as described below.
If SQWE1, E32K=1, and the Auxiliary Battery Enable bit (ABE, bank 1; register 04BH) is enabled, and
voltage is applied to VBAUX then the 32 kHz square wave output signal will be output on the SQW pin in
the absence of VCC. This facility is provided to clock external power management circuitry. If any of the
above requirements are not met, no square wave output signal will be generated on the SQW pin in the
absence of VCC.
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DS1689/DS1693
A pattern of 01X in the DV2, DV1, and DV0, bits respectively, will turn the oscillator on and enable the
countdown chain. Note that this is different than the DS1287, which required a pattern of 010 in these
bits. DV0 is now a “don’t care” because it is used for selection between register banks 0 and 1. A pattern
of 11X will turn the oscillator on, but the oscillator’s countdown chain will be held in reset, as it was in
the DS1287. Any other bit combination for DV2 and DV1 will keep the oscillator off.
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms to once
every 122 ms. This function is separate from the alarm interrupt which can be output from once per
second to once per day. The periodic interrupt rate is selected using the same RS3-0 bits in Register A
which select the square wave frequency (see Table 2). Changing the bits affects both the square wave
frequency and the periodic interrupt output. However, each function has a separate enable bit in Register
B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE
bit in Register B. The periodic interrupt can be used with software counters to measure inputs, create
output intervals, or await the next needed software function.
UPDATE CYCLE
The Serialized RTC executes an update cycle once per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, alarm and
elapsed time byte is frozen and will not update as the time increments. However, the time countdown
chain continues to update the internal copy of the buffer. This feature allows the time to maintain
accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees that
time and calendar information is consistent. The update cycle also compares each alarm byte with the
corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three
positions.
There are three methods that can handle access of the real-time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If
enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs
244 ms later. If a low is read on the UIP bit, the user has at least 244 ms before the time/calendar data will
be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed
to read valid time/calendar data to exceed 244 ms.
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DS1689/DS1693
PERIODIC INTERRUPT RATE AND
SQUARE WAVE OUTPUT FREQUENCY Table 2
EXT. REG. B
SELECT BITS REGISTER A
tPI PERIODIC
INTERRUPT RATE
E32K
RS3
RS2
RS1
RS0
0
0
0
0
0
None
0
0
0
0
1
3.90625 ms
0
0
0
1
0
7.8125 ms
0
0
0
1
1
122.070 ms
0
0
1
0
0
244.141 ms
0
0
1
0
1
488.281 ms
0
0
1
1
0
976.5625 ms
0
0
1
1
1
1.953125 ms
0
1
0
0
0
3.90625 ms
0
1
0
0
1
7.8125 ms
0
1
0
1
0
15.625 ms
0
1
0
1
1
31.25 ms
0
1
1
0
0
62.5 ms
0
1
1
0
1
125 ms
0
1
1
1
0
250 ms
0
1
1
1
1
500 ms
1
X
X
X
X
*
*RS3-RS0 determine periodic interrupt rates as listed for E32K=0.
SQW OUTPUT
FREQUENCY
None
256 Hz
128 Hz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
32.768 kHz
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interrupts
that occur at a rate of greater than tBUC allow valid time and date information to be reached at each
occurrence of the periodic interrupt. The reads should be complete within (tPI / 2+tBUC) to ensure that data
is not read during the update cycle.
UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3
11 of 32
DS1689/DS1693
REGISTER A
MSB
BIT 7
UIP
BIT 6
DV2
BIT 5
DV1
BIT 4
DV0
BIT 3
RS3
BIT 2
RS2
BIT 1
RS1
LSB
BIT 0
RS0
UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the
update transfer will soon occur. When UIP is a 0, the update transfer will not occur for at least 244 ms.
The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The
UIP bit is read-only. Writing the SET bit in Register B to a one inhibits any update transfer and clears the
UIP status bit.
DV0, DV1, DV2 - These bits are defined as follows:
DV2
=
Countdown Chain
1 - resets countdown chain only if DV1=1
0 - countdown chain enabled
DV1
=
Oscillator Enable
0 - oscillator off
1 - oscillator on
DV0
=
Bank Select
0 - original bank
1 - extended registers
A pattern of 01X is the only combination of bits that will turn the oscillator on and allow the RTC to keep
time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update
will occur at 500 ms after a pattern of 01X is written to DV2, DV1, and DV0.
RS3, RS2, RS1, RS0 - These four rate-selection bits select one of the 13 taps on the 15-stage divider or
disable the divider output. The tap selected can be used to generate an output square wave (SQW pin)
and/or a periodic interrupt. The user can do one of the following:
Enable the interrupt with the PIE bit;
Enable the SQW output pin with the SQWE bit;
Enable both at the same time and the same rate; or
Enable neither.
Table 2 lists the periodic interrupt rates and the square wave frequencies that can be chosen with the RS
bits.
12 of 32
DS1689/DS1693
REGISTER B
MSB
BIT 7
SET
BIT 6
PIE
BIT 5
AIE
BIT 4
UIE
BIT 3
SQWE
BIT 2
DM
BIT 1
24/12
LSB
BIT 0
DSE
SET - When the SET bit is a 0, the update transfer functions normally by advancing the counts once per
second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize
the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be
executed in a similar manner. SET is a read/write bit that is not modified by internal functions of the
DS1689/DS1693.
PIE - The Periodic Interrupt Enable bit is a read/write bit which allows the Periodic Interrupt Flag (PF)
bit in Register C to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are generated
by driving the IRQ pin low at a rate specified by the RS3-RS0 bits of Register A. A 0 in the PIE bit
blocks the IRQ output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is still set
at the periodic rate. PIE is not modified by any internal DS1689/DS1693 functions.
AIE - The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to a 1, permits the Alarm
Flag (AF) bit in register C to assert IRQ . An alarm interrupt occurs for each second that the 3 time bytes
equal the 3 alarm bytes including a don’t care alarm code of binary 11XXXXXX. When the AIE bit is set
to 0, the AF bit does not initiate the IRQ signal. The internal functions of the DS1689/DS1693 do not
affect the AIE bit.
UIE - The Update Ended Interrupt Enable (UIE) bit is a read/write that enables the Update End Flag (UF)
bit in Register C to assert IRQ . The SET bit going high clears the UIE bit.
SQWE - When the Square Wave Enable (SQWE) bit is set to a 1, a square wave signal at the frequency
set by the rate-selection bits RS3 through RS0 and the E32K bit is driven out on the SQW pin. When the
SQWE bit is set to 0, the SQW pin is held low. SQWE is a read/write bit.
DM - The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD
format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is
not modified by internal functions. A 1 in DM signifies binary data while a 0 in DM specifies Binary
Coded Decimal (BCD) data.
24/12 - The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and
a 0 indicates the 12-hour mode. This bit is read/write.
DSE - The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when
DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 am to 3:00:00 AM. On the
last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These special
updates do not occur when the DSE bit is a 0. This bit is not affected by internal functions.
13 of 32
DS1689/DS1693
REGISTER C
MSB
BIT 7
IRQF
BIT 6
PF
BIT 5
AF
BIT 4
UF
BIT 3
0
BIT 2
0
BIT 1
0
LSB
BIT 0
0
IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
WF = WIE = 1
KF = KSE = 1
RF = RIE = 1
i.e., IRQF = (PF · PIE) + (AF · AIE) + (UF · UIE) + (WF · WIE) + (KF · KSE) + (RF · RIE)
Any time the IRQF bit is a one, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after
Register C is read by the program.
PF - The Periodic Interrupt Flag (PF) is a read-only bit which is set to a 1 when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1
independent of the state of the PIE bit. When both PF and PIE are 1s, the IRQ signal is active and will set
the IRQF bit. The PF bit is cleared by a software read of Register C.
AF - A one in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm
time. If the AIE bit is also a 1, the IRQ pin will go low and a one will appear in the IRQF bit. A read of
Register C will clear AF.
UF - The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to
1, the one in UF causes the IRQF bit to be a 1, which will assert the IRQ pin. UF is cleared by reading
Register C.
BIT 0 THROUGH BIT 3 - These are unused bits of the status Register C. These bits always read 0 and
cannot be written.
REGISTER D
MSB
BIT 7
VRT
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
LSB
BIT 0
0
VRT - The Valid RAM and Time (VRT) bit indicates the condition of the battery connected to the VBAT
pin or the battery connected to VBAUX, whichever is at a higher voltage. This bit is not writable and should
always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both
the contents of the RTC data and RAM data are questionable.
BIT 6 THROUGH BIT 0 - The remaining bits of Register D are not usable. They cannot be written and,
when read, they will always read 0.
14 of 32
DS1689/DS1693
EXTENDED FUNCTIONS
The extended functions provided by the DS1689/DS1693 that are new to the RAMified RTC family are
accessed via a software controlled bank switching scheme, as illustrated in Figure 4. In bank 0, the
clock/calendar registers and 50 bytes of user RAM are in the same locations as for the DS1287. As a
result, existing routines implemented within BIOS, DOS, or application software packages can gain
access to the DS1689/DS1693 clock registers with no changes. Also in bank 0, an extra 64 bytes of RAM
are provided at addresses just above the original locations for a total of 114 directly addressable bytes of
user RAM.
When bank 1 is selected, the clock/calendar registers and the original 50 bytes of user RAM still appear
as bank 0. However, the Dallas registers which provide control and status for the extended functions will
be accessed in place of the additional 64 bytes of user RAM. The major extended functions controlled by
the Dallas registers are listed below:
1. Silicon Revision byte
2. Serial Number
3. 8-Byte Customer Specific ROM or Serial Number
4. Century counter
5. Auxiliary Battery Control/Status
6. Wake-Up
7. Kickstart
8. RAM Clear Control/Status
9. VCC Powered Elapsed Time Counter
10. VBAT Powered Elapsed Time Counter
11. Power-on Cycle Counter
The bank selection is controlled by the state of the DV0 bit in register A. To access bank 0 the DV0 bit
should be written to a 0. To access bank 1, DV0 should be written to a 1. Register locations designated as
reserved in the bank 1 map are reserved for future use by Dallas Semiconductor. Bits in these locations
cannot be written and will return a 0 if read.
15 of 32
DS1689/DS1693
DS1689/DS1693 EXTENDED REGISTER BANK DEFINITION Figure 4
16 of 32
DS1689/DS1693
SILICON SERIAL NUMBER/CUSTOMER SPECIFIC ROM
A total of 128 bits are available for use as serial number/ROM. These bits may be used as a 128-bit serial
number or as a unique 64-bit serial number and 64-bit customer specific serial number or ROM. The
unique 64-bit serial number is located in bank 1 registers 40H-47H. This serial number is divided into
three parts. The first byte in register 40H contains a model number to identify the device type and
revision of the DS1689/DS1693. Registers 41H-46H contain a unique binary number. Register 47H
contains a CRC byte used to validate the data in registers 40H-46H. The method used to create the CRC
byte is proprietary to Dallas Semiconductor, but can be made available if required. Typical applications
should consider this byte simply as part of the overall unique serial number. All 8 bytes of the serial
number are read-only registers.
The DS1689/DS1693 is manufactured such that no two devices will contain an identical number in
locations 41H-47H. Blocks of numbers for these locations can be reserved by the customer. Contact
Dallas Semiconductor for special ordering information for DS1689/DS1693 with reserved blocks of serial
numbers.
As already mentioned, another 64 bits are available for use as an additional serial number or customer
specific ROM. These 64 bits are located in bank 1 registers 60H-67H.
CENTURY COUNTER
A register has been added in bank 1, location 48H, to keep track of centuries. The value is read in either
binary or BCD according to the setting of the DM bit.
AUXILIARY BATTERY
The VBAUX input is provided to supply power from an auxiliary battery for the DS1689/DS1693 kickstart,
wake-up, and SQW output features in the absence of VCC. This power source must be available in order to
use these auxiliary features when no VCC is applied to the device.
The Auxiliary Battery Enable (ABE; bank 1, register 04BH) bit in extended control register B is used to
turn on and off the auxiliary battery for the above functions in the absence of VCC. When set to a 1, VBAUX
battery power is enabled, and when cleared to 0, VBAUX battery power is disabled to these functions.
In the DS1689/DS1693, this auxiliary battery may be used as the primary backup power source for
maintaining the clock/calendar, user RAM, and extended external RAM functions. This occurs if the
VBAT pin is at a lower voltage than VBAUX. If the DS1689 is to be backed-up using a single battery with
the auxiliary features enabled, then VBAUX should be used and connected to VBAT. If VBAUX is not to be
used, it should be grounded and ABE should be cleared to 0.
WAKE-UP/KICKSTART
The DS1689/DS1693 incorporates a wake-up feature, which can power the system on at a predetermined
date through activation of the PWR output pin. In addition, the kickstart feature can allow the system to
be powered-up in response to a low going transition on the KS pin, without operating voltage applied to
the VCC pin. As a result, system power may be applied upon such events as a key closure, or modem ring
detect signal. In order to use either the wake-up or the kickstart features, the DS1689/DS1693 must have
an auxiliary battery connected to the VBAUX pin and the oscillator must be running and the countdown
chain must not be in reset (Register A DV2, DV1, DV0 = 01X). If DV2, DV1, and DV0 are not in this
required state, the PWR pin will not be driven low in response to a kickstart or wakeup condition, while
in battery-backed mode.
The wake-up feature is controlled through the Wake-up Interrupt Enable bit in extended control register B
(WIE, bank 1, 04BH). Setting WIE to 1 enables the wake-up feature, clearing WIE to 0 disables it.
17 of 32
DS1689/DS1693
Similarly, the kickstart feature is controlled through the Kickstart Interrupt Enable bit in extended control
register B (KSE, bank 1, 04BH).
A wake-up sequence will occur as follows: When wake-up is enabled via WIE = 1 while the system is
powered down (no VCC voltage), the clock/calendar will monitor the current date for a match condition
with the date alarm register (bank 1, register 049H). In conjunction with the date alarm register, the hours,
minutes, and seconds alarm bytes in the clock/calendar register map (bank 0, registers 05H, 03H, and
01H) are also monitored. As a result, a wake-up will occur at the date and time specified by the date,
hours, minutes, and seconds alarm register values. This additional alarm will occur regardless of the
programming of the AIE bit (bank 0, register B, 0BH). When the match condition occurs, the PWR pin
will automatically be driven low. This output can be used to turn on the main system power supply which
provides VCC voltage to the DS1689/DS1693 as well as the other major components in the system. Also
at this time, the Wake-Up flag (WF, bank 1, register 04AH) will be set, indicating that a wake-up
condition has occurred.
A kickstart sequence will occur when kickstarting is enabled via KSE = 1. While the system is powered
down, the KS input pin will be monitored for a low going transition of minimum pulse width tKSPW. When
such a transition is detected, the PWR line will be pulled low, as it is for a wake-up condition. Also at this
time, the Kickstart Flag (KF, bank 1, register 04AH) will be set, indicating that a kickstart condition has
occurred.
The timing associated with both the wake-up and kickstarting sequences is illustrated in the Wake-Up /
Kickstart Timing Diagram in the Electrical Specifications section of this data sheet. The timing associated
with these functions is divided into 5 intervals, labeled 1-5 on the diagram.
The occurrence of either a kickstart or wake-up condition will cause the PWR pin to be driven low, as
described above. During interval 1, if the supply voltage on the DS1689/DS1693 VCC pin rises above the
3-volt power-fail level before the power-on timeout period (tPOTO) expires, then PWR will remain at the
active low level. If VCC does not rise above the 3-volt power fail voltage in this time, then the PWR
output pin will be turned off and will return to its high impedance level. In this event, the IRQ pin will
also remain tri-stated. The interrupt flag bit (either WF or KF) associated with the attempted power-on
sequence will remain set until cleared by software during a subsequent system power-on.
If VCC is applied within the timeout period, then the system power-on sequence will continue as shown in
intervals 2-5 in the timing diagram. During interval 2, PWR will remain active and IRQ will be driven to
its active low level, indicating that either WF or KF was set in initiating the power-on. In the diagram KS
is assumed to be pulled up to the VBAUX supply. Also at this time, the PAB bit will be automatically
cleared to 0 in response to a successful power-on. The PWR line will remain active as long as the PAB
remains cleared to 0.
At the beginning of interval 3, the system processor has begun code execution and clears the interrupt
condition of WF and/or KF by writing 0s to both of these control bits. As long as no other interrupt within
the DS1689/DS1693 is pending, the IRQ line will be taken inactive once these bits are reset. Execution of
the application software may proceed. During this time, both the wake-up and kickstart functions may be
used to generate status and interrupts. WF will be set in response to a date, hours, and minutes match
condition. KF will be set in response to a low going transition on KS . If the associated interrupt enable bit
is set (WIE and/or KSE) then the IRQ line will driven active low in response to enabled event. In
18 of 32
DS1689/DS1693
addition, the other possible interrupt sources within the DS1689/DS1693 may cause IRQ to be driven
low. While system power is applied, the on chip logic will always attempt to drive the PWR pin active in
response to the enabled kickstart or wake-up condition. This is true even if PWR was previously inactive
as the result of power being applied by some means other than wake-up or kickstart.
The system may be powered down under software control by setting the PAB bit to a logic 1. This causes
the open-drain PWR pin to be placed in a high impedance state, as shown at the beginning of interval 4 in
the timing diagram. As VCC voltage decays, the IRQ output pin will be placed in a high impedance state
when VCC goes below VPF. If the system is to be again powered on in response to a wake-up or kickstart,
then the both the WF and KF flags should be cleared and WIE and/or KSE should be enabled prior to
setting the PAB bit.
During interval 5, the system is fully powered down. Battery backup of the clock calendar and
nonvolatile RAM is in effect, PWR and IRQ are tri-stated, and monitoring of wake-up and kickstart takes
place.
RAM CLEAR
The DS1689/DS1693 provides a RAM clear function for the 114 bytes of user RAM. When enabled, this
function can be performed regardless of the condition of the VCC pin.
The RAM clear function is enabled or disabled via the RAM Clear Enable bit (RCE; bank 1, register
04BH). When this bit is set to a logic 1, the 114 bytes of user RAM will be cleared (all bits set to 1)
when an active low transition is sensed on the RCLR pin. This action will have no effect on either the
clock/calendar settings or upon the contents of the external extended RAM. The RAM clear Flag (RF,
bank 1, register 04BH) will be set when the RAM clear operation has been completed. If VCC is present at
the time of the RAM clear and RIE=1, the IRQ line will also be driven low upon completion. The
interrupt condition can be cleared by writing a 0 to the RF bit. The IRQ line will then return to its inactive
high level provided there are no other pending interrupts. Once the RCLR pin is activated, all read/write
accesses are locked out for a minimum recover time, specified as tREC in the Electrical Characteristics
section.
When RCE is cleared to 0, the RAM clear function is disabled. The state of the RCLR pin will have no
effect on the contents of the user RAM, and transitions on the RCLR pin have no effect on RF.
EXTENDED CONTROL REGISTERS
Two extended control registers are provided to supply controls and status information for the extended
features offered by the DS1689/DS1693. These are designated as extended control registers A and B and
are located in register bank 1, locations 04AH and 04BH, respectively. The functions of the bits within
these registers are described as follows.
EXTENDED CONTROL REGISTER 4A
MSB
BIT 7
VRT2
BIT 6
INCR
BIT 5
*
BIT 4
*
BIT 3
PAB
19 of 32
BIT 2
RF
BIT 1
WF
LSB
BIT 0
KF
DS1689/DS1693
VRT2 - This status bit gives the condition of the auxiliary battery. It is set to a logic 1 condition when the
external lithium battery is connected to the VBAUX. If this bit is read as a logic 0, the external battery
should be replaced.
INCR - Increment in Progress status bit. This bit is set to a 1 when an increment to the time/date registers
is in progress and the alarm checks are being made. INCR will be set to a 1 at 122 ms before the update
cycle starts and will be cleared to 0 at the end of each update cycle.
PAB - Power Active Bar control bit. When this bit is 0, the PWR pin is in the active low state. This bit
can be written to a logic 1 or 0 by the user. If either WF AND WIE = 1 OR KF AND KSE = 1, the PAB
bit will be cleared to 0.
RF - Ram Clear Flag - This bit will be set to a logic 1 when a high to low transition occurs on the RCLR
input if RCE=1. The RF bit is cleared by writing it to a logic 0. This bit can also be written to a logic 1 to
force an interrupt condition.
WF – Wake-up Alarm Flag - This bit is set to 1 when a wake-up alarm condition occurs or when the user
writes it to a 1. WF is cleared by writing it to a 0.
KF - Kickstart Flag - This bit is set to a 1 when a kickstart condition occurs or when the user writes it to a
1. This bit is cleared by writing it to a logic 0.
EXTENDED CONTROL REGISTER 4B
MSB
BIT 7
ABE
BIT 6
E32K
BIT 5
CS
BIT 4
RCE
BIT 3
PRS
BIT 2
RIE
BIT 1
WIE
LSB
BIT 0
KSE
ABE - Auxiliary Battery Enable. This bit when written to a logic 1 will enable the VBAUX pin for
extended functions.
E32K - Enable 32,768 output. This bit when written to a logic 1 will enable the 32,768 Hz oscillator
frequency to be output on the SQW pin provided SQWE=1.
CS - Crystal Select Bit. When CS is set to a 0, the oscillator is configured for operation with a crystal that
has a 6 pF specified load capacitance. When CS=1, the oscillator is configured for a 12.5 pF crystal.
RCE - RAM Clear Enable bit. When set to a 1, this bit enables a low level on pin 4 ( RCLR ) to clear all
114 bytes of user RAM. When RCE = 0, the RAM clear function is disabled.
PRS - PAB Reset Select Bit. When set to a 0 the PWR pin will be set hi-Z when the DS1689 goes into
power-fail. When set to a 1, the PWR pin will remain active upon entering power-fail.
RIE - Ram Clear Interrupt Enable. When RIE is set to a 1, the IRQ pin will be driven low when a RAM
clear function is completed.
WIE – Wake-Up Alarm Interrupt Enable. When VCC voltage is absent and WIE is set to a 1, the PWR pin
will be driven active low when a wake-up condition occurs, causing the WF bit to be set to 1. When VCC
is then applied, the IRQ pin will also be driven low. If WIE is set while system power is applied, both
20 of 32
DS1689/DS1693
and PWR will be driven low in response to WF being set to 1. When WIE is cleared to a 0, the WF
bit will have no effect on the PWR or IRQ pins.
IRQ
KSE - Kickstart Interrupt Enable. When VCC voltage is absent and KSE is set to a 1, the PWR pin will be
driven active low when a kickstart condition occurs ( KS pulsed low), causing the KF bit to be set to 1.
When VCC is then applied, the IRQ pin will also be driven low. If KSE is set to 1 while system power is
applied, both IRQ and PWR will be driven low in response to KF being set to 1. When KSE is cleared to
a 0, the KF bit will have no effect on the PWR or IRQ pins.
* Reserved bits. These bits are reserved for future use by Dallas Semiconductor. They can be read and
written, but have no effect on operation.
ELAPSED TIME COUNTERS
The DS1689/DS1693 has two 32-bit elapsed time counters, which reside in bank 1 of the RTC registers.
To access these counters the DV0 bit in register A must first be set to a logical 1.
The VCC powered elapsed time counter resides in register 54H through 57H. The LSB of this counter
resides in register 54 and the MSB is in 57H. The VCC powered elapsed time counter runs only while the
VCCI input is within nominal limits. The elapsed time counter is a binary counter that records the number
of seconds that have elapsed. The counter can be read or written at the user's discretion. The VBAT
powered elapsed time counter resides in register 58H through 5BH. The LSB of this counter resides in
register 58 and the MSB is in 5BH.
The VBAT powered elapsed time counter runs continually as long as the VBAT or VBAUX pin is within
nominal limits regardless of the condition of VCCI. The number of seconds that have elapsed is recorded
in a binary counter and the counter may be read or written at the user’s discretion.
In a typical application the VBAT powered elapsed time counter can be used to record the length of time
that has elapsed from which the equipment which contains the device was first put into service. The VCC
powered counter can then be used to record the length of time that VCC power is applied. These functions
can be particularly useful for warranty and maintenance information. In addition, battery life can be
predicted based on known loading factors. However, it is worth noting that a properly selected battery
should power the DS1689/DS1693 and external RAM for the useful life of most equipment.
POWER CYCLE COUNTER
The DS1689/DS1693 has a 16-bit power cycle counter that resides in register 5C and 5D of bank 1. The
LSB of this counter resides in 5C and the MSB is in 5D. This binary counter is incremented by one count
each time VCCI power is applied within nominal limits. This counter can be read or written at the user’s
discretion.
21 of 32
DS1689/DS1693
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
-40°C to +70°C
260°C for 10 seconds (See Note 18)
See IPC/JEDEC Standard J-STD-020A for
surface mount devices
*This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Temperature
0°C to +70°C
-40ºC to 85ºC
VCC
3V ± 10% or 5V ± 10%
3V ± 10% or 5V ± 10%
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage 5-Volt Operation
Power Supply Voltage 3-Volt Operation
Input Logic 1
Input Logic 0
Battery Voltage
Auxiliary Battery Voltage
SYMBOL
VCCI
VCCI
VIH
VIL
VBAT
VBAUX
MIN
4.5
2.7
2.2
-0.3
2.5
2.5
22 of 32
Over the operating range
TYP
5.0
3.0
MAX
5.5
4.0
VCC+0.3
0.6
3.7
3.7
UNITS
V
V
V
V
V
V
NOTES
1
1
1
1
1
1
DS1689/DS1693
DC ELECTRICAL CHARACTERISTICS
Over the operating range (5V)
PARAMETER
Average VCC Power Supply Current
CMOS Standby Current ( CS =VCC-0.2V)
Input Leakage Current (any input)
Input Leakage
PSEL Input Leakage
Output Leakage Current
Output Logic 1 Voltage (IOUT = -1.0 mA)
Output Logic 0 Voltage (IOUT = +2.1 mA)
Output Voltage
CEI
SYMBOL
ICC1
ICC2
IIL
I CEI
IPSEL
IOL
VOH
VOL
VCCO1
Output Current
Power-Fail Trip Point
Battery Switch Voltage
ICCO1
VPF
VSW
Output Voltage
VCCO2
Output Current
Battery Leakage OSC ON
Battery Leakage OSC OFF
I/O Leakage
ICCO2
IBAT1
IBAT2
ILO
IOLPWR
ZCE
Output @ 0.4V
CEI to CEO Impedance
PWR
23 of 32
MIN
TYP
7
1
-1
-200
-1
-1
2.4
MAX
15
3
+1
+1
+200
+1
0.4
VCC
-0.3
4.25
4.37
VBAT,
VBAUX
85
4.5
VBAT
-0.3
500
50
-1
100
1000
150
+1
10.0
60
UNITS
mA
mA
mA
mA
mA
mA
V
V
V
NOTES
2, 3
2, 3
15
16
8
4
mA
V
V
4
5
V
6
mA
nA
nA
mA
mA
6
W
17
7
1
12
DS1689/DS1693
DC ELECTRICAL CHARACTERISTICS
Over the operating range (3V)
PARAMETER
Average VCC Power Supply Current
CMOS Standby Current ( CS =VCC-0.2V)
Input Leakage Current (any input)
Input Leakage
PSEL Input Leakage
Output Leakage Current
Output Logic 1 Voltage (IOUT = 0.4 mA)
Output Logic 0 Voltage (IOUT = 0.8 mA)
Output Voltage
CEI
SYMBOL
ICC1
ICC2
IIL
I CEI
IPSEL
IOL
VOH
VOL
VCCO1
Output Current
Power-Fail Trip Point
Output Voltage
ICCO1
VPF
VCCO2
Output Current
Battery Leakage OSC ON
Battery Leakage OSC OFF
I/O Leakage
ICCO2
IBAT1
IBAT2
ILO
IOLPWR
ZCE
Output @ 0.4V
CEI to CEO Impedance
PWR
MIN
TYP
5
0.5
-1
-160
+1
+160
2.4
MAX
10
2
+1
+1
-160
-1
0.4
VCC
-0.3
2.5
VBAT
-0.3
2.6
500
50
-1
UNITS
mA
mA
mA
mA
mA
mA
V
V
V
NOTES
2, 3
2, 3
15
16
8
4
50
2.7
mA
V
V
4
5
6
100
1000
150
+1
4
120
mA
nA
nA
mA
mA
6
W
17
7
1
12
RTC AC TIMING CHARACTERISTICS
Over the operating range (3V)
PARAMETER
Cycle Time
Pulse Width, RD / WR Low
Pulse Width, RD / WR High
Input Rise and Fall Time
Chip Select Setup Time Before WR , or RD
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
Muxed Address Valid Time to ALE Fall
Muxed Address Hold Time from ALE Fall
RD or WR High Setup to ALE Rise
Pulse Width ALE High
ALE Low Setup to RD or WR Fall
Output Data Delay Time from RD
Data Setup Time
IRQ Release from RD
CEI
to CEO Delay
SYMBOL
tCYC
PWRWL
PWRWH
tR, tF
tCS
tCH
tDHR
tDHW
tASL
tAHL
tASD
PWASH
tASED
tDDR
tDSW
tIRD
tCED
24 of 32
MIN
915
375
450
TYP MAX
DC
30
75
0
10
0
90
30
30
180
120
20
180
120
370
2
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
NOTES
9
DS1689/DS1693
DS1689/DS1693 BUS TIMING FOR READ CYCLE TO RTC
RTC AC TIMING CHARACTERISTICS
Over the operating range (5V)
PARAMETER
Cycle Time
Pulse Width, RD / WR Low
Pulse Width, RD / WR High
Input Rise and Fall Time
Chip Select Setup Time Before WR , or RD
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
Muxed Address Valid Time to ALE Fall
Muxed Address Hold Time from ALE Fall
RD or WR High Setup to ALE Rise
Pulse Width ALE High
ALE Low Setup to RD or WR Fall
Output Data Delay Time from RD
Data Setup Time
IRQ Release from RD
CEI
to CEO Delay
SYMBOL
tCYC
PWRWL
PWRWH
tR, tF
tCS
tCH
tDHR
tDHW
tASL
tAHL
tASD
PWASH
tASED
tDDR
tDSW
tIRD
tCED
25 of 32
MIN
305
125
150
TYP MAX
DC
30
20
0
10
0
30
10
25
60
40
20
100
80
120
2
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
NOTES
9
DS1689/DS1693
DS1689/DS1693 BUS TIMING FOR
WRITE CYCLE TO RTC AND RTC REGISTERS
POWER-UP CONDITION 3-VOLT OPERATION
26 of 32
DS1689/DS1693
POWER-DOWN CONDITION 3-VOLT OPERATION
POWER-UP CONDITION 5.0-VOLT OPERATION
POWER-DOWN CONDITION 5.0-VOLT OPERATION
27 of 32
DS1689/DS1693
POWER-UP POWER-DOWN TIMING 5-VOLT OPERATION
PARAMETER
CS High to Power-Fail
Recovery at Power-up
VCC Slew Rate Power-down
VCC Slew Rate Power-down
VCC Slew Rate Power-up
Expected Data Retention
SYMBOL
tPF
tREC
tF
4.0 £ VCC £ 4.5V
tFB
3.0 £ VCC £ 4.0V
tR
4.5V ³ VCC ³ 4.0V
tDR
MIN
TYP
MAX
0
300
UNITS
ns
ms
ms
10
ms
0
ms
10
years
150
POWER-UP POWER-DOWN TIMING 3-VOLT OPERATION
PARAMETER
CS High to Power-Fail
Recovery at Power-up
VCC Slew Rate Power-down
VCC Slew Rate Power-up
Expected Data Retention
SYMBOL
tPF
tREC
tF
2.5 £ VCC £ 3.0V
tR
3.0V ³ VCC ³ 2.5V
tDR
(tA = 25°C)
MIN
TYP
MAX
0
13, 14
(tA = 25°C)
300
UNITS
ns
ms
ms
0
ms
10
years
150
NOTES
NOTES
13, 14
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery
back-up mode.
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
(tA = 25°C)
SYMBOL
CIN
COUT
MIN
TYP
MAX
12
12
WAKE-UP/KICKSTART TIMING
PARAMETER
Kickstart Input Pulse Width
Wake-up/Kickstart Power-on Timeout
UNITS
pF
pF
NOTES
(tA = 25°C)
SYMBOL
tKSPW
tPOTO
MIN
2
2
28 of 32
TYP
MAX
UNITS
ms
seconds
NOTES
10
DS1689/DS1693
WAKE-UP/KICKSTART TIMING
NOTE:
Time intervals shown above are referenced in Wake-up/Kickstart section.
* This condition can occur when the device is operated in 3-volt mode.
29 of 32
DS1689/DS1693
NOTES:
1. All voltages are referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Value for voltage and currents is from the VCCI input pin to the VCCO pin.
5. Write protection trip point occurs during power fail prior to switchover from VCC to VBAT.
6. Value for voltage and currents is from the VBAT input pin to the VCCO pin.
7. Applies to the AD0-AD7 pins, and the SQW pin when each is in a high impedance state.
8. The IRQ pin is open drain.
9. Measured with a load of 50 pF + 1 TTL gate.
10. Wakeup kickstart timeout generated only when the oscillator is enabled and the countdown chain is
not reset.
11. VSW is determined by the larger of VBAT and VBAUX.
12. ZCE is an average input to output impedance as the input is swept from GND to VCCI and less than
4 mA is forced through ZCE.
13. The DS1693 will keep time to an accuracy of ±1 minute per month during data retention time for the
period of tDR.
14. tDR is the amount of time that the internal battery can power the internal oscillator and internal
registers of the DS1693. As such, tDR is specified with VCCO floating. If VCCO is powering an external
SRAM, an auxiliary battery must be connected to the VBAUX pin. The auxiliary battery should be sized
such that it can power the external SRAM for the tDR period.
15. The CEI pin has an internal pull-up of 60 kW.
16. The PSEL pin has an internal pull-down of 60 kW.
17. For industrial grade parts, IBAT (with OSC off) limit increases to 250 nA.
18. Real-Time Clock Modules can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used.
30 of 32
DS1689/DS1693
DS1689S 28-PIN SOIC
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
31 of 32
28-PIN
MIN
MAX
0.697
0.728
17.70
18.50
0.324
0.350
8.23
8.90
0.087
0.118
2.20
3.00
0.016
0.050
0.40
1.27
0.002
0.014
0.05
0.35
0.100
0.120
2.55
3.05
0.050 BSC
1.27 BSC
0.453
0.500
11.50
12.70
0.006
0.013
0.14
0.32
0.014
0.020
0.35
0.50
DS1689/DS1693
DS1693 28-PIN 740-MIL MODULE
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
NOTE:
32 of 32
28-PIN
MIN
MAX
1.520
1.540
38.61
39.12
0.695
0.740
17.65
18.80
0.350
0.375
8.89
9.52
0.100
0.130
2.54
3.30
0.015
0.030
0.38
0.76
0.110
0.140
2.79
3.56
0.090
0.110
2.29
2.79
0.590
0.630
14.99
16.00
0.008
0.012
0.20
0.30
0.015
0.021
0.38
0.53
PINS 2, 3, 19 AND 23 ARE MISSING BY DESIGN.