TI HC125 High speed cmos logic quad buffer, three-state Datasheet

[ /Title
(CD74
HC125
,
CD74
HCT12
5)
/Subject
(High
Speed
CMOS
Logic
Quad
Buffer,
ThreeState)
CD74HC125,
CD74HCT125
Data sheet acquired from Harris Semiconductor
SCHS143
High Speed CMOS Logic
Quad Buffer, Three-State
November 1997
Features
Description
• Three-State Outputs
The Harris CD74HC125 and CD74HCT125 contain 4 independent three-state buffers, each having its own output
enable input, which when “HIGH” puts the output in the high
impedance state
• Separate Output Enable Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
PART NUMBER
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
TEMP. RANGE
(oC)
PKG.
NO.
PACKAGE
CD74HC125E
-55 to 125
14 Ld PDIP
E14.3
CD74HCT125E
-55 to 125
14 Ld PDIP
E14.3
CD74HC125M
-55 to 125
14 Ld SOIC
M14.15
CD74HCT125M
-55 to 125
14 Ld SOIC
M14.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD74HC125, CD74HCT125
(PDIP, SOIC)
TOP VIEW
1OE 1
14 VCC
1A 2
13 4OE
1Y 3
12 4A
2OE 4
11 4Y
2A 5
10 3OE
2Y 6
9 3A
GND 7
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number
1771.1
CD74HC125, CD74HCT125
Functional Diagram
1OE
1A
2OE
1
3
2
1Y
4
6
5
2A
2Y
10
3OE
8
9
3Y
3A
13
4OE
11
12
4Y
GND = 7
VCC = 14
4A
TRUTH TABLE
INPUTS
OUTPUTS
nA
nOE
nY
H
L
H
L
L
L
X
H
Z
NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance, OFF State
Logic Diagram
P
nA
nY
n
nOE
2
CD74HC125, CD74HCT125
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
-
3
CD74HC125, CD74HCT125
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
Quiescent Device
Current
ICC
VCC or
GND
0
Three-State Leakage
Current
IOZ
VIL or
VIH
High Level Input
Voltage
VIH
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
-
8
-
80
-
160
µA
-
6
-
-
±0.5
-
±5
-
±10
µA
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
VOH
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
II
VCC to
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Three-State Leakage
Current
IOZ
VIL or
VIH
-
5.5
-
-
±0.5
-
±5
-
±10
µA
Input Leakage
Current
Quiescent Device
Current
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
nA, nOE
1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.
4
CD74HC125, CD74HCT125
Switching Specifications
PARAMETER
Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC (V)
TYP
MAX
MAX
MAX
UNITS
2
-
100
125
150
ns
4.5
-
20
25
30
ns
CL = 15pF
5
8
-
-
-
ns
CL = 50pF
6
-
17
21
26
ns
CL = 50pF
2
-
125
155
190
ns
4.5
-
25
31
38
ns
CL = 15pF
5
10
-
-
-
ns
CL = 50pF
6
-
21
26
32
ns
CL = 50pF
2
-
125
155
190
ns
CL = 50pF
4.5
-
25
31
38
ns
CL = 15pF
5
10
-
-
-
ns
CL = 50pF
6
-
21
26
32
ns
CL = 50pF
2
-
60
75
90
ns
4.5
-
12
15
18
ns
6
-
10
13
15
ns
HC TYPES
Propagation Delay Time
nA to nY
Enable Delay Time
Disable Delay Time
Output Transition Time
tPZL, tPZH
tPLZ, tPHZ
tTLH, tTHL
Input Capacitance
CI
-
-
-
10
10
10
pF
Three-State Output
Capacitance
CO
-
-
-
20
20
20
pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD
-
5
29
-
-
-
pF
CL = 50pF
4.5
-
25
31
38
ns
CL = 15pF
5
10
-
-
-
ns
CL = 50pF
4.5
-
25
31
38
ns
CL = 15pF
5
10
-
-
-
ns
CL = 50pF
4.5
-
28
35
42
ns
CL = 15pF
5
11
-
-
-
ns
CL = 50pF
4.5
-
12
15
18
ns
HCT TYPES
Propagation Delay Time
nA to nY
tPLH, tPHL
Output Enable Time
tPZL, tPZH
Output Disabling Time
Output Transition Times
tPLZ, tPHZ
tTLH, tTHL
Input Capacitance
CI
-
-
-
10
10
10
pF
Three-State Output
Capacitance
CO
-
-
-
20
20
20
pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD
-
5
34
-
-
-
pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per channel.
6. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
5
CD74HC125, CD74HCT125
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
tPHL
6ns
10%
2.7
1.3
OUTPUT LOW
TO OFF
90%
OUTPUT HIGH
TO OFF
50%
OUTPUTS
DISABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
IC WITH
THREESTATE
OUTPUT
GND
1.3V
tPZH
90%
OUTPUTS
ENABLED
OUTPUTS
ENABLED
0.3
10%
tPHZ
tPZH
3V
tPZL
tPLZ
50%
OUTPUTS
ENABLED
6ns
GND
10%
tPHZ
tf
OUTPUT
DISABLE
tPZL
tPLZ
OUTPUT HIGH
TO OFF
6ns
tr
VCC
90%
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
OUTPUT LOW
TO OFF
1.3V
10%
INVERTING
OUTPUT
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
50%
tTLH
90%
tPLH
tPHL
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
OUTPUT
DISABLE
tf = 6ns
tr = 6ns
VCC
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OUTPUT
RL = 1kΩ
CL
50pF
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
6
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