AD AD9433 12-bit, 105 msps/125 msps if sampling a/d converter Datasheet

a
FEATURES
IF Sampling up to 350 MHz
SNR = 67.5 dB, fIN up to Nyquist @ 105 MSPS
SFDR = 83 dBc, fIN 70 MHz @ 105 MSPS
SFDR = 72 dBc, f IN 150 MHz @ 105 MSPS
2 V p-p Analog Input Range Option
On-Chip Clock Duty Cycle Stabilization
On-Chip Reference and Track/Hold
SFDR Optimization Circuit
Excellent Linearity:
DNL = 0.25 LSB (Typ)
INL = 0.5 LSB (Typ)
750 MHz Full Power Analog Bandwidth
Power Dissipation = 1.35 W Typical @ 125 MSPS
Two’s Complement or Offset Binary Data Format
5.0 V Analog Supply Operation
2.5 V to 3.3 V TTL/CMOS Outputs
APPLICATIONS
Cellular Infrastructure Communication Systems
3G Single and Multicarrier Receivers
IF Sampling Schemes
Wideband Carrier Frequency Systems
Point to Point Radios
LMDS, Wireless Broadband
MMDS Base Station Units
Cable Reverse Path
Communications Test Equipment
Radar and Satellite Ground Systems
GENERAL INTRODUCTION
The AD9433 is a 12-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is designed
for ease of use. The product operates up to 125 MSPS conversion rate and is optimized for outstanding dynamic performance
in wideband and high IF carrier systems.
The ADC requires a 5 V analog power supply and a differential
encode clock for full performance operation. No external reference or driver components are required for many applications.
The digital outputs are TTL/CMOS compatible and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
A user-selectable, on-chip proprietary circuit optimizes spuriousfree dynamic range (SFDR) versus signal-to-noise-and-distortion
(SINAD) ratio performance for different input signal frequencies,
providing as much as 83 dBc SFDR performance over the dc
to 70 MHz band.
12-Bit, 105 MSPS/125 MSPS
IF Sampling A/D Converter
AD9433
FUNCTIONAL BLOCK DIAGRAM
AD9433
VCC
AIN
AIN
ENCODE
ENCODE
PIPELINE
ADC
T/H
12
VDD
OUTPUT
STAGING
D11–D0
12
DFS
ENCODE
TIMING
GND
REF
SFDR
REF REF
OUT IN
The encode clock supports either differential or single-ended
input and is PECL-compatible. The output format is userselectable for binary or two’s complement and provides an
overrange (OR) signal.
Fabricated on an advanced BiCMOS process, the AD9433 is
available in a thermally enhanced 52-lead plastic quad flatpack
specified over the industrial temperature range (–40°C to
+85°C) and is pin-compatible with the AD9432.
PRODUCT HIGHLIGHTS
1. IF Sampling
The AD9433 maintains outstanding ac performance up to
input frequencies of 350 MHz. Suitable for 3G Wideband
Cellular IF sampling receivers.
2. Pin-Compatibility
This ADC has the same footprint and pin layout as the
AD9432, 12-Bit 80/105 MSPS ADC.
3. SFDR Performance
A user-selectable on-chip circuit optimizes SFDR performance
as much at 85 dBc from dc to 70 MHz.
4. Sampling Rate
At 125 MSPS, this ADC is ideally suited for current wireless
and wired broadband applications such as LMDS/MMDS
and cable reverse path.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9433–SPECIFICATIONS
DC SPECIFICATIONS (V
DD
= 3.3 V, VCC = 5 V; internal reference; differential encode input, unless otherwise noted.)
Parameter
◊
Temp
Test
Level
AD9433BSQ-105
Min
Typ
Max
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
12
Full
Full
25⬚C
25⬚C
Full
25⬚C
Full
VI
VI
I
I
VI
I
VI
THERMAL DRIFT
Offset Error
Gain Error1
Reference
Full
Full
Full
V
V
V
REFERENCE
Internal Reference Volatge (VREFOUT)
Output Current (VREFOUT)
Input Current (VREFIN)
Full
Full
Full
I
V
IV
Integral Nonlinearity (INL)2
–5
–7
–0.75
–1
–1.0
–1.3
Guaranteed
0
+5
⫾1
+3
⫾0.25 +0.75
+1
⫾0.5
+1.0
+1.3
–5
–7
–0.75
–1
–1.0
–1.3
–50
–125
± 80
2.4
2.5
100
2.6
2.4
Full
V
Bits
Guaranteed
0
+5
⫾1
+3
⫾0.3 +0.75
+1
⫾0.5 +1.0
+1.3
mV
% FS
LSB
LSB
LSB
LSB
–50
–125
± 80
ppm/⬚C
ppm/⬚C
ppm/⬚C
2.5
100
Full
Full
Full
Full
V
VI
V
V
POWER SUPPLY
VCC
VDD
Power Dissipation3
Power Supply Rejection Ratio (PSRR)
IVCC2
IVDD2
Full
Full
Full
25⬚C
Full
Full
IV
IV
VI
I
VI
VI
ENCODE INPUTS
Internal Common-Mode Bias
Differential Input (ENC – ENC)
Input Voltage Range
Input Common-Mode Range
Input Resistance
Input Capacitance
Full
Full
Full
Full
Full
25⬚C
V
V
IV
IV
VI
V
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input High Current (VIN = 5 V)
Input Low Current (VIN = 0 V)
Full
Full
Full
Full
I
I
V
V
2.0
Full
Full
VI
VI
VDD – 0.05
2
4.75
2.7
4.0
3
4
750
5.0
1275
⫾3
255
12.5
2.0
4
2
5.25
3.3
1425
4.75
2.7
4.0
3
4
750
5.0
1350
⫾3
270
16
285
14
3.75
500
3.75
500
VCC + 0.05
4.25
–0.5
2.0
2.6
50
2.0
–0.5
2.0
6
3
6
3
4
5.25
3.3
1500
300
18
V
kΩ
pF
MHz
V
V
mW
mV/V
mA
mA
V
mV
VCC + 0.05 V
4.25
V
kΩ
pF
0.8
50
50
VDD – 0.05
0.05
Two’s Complement or Offset Binary
V
µA
µA
V
2.0
0.8
50
50
Unit
12
50
ANALOG INPUTS
Differential Input Voltage Range
(AIN, AIN)
Common-Mode Voltage
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Output Coding
AD9433BSQ-125
Min
Typ
Max
0.05
V
V
µA
µA
V
V
NOTES
1
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).
2
SFDR disabled (SFDR = GND) for DNL and INL specifications.
3
Power dissipation measured with rated encode and a dc analog input (Outputs Static, I VDD = 0). IVCC and IVDD measured with 10.3 MHz analog input @ –0.5 dBFS.
Specifications subject to change without notice.
–2–
REV. 0
AD9433
AC SPECIFICATIONS (V
DD
= 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE*
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
Signal-to-Noise Ratio and Distortion (SINAD)
(With Harmonics)
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
Effective Number of Bits
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
2nd and 3rd Harmonic Distortion
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
Worst Other Harmonic or Spur
(Excluding Second and Third)
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
Two-Tone Intermod Distortion (IMD3)
fIN1 = 49.3 MHz, fIN2 = 50.3 MHz
fIN1 = 150 MHz, fIN2 = 151 MHz
Temp
Test
Level
AD9433BSQ-105
Min
Typ
Max
AD9433BSQ-125
Min
Typ
Max
25⬚C
25⬚C
25⬚C
25⬚C
25⬚C
I
I
V
V
V
66.5
65.5
68.0
67.5
67.0
65.4
63.7
66.0
64.0
67.7
66.0
65.4
62.0
60.0
dB
dB
dB
dB
dB
25⬚C
25⬚C
25⬚C
25⬚C
25⬚C
I
I
V
V
V
66.0
64.0
68.0
67.5
66.9
64.0
61.2
65.0
63.5
67.0
65.5
64.5
61.5
57.7
dB
dB
dB
dB
dB
25⬚C
25⬚C
25⬚C
25⬚C
25⬚C
I
I
V
V
V
10.9
10.7
10.6
10.0
9.4
Bits
Bits
Bits
Bits
Bits
25⬚C
25⬚C
25⬚C
25⬚C
25⬚C
I
I
V
V
V
–78
–73
–85
–80
–83
–72
–67
–76
–72
–85
–76
–78
–67
–65
dBc
dBc
dBc
dBc
dBc
25⬚C
25⬚C
25⬚C
25⬚C
25⬚C
I
I
V
V
V
–88
–82
–92
–89
–87
–87
–85
–84
–82
–90
–87
–85
–84
–76
dBc
dBc
dBc
dBc
dBc
25⬚C
25⬚C
V
V
–90
–76
dBc
dBc
11.1
11.0
10.9
10.4
9.9
–92
–80
Unit
*SNR/Harmonics based on an analog input voltage of –0.5 dBFS referenced to a 2 V full-scale input range. Harmonics are specified with the SFDR active
(SFDR = +5 V). SNR/SINAD specified with SFDR disabled (SFDR = Ground).
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS (V
DD
= 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.)
Parameter
Temp
Test
Level
AD9433BSQ-105
Min
Typ
Max
AD9433BSQ-125
Min
Typ
Max
Encode Rate
Encode Pulsewidth High (tEH)
Encode Pulsewidth Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)1
Output Valid Time (tV)2
Output Propagation Delay (tPD)2
Output Rise Time (tR)
Output Fall Time (tF)
Out of Range Recovery Time
Transient Response Time
Latency
Full
Full
Full
25⬚C
25⬚C
Full
Full
Full
Full
25⬚C
25⬚C
Full
IV
IV
IV
V
V
VI
VI
V
V
V
V
IV
10
2.9
2.9
10
2.4
2.4
2.5
105
2.1
0.25
4.0
4.0
2.1
1.9
2
2
10
2.5
5.5
125
2.1
0.25
4.0
4.0
2.1
1.9
2
2
10
5.5
Unit
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
Cycles
NOTES
1
Aperture uncertainty includes contribution of the AD9433, crystal clock reference, and encode drive circuit.
2
tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital output swing. The digital output load during testing is
not to exceed an ac load of 10 pF or a dc current of 50 µA. Rise and fall times measured from 10% to 90%.
Specifications subject to change without notice.
REV. 0
–3–
AD9433
THERMAL CHARCTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Parameter
Min
ELECTRICAL
VDD Voltage
VCC Voltage
Analog Input Voltage
Digital Input Voltage
Digital Output Current
–0.5
–0.5
–0.5
–0.5
ENVIRONMENTAL
Operating Temperature
Range (Ambient)
Maximum Junction
Temperature
Storage Temperature
Range (Ambient)
Max
+6.0
+6.0
VCC + 0.5
VCC + 0.5
20
Unit
Thermal Resitance
52-Lead PowerQuad® 4 LQFP_ED
␪JA = 25°C/W, Soldered Heat Sink, No Airflow
␪JA = 33°C/W, Unsoldered Heat Sink, No Airflow
␪JC = 2°C/W, Bottom of Package (Heat Sink)
V
V
V
V
mA
Simulated typical performance for 4-layer JEDEC board, horizontal orientation.
EXPLANATION OF TEST LEVELS
Test Level
–40
–65
+85
⬚C
+150
⬚C
+125
⬚C
I
II
100% production tested.
100% production tested at 25⬚C and guaranteed by design
and characterization at specified temperatures.
III Sample Tested Only
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25⬚C and guaranteed by design
and characterization for industrial temperature range.
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9433BSQ-105
AD9433BSQ-125
AD9433/PCB
–40°C to +85°C (Ambient)
–40°C to +85°C (Ambient)
25°C
52-Lead Plastic Thermally Enhanced Quad Flatpack
52-Lead Plastic Thermally Enhanced Quad Flatpack
Evaluation Board with AD9433BSQ-125
(Supports – 105 Evaluation)
SQ-52
SQ-52
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9433 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PowerQuad is a registered trademark of AMkor Technology, Inc.
–4–
REV. 0
AD9433
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Function
1, 3, 4, 9, 11, 33, 34, 35, 38, 39, 40,
43, 48, 51
2, 5, 6, 10, 36, 37, 44, 47, 52
7
8
GND
Analog Ground
VCC
ENCODE
ENCODE
14
15–20, 25–30
13, 22, 23, 32
12, 21, 24, 31
41
OR
D11–D0
VDD
DGND
DFS
42
SFDR MODE
45
46
VREFIN
VREFOUT
49
50
AIN
AIN
Analog Supply (5 V)
Encode Clock for ADC-Complementary
Encode Clock for ADC-True (ADC samples on rising edge of
ENCODE)
Out of Range Output
Digital Output
Digital Output Power Supply (3 V)
Digital Output Ground
Data Format Select. Low = Two’s Complement, High = Binary;
Floats Low
CMOS control pin that enables (SFDR MODE = 1), a proprietary
circuit that may improve the spurious free dynamic range (SFDR)
performance of the AD9433. It is useful in applications where the
dynamic range of the system is limited by discrete spurious
frequency content caused by nonlinearities in the ADC transfer
function. SFDR MODE = 0 for normal operation; Floats Low.
Reference Input for ADC (2.5 V typical)
Internal Reference Output (2.5 V typical); bypass with 0.1 µF to
Ground
Analog Input-True
Analog Input-Complement
GND
DFS
SFDR MODE
VCC
GND
VREFIN
VCC
VREFOUT
GND
AIN
AIN
VCC
GND
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
GND 1
PIN 1
IDENTIFIER
VCC 2
GND
38
GND
GND 3
37
VCC
GND 4
36
VCC
VCC 5
VCC 6
ENCODE 7
ENCODE 8
35
GND
AD9433BSQ
34
GND
TOP VIEW
(Not to Scale)
33
GND
32
VDD
GND 9
31
DGND
VCC 10
GND 11
30
D0 (LSB)
29
D1
DGND 12
28
D2
VDD 13
27
D3
–5–
D4
D5
DGND
VDD
VDD
DGND
D6
D7
D8
D9
D10
OR
(MSB) D11
14 15 16 17 18 19 20 21 22 23 24 25 26
REV. 0
39
AD9433
Integral Nonlinearity
DEFINITIONS OF SPECIFICATIONS
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best fit straight line
determined by a least square curve fit.
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.
Maximum Conversion Rate
The maximum encode rate at which parametric testing is performed.
Aperture Uncertainty (Jitter)
Output Propagation Delay
The sample-to-sample variation in aperture delay.
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a
network analyzer.
Noise (for Any Range within the ADC)
Differential Analog Input Voltage Range
Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and SIGNAL is the signal level within the ADC
reported in dB below full scale. This value includes both thermal
and quantization noise.
 FSdBm – SNRdBc – SignaldBFS 

10


VNOISE = Z × 0.001 × 10 
The peak-to-peak differential voltage that must be applied to
the converter to generate a fullscale response. Peak differential voltage is computed by observing the voltage on a single
pin and subtracting the voltage from the other pin, which is
180 degrees out of phase. Peak to peak differential is computed
by rotating the inputs phase 180 degrees and taking the peak
measurement again. Then the difference is computed between
both peak measurements.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD)
Differential Nonlinearity
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
 Full - Scale Amplitude 
SNRMEASURED – 1.76 dB + 20 log 

 Input Amplitude 
ENOB =
6.02
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component
may or may not be a harmonic. May be reported in dBc (i.e.,
degrades as signal level is lowered), or dBFS (always related back
to converter full scale).
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone (f1, f2) to the rms
value of the worst third order intermodulation product; reported
in dBc. Products are located at 2f1 – f2 and 2f2 – f1.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
PowerFull Scale
 2
V FullScale rms
= 10 log 
Z


0.001
Two-Tone SFDR
The ratio of the rms value of either input tone (f1, f2) to the rms
value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in
dBc (i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).





Gain
Worst Other Spur
Gain error is the difference between the measured and ideal
full-scale input voltage range of the ADC.
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
Harmonic Distortion
The ratio of the rms signal amplitude fundamental frequency to
the rms signal amplitude of a single harmonic component (second,
third, etc.), reported in dBc.
–6–
REV. 0
AD9433
SAMPLE N
SAMPLE N+10
SAMPLE N+9
SAMPLE N–1
AIN
SAMPLE N+1
SAMPLE N+8
tA
tEH
tEL
1/fS
ENCODE
ENCODE
tPD
D11–D0
DATA N–11
DATA
N–9
DATA N–10
DATA
N–2
DATA N–1
tV
DATA N
DATA N+1
Figure 1. AD9433 Timing Diagram
EQUIVALENT CIRCUITS
VDD
VCC
VCC
3.75k
3.75k
AIN
DX
VREFOUT
AIN
15k
15k
Figure 2. Digital Output
Figure 3. Analog Input
Figure 4. Reference Output
VCC
VCC
8k
8k
VREFIN
ENCODE
ENCODE
24k
24k
Figure 5. Encode Inputs
REV. 0
Figure 6. Reference Input
–7–
AD9433 –Typical Performance Characteristics
–95
0
SNR = 67.5dB
SFDR = 85.0dBFS
–10
–90
–20
–30
WORST OTHER
–85
–40
–80
dBc
dB
–50
–60
–70
3RD HARMONIC
–75
–80
–70
–90
2ND HARMONIC
–100
–65
–110
–60
–120
0
13.1
26.3
FREQUENCY – MHz
39.4
52.5
0
200
250
TPC 4. Harmonics (Second, Third, Worst Other) vs. AIN
Frequency. AIN @ –0.5 dBFS, fS = 105 MSPS, SFDR Enabled
TPC 1. FFT: fS = 105 MSPS, fIN = 49.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled
0
SNR = 68.0dB
SFDR = 80.0dBFS
–10
100
150
AIN – MHz
50
68
11.1
67
10.9
–20
SNR/SINAD – dB
–50
–60
–70
–80
–90
–100
10.6
65
SINAD
64
10.4
63
10.3
62
10.1
61
9.9
ENOBs – Bits
SNR
–40
dB
10.8
66
–30
–110
60
–120
0
13.1
26.3
FREQUENCY – MHz
39.4
52.5
TPC 2. FFT: fS = 105 MSPS, fIN = 49.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Disabled
0
50
100
150
AIN – Hz
9.8
300
100
SNR = 67.7dB
SFDR = 76.0dBFS
95
3RD
–dBc
–20
90
–30
SNR/SINAD – dB
–40
–50
–60
–70
–80
85
2ND
–dBc
80
75
SNR
70
–90
–100
65
–110
–120
250
TPC 5. SNR vs. AIN Frequency. Differential AIN @
–0.5 dBFS, 105 MSPS, SFDR Disabled
0
–10
dB
200
SINAD
0
15.6
31.2
FREQUENCY – MHz
46.8
60
10
62.5
TPC 3. FFT: fS = 125 MSPS, fIN = 49.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled
30
50
70
90
ENCODE – MSPS
110
140
TPC 6. SNR/SINAD and Harmonic Distortion vs.
Encode Frequency. Differential AIN @ –0.5 dBFS
–8–
REV. 0
AD9433
0
11.3
67
10.9
–30
10.6
65
SNR/SINAD – dB
–40
–50
–60
–70
–80
–90
–100
SINAD
SNR
63
10.3
61
9.9
59
9.6
57
9.3
ENOB – Bits
–20
dB
69
IMD3 = 92dBFS
–10
–110
–120
0
7.5
15.0
22.5
30.0
37.5
FREQUENCY – MHz
45.0
10.3
TPC 7. FFT: fS = 105 MSPS, fIN = 49.3 MHz and 50.3 MHz,
Differential AIN @ –7 dBFS for Each Tone, SFDR Enabled
80.3
AIN – MHz
170.3
250.3
100
100
90
SFDR dBc
90
3RD HARMONIC
80
2ND HARMONIC
80
70
70
SNR
60
60
dB
SFDR – dB
49.3
TPC 10. SNR and SINAD vs. AIN Frequency.
Differential AIN @ –0.50 dBFS, fS = 125 MSPS,
SFDR Enabled
110
50
8.9
55
52.5
SNR dBFS
SFDR dBFS
50
40
40
30
30
20
90dBFS
REFERENCE
10
0
–90
–80
–70
fS = 105MSPS
fIN = 49.3MHz
DIFFERENTIAL AIN
SFDR ENABLED
–60
–50
–40
–30
AIN LEVEL – dBFS
–20
–10
20
10
0
3.5
0
TPC 8. SNR and SFDR vs. AIN Level, fS = 105 MSPS,
fIN = 49.3 MHz, Differential AIN, SFDR Enabled
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
AIN COMMON-MODE VOLTAGE – V
4.4
4.5
TPC 11. Dynamic Performance vs. AIN Common-Mode
Voltage. Differential AIN @ –0.5 dBFS, fIN = 49.3 MHz,
fS = 105 MSPS
110
69
68
100
90
66
SNR – dB
THIRD ORDER IMD – dB
67
80
70
–40C
65
64
+25C
63
62
60
+85C
61
50
–90
–80
–70
–60
–50
–40
–30
AIN LEVEL – dBFS
–20
–10
60
0
10.3
TPC 9. Third Order IMD vs. AIN Level, fS = 105 MSPS,
fIN = 49.3 MHz and 50.3 MHz, Differential AIN, SFDR
Enabled
REV. 0
49.3
80.3
AIN – MHz
170.3
250.3
TPC 12. SNR vs. AIN Frequency/Temperature,
fS = 105 MSPS, Differential AIN, SFDR Disabled
–9–
AD9433
–95
300
18
280
15
WORST OTHER (dBc)
3RD HARMONIC (dBc)
260
–80
2ND HARMONIC (dBc)
–75
9
240
IDD (mA)
220
6
200
3
–70
SNR (dB)
–65
0
125
180
–60
0
10
20
30
40
50
60
DUTY CYCLE HIGH – %
70
80
0.50
0.50
0.25
0.25
INL – LSBs
0.75
0
–0.25
–0.50
–0.50
512
1024
1536
2048
2560
3072
3584
–0.75
4095
0
512
1024
OUTPUT CODE
TPC 14. Integral Nonlinearity vs. Output Code
with SFDR Disabled
100
0
–0.25
0
50
75
ENCODE FREQUENCY – MHz
TPC 16. IDD and ICC vs. Encode Rate. fIN = 10.3 MHz,
Differential AIN @ –0.5 dBFS
0.75
–0.75
25
0
90
TPC 13. Dynamic Performance vs. Encode Duty Cycle
fS = 105 MSPS, fIN = 49.3 MHz, Differential AIN @ –0.5 dBFS,
SFDR Enabled
INL – LSBs
12
ICC (mA)
IDD – mA
–85
ICC – mA
DYNAMIC PERFORMANCE – dB
–90
1536
2048
2560
OUTPUT CODE
3072
3584
4095
TPC 17. Integral Nonlinearity vs. Output Code with
SFDR Enabled
0
0.5
–10
0.4
–20
0.3
–30
–40
0.1
–50
dB
DNL – LSBs
0.2
0
–60
–70
–0.1
–80
–0.2
–90
–0.3
–100
–0.4
–110
–120
–0.5
0
512
1024
1536
2048
2560
OUTPUT CODE
3072
3584
0
4095
TPC 15. Differential Nonlinearity vs. Output Code
7.68
15.36
FREQUENCY – MHz
23.04
30.72
TPC 18. FFT: fS = 61.44 MSPS, fIN = 46.08 MHz, 4 WCDMA
Carriers, Differential AIN, SFDR Enabled
–10–
REV. 0
AD9433
TYPICAL IF SAMPLING PERFORMANCE
0
0
SNR = 66.8dB
SFDR = 83.0dBFS
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
–120
0
15.0
7.5
22.5
30.0
37.5
FREQUENCY – MHz
45.0
52.5
0
TPC 19. FFT: fS = 105 MSPS, fIN = 70.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled
7.5
15.0
22.5
30.0
37.5
FREQUENCY – MHz
45.0
52.5
TPC 22. FFT: fS = 105 MSPS, fIN = 70.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Disabled
110
0
SNR = 65.5dB
SFDR = 78.0dBFS
–10
100
–20
90
–30
80
SNR/SFDR – dB
–40
–50
dB
SNR = 67.0dB
SFDR = 80.0dBFS
–10
dB
dB
–10
–60
–70
SFDR – dBFS
70
60
SFDR – dBc
50
SNR – dBFS
80dBFS REFERENCE LINE
40
–80
30
–90
fS = 105MSPS
fIN = 70.3MHz
DIFFERENTIAL AIN
SFDR ENABLED
20
–100
10
–110
–120
0
6.2
12.5
18.7 25.0 31.2 37.5 43.7
FREQUENCY – MHz
50.0
56.2
0
–90
62.5
–80
TPC 20. FFT: fS = 125 MSPS, fIN = 70.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled
–70
–60
–50
–40
–30
AIN LEVEL – dBFS
–20
–10
0
TPC 23. SNR/SFDR vs. AIN Level
–110
0
IMD3 – 85dBc
–10
–20
–100
–30
–90
–40
dBFS
dB
–50
–60
–80
–70
–70
–80
–90
fS = 105MSPS
fIN = 70.3MHz AND 69.3MHz
–60
–100
DIFFERENTIAL AIN
SFDR ENABLED
–110
–120
0
7.5
15.0
22.5
30.0
37.5
FREQUENCY – MHz
45.0
–50
–90
52.5
TPC 21. FFT: fS = 105 MSPS, fIN = 69.3 and 70.3 MHz,
Differential AIN @ –7 dBFS for Each Tone, SFDR Enabled
REV. 0
–80
–70
–60
–50
–40
dBFS
–30
–20
–10
0
TPC 24. Third Order IMD vs. AIN Level,
fS = 105 MSPS, fIN = 70.3 MHz and 69.3 MHz,
Differential AIN, SFDR Enabled
–11–
AD9433
0
0
SNR = 64.0dB
SFDR = 78.0dBFS
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
–120
0
7.5
15.0
22.5
30.0
37.5
FREQUENCY – MHz
45.0
52.5
TPC 25. FFT: fS = 105 MSPS, fIN = 150.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled
0
6.25
12.5
18.7
25.0 31.2 37.5 43.7
FREQUENCY – MHz
50.0
56.2
62.5
TPC 28. FFT: fS = 125 MSPS, fIN = 150.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled
0
0
SNR = 61.2dB
SFDR = 67.0dBFS
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
–120
0
7.5
15.0
SNR = 54.6dB
SFDR = 58.0dBFS
–10
dB
dB
SNR = 62.0dB
SFDR = 70.0dBFS
–10
dB
dB
–10
22.5
30.0
37.5
FREQUENCY – MHz
45.0
52.5
TPC 26. FFT: fS = 105 MSPS, fIN = 250.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled
0
6.2
12.5
18.7
25.0 31.2 37.5 43.7
FREQUENCY – MHz
50.0
56.2
62.5
TPC 29. FFT: fS = 125 MSPS, fIN = 350.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled
0
–110
SNR = 55.3dB
SFDR = 61.0dBFS
–10
–100
IMD3
–20
–90
–30
–80
–40
–70
dBFS
dB
–50
–60
–70
–60
–50
–40
–80
–90
–30
–100
–20
–110
–10
–120
0
7.5
15.0
22.5
30.0
37.5
FREQUENCY – MHz
45.0
0
–90
52.5
TPC 27. FFT: fS = 105 MSPS, fIN = 350.3 MHz, Differential
AIN @ –0.5 dBFS, SFDR Enabled
–80
–70
–60
–50
–40
dBFS
–30
–20
–10
0
TPC 30. Third Order IMD vs. AIN Level, fS = 105 MSPS,
fIN = 150.3 and 151.3 MHz, Differential AIN, SFDR Enabled
–12–
REV. 0
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
dB
dB
AD9433
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
–120
0
9.6
19.2
FREQUENCY – MHz
28.8
0
38.4
TPC 31. FFT: fS = 76.8 MSPS, fIN = 59.6 MHz, 2 WCDMA
Carriers, Differential AIN, SFDR Enabled
11.52
23.04
FREQUENCY – MHz
ENCODE
The AD9433 is a multibit pipeline converter that uses a switched
capacitor architecture. Optimized for high speed, this converter
provides flat dynamic performance up to and beyond the Nyquist
limit. DNL transitional errors are calibrated at final test to a
typical accuracy of 0.25 LSB or less.
PECL
GATE
AD9433
ENCODE
510
USING THE AD9433
ENCODE Input
The AD9433 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of ENCODE (falling edge
of ENCODE if driven differentially), and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern, and is not
reduced by the internal stabilization circuit. This circuit is
always on, and cannot be disabled by the user.
46.08
TPC 32. FFT: fS = 92.16 MSPS, fIN = 70.3 MHz, WCDMA @
70.0 MHz, SFDR Enabled
APPLICATION NOTES
Theory of Operation
Any high-speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A track/hold circuit
is essentially a mixer, and any noise, distortion, or timing jitter
on the clock will be combined with the desired signal at the A/D
output. For that reason, considerable care has been taken in the
design of the ENCODE input of the AD9433, and the user is
advised to give commensurate thought to the clock source.
34.56
510
Figure 7. Using PECL to Drive the ENCODE Inputs
Often, the cleanest clock source is a crystal oscillator producing
a pure, single-ended sine wave. In this configuration, or with
any roughly symmetrical, single-ended clock source, the signal
can be ac-coupled to the ENCODE input. To minimize jitter,
the signal amplitude should be maximized within the input
range described in Table I below. The 12 kΩ resistors to
ground at each of the inputs, in parallel with the internal bias
resistors, set the common-mode voltage to approximately 2.5 V,
allowing the maximum swing at the input. The ENCODE input
should be bypassed with a capacitor to ground to reduce noise.
This ensures that the internal bias voltage is centered on the
encode signal. For best dynamic performance, impedances at
ENCODE and ENCODE should match.
The ENCODE and ENCODE inputs are internally biased to
3.75 V (nominal), and support either differential or singleended signals. For best dynamic performance, a differential
signal is recommended. Good performance is obtained using
an MC10EL16 in the circuit to directly drive the encode
inputs, as illustrated in Figure 7.
ENCODE
0.1F
0.1F
50
SINE
SOURCE
12k
AD9433
ENCODE
50
25
12k
Figure 8. Single-Ended Sine Source Encode Circuit
REV. 0
–13–
AD9433
Shown in Figure 9 is another preferred method for clocking the
AD9433. The clock source (low jitter) is converted from singleended to differential using an RF transformer. The back-to-back
Schottky diodes across the transformer secondary limit clock
excursions into the AD9433 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock
from feeding through to the other portions of the AD9433, and
limits the noise presented to the ENCODE inputs. A crystal
clock oscillator can also be used to drive the RF transformer if
an appropriate limiting resistor (typically 100 Ω) is placed in the
series with the primary.
0.1F
CLOCK
SOURCE
100
T1–4T
ENCODE
AD9433
ENCODE
HMS2812
DIODES
Figure 9. Transformer-Coupled Encode Circuit
ENCODE Voltage Level Definition
The voltage level definitions for driving ENCODE and
ENCODE in single-ended and differential mode are shown
in Figure 10.
AIN
50
ANALOG
SIGNAL
SOURCE
ENCODE
750 mV
ENCODE
AIN
25
0.1F
AD9433
25
1:1
1:1
AIN
5.5 V
Figure 12. Driving the Analog Input with Two Transformers
for Improved Even-Order Harmonics
VCC + 0.5 V
3.750 V
4.25 V
Driving the ADC single-endedly will degrade performance,
particularly even-order harmonics. For best dynamic performance,
impedances at AIN and AIN should match.
Special care was taken in the design of the analog input section
of the AD9433 to prevent damage and corruption of data when
the input is overdriven.
VIHD
VILD
VIHS
VICM , V ECM
ENCODE
0.1F
AIN
In the highest frequency applications, two transformers connected in series may be necessary to minimize even-order
harmonic distortion. The first transformer will isolate and convert the signal to a differential signal, but the grounded input on
the primary side will degrade amplitude balance on the secondary winding. Capacitive coupling between the windings causes
this imbalance. Since one input to the first transformer is
grounded, there is little or no capacitive coupling, resulting in an
amplitude mismatch at the first transformers output. A second
transformer will improve the amplitude balance, and thus
improve the harmonic distortion. A wideband transformer, such
as the ADT1-1WT from Mini Circuits, is recommended for
these applications, as the bandwidth through the two transformers
will be reduced by the √2.
50
ANALOG
SIGNAL
SOURCE
VICM , V ECM
ENCODE
25
Figure 11. Transformer-Coupled Analog Input Circuit
Minimum Nominal Maximum
Differential Signal Amplitude 200 mV
(VID)
Input Voltage Range
–0.5 V
(VIHD, VILD, VIHS, VILS)
Internal Common-Mode Bias
(VICM)
External Common-Mode Bias 2.0 V
(VECM)
0.1F
1:1
Table I. ENCODE Inputs
Description
25
VILS
Figure 10. Differential and Single-Ended Input Levels
Analog Input
The analog input to the AD9433 is a differential buffer.
The input buffer is self-biased by an on-chip resistor divider
that nominally sets the dc common-mode voltage to 4 V (see
Equivalent Circuits section). Rated performance is achieved
by driving the input differentially. Minimum input offset voltage
is obtained when driving from a source with a low differential
source impedance, such as a transformer, in ac applications (See Figure 11). Capacitive coupling at the inputs will
increase the input offset voltage by as much as 50 mV.
SFDR Optimization
The SFDR MODE pin enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious free dynamic range
(SFDR) performance of the AD9433. It is useful in applications
where the dynamic range of the system is limited by discrete
spurious frequency content caused by nonlinearities in the ADC
transfer function.
Enabling this circuit will give the circuit a dynamic transfer
function, meaning that the voltage threshold between two
adjacent output codes may change from clock cycle to clock
cycle. While improving spurious frequency content, this
dynamic aspect of the transfer function may be inappropriate
for some time domain applications of the converter. Connecting
the SFDR MODE pin to ground will disable this function. The
typical performance curves section of the data sheet illustrates
the improvement in the linearity of the converter and its effect
on spurious free dynamic range (TPC 1, 2, 15, 18).
–14–
REV. 0
AD9433
Digital Outputs
Layout Information
The digital outputs are 3 V (2.7 V to 3.3 V) TTL/CMOScompatible for lower power consumption. The output data
format is selectable through the data format select (DFS)
CMOS input. DFS = 1 selects offset binary; DFS = 0 selects
two’s complement coding.
The schematic and layout of the evaluation board (Figures 13–21)
represents a typical implementation of the AD9433. A multilayer board is recommended to achieve best results. It is highly
recommended that high quality, ceramic chip capacitors be used
to decouple each supply pin to ground directly at the device.
The pinout of the AD9433 facilitates ease of use in the implementation of high frequency, high resolution design practices. All of the
digital outputs and their supply and ground pin connections are
segregated to one side of the package, with the inputs on the
opposite side for isolation purposes.
Table II. Offset Binary Output Coding (DFS = 1, VREF = 2.5 V)
Code
AIN – AIN (V)
Range = 2 V p-p
Digital
Output
4095
+1.000
1111 1111 1111
●
●
●
●
●
●
2048
2047
0
–0.00049
1000 0000 0000
0111 1111 1111
●
●
●
●
●
●
0
–1.000
0000 0000 0000
Table III. Two’s Complement Output Coding (DFS = 0, VREF = 2.5 V)
Code
AIN – AIN (V)
Range = 2 V p-p
Digital
Output
+2047
+1.000
0111 1111 1111
●
●
●
●
●
●
0
–1
0
–0.00049
0000 0000 0000
1111 1111 1111
●
●
●
●
●
●
–2048
–1.000
1000 0000 0000
Care should be taken when routing the digital output traces. To
prevent coupling through the digital outputs into the analog portion of
the AD9433 (VCC, AIN, and VREF), minimal capacitive loading
should be placed on these outputs.
It is recommended that a fan-out of only one gate should be used
for all AD9433 digital outputs.
The layout of the encode circuit is equally critical, and should
be treated as an analog input. Any noise received on this circuitry
will result in corruption in the digitization process and lower
overall performance. The Encode clock must be isolated from
the digital outputs and the analog inputs.
Replacing the AD9432 with the AD9433
The AD9433 is pin-compatible with the AD9432, although
there are two control pins on the AD9433 that do not connect
(DNC) and supply (VCC) connections on the AD9432. They are
summarized in the table below.
Table IV. AD9432/AD9433 Pin Differences
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9433 (VREFOUT). In normal operation the internal reference
is used by strapping Pin 45 to Pin 46 and placing a 0.1 ␮F
decoupling capacitor at VREFIN. The input range can be
adjusted by varying the reference voltage applied to the
AD9433. No appreciable degradation in performance occurs
when the reference is adjusted to 50. The full-scale range of the
ADC tracks reference voltage changes linearly.
Timing
The AD9433 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (see Timing Diagram). The length of the output data lines and loads placed on
them should be minimized to reduce transients within the AD9433;
these transients can detract from the converter’s dynamic performance. The minimum guaranteed conversion rate of the
AD9433 is 10 MSPS. At internal clock rates below 10 MSPS,
dynamic performance may degrade.
REV. 0
Pin
AD9432
AD9433
41
42
DNC
VCC
DFS
SFDR MODE
Using the AD9433 in an AD9432 pin assignment will configure
the AD9433 as follows:
• The SFDR improvement circuit will be enabled.
• The DFS pin will float LOW, selecting two’s complement
coding for the digital outputs, which is the same as the AD9432.
Table V summarizes differences between the AD9432 and
AD9433 analog and encode input common-mode voltages.
These inputs may be ac-coupled so that the devices can be used
interchangeably.
Table V. Other AD9432/AD9433 Differences
Attribute
AD9432
AD9433
ENCODE/ENCODE VCOMMON MODE
AIN/AIN VCOMMON MODE
1.6 V
3.0 V
3.75 V
4.0 V
–15–
AD9433
Table VI. Power Supply Connections for the AD9433 Evaluation Board
Connector
Pin
Designator
External Supply Required
P42
P1, P3
P2
P4
P1, P3
P2
P4
GND
–5 V (Optional U10 Supply)
VDL
GND
VO
VCC
Ground
–5 V
+3 V
Ground
+3 V
+5 V
P43
The AD9433 evaluation board offers designers an easy way to
evaluate device performance. The user must supply an analog
input signal, encode clock reference, and power supplies. The
digital outputs of the AD9433 are latched on the evaluation
board, and are available with a data ready signal at a 40-pin
edge connector. Please refer to the evaluation board schematic,
layout, and bill of materials that follow.
10 mA
325 mA Without U10
355 mA With U10
Analog Input
The analog input signal is ac-coupled to the evaluation board by
SMB connector P39. Transformers T1 and T2 (ADT1-1WT)
convert this signal to a differential signal to drive AIN and AIN
of the AD9433. These RF transformers are specified as 1:1, but
their turns ratio is actually 6:7. T1 is rotated 180° and mounted
on the board such that its secondary and primary are reversed,
making its ratio 7:6. The second transformer in series now form
a combined 1:1 turns ration for the analog signal, and provide a
50 Ω termination for connector J1 via 25 Ω resistors R3 and R4.
Resistor R3, normally omitted, can be used to terminate P39 if
the transformers are removed for single ended drive. In this
configuration, the user will need to short the input signal from
Pin 3 of T1 to Pin 6 of T2, and remove resistor R4. Resistor R3
should remain in place to match the impedance of AIN and AIN.
Power Connections
Power to the board is supplied via two detachable, four-pin
power strips (P42 and P43). These eight pins should be driven
as outlined in Table VI. Please note that the –5 V supply is
optional, and only required if the user adds differential op amp
U10 to the board.
Jumper Options
The table below describes the jumper options on the AD9433
Evaluation board.
Table VII. AD9433 Evaluation Board Jumper Options
Using the AD8350
Jumper
Designation
Connection
Configuration
SFDR
5V
SFDR Enhancement
Circuit Enabled
SFDR Enhancement
Circuit Disabled
Offset Binary Output
Data Format
Two’s Complement
Output Data Storage
Output Register (U7–U8)
Clock is Buffered
Output Register (U7–U8)
Clock is Inverted
Data Ready Signal is
Buffered
Data Ready Signal is
Inverted
GND
5V
GND
LATCH
30 mA
144 mA
the AD9433. U1 (DS90LV048A) also converts the signal at P38
to a CMOS level signal to drive the clock inputs of the two output data registers U7–U8, (74LVT574WM), the reconstruction
DAC U3 (AD9772AAST), and the output data connector.
Evaluation Board
DFS
Approximate Current Level
E10 to E6
E10 to E5
DATA READY E7 to E8
E7 to E9
Encode Signal and Distribution
The encode input signal should drive SMB connector P38,
which has an on-board 50 Ω termination. This signal is ac-coupled,
and may be either a low jitter pulse or a sine wave reference,
with up to 4 V p-p amplitude. U2 (MC10EP16) converts this
single-ended input signal to a differential PECL signal to drive
An optional driver circuit for the analog input, based on the
AD8350 differential amplifier, is included in the layout of the
AD9433 evaluation board. This portion of the evaluation circuit
is not populated when the board is manufactured, but can be
easily added by the user. Removing resistors R29 and R30 will
disconnect the normal analog input signal path, and populating
R17 and R31 will connect the AD8350 output network.
DAC Reconstruction Circuit
The data available at output connector U2 is also reconstructed
by DAC U3, the AD772A. This 14-bit, high-speed digital-toanalog converter is included as a tool in setting up and debugging the
evaluation board. It should not be used to measure the performance
of the AD9433, as its performance will not accurately reflect the
performance of the ADC. As configured on the AD9433 evaluation
board, the AD9772A divides the input clock frequency by a factor
of two, and ignores every other sample from the AD9433. The
AD9772 internally interpolates the missing samples so that the
DAC output will reflect the input of the AD9433 only when the
analog input frequency is less than or equal to 1/4 the ADC
encode rate. The AD9772 requires offset binary format so the
DFS jumper should be connected to 5 V. The DAC’s output,
available at J1, will drive 50 Ω. The user may move the jumper
wire between E43 and E42 to connect E43 to E44, thus activating
the SLEEP function of the DAC.
–16–
REV. 0
AD9433
Evaluation Board Bill of Materials
Item
Qty
Reference Designator
Device
1
2
3
4
5
6
7
8
1
1
1
1
1
2
2
35
PCB
ADC
DAC
Quad LVDS/CMOS
Diff. ECL Receiver
D Flip-Flop
1:1 Transformer
Capacitor
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
3
1
2
2
4
3
3
2
2
1
2
2
3
1
2
AD9433/PCB
U4
U3
U1
U2
U7–U8
T1–T2
C1, C2, C4–C8, C10, C12–C18,
C20–C24, C27–C28, C30–C38, C42–
C43, C45, C48
C9, C40–C41
C11
R10, R23
R29–R30
R1–R2, R24–R25
R3–R4, R7
R6, R8, R14
R9, R13
R11, R16
R12
RZ1–RZ2
RZ4–RZ5
J1, P38–P39
P44
P42–P43
24
15
25
26*
27*
28*
29*
30*
31*
32*
33*
34*
35*
36*
4
1
1
7
1
2
2
2
2
6
1
6
E5–E7, E8–E10, E19–E21, E25–E27,
E31–E33
E28/E29, E36/E37, E39/E40, E42/E43
T3
U10
C3, C46–C47, C50–C53
C44
R15, R27
R18–R19
R20, R33
R21, R28
L1–L2, R17, R22, R31, C29, C49
P41
E30, E34–E35, E38, E41, E44
Value
QFP52
LQFP48
SO16
SO8NB
AD9433BST-XXX
AD9772AAST
DS90LV048A
MC10EP16
74LVT574WM
ADT1-1WT
0.1 µF
CD542
0603A
Capacitor
Capacitor
BRES603
BRES603
BRES603
BRES603
BRES603
BRES603
BRES603
BRES603
Resistor Pack
Resistor Pack
SMBPN
40 Pin Header
Power Connector
BCAPTAJD
0603A
0603A
0603A
0603A
0603A
0603A
0603A
0603A
0603A
SO16RES
SO16RES
SMB
C40MS
PTMICRO4
“E” Holes
Jumper Blocks
“E” Holes
1:1 Transformer
Op Amp
Capacitor
Capacitor
BRES604
BRES606
BRES608
BRES605
Select (R, L, C)
SMBPN
“E” Holes
Wire Straps
CD543
SO8
0603A
BCAPTAJD
0603A
0603A
0603A
0603A
0603A
SMB
Option Holes
*Items are included in the PCB design, but are omitted at assembly.
REV. 0
Package
–17–
10 µF
10 µF
50 Ω
33 Ω
510 Ω
25 Ω
2 kΩ
1.2 kΩ
1 kΩ
220 Ω
742C163221 (220 Ω)
742C163220 (22 Ω)
PC-Mount SMB
Samtec Tsw-120-07-G-D
Weiland
Z5.531.3425.0 Posts
25.602.5453.0 Top
TSW-120-07-G-S
SMT-100-BK-G
Short at Assembly
ADT1-1WT
AD8350
0.1 µF
10 µF
50 Ω
25 Ω
1.5 kΩ
100 Ω
Select
PC-Mount SMB
P39
SMBMST
OPTIONAL
GND
Figure 13. Evaluation Board Schematic
–18–
ENCODE
GND
P38
SMBMST
R23
50
C7
0.1F
AD8350
C4
0.1F
–5V
6
7
3
5
OUT–
OUT+
4 U10
C51
C29
C50
R12
220
R24
510
PRI
7:6
SEC
C24
6:7
PRI
Q
GND
VBB VEE
4
5
CLKN
C2
0.1F
R25
510
3
U2
10EL16
1
8
A VCC
2 CLK
Q
SEC
6
7
VCC
R2
510
GND
R17
C1
0.1F
C13
0.1F
R3
25
R4
25
R31
C49
R1
510
L2
L1
GND
T1 ADT1-WT1 T2 ADT1-WT1
4
1
3
6
2
5
2 C8 0.1F
5
GND
6
3
1
4
8
R21 C53
100 100nF IN–
R15
50
GND
R22
C3
OPTIONAL
SELECT
0.1F
GND
ANALOG
T1
R18
25
R19
25
2
GND
IN+
1
ENBL
VCC
GND
T18
T3
ADT1-WT1
4
1
2
5
3
6
AIN
AIN
R30
33
AIN
C11 10pF GND
C10
0.1F
R29
33
ENC
ENC
GND
GND
34 9 10
C15
0.1F
C14
0.1F
R9
1.2k
ENC
ENC
AIN
AIN
VREFOUT
VREFIN
GAIN
SCLK
DFS
SFDR
R13
1.2k
C17
0.1F
C16
0.1F
7
8
50
49
46
45
39
GND
GND
C6
0.1F
40
41
42
GND
U4
GND
C18
0.1F
VO
P5
PAD UNDER PART
GND
13 32 23 22 36 52 47 44 37 6 5 2
VCC
AD9433QFP52
R14
2k
R8
2k
VDL
8
7
6
5
3
4
2
1
VDL
10
VDL
OUT4
GND ENN ENP
12 9 16
IN4N
IN4P
IN3P
13
IN1N VCC OUT1 15
IN1P
14
IN2P
OUT2
IN2N
DS90LV04BATM
11
OUT3
IN3N
U1
GND
VDL
D3
D2
D1
D0
27
D3
28
D2
29
D1
30
D0
E7
E10
E9
E8
E6
E5
GND
19
20
25
26
DR
LATCH
D10
D9
D8
D7
D6
D5
D4
D10
D9
D8
D7
D6
D5
D4
17
18
16
OR
D11
14
VCC
15
OR
(MSB) D11
12 31 24 21 33 11 35 51 48 43 38 4 3 1
DGND
E19
E21
GND
E20
VCC
E27
E25
GND
E26
VCC
STRAPPED
E30
TO GND
E28
GND
E29 STRAPPED
VCC
E33 TO GND
E31
GND
E32
VCC
DGND
OPTIONAL
ANALOG INPUT
VDD
DGND
VCC
GND
GND
VDD
VDD
GND
OUT+
VDD
GND
R20
1.5k
VCC
GND
IN–
C52
100nF
GND
OUT–
R21
100
GND
R33
1.5k
VCC
GND
GND
GND
VCC
DGND
VCC
VCC
GND
VCC
VCC
VCC
VCC
GND
GND
IN+
AD9433
REV. 0
AD9433
GND
R7
25
GND
J1
R10
50
VDL
C34
0.1F
C33
0.1F
C12
0.1F
R6
2k
C5
0.1F
GND
GND GND
VDL
GND
GND
C38
0.1F
VDL
VDL
VDL
C42
0.1F
GND
GND
4
B9
5
B8
6
B7
7
B6
8
B5
9
B4
10
B3
11
ACOM
REFIO
REFLO
ACOM
FSADJ
IOUTB
IOUTA
AVDD
AVDD
DCOM
LPF
DB13
PLLVDD
DB12
PLLCOM
DB11
CLKVDD
AD9772A
DB10
CLKCOM
DB9
CLK+
U3
DB8
CLK–
DB7
DIV0
DB6
DIV1
DB5
RESET
DB4
PLLLOCK
DB3
DB2
DB1
DB0
B2
12
E44
SLEEP
36
35
VDL
E43
GND
E42
33
32
31
GND
VDL
GND
30
29
27
26
VDL
VDL
GND
E41
GND
VDL
E40
GND
E39
VDL
E38
STRAPPED TO
GROUND
E37
GND
E36
Figure 14. Evaluation Board Schematic
REV. 0
–19–
R16
1k
GND
GND
25
NC = NO CONNECT
B0
VDL
R11
1k
LATCH
28
13 14 15 16 17 18 19 20 21 22 23 24
B1
STRAPPED TO
GROUND
34
NC
NC
B10
DCOM
DCOM
DCOM
DVDD
DVDD
2
3
ACOM
1
MOD1
MOD0
GND
GND
B11
DVDD
DVDD
48 47 46 45 44 43 42 41 40 39 38 37
C43
0.1F
GND
AD9433
OPTIONAL
VCC
–5V
C48
0.1F
C44
10F
GND
C47
0.1F
+
GND
VDL
C45
DUT BYPASS – 0.1F
C22
VCC
GND
C41 +
10F
C30
C28
C23
C27
C32
C31
GND
OPTIONAL
P1
P2
P42 PTMICRO4
P3
1
2
3
P2
P43 PTMICRO4
P3
E34
–5V
VD
E35
VDL
C9 +
10F
C20
DUT BYPASS – 0.1F
VD
LATCHES – 0.1F
C40 +
10F
C21
C37
1
GND
GND
2
VO (+3V)
3
GND
VCC (+5V)
U8
RZ1 221
R5016I50
GND
1
OUT EN
D0
1
R1
16
2
2
R2
15
3
3
R3
14
4
4
R4
13
A0
5
D1
5
R5
12
A1
6
D2
6
R6
11
A2
7
D3
7
R7
10
A3
8
D4
8
R8
9
A4
9
10
GND
VCC
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
GND
CLOCK
20
RZ1 220
R5016I50
VDL
19
1
R1
16
18
2
R2
15
17
3
R3
14
16
4
R4
13
B0
15
5
R5
12
B1
14
6
R6
11
B2
13
7
R7
10
B3
5
12
8
R8
9
B4
7
11
P44
C40M5
GND
B0R
LATCH
74AC574M
GND
1
OUT EN
D0
D5
1
R1
16
A5
2
D6
2
R2
15
A6
3
D7
3
R3
14
A7
4
4
R4
5
R5
6
R6
D9
D10
D11
7
OR
8
R7
R8
B1
U7
RZ1 221
R5016I50
13
A8
A9
12
A10
11
5
6
7
10
A11
8
9
ADR
9
GND
10
VCC
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
20
VDL
CLOCK
B2
RZ1 220
R5016I50
B3
19
1
R1
16
B5
B4
18
2
R2
15
B6
B5
17
3
R3
14
B7
4
R4
5
R5
6
R6
16
15
14
13
GND
12
11
7
R7
8
R8
13
12
11
B8
B9
B10
10
B11
9
B0R
LATCH
H2
MTHOLES
B6
B7
B8
B9
B10
B11
GND
DR
GND
74AC574M
H1
MTHOLES
1
3
9
B0
D8
C35
C36
GND
VDL (+3V)
P4 4
D0
VDL
GND
P4 4
P1
GND
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
32
GND
34
GND
36
GND
38
40
GND
OPTIONAL
P41
5MBM5T
DR
R27
50
H3
MTHOLES
GND
H4
MTHOLES
GND
Figure 15. Evaluation Board Schematic
–20–
REV. 0
AD9433
AD9433 EVALUATION BOARD LAYOUT
REV. 0
Figure 16. Top Silkscreen
Figure 18. Ground Plane
Figure 17. Top Level Routing
Figure 19. Power Plane
–21–
AD9433
Figure 20. Bottom Layer Routing
Figure 21. Bottom Silkscreen
–22–
REV. 0
AD9433
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Thermally Enhanced
52-Lead Power Thin Plastic Quad Flatpack (LQFP_ED)
(SQ-52)
0.104 (2.65)
0.098 (2.50) (4 PLCS)
0.093 (2.35)
0.472 (12.00) SQ
0.307 (7.80)
52
40
1
40
39
27
14
1
0.236 (6.00)
0.232 (5.90)
0.228 (5.80)
EXPOSED
HEATSINK
(CENTERED)
27
26
0.026 (0.65)
52
39
0.402 (10.20)
0.394 (10.00) SQ
0.386 (9.80)
TOP VIEW
(PINS DOWN)
13
0.093 (2.35)
0.087 (2.20) (4 PLCS)
0.081 (2.05)
13
26
14
0.236 (6.00)
0.232 (5.90)
0.228 (5.80)
0.015 (0.38)
0.013 (0.32)
0.009 (0.22)
BOTTOM VIEW
(PINS UP)
0.063
(1.60)
MAX
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
SEATING
PLANE
VIEW A
0.006 (0.15)
0.002 (0.05)
0.004 (0.10)
COPLANARITY
VIEW A
NOTES
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED OFF MILLIMETER
EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
2. ALTHOUGH NOT REQUIRED IN ALL APPLICATIONS, THE AD9433 HAS AN EXPOSED METALLIC PAD ON THE
PACKAGE BOTTOM WHICH IS INTENDED TO ENHANCE THE HEAT REMOVAL PATH. TO MAXIMIZE THE REMOVAL
OF HEAT, A LAND PATTERN WITH CLOSELY SPACED THERMAL VIAS TO THE GROUND PLANE(S) SHOULD
BE INCORPORATED ON THE PCB WITHIN THE FOOTPRINT OF THE PACKAGE CORRESPONDING TO THE
EXPOSED METAL PAD DIMENSIONS OF THE PACKAGE. THE SOLDERABLE LAND AREA SHOULD BE SOLDER
MASK DEFINED AND BE AT LEAST THE SAME SIZE AND SHAPE AS THE EXPOSED PAD AREA ON THE
PACKAGE. AT LEAST 0.25 MM CLEARANCE BETWEEN THE OUTER EDGES OF THE LAND PATTERN AND THE
INNER EDGES OF THE PAD PATTERN SHOULD BE MAINTAINED TO AVOID ANY SHORTS.
REV. 0
–23–
–24–
PRINTED IN U.S.A.
C01977–.8–10/01(0)