NTD6416ANL, NVD6416ANL N-Channel Power MOSFET 100 V, 19 A, 74 mW Features Low RDS(on) High Current Capability 100% Avalanche Tested AEC−Q101 Qualified and PPAP Capable − NVD6416ANL These Devices are Pb−Free and are RoHS Compliant http://onsemi.com MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 100 V Gate−to−Source Voltage − Continuous VGS $20 V ID 19 A Continuous Drain Current Steady State Power Dissipation Steady State Pulsed Drain Current TC = 25°C TC = 100°C TC = 25°C tp = 10 ms Operating and Storage Temperature Range Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (VDD = 50 Vdc, VGS = 10 Vdc, IL(pk) = 18.2 A, L = 0.3 mH, RG = 25 W) Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds V(BR)DSS RDS(on) MAX ID MAX 100 V 74 mW @ 10 V 19 A D G 13 PD 71 W IDM 70 A TJ, Tstg −55 to +175 °C IS 19 A EAS 50 mJ 3 DPAK CASE 369AA STYLE 2 TL 260 °C Symbol Max Unit Junction−to−Case (Drain) − Steady State RqJC 2.1 °C/W Junction−to−Ambient − Steady State (Note 1) RqJA 47 S 4 4 1 2 THERMAL RESISTANCE RATINGS Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface mounted on FR4 board using 1 sq in pad size, (Cu Area 1.127 sq in [2 oz] including traces). 2 3 IPAK CASE 369D STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain 4 Drain YWW 64 16ANLG Parameter 1 1 Gate 2 Drain 6416ANL Y WW G YWW 64 16ANLG • • • • • 3 Source 1 Gate = Device Code = Year = Work Week = Pb−Free Package 2 Drain 3 Source ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2012 June, 2012 − Rev. 4 1 Publication Order Number: NTD6416ANL/D NTD6416ANL, NVD6416ANL ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 100 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 120 VGS = 0 V, VDS = 100 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA "100 mA nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On−Resistance RDS(on) Forward Transconductance 1.0 2.2 5.4 gFS V mV/°C VGS = 4.5 V, ID = 10 A 70 80 VGS = 10 V, ID = 10 A 62 74 VGS = 10 V, ID = 19 A 68 74 VDS = 5 V, ID = 10 A 18 mW S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance 700 VGS = 0 V, f = 1.0 MHz, VDS = 25 V 1000 pF 40 nC 110 CRSS 50 Total Gate Charge QG(TOT) 25 Threshold Gate Charge QG(TH) 0.7 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 9.6 Plateau Voltage VGP 3.2 V Gate Resistance RG 2.4 W td(on) 7.0 ns VGS = 10 V, VDS = 80 V, ID = 19 A 2.4 SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = 10 V, VDD = 80 V, ID = 19 A, RG = 6.1 W tf 16 35 40 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time Ta Discharge Time Reverse Recovery Charge Tb VGS = 0 V, IS = 19 A TJ = 25°C 0.9 TJ = 125°C 0.72 50 VGS = 0 V, dIS/dt = 100 A/ms, IS = 19 A QRR http://onsemi.com 2 V ns 38 14 112 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperatures. 1.2 nC NTD6416ANL, NVD6416ANL 40 40 4.5 V 30 3.6 V 20 3.2 V 10 3.0 V 2.8 V 0 30 20 TJ = 125°C 10 1 2 3 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0 5 0 1 2 3 4 VGS, GATE−TO−SOURCE VOLTAGE (V) ID = 19 A TJ = 25°C 0.1 0.09 0.08 0.07 0.06 2 4 6 8 10 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.080 TJ = 25°C 0.075 0.065 VGS = 10 V 0.060 0.055 0.050 2 6 10 14 18 ID, DRAIN CURRENT (A) Figure 4. On−Region versus Drain Current and Gate−To−Source Voltage 10000 3 VGS = 0 V VGS = 10 V ID = 19 A IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) VGS = 4.5 V 0.070 Figure 3. On−Region versus Gate−To−Source Voltage 2.5 5 Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 0.11 TJ = 25°C TJ = −55°C VGS = 2.4 V 0 VDS w 10 V 10 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) TJ = 25°C 2 1.5 TJ = 150°C 1000 TJ = 125°C 100 1 0.5 −50 −25 0 25 50 75 100 125 150 175 10 10 TJ, JUNCTION TEMPERTURE (°C) 20 30 40 50 60 70 80 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature 90 Figure 6. Drian−to−Source Leakage Current versus Voltage http://onsemi.com 3 10 NTD6416ANL, NVD6416ANL 1000 800 Ciss 600 400 200 0 0 1000 t, TIME (ns) Coss Crss 10 20 30 40 50 60 70 80 90 100 80 VGS 6 4 Qgs VDS = 80 V ID = 19 A TJ = 25°C 0 10 15 20 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−to−Source Voltage and Drain−to−Source Voltage versus Total Charge 20 0 25 20 VDS = 80 V ID = 19 A VGS = 10 V td(off) tf 10 td(on) 1 10 TJ = 25°C VGS = 0 V 15 10 5 0 0.5 100 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 50 EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) 100 ID, DRAIN CURRENT (A) 5 Figure 7. Capacitance Variation tr 10 mS 10 1 VGS = 10 V SINGLE PULSE TC = 25°C 0.1 100 mS 1 mS 10 mS dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.001 40 Qgd 2 0 60 VDS VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 1 8 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1200 100 QT IS, SOURCE CURRENT (A) C, CAPACITANCE (pF) TJ = 25°C VGS = 0 V VGS, GATE−TO−SOURCE VOLTAGE (V) 10 1400 0.1 1 10 100 1000 ID = 18.2 A 40 30 20 10 0 25 50 75 100 125 150 175 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 4 NTD6416ANL, NVD6416ANL 100 50% Duty Cycle RqJA (°C/W) 10 1 20% 10% 5% 2% 1% P(pk) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 RqJA(t) = r(t) RqJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJA(t) 10 100 1000 t, PULSE TIME (sec) Figure 13. Thermal Response (NTD6416ANL DPAK PCB Cu Area 720 mm2 PCB Cu thk 2 oz) ORDERING INFORMATION Package Shipping† NTD6416ANLT4G DPAK (Pb−Free) 2500 / Tape & Reel NTD6416ANL−1G IPAK (Pb−Free) 75 Units / Rail NVD6416ANLT4G DPAK (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 5 NTD6416ANL, NVD6416ANL PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA ISSUE B A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NTD6416ANL, NVD6416ANL PACKAGE DIMENSIONS IPAK CASE 369D ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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