MSP430F673x
MSP430F672x
www.ti.com
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
•
2
•
•
•
•
•
Low Supply Voltage Range: 1.8 V to 3.6 V
Ultra-Low Power Consumption
– Active Mode (AM):
All System Clocks Active
265 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
140 µA/MHz at 8 MHz, 3.0 V, RAM Program
Execution (Typical)
– Standby Mode (LPM3):
Real-Time Clock With Crystal, Watchdog,
and Supply Supervisor Operational, Full
RAM Retention, Fast Wake-Up:
1.7 µA at 2.2 V, 2.5 µA at 3.0 V (Typical)
– Off Mode (LPM4):
Full RAM Retention, Supply Supervisor
Operational, Fast Wake-Up:
1.6 µA at 3.0 V (Typical)
– Shutdown RTC Mode (LPM3.5):
Shutdown mode, Active Real Time Clock
with Crystal:
1.24 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.78 µA at 3.0 V (Typical)
Wake-Up From Standby Mode in 3 µs (Typical)
16-Bit RISC Architecture, Extended Memory,
up to 25-MHz System Clock
Flexible Power Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring,
and Brownout
– System Operation From up to Two Auxiliary
Power Supplies
Unified Clock System
– FLL Control Loop for Frequency
Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals (XT1)
One 16-Bit Timer With Three Capture/Compare
Registers
•
•
•
•
•
•
•
•
•
•
•
•
•
Three 16-Bit Timers With Two
Capture/Compare Registers Each
Enhanced Universal Serial Communication
Interfaces
– eUSCI_A0, eUSCI_A1, and eUSCI_A2 Each
Support:
– Enhanced UART Supporting AutoBaudrate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– eUSCI_B0 Supports:
– I2C With Multi-Slave Addressing
– Synchronous SPI
Password-Protected Real-Time Clock With
Crystal Offset Calibration and Temperature
Compensation
Separate Voltage Supply for Backup
Subsystem
– 32-kHz Low-Frequency Oscillator (XT1)
– Real-Time Clock
– Backup Memory (4 x 16 Bits)
Three 24-Bit Sigma-Delta Analog-to-Digital
(A/D) Converters With Differential PGA Inputs
Integrated LCD Driver With Contrast Control
for up to 320 Segments in 8-Mux Mode
Hardware Multiplier Supports 32-Bit
Operations
10-Bit 200-ksps A/D Converter
– Internal Reference
– Sample-and-Hold, Autoscan Feature
– Up to Six External Channels, Two Internal
Channels, Including Temperature Sensor
Three-Channel Internal DMA
Serial Onboard Programming, No External
Programming Voltage Needed
Family Members are Summarized in Table 1
Available in 100-Pin and 80-Pin LQFP
Packages
For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of others.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive lowpower modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in 3 µs
(typical).
The MSP430F67xx series are microcontroller configurations with three high-performance 24-bit sigma-delta A/D
converters, a 10-bit analog-to-digital (A/D) converter, four enhanced universal serial communication interfaces
(three eUSCI_A and one eUSCI_B), four 16-bit timers, hardware multiplier, DMA, real-time clock module with
alarm capabilities, LCD driver with integrated contrast control, auxiliary supply system, and up to 72 I/O pins in
100-pin devices and 52 I/O pins in 80-pin devices.
Typical applications for these devices are 2-wire and 3-wire single-phase metering, including tamper-resistant
meter implementations.
Family members available are summarized in Table 1.
Table 1. Family Members
eUSCI
Device
Flash
(KB)
SRAM
(KB)
SD24_B
Converters
ADC10_A
Channels
Timer_A (1)
Channel A:
UART, IrDA,
SPI
Channel B:
SPI, I2C
I/O
Package
Type
MSP430F6736IPZ
128
8
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6735IPZ
128
4
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6734IPZ
96
4
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6733IPZ
64
4
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6731IPZ
32
2
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6730IPZ
16
1
3
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6726IPZ
128
8
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6725IPZ
128
4
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6724IPZ
96
4
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6723IPZ
64
4
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6721IPZ
32
2
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6720IPZ
16
1
2
6 ext, 2 int
3, 2, 2, 2
3
1
72
100 PZ
MSP430F6736IPN
128
8
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6735IPN
128
4
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6734IPN
96
4
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6733IPN
64
4
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6731IPN
32
2
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6730IPN
16
1
3
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6726IPN
128
8
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6725IPN
128
4
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6724IPN
96
4
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6723IPN
64
4
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6721IPN
32
2
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
MSP430F6720IPN
16
1
2
3 ext, 2 int
3, 2, 2, 2
3
1
52
80 PN
(1)
2
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430F673x
MSP430F672x
www.ti.com
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 2. Ordering Information (1)
TA
PACKAGED DEVICES (2)
PLASTIC 100-PIN LQFP (PZ)
PLASTIC 80-PIN LQFP (PN)
MSP430F6736IPZ
MSP430F6736IPN
MSP430F6735IPZ
MSP430F6735IPN
MSP430F6734IPZ
MSP430F6734IPN
MSP430F6733IPZ
MSP430F6733IPN
MSP430F6731IPZ
MSP430F6731IPN
MSP430F6730IPZ
MSP430F6730IPN
MSP430F6726IPZ
MSP430F6726IPN
MSP430F6725IPZ
MSP430F6725IPN
MSP430F6724IPZ
MSP430F6724IPN
MSP430F6723IPZ
MSP430F6723IPN
MSP430F6721IPZ
MSP430F6721IPN
MSP430F6720IPZ
MSP430F6720IPN
–40°C to 85°C
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Copyright © 2011–2012, Texas Instruments Incorporated
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MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
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Functional Block Diagram, MSP430F673xIPZ, MSP430F672xIPZ
XIN
DVCC DVSS
XOUT
AVCC AVSS
AUX1 AUX2 AUX3
PA
P1.x P2.x
RST/NMI
PB
P3.x P4.x
PC
P5.x P6.x
P7.x
PD
P8.x
PE
P9.x
(32kHz)
ACLK
Unified
Clock
System
SMCLK
SYS
128kB
96KB
64KB
32KB
16KB
8kB
4KB
2KB
1KB
Flash
RAM
MCLK
Watchdog
Port
Mapping
Controller
MPY32
CRC16
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
I/O Ports
P7/P8
2×8 I/Os
I/O Ports
P9
1×4 I/O
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
PE
1×4 I/O
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 3+1)
PMM
Auxiliary
Supplies
JTAG/
SBW
Interface/
LDO
SVM/SVS
BOR
Port PJ
SD24_B
3 Channel
2 Channel
LCD_C
ADC10_A
10 Bit
200 KSPS
REF
8MUX
Up to 320
Segments
RTC_C
Reference
1.5V, 2.0V,
2.5V
Timer_A
3 CC
Registers
PJ.x
eUSCI_A0
eUSCI_A1
eUSCI_A2
TA1
TA2
TA3
TA0
Timer_A
2 CC
Registers
(UART,
IrDA,SPI)
eUSCI_B0
(SPI, I2C)
DMA
3 Channel
Functional Block Diagram, MSP430F673xIPN, MSP430F672xIPN
XIN
XOUT
DVCC DVSS
AVCC AVSS
AUX1 AUX2 AUX3
PA
P1.x P2.x
RST/NMI
PB
P3.x P4.x
PC
P5.x P6.x
(32kHz)
ACLK
Unified
Clock
System
SMCLK
MCLK
128KB
96KB
64KB
32KB
16KB
8KB
4KB
2KB
1KB
Flash
RAM
SYS
DMA
Watchdog
3 Channel
Port
Mapping
Controller
CRC16
MPY32
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
TA0
TA1
TA2
TA3
eUSCI_A0
eUSCI_A1
eUSCI_A2
Timer_A
3 CC
Registers
Timer_A
2 CC
Registers
(UART,
IrDA,SPI)
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 3+1)
JTAG/
SBW
Interface/
Port PJ
PMM
Auxiliary
Supplies
LDO
SVM/SVS
BOR
SD24_B
3 Channel
2 Channel
ADC10_A
10 Bit
200 KSPS
LCD_C
8MUX
Up to 320
Segments
REF
Reference
1.5V, 2.0V,
2.5V
RTC_C
eUSCI_B0
(SPI, I2C)
PJ.x
4
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MSP430F673x
MSP430F672x
www.ti.com
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
P6.1/S18
P6.2/S17
P6.3/S16
P6.4/S15
P6.5/S14
P6.6/S13
P6.7/S12
P7.0/S11
P7.1/S10
P7.2/S9
P7.3/S8
P7.4/S7
P7.5/S6
P7.6/S5
P7.7/S4
P8.0/S3
P8.1/S2
P8.2/S1
P8.3/S0
TEST/SBWTCK
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
RST/NMI/SBWTDIO
Pin Designation, MSP430F673xIPZ
SD0P0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
DVSS
SD0N0
2
74
DVSYS
SD1P0
3
73
P6.0/S19
SD1N0
4
72
P5.7/S20
SD2P0
5
71
P5.6/S21
SD2N0
6
70
P5.5/S22
VREF
7
69
P5.4/S23
AVSS
8
68
P5.3/S24
AVCC
9
67
P5.2/S25
VASYS
10
66
P5.1/S26
P9.1/A5
11
65
P5.0/S27
P9.2/A4
12
64
P4.7/S28
P9.3/A3
13
63
P4.6/S29
P1.0/PM_TA0.0/VeREF-/A2
14
62
P4.5/S30
P1.1/PM_TA0.1/VeREF+/A1
15
61
P4.4/S31
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
16
60
P4.3/S32
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
17
59
P4.2/S33
AUXVCC2
18
58
P4.1/S34
AUXVCC1
19
57
P4.0/S35
VDSYS
20
56
P3.7/PM_SD2DIO/S36
DVCC
21
55
P3.6/PM_SD1DIO/S37
DVSS
22
54
P3.5/PM_SD0DIO/S38
VCORE
23
53
P3.4/PM_SDCLK/S39
XIN
24
52
P3.3/PM_TA0.2
P3.2/PM_TACLK/PM_RTCCLK
P3.1/PM_TA2.1/BSL_RX
P3.0/PM_TA2.0/BSL_TX
P2.7/PM_TA1.1
P2.6/PM_TA1.0
P2.5/PM_UCA2CLK
P2.4/PM_UCA1CLK
P2.3/PM_UCA2TXD/PM_UCA2SIMO
P2.2/PM_UCA2RXD/PM_UCA2SOMI
P9.0/TACLK/RTCCLK
P8.7/TA2.1
P8.6/TA2.0
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P1.7/PM_UCB0CLK/COM5
P1.6/PM_UCA0CLK/COM4
COM3
COM2
COM1
COM0
P8.5/TA1.1
P8.4/TA1.0
LCDCAP/R33
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
AUXVCC3
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
XOUT
PZ PACKAGE
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default
mapping. See Table 14 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Copyright © 2011–2012, Texas Instruments Incorporated
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MSP430F672x
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Table 3. Pinout Differences Between MSP430F673xIPZ and MSP430F672xIPZ (1)
PIN NUMBER
(1)
6
PIN NAME
MSP430F673xIPZ
MSP430F672xIPZ
1
SD0P0
SD0P0
2
SD0N0
SD0N0
3
SD1P0
SD1P0
4
SD1N0
SD1N0
5
SD2P0
NC
6
SD2N0
NC
7
VREF
VREF
53
P3.4/PM_SDCLK/S39
P3.4/PM_SDCLK/S39
54
P3.5/PM_SD0DIO/S38
P3.5/PM_SD0DIO/S38
55
P3.6/PM_SD1DIO/S37
P3.6/PM_SD1DIO/S37
56
P3.7/PM_SD2DIO/S36
P3.7/PM_NONE/S36
Signal names that differ between devices are indicated by italic typeface.
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MSP430F672x
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
P5.2/S13
P5.3/S12
P5.4/S11
P5.5/S10
P5.6/S9
P5.7/S8
P6.0/S7
P6.1/S6
P6.2/S5
P6.3/S4
P6.4/S3
P6.5/S2
P6.6/S1
P6.7/S0
TEST/SBWTCK
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
RST/NMI/SBWTDIO
Pin Designation, MSP430F673xIPN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SD0P0
1
60
DVSS
SD0N0
2
59
DVSYS
SD1P0
3
58
P5.1/S14
SD1N0
4
57
P5.0/S15
SD2P0
5
56
P4.7/S16
SD2N0
6
55
P4.6/S17
VREF
7
54
P4.5/S18
AVSS
8
53
P4.4/S19
AVCC
9
52
P4.3/S20
VASYS
10
51
P4.2/S21
P1.0/PM_TA0.0/VeREF-/A2
11
50
P4.1/S22
P1.1/PM_TA0.1/VeREF+/A1
12
49
P4.0/S23
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
13
48
P3.7/PM_SD2DIO/S24
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
14
47
P3.6/PM_SD1DIO/S25
AUXVCC2
15
46
P3.5/PM_SD0DIO/S26
AUXVCC1
16
45
P3.4/PM_SDCLK/S27
VDSYS
17
44
P3.3/PM_TA0.2/S28
DVCC
18
43
P3.2/PM_TACLK/PM_RTCCLK/S29
DVSS
19
42
P3.1/PM_TA2.1/S30/BSL_RX
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P3.0/PM_TA2.0/S31/BSL_TX
P2.7/PM_TA1.1/S32
P2.6/PM_TA1.0/S33
P2.5/PM_UCA2CLK/S34
P2.4/PM_UCA1CLK/S35
P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P1.7/PM_UCB0CLK/COM5
P1.6/PM_UCA0CLK/COM4
COM3
COM2
COM1
COM0
LCDCAP/R33
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
AUXVCC3
XIN
XOUT
VCORE
PN PACKAGE
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default
mapping. See Table 14 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
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Table 4. Pinout Differences Between MSP430F673xIPN and MSP430F672xIPN (1)
PIN NUMBER
(1)
8
PIN NAME
MSP430F673xIPN
MSP430F672xIPN
1
SD0P0
SD0P0
2
SD0N0
SD0N0
3
SD1P0
SD1P0
4
SD1N0
SD1N0
5
SD2P0
NC
6
SD2N0
NC
7
VREF
VREF
45
P3.4/PM_SDCLK/S27
P3.4/PM_SDCLK/S27
46
P3.5/PM_SD0DIO/S26
P3.5/PM_SD0DIO/S26
47
P3.6/PM_SD1DIO/S25
P3.6/PM_SD1DIO/S25
48
P3.7/PM_SD2DIO/S24
P3.7/PM_NONE/S24
Signal names that differ between devices are indicated by italic typeface.
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MSP430F672x
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Table 5. Terminal Functions, MSP430F67xxIPZ
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
SD0P0
1
I
SD24_B positive analog input for converter 0 (2)
SD0N0
2
I
SD24_B negative analog input for converter 0 (2)
SD1P0
3
I
SD24_B positive analog input for converter 1 (2)
SD1N0
4
I
SD24_B negative analog input for converter 1 (2)
SD2P0
5
I
SD24_B positive analog input for converter 2 (2) (not available on F672x devices)
SD2N0
6
I
SD24_B negative analog input for converter 2 (2) (not available on F672x devices)
VREF
7
I
SD24_B external reference voltage
AVSS
8
Analog ground supply
AVCC
9
Analog power supply
VASYS
10
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended
Operating Conditions).
P9.1/A5
11
I/O
General-purpose digital I/O
Analog input A5 - 10-bit ADC
P9.2/A4
12
I/O
General-purpose digital I/O
Analog input A4 - 10-bit ADC
P9.3/A3
13
I/O
General-purpose digital I/O
Analog input A3 - 10-bit ADC
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
Negative terminal for the ADC's reference voltage for an external applied reference
voltage
Analog input A2 - 10-bit ADC
P1.0/PM_TA0.0/VeREF-/A2
14
P1.1/PM_TA0.1/VeREF+/A1
15
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Positive terminal for the ADC's reference voltage for an external applied reference
voltage
Analog input A1 - 10-bit ADC
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
16
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in
Analog input A0 - 10-bit ADC
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
17
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out
Input/output port of lowest analog LCD voltage (V5)
AUXVCC2
18
Auxiliary power supply AUXVCC2
AUXVCC1
19
Auxiliary power supply AUXVCC1
VDSYS (3)
20
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended
Operating Conditions).
DVCC
21
Digital power supply
DVSS
22
Digital ground supply
VCORE
XIN
(1)
(2)
(3)
(4)
(4)
23
24
Regulated core power supply (internal use only, no external current loading)
I
Input terminal for crystal oscillator
I = input, O = output
It is recommended to short unused analog input pairs and connect them to analog ground.
The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Copyright © 2011–2012, Texas Instruments Incorporated
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Table 5. Terminal Functions, MSP430F67xxIPZ (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
XOUT
25
AUXVCC3
26
Auxiliary power supply AUXVCC3 for back up subsystem
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/LCDREF/R13
27
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master in
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
28
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out
Input/output port of second most positive analog LCD voltage (V2)
LCDCAP/R33
29
I/O
LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
P8.4/TA1.0
30
I/O
General-purpose digital I/O
Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output
P8.5/TA1.1
31
I/O
General-purpose digital I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
COM0
32
O
LCD common output COM0 for LCD backplane
COM1
33
O
LCD common output COM1 for LCD backplane
COM2
34
O
LCD common output COM2 for LCD backplane
COM3
35
O
LCD common output COM3 for LCD backplane
P1.6/PM_UCA0CLK/COM4
36
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 clock input/output
LCD common output COM4 for LCD backplane
P1.7/PM_UCB0CLK/COM5
37
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 clock input/output
LCD common output COM5 for LCD backplane
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
38
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
LCD common output COM6 for LCD backplane
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
39
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
LCD common output COM7 for LCD backplane
P8.6/TA2.0
40
I/O
General-purpose digital I/O
Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output
P8.7/TA2.1
41
I/O
General-purpose digital I/O
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
P9.0/TACLK/RTCCLK
42
I/O
General-purpose digital I/O
Timer clock input TACLK for TA0, TA1, TA2, TA3
RTCCLK clock output
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
43
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
44
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out
10
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O
Output terminal for crystal oscillator
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430F673x
MSP430F672x
www.ti.com
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 5. Terminal Functions, MSP430F67xxIPZ (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
P2.4/PM_UCA1CLK
45
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A1 clock input/output
P2.5/PM_UCA2CLK
46
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 clock input/output
P2.6/PM_TA1.0
47
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
P2.7/PM_TA1.1
48
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
P3.0/PM_TA2.0/BSL_TX
49
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
Bootstrap loader: Data transmit
P3.1/PM_TA2.1/BSL_RX
50
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
Bootstrap loader: Data receive
P3.2/PM_TACLK/PM_RTCCLK
51
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock
output
P3.3/PM_TA0.2
52
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
P3.4/PM_SDCLK/S39
53
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SD24_B bit stream clock input/output
LCD segment output S39
P3.5/PM_SD0DIO/S38
54
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SD24_B converter-0 bit stream data input/output
LCD segment output S38
P3.6/PM_SD1DIO/S37
55
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SD24_B converter-1 bit stream data input/output
LCD segment output S37
P3.7/PM_SD2DIO/S36
56
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SD24_B converter-2 bit stream data input/output (not available on
F672x devices)
LCD segment output S36
P4.0/S35
57
I/O
General-purpose digital I/O
LCD segment output S35
P4.1/S34
58
I/O
General-purpose digital I/O
LCD segment output S34
P4.2/S33
59
I/O
General-purpose digital I/O
LCD segment output S33
P4.3/S32
60
I/O
General-purpose digital I/O
LCD segment output S32
P4.4/S31
61
I/O
General-purpose digital I/O
LCD segment output S31
P4.5/S30
62
I/O
General-purpose digital I/O
LCD segment output S30
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Table 5. Terminal Functions, MSP430F67xxIPZ (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
P4.6/S29
63
I/O
General-purpose digital I/O
LCD segment output S29
P4.7/S28
64
I/O
General-purpose digital I/O
LCD segment output S28
P5.0/S27
65
I/O
General-purpose digital I/O
LCD segment output S27
P5.1/S26
66
I/O
General-purpose digital I/O
LCD segment output S26
P5.2/S25
67
I/O
General-purpose digital I/O
LCD segment output S25
P5.3/S24
68
I/O
General-purpose digital I/O
LCD segment output S24
P5.4/S23
69
I/O
General-purpose digital I/O
LCD segment output S23
P5.5/S22
70
I/O
General-purpose digital I/O
LCD segment output S22
P5.6/S21
71
I/O
General-purpose digital I/O
LCD segment output S21
P5.7/S20
72
I/O
General-purpose digital I/O
LCD segment output S20
P6.0/S19
73
I/O
General-purpose digital I/O
LCD segment output S19
DVSYS (5)
74
Digital power supply for I/Os
DVSS
75
Digital ground supply
P6.1/S18
76
I/O
General-purpose digital I/O
LCD segment output S18
P6.2/S17
77
I/O
General-purpose digital I/O
LCD segment output S17
P6.3/S16
78
I/O
General-purpose digital I/O
LCD segment output S16
P6.4/S15
79
I/O
General-purpose digital I/O
LCD segment output S15
P6.5/S14
80
I/O
General-purpose digital I/O
LCD segment output S14
P6.6/S13
81
I/O
General-purpose digital I/O
LCD segment output S13
P6.7/S12
82
I/O
General-purpose digital I/O
LCD segment output S12
P7.0/S11
83
I/O
General-purpose digital I/O
LCD segment output S11
P7.1/S10
84
I/O
General-purpose digital I/O
LCD segment output S10
(5)
12
The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
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MSP430F672x
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 5. Terminal Functions, MSP430F67xxIPZ (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PZ
P7.2/S9
85
I/O
General-purpose digital I/O
LCD segment output S9
P7.3/S8
86
I/O
General-purpose digital I/O
LCD segment output S8
P7.4/S7
87
I/O
General-purpose digital I/O
LCD segment output S7
P7.5/S6
88
I/O
General-purpose digital I/O
LCD segment output S6
P7.6/S5
89
I/O
General-purpose digital I/O
LCD segment output S5
P7.7/S4
90
I/O
General-purpose digital I/O
LCD segment output S4
P8.0/S3
91
I/O
General-purpose digital I/O
LCD segment output S3
P8.1/S2
92
I/O
General-purpose digital I/O
LCD segment output S2
P8.2/S1
93
I/O
General-purpose digital I/O
LCD segment output S1
P8.3/S0
94
I/O
General-purpose digital I/O
LCD segment output S0
TEST/SBWTCK
95
I
PJ.0/SMCLK/TDO
96
I/O
General-purpose digital I/O
SMCLK clock output
Test data output
PJ.1/MCLK/TDI/TCLK
97
I/O
General-purpose digital I/O
MCLK clock output
Test data input or Test clock input
PJ.2/ADC10CLK/TMS
98
I/O
General-purpose digital I/O
ADC10_A clock output
Test mode select
PJ.3/ACLK/TCK
99
I/O
General-purpose digital I/O
ACLK clock output
Test clock
RST/NMI/SBWTDIO
100
I/O
Reset input active low
Non-maskable interrupt input
Spy-Bi-Wire data input/output
Copyright © 2011–2012, Texas Instruments Incorporated
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
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Table 6. Terminal Functions, MSP430F67xxIPN
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PN
SD0P0
1
I
SD24_B positive analog input for converter 0 (2)
SD0N0
2
I
SD24_B negative analog input for converter 0 (2)
SD1P0
3
I
SD24_B positive analog input for converter 1 (2)
SD1N0
4
I
SD24_B negative analog input for converter 1 (2)
SD2P0
5
I
SD24_B positive analog input for converter 2 (2) (not available on F672x devices)
SD2N0
6
I
SD24_B negative analog input for converter 2 (2) (not available on F672x devices)
VREF
7
I
SD24_B external reference voltage
AVSS
8
Analog ground supply
AVCC
9
Analog power supply
VASYS
10
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended
Operating Conditions).
11
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
Negative terminal for the ADC's reference voltage for an external applied reference
voltage
Analog input A2 - 10-bit ADC
P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1
12
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Positive terminal for the ADC reference voltage for an external applied reference voltage
Analog input A1 - 10-bit ADC
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
13
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in
Analog input A0 - 10-bit ADC
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
14
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out
Input/output port of lowest analog LCD voltage (V5)
AUXVCC2
15
Auxiliary power supply AUXVCC2
AUXVCC1
16
Auxiliary power supply AUXVCC1
VDSYS (3)
17
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect
recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended
Operating Conditions).
DVCC
18
Digital power supply
DVSS
19
Digital ground supply
VCORE (4)
20
Regulated core power supply (internal use only, no external current loading)
XIN
21
I
Input terminal for crystal oscillator
XOUT
22
O
Output terminal for crystal oscillator
AUXVCC3
23
Auxiliary power supply AUXVCC3 for back up subsystem
24
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master in
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/LCDREF/R13
(1)
(2)
(3)
(4)
14
I/O
I = input, O = output
It is recommended to short unused analog input pairs and connect them to analog ground.
The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
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MSP430F672x
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 6. Terminal Functions, MSP430F67xxIPN (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PN
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
25
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out
Input/output port of second most positive analog LCD voltage (V2)
LCDCAP/R33
26
I/O
LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
COM0
27
O
LCD common output COM0 for LCD backplane
COM1
28
O
LCD common output COM1 for LCD backplane
COM2
29
O
LCD common output COM2 for LCD backplane
COM3
30
O
LCD common output COM3 for LCD backplane
P1.6/PM_UCA0CLK/COM4
31
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A0 clock input/output
LCD common output COM4 for LCD backplane
P1.7/PM_UCB0CLK/COM5
32
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 clock input/output
LCD common output COM5 for LCD backplane
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
LCD common output COM6 for LCD backplane
LCD segment output S39
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39
33
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38
34
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
LCD common output COM7 for LCD backplane
LCD segment output S38
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
35
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 UART receive data; eUSCI_A2 SPI slave out/master in
LCD segment output S37
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
36
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 UART transmit data; eUSCI_A2 SPI slave in/master out
LCD segment output S36
P2.4/PM_UCA1CLK/S35
37
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A1 clock input/output
LCD segment output S35
P2.5/PM_UCA2CLK/S34
38
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: eUSCI_A2 clock input/output
LCD segment output S34
P2.6/PM_TA1.0/S33
39
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
LCD segment output S33
P2.7/PM_TA1.1/S32
40
I/O
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
LCD segment output S32
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Table 6. Terminal Functions, MSP430F67xxIPN (continued)
TERMINAL
NAME
P3.0/PM_TA2.0/S31/BSL_TX
P3.1/PM_TA2.1/S30/BSL_RX
NO.
I/O (1)
DESCRIPTION
PN
41
42
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
LCD segment output S31
Bootstrap loader: Data transmit
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
LCD segment output S30
Bootstrap loader: Data receive
P3.2/PM_TACLK/PM_RTCCLK/
S29
43
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3; RTCCLK clock
output
LCD segment output S29
P3.3/PM_TA0.2/S28
44
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
LCD segment output S28
P3.4/PM_SDCLK/S27
45
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SD24_B bit stream clock input/output
LCD segment output S27
P3.5/PM_SD0DIO/S26
46
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SD24_B converter-0 bit stream data input/output
LCD segment output S26
P3.6/PM_SD1DIO/S25
47
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SD24_B converter-1 bit stream data input/output
LCD segment output S25
P3.7/PM_SD2DIO/S24
48
I/O
General-purpose digital I/O with mappable secondary function
Default mapping: SD24_B converter-2 bit stream data input/output (not available on
F672x devices)
LCD segment output S24
P4.0/S23
49
I/O
General-purpose digital I/O
LCD segment output S23
P4.1/S22
50
I/O
General-purpose digital I/O
LCD segment output S22
P4.2/S21
51
I/O
General-purpose digital I/O
LCD segment output S21
P4.3/S20
52
I/O
General-purpose digital I/O
LCD segment output S20
P4.4/S19
53
I/O
General-purpose digital I/O
LCD segment output S19
P4.5/S18
54
I/O
General-purpose digital I/O
LCD segment output S18
P4.6/S17
55
I/O
General-purpose digital I/O
LCD segment output S17
P4.7/S16
56
I/O
General-purpose digital I/O
LCD segment output S16
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Table 6. Terminal Functions, MSP430F67xxIPN (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PN
P5.0/S15
57
I/O
General-purpose digital I/O
LCD segment output S15
P5.1/S14
58
I/O
General-purpose digital I/O
LCD segment output S14
DVSYS (5)
59
Digital power supply for I/Os
DVSS
60
Digital ground supply
P5.2/S13
61
I/O
General-purpose digital I/O
LCD segment output S13
P5.3/S12
62
I/O
General-purpose digital I/O
LCD segment output S12
P5.4/S11
63
I/O
General-purpose digital I/O
LCD segment output S11
P5.5/S10
64
I/O
General-purpose digital I/O
LCD segment output S10
P5.6/S9
65
I/O
General-purpose digital I/O
LCD segment output S9
P5.7/S8
66
I/O
General-purpose digital I/O
LCD segment output S8
P6.0/S7
67
I/O
General-purpose digital I/O
LCD segment output S7
P6.1/S6
68
I/O
General-purpose digital I/O
LCD segment output S6
P6.2/S5
69
I/O
General-purpose digital I/O
LCD segment output S5
P6.3/S4
70
I/O
General-purpose digital I/O
LCD segment output S4
P6.4/S3
71
I/O
General-purpose digital I/O
LCD segment output S3
P6.5/S2
72
I/O
General-purpose digital I/O
LCD segment output S2
P6.6/S1
73
I/O
General-purpose digital I/O
LCD segment output S1
P6.7/S0
74
I/O
General-purpose digital I/O
LCD segment output S0
TEST/SBWTCK
75
I
PJ.0/SMCLK/TDO
76
I/O
General-purpose digital I/O
SMCLK clock output
Test data output
PJ.1/MCLK/TDI/TCLK
77
I/O
General-purpose digital I/O
MCLK clock output
Test data input or Test clock input
(5)
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
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Table 6. Terminal Functions, MSP430F67xxIPN (continued)
TERMINAL
NAME
NO.
I/O (1)
DESCRIPTION
PN
PJ.2/ADC10CLK/TMS
78
I/O
General-purpose digital I/O
ADC10_A clock output
Test mode select
PJ.3/ACLK/TCK
79
I/O
General-purpose digital I/O
ACLK clock output
Test clock
RST/NMI/SBWTDIO
80
I/O
Reset input active low
Non-maskable interrupt input
Spy-Bi-Wire data input/output
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SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
General-Purpose Register
R10
General-Purpose Register
R11
Instruction Set
General-Purpose Register
R12
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data. Table 7 shows examples of the three
types of instruction formats; Table 8 shows the
address modes.
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Table 7. Instruction Word Formats
INSTRUCTION WORD FORMAT
EXAMPLE
Dual operands, source-destination
ADD
R4,R5
Single operands, destination only
CALL
Relative jump, un/conditional
JNE
R8
OPERATION
R4 + R5 → R5
PC → (TOS), R8 → PC
Jump-on-equal bit = 0
Table 8. Address Mode Descriptions
(1)
ADDRESS MODE
S (1)
D (1)
Register
+
+
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
+
+
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
+
+
MOV EDE,TONI
Absolute
+
+
MOV & MEM, & TCDAT
Indirect
+
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
+
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
+
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
SYNTAX
EXAMPLE
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source, D = destination
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Operating Modes
The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No RAM retention, Backup RAM retained
– I/O pad state retention
– RTC clocked by low-frequency oscillator
– Wakeup from RST/NMI, RTC_C events, Ports P1 and P2
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No RAM retention, Backup RAM retained
– RTC is disabled
– I/O pad state retention
– Wakeup from RST/NMI, Ports P1 and P2
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 9. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-Up
External Reset
Watchdog Timeout, Key Violation
Flash Memory Key Violation
WDTIFG, KEYV (SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV) (1) (3)
(Non)maskable
0FFFCh
62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
Supply Switch
NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
61
Watchdog Timer_A Interval Timer
Mode
WDTIFG
Maskable
0FFF8h
60
eUSCI_A0 Receive/Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (4)
Maskable
0FFF6h
59
eUSCI_B0 Receive/Transmit
(1) (4)
Maskable
0FFF4h
58
ADC10_A
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG
(ADC10IV) (1) (4)
Maskable
0FFF2h
57
SD24_B
SD24_B Interrupt Flags (SD24IV) (1) (4)
Maskable
0FFF0h
56
Timer TA0
TA0CCR0 CCIFG0 (4)
Maskable
0FFEEh
55
Timer TA0
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV) (1) (4)
Maskable
0FFECh
54
eUSCI_A1 Receive/Transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV)
(1) (4)
Maskable
0FFEAh
53
eUSCI_A2 Receive/Transmit
UCA2RXIFG, UCA2TXIFG (UCA2IV) (1) (4)
Maskable
0FFE8h
52
(1) (4)
Maskable
0FFE6h
51
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1) (4)
Maskable
0FFE4h
50
Timer TA1
TA1CCR0 CCIFG0 (4)
Maskable
0FFE2h
49
Timer TA1
TA1CCR1 CCIFG1,
TA1IFG (TA1IV) (1) (4)
Maskable
0FFE0h
48
Maskable
0FFDEh
47
Maskable
0FFDCh
46
Maskable
0FFDAh
45
Auxiliary Supplies
(1)
(2)
(3)
(4)
UCB0RXIFG, UCB0TXIFG (UCB0IV)
Auxiliary Supplies Interrupt Flags (AUXIV)
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV)
Timer TA2
TA2CCR0 CCIFG0 (4)
Timer TA2
TA2CCR1 CCIFG1,
TA2IFG (TA2IV) (1) (4)
(1) (4)
(1) (4)
I/O Port P2
P2IFG.0 to P2IFG.7 (P2IV)
Maskable
0FFD8h
44
Timer TA3
TA3CCR0 CCIFG0 (4)
Maskable
0FFD6h
43
Timer TA3
TA3CCR1 CCIFG1,
TA3IFG (TA3IV) (1) (4)
Maskable
0FFD4h
42
LCD_C
LCD_C Interrupt Flags (LCDCIV) (1) (4)
Maskable
0FFD2h
41
RTC_C
RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1) (4)
Maskable
0FFD0h
40
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
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Table 9. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations (continued)
(5)
INTERRUPT SOURCE
INTERRUPT FLAG
Reserved
Reserved (5)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
0FFCEh
39
⋮
⋮
0FF80h
0, lowest
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
Memory Organization
Table 10. Memory Organization
Main Memory
(flash)
MSP430F6730
MSP430F6720
MSP430F6731
MSP430F6721
MSP430F6733
MSP430F6723
16kB
32kB
64kB
00FFFFh to 00FF80h
00FFFFh to 00FF80h
00FFFFh to 00FF80h
Bank 3
not available
not available
not available
Bank 2
not available
not available
not available
Bank 1
not available
16kB
00FFFFh to 00C000h
32kB
013FFFh to 00C000h
Bank 0
16kB
00FFFFh to 00C000h
16kB
00BFFFh to 008000h
32kB
00BFFFh to 004000h
1kB
2kB
4kB
Sector 3
not available
not available
not available
Sector 2
not available
not available
not available
Sector 1
not available
not available
2kB
002BFFh to 002400h
Sector 0
1kB
001FFFh to 001C00h
2kB
0023FFh to 001C00h
2kB
0023FFh to 001C00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
Total Size
Main: Interrupt
vector
Main: code
memory
RAM
Total Size
Information
memory (flash)
Bootstrap loader
(BSL) memory
(flash)
Peripherals
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Main Memory (flash)
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RAM
Information memory
(flash)
Bootstrap loader
(BSL) memory (flash)
Peripherals
MSP430F6735
MSP430F6725
MSP430F6736
MSP430F6726
96kB
128kB
128kB
Total
Size
Main: Interrupt vector
Main: code memory
MSP430F6734
MSP430F6724
00FFFFh to 00FF80h
00FFFFh to 00FF80h
00FFFFh to 00FF80h
Bank 3
not available
32kB
023FFFh to 01C000h
32kB
023FFFh to 01C000h
Bank 2
32kB
01BFFFh to 014000h
32kB
01BFFFh to 014000h
32kB
01BFFFh to 014000h
Bank 1
32kB
013FFFh to 00C000h
32kB
013FFFh to 00C000h
32kB
013FFFh to 00C000h
Bank 0
32kB
00BFFFh to 004000h
32kB
00BFFFh to 004000h
32kB
00BFFFh to 004000h
4kB
4kB
8kB
Sector 3
not available
not available
2kB
003BFFh to 003400h
Sector 2
not available
not available
2kB
0033FFh to 002C00h
Sector 1
2kB
002BFFh to 002400h
2kB
002BFFh to 002400h
2kB
002BFFh to 002400h
Sector 0
2kB
0023FFh to 001C00h
2kB
0023FFh to 001C00h
2kB
0023FFh to 001C00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
4 KB
000FFFh to 0h
Total
Size
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Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory via the BSL is protected by an user-defined password. BSL entry requires a specific entry
sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the
BSL and its implementation, see MSP430 Programming via the Bootstrap Loader (BSL) (SLAU319).
Table 11. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P3.0
Data transmit
P3.1
Data receive
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 12. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide (SLAU278) and MSP430 Programming Via the JTAG Interface (SLAU320).
Table 12. JTAG Pin Requirements and Functions
DEVICE SIGNAL
Direction
FUNCTION
PJ.3/ACLK/TCK
IN
JTAG clock input
PJ.2/ADC10CLK/TMS
IN
JTAG state control
PJ.1/MCLK/TDI/TCLK
IN
JTAG data input/TCLK input
PJ.0/SMCLK/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 13. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278) and MSP430 Programming Via
the JTAG Interface (SLAU320).
Table 13. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
24
Direction
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
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Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A can be locked separately.
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors of 2k bytes each.
• Each sector 0 to n can be complete disabled; however, data retention is lost.
• Each sector 0 to n automatically enters low-power retention mode when possible.
Backup RAM Memory
The Backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5. This Backup RAM
is part of Backup subsystem in MSP430F67xx that operates on dedicated power supply AUXVCC3.There are 8
bytes of Backup RAM available in this device. It can be wordwise accessed via the registers BAKMEM0,
BAKMEM1, BAKMEM2, and BAKMEM3. The Backup RAM registers can not be accessed by CPU when the high
side SVS is disabled by user.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
Oscillator and System Clock
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal
very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), and an
integrated internal digitally-controlled oscillator (DCO). The UCS module is designed to meet the requirements of
both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple
of the selected FLL reference frequency. The internal DCO provides a fast turn-on clock source and stabilizes in
3 µs (typical). The UCS module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, the internal low-frequency oscillator (VLO), or
the trimmed low-frequency oscillator (REFO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
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Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Auxiliary Supply System
The auxiliary supply system provides the possibility to operate the device from auxiliary supplies when the
primary supply fails.There are two auxililary supplies AUXVCC1 and AUXVCC2 supported in MSP430F67xx.
This module supports automatic and manual switching from primary supply to auxiliary suppllies while
maintaining full functionality. It allows threshold based monitoring of primary and auxiliary supplies. The device
can be started from primary supply or AUXVCC1, whichever is higher. Auxiliary supply system enables internal
monitoring of voltage levels on primary and auxiliary supplies using ADC10_A. Also this module implements
simple charger for backup supplies.
Backup Subsystem
The Backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes lowfrequency oscillator (XT1), Real-Time Clock module, and Backup RAM. The functionality of Backup subsystem is
retained during LPM3.5. The Backup susb-system module registers can not be accessed by CPU when the high
side SVS is disabled by user. It is necessary to keep the high side SVS enabled with SVSHMD = 1 and
SVSMHACE = 0 to turn off the low-frequency oscillator (XT1) in LPM4.
Digital I/O
There are up to nine 8-bit I/O ports implemented. For 100 pin options, Ports P1 to P8 are complete. P9 is
reduced to 4-bit I/O. For 80 pin options, Ports P1 to P6 are complete. P7, P8 and P9 are completely removed.
Port PJ contains four individual I/O pins, common to all devices. All I/O bits are individually programmable.
• Any combination of input, output and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Programmable drive strength on all ports.
• Edge-selectable interrupt and LPM3.5, LPM4.5 wakeup input capability available for all bits of ports P1 and
P2.
• Read-write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PE).
26
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Port Mapping Controller
The port mapping controller allows flexible and reconfigurable mapping of digital functions to P1, P2, and P3.
Table 14. Port Mapping, Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
1
2
3
4
5
6
7
8
9
10
PM_UCA0RXD
eUSCI_A0 UART RXD (direction controlled by eUSCI – Input)
PM_UCA0SOMI
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
PM_UCA0TXD
eUSCI_A0 UART TXD (direction controlled by eUSCI – Output)
PM_UCA0SIMO
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
PM_UCA0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
PM_UCA0STE
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA1RXD
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
PM_UCA1SOMI
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
PM_UCA1TXD
eUSCI_A1 UART TXD (direction controlled by eUSCI – Output)
PM_UCA1SIMO
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
PM_UCA1STE
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA2RXD
eUSCI_A2 UART RXD (direction controlled by eUSCI – Input)
PM_UCA2SOMI
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
PM_UCA2TXD
eUSCI_A2 UART TXD (direction controlled by eUSCI – Output)
PM_ UCA2SIMO
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
11
PM_UCA2CLK
eUSCI_A2 clock input/output (direction controlled by eUSCI)
12
PM_UCA2STE
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
13
14
PM_UCB0SIMO
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
PM_UCB0SDA
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
PM_UCB0SOMI
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
PM_UCB0SCL
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
15
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
16
PM_UCB0STE
eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI)
17
PM_TA0.0
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
18
PM_TA0.1
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
19
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
20
PM_TA1.0
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
21
PM_TA1.1
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
22
PM_TA2.0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
23
PM_TA2.1
TA2 CCR1 capture input CCI1A
TA2 CCR1 compare output Out1
24
PM_TA3.0
TA3 CCR0 capture input CCI0A
TA3 CCR0 compare output Out0
25
PM_TA3.1
TA3 CCR1 capture input CCI1A
TA3 CCR1 compare output Out1
PM_TACLK
Timer_A clock input to
TA0, TA1, TA2, TA3
None
None
RTC_C clock output
26
PM_RTCCLK
27
PM_SDCLK
SD24_B bit stream clock input/output (direction controlled by SD24_B)
28
PM_SD0DIO
SD24_B converter-0 bit stream data input/output (direction controlled by SD24_B)
29
PM_SD1DIO
SD24_B converter-1 bit stream data input/output (direction controlled by SD24_B)
30
PM_SD2DIO
31(0FFh) (1)
(1)
PM_ANALOG
SD24_B converter-2 bit stream data input/output (direction controlled by SD24_B)
Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross
currents when applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.
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Table 15. Default Mapping
PIN NAME
PZ
PN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
P1.0/PM_TA0.0/
VeREF-/A2
P1.0/PM_TA0.0/
VeREF-/A2
PM_TA0.0
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
P1.1/PM_TA0.1/
VeREF+/A1
P1.1/PM_TA0.1/
VeREF+/A1
PM_TA0.1
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
PM_UCA0RXD,
PM_UCA0SOMI
eUSCI_A0 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in
(direction controlled by eUSCI)
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
PM_UCA0TXD,
PM_UCA0SIMO
eUSCI_A0 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out
(direction controlled by eUSCI)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
PM_UCA1RXD,
PM_UCA1SOMI
eUSCI_A1 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in
(direction controlled by eUSCI)
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
PM_UCA1TXD,
PM_UCA1SIMO
eUSCI_A1 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out
(direction controlled by eUSCI)
P1.6/PM_UCA0CLK/
COM4
P1.6/PM_UCA0CLK/
COM4
PM_UCA0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
P1.7/PM_UCB0CLK/
COM5
P1.7/PM_UCB0CLK/
COM5
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39
PM_UCB0SOMI,
PM_UCB0SCL
eUSCI_B0 SPI slave out master in
(direction controlled by eUSCI),
eUSCI_B0 I2C clock
(open drain and direction controlled by eUSCI)
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38
PM_UCB0SIMO,
PM_UCB0SDA
eUSCI_B0 SPI slave in master out
(direction controlled by eUSCI),
eUSCI_B0 I2C data
(open drain and direction controlled by eUSCI)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
PM_UCA2RXD,
PM_UCA2SOMI
eUSCI_A2 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in
(direction controlled by eUSCI)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
PM_UCA2TXD,
PM_UCA2SIMO
eUSCI_A2 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out
(direction controlled by eUSCI)
P2.4/PM_UCA1CLK
P2.4/PM_UCA1CLK/S35
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
P2.5/PM_UCA2CLK
P2.5/PM_UCA2CLK/S34
PM_UCA2CLK
P2.6/PM_TA1.0
P2.6/PM_TA1.0/S33
PM_TA1.0
TA1 CCR0 capture input CCI0A
TA1 CCR0 compare output Out0
P2.7/PM_TA1.1
P2.7/PM_TA1.1/S32
PM_TA1.1
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
P3.0/PM_TA2.0
P3.0/PM_TA2.0/S31
PM_TA2.0
TA2 CCR0 capture input CCI0A
TA2 CCR0 compare output Out0
P3.1/PM_TA2.1
P3.1/PM_TA2.1/S30
PM_TA2.1
TA2 CCR1 capture input CCI1A
TA2 CCR1 compare output Out1
P3.2/PM_TACLK/
PM_RTCCLK
P3.2/PM_TACLK/
PM_RTCCLK/S29
PM_TACLK,
PM_RTCCLK
Timer_A clock input to
TA0, TA1, TA2, TA3
RTC_C clock output
P3.3/PM_TA0.2
P3.3/PM_TA0.2/S28
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
eUSCI_A2 clock input/output (direction controlled by eUSCI)
P3.4/PM_SDCLK/S39
P3.4/PM_SDCLK/S27
PM_SDCLK
SD24_B bit stream clock input/output
(direction controlled by SD24_B)
P3.5/PM_SD0DIO/S38
P3.5/PM_SD0DIO/S26
PM_SD0DIO
SD24_B converter-0 bit stream data input/output
(direction controlled by SD24_B)
P3.6/PM_SD1DIO/S37
P3.6/PM_SD1DIO/S25
PM_SD1DIO
SD24_B converter-1 bit stream data input/output
(direction controlled by SD24_B)
P3.7/PM_SD2DIO/S36
P3.7/PM_SD2DIO/S24
PM_SD2DIO
SD24_B converter-2 bit stream data input/output
(direction controlled by SD24_B)
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System Module (SYS)
The SYS module handles many of the system functions within the device. These include power on reset (POR)
and power up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators,
boot strap loader entry mechanisms, as well as, configuration management (device descriptors). It also includes
a data exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.
Table 16. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
SYSRSTIV, System Reset
INTERRUPT EVENT
WORD
ADDRESS
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (POR)
04h
DoBOR (BOR)
06h
Wakeup from LPMx.5 (BOR)
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
019Eh
SYSUNIV, User NMI
WDT timeout (PUC)
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
Highest
0Ah
JMBINIFG
0Ch
0Eh
VLRLIFG
10h
VLRHIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIFG
02h
OFIFG
Lowest
08h
019Ch
JMBOUTIFG
ACCVIFG
Highest
12h
14h
VMAIFG
PRIORITY
10h
DoPOR (POR)
DLYHIFG
SYSSNIV, System NMI
OFFSET
019Ah
Lowest
Highest
04h
06h
AUXSWNMIFG
08h
Reserved
0Ah to 1Eh
Lowest
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the timer can be configured as an interval timer and can generate
interrupts at selected time intervals.
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DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC10_A conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
Table 17. DMA Trigger Assignments (1)
Trigger
DMAREQ
1
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
4
Reserved
5
TA2CCR0 CCIFG
6
Reserved
7
TA3CCR0 CCIFG
8
Reserved
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
SD24IFG
14
Reserved
15
Reserved
16
UCA0RXIFG
17
UCA0TXIFG
18
UCA1RXIFG
19
UCA1TXIFG
20
UCA2RXIFG
21
UCA2TXIFG
22
UCB0RXIFG0
23
UCB0TXIFG0
24
ADC10IFG0
25
Reserved
26
Reserved
27
Reserved
28
Reserved
29
MPY ready
31
30
1
0
30
(1)
Channel
0
DMA2IFG
DMA0IFG
2
DMA1IFG
Reserved
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not
cause any DMA trigger event when selected.
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CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.
Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module supports for SPI (3 or 4 pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module supports for SPI (3 or 4 pin) or I2C.
Three eUSCI_A and one eUSCI_B module are implemented in MSP430F67xx devices.
ADC10_A
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and a conversion results buffer. A window comparator with a
lower and upper limit allows CPU independent result monitoring with three window comparator interrupt flags.
SD24_B
The SD24_B module integrates up to three independent 24-bit sigma-delta A/D converters. Each converter is
designed with a fully differential analog input pair and programmable gain amplifier input stage. The converters
are based on second-order over-sampling sigma-delta modulators and digital decimation filters. The decimation
filters are comb type filters with selectable oversampling ratios of up to 1024.
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TA0
TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 18. TA0 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
NA
NA
PM_TA0.0
CCR0
TA0
DVCC
VCC
PM_TA0.1
CCI1A
PM_TA0.1
ACLK (internal)
CCI1B
ADC10_A (internal)
ADC10SHSx = {1}
DVSS
GND
CCR1
DVCC
VCC
PM_TA0.2
CCI2A
DVSS
CCI2B
DVSS
GND
DVCC
VCC
TA1
SD24_B (internal)
SD24SCSx = {1}
PM_TA0.2
CCR2
TA2
TA1
TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 19. TA1 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
32
PM_TA1.1
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
DVCC
VCC
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MODULE BLOCK
Timer
MODULE OUTPUT
SIGNAL
NA
DEVICE OUTPUT
SIGNAL
PZ
NA
PM_TA1.0
CCR0
TA0
PM_TA1.1
CCR1
TA1
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TA2
TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA2 can support multiple
capture/compares, PWM outputs, and interval timing. TA2 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 20. TA2 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA2.0
CCI0A
DVSS
CCI0B
DVSS
GND
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
NA
NA
PM_TA2.0
CCR0
TA0
DVCC
VCC
PM_TA2.1
CCI1A
PM_TA2.1
ACLK (internal)
CCI1B
SD24_B (internal)
SD24SCSx = {2}
DVSS
GND
DVCC
VCC
CCR1
TA1
TA3
TA3 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA3 can support multiple
capture/compares, PWM outputs, and interval timing. TA3 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 21. TA3 Signal Connections
DEVICE INPUT SIGNAL
MODULE INPUT NAME
PM_TACLK
TACLK
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
DEVICE OUTPUT
SIGNAL
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
PM_TACLK
INCLK
PM_TA3.0
CCI0A
PM_TA3.0
DVSS
CCI0B
TA0
ADC10_A (internal)
ADC10SHSx = {2}
DVSS
GND
TA1
CCR0
DVCC
VCC
PM_TA3.1
CCI1A
PM_TA3.1
ACLK (internal)
CCI1B
SD24_B (internal)
SD24SCSx = {3}
DVSS
GND
DVCC
VCC
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SD24_B Triggers
Table 22 shows the input trigger connections to SD24_B converters from Timer_A modules and output trigger
pulse connection from SD24_B to ADC10_A.
Table 22. SD24_B Input/Output Trigger Connections
DEVICE INPUT SIGNAL MODULE INPUT SIGNAL
TA0.1 (internal)
SD24_B
SD24SCSx = {1}
TA2.1 (internal)
SD24_B
SD24SCSx = {2}
TA3.1 (internal)
SD24_B
SD24SCSx = {3}
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Trigger Pulse
ADC10_A (internal)
ADC10SHSx = {3}
SD24_B
ADC10_A Triggers
Table 23 shows input trigger connections to ADC10_A from Timer_A modules and SD24_B.
Table 23. ADC10_A Input Trigger Connections
DEVICE INPUT SIGNAL
MODULE INPUT SIGNAL
TA0.1 (internal)
ADC10_A
ADC10SHSx = {1}
TA3.0 (internal)
ADC10_A
ADC10SHSx = {2}
SD24_B
trigger pulse (internal)
ADC10_A
ADC10SHSx = {3}
MODULE BLOCK
ADC10_A
Real-Time Clock (RTC_C)
The RTC_C module can be configured for real-time clock (RTC) or calendar mode providing seconds, hours, day
of week, day of month, month, and year. The RTC_C control and configuration registers are password protected
to ensure clock integrity against runaway code. Calendar mode integrates an internal calendar that compensates
for months with less than 31 days and includes leap year correction. The RTC_C also supports flexible alarm
functions, offset calibration, and temperature compensation. The RTC_C on this device operates on dedicated
AUXVCC3 supply and supports operation in LPM3.5.
REF Voltage Reference
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device. These include the ADC10_A, LCD_C, and SD24_B modules.
LCD_C
The LCD_C driver generates the segment and common signals required to drive a liquid crystal display (LCD).
The LCD_C controller has dedicated data memories to hold segment drive information. Common and segment
signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, up to 8-mux LCDs are supported.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is
possible to control the level of the LCD voltage and thus contrast by software. The module also provides an
automatic blinking capability for individual segments in static, 2-mux, 3-mux, and 4-mux modes.
Embedded Emulation Module (EEM) (S Version)
The Embedded Emulation Module (EEM) supports real-time in-system debugging. The S version of the EEM
implemented on all devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
34
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Peripheral File Map
Table 24. Peripherals
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 25)
0100h
000h - 01Fh
PMM (see Table 26)
0120h
000h - 01Fh
Flash Control (see Table 27)
0140h
000h - 00Fh
CRC16 (see Table 28)
0150h
000h - 007h
RAM Control (see Table 29)
0158h
000h - 001h
Watchdog (see Table 30)
015Ch
000h - 001h
UCS (see Table 31)
0160h
000h - 01Fh
SYS (see Table 32)
0180h
000h - 01Fh
Shared Reference (see Table 33)
01B0h
000h - 001h
Port Mapping Control (see Table 34)
01C0h
000h - 007h
Port Mapping Port P1 (see Table 35)
01C8h
000h - 007h
Port Mapping Port P2 (see Table 36)
01D0h
000h - 007h
Port Mapping Port P3 (see Table 37)
01D8h
000h - 007h
Port P1/P2 (see Table 38)
0200h
000h - 01Fh
Port P3/P4 (see Table 39)
0220h
000h - 00Bh
Port P5/P6 (see Table 40)
0240h
000h - 00Bh
Port P7/P8 (see Table 41)
(Port P7/P8 not available in MSP430F67xxIPN)
0260h
000h - 00Bh
Port P9 (Port P9 not available in MSP430F67xxIPN)
(see Table 42)
0280h
000h - 00Bh
Port PJ (refer toTable 43)
0320h
000h - 01Fh
Timer TA0 (see Table 44)
0340h
000h - 03Fh
Timer TA1 (see Table 45)
0380h
000h - 03Fh
Timer TA2 (see Table 46)
0400h
000h - 03Fh
Timer TA3 (see Table 47)
0440h
000h - 03Fh
Backup Memory (see Table 48)
0480h
000h - 00Fh
RTC_C (see Table 49)
04A0h
000h - 01Fh
32-bit Hardware Multiplier (see Table 50)
04C0h
000h - 02Fh
DMA General Control (see Table 51)
0500h
000h - 00Fh
DMA Channel 0 (see Table 52)
0500h
010h - 01Fh
DMA Channel 1 (see Table 53)
0500h
020h - 02Fh
DMA Channel 2 (see Table 54)
0500h
030h - 03Fh
eUSCI_A0 (see Table 55)
05C0h
000h - 01Fh
eUSCI_A1 (see Table 56)
05E0h
000h - 01Fh
eUSCI_A2 (see Table 57)
0600h
000h - 01Fh
eUSCI_B0 (see Table 58)
0640h
000h - 02Fh
ADC10_A (see Table 59)
0740h
000h - 01Fh
SD24_B(see Table 60)
0800h
000h - 06Fh
Auxiliary Supply (see Table 54)
09E0h
000h - 01Fh
LCD_C (see Table 62)
0A00h
000h - 05Fh
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Table 25. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 26. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
SVS high side control
SVSMHCTL
04h
SVS low side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMM interrupt enable
PMMIE
0Eh
PMM Power Mode 5 control register 0
PM5CTL0
10h
Table 27. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 28. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC result
CRCINIRES
04h
Table 29. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
RCCTL0
OFFSET
00h
Table 30. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 31. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
36
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Table 32. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
Bootstrap loader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 33. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 34. Port Mapping Controller (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping password register
PMAPPWD
00h
Port mapping control register
PMAPCTL
02h
Table 35. Port Mapping for Port P1 (Base Address: 01C8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1.0 mapping register
P1MAP0
00h
Port P1.1 mapping register
P1MAP1
01h
Port P1.2 mapping register
P1MAP2
02h
Port P1.3 mapping register
P1MAP3
03h
Port P1.4 mapping register
P1MAP4
04h
Port P1.5 mapping register
P1MAP5
05h
Port P1.6 mapping register
P1MAP6
06h
Port P1.7 mapping register
P1MAP7
07h
Table 36. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P2.0 mapping register
P2MAP0
00h
Port P2.1 mapping register
P2MAP2
01h
Port P2.2 mapping register
P2MAP2
02h
Port P2.3 mapping register
P2MAP3
03h
Port P2.4 mapping register
P2MAP4
04h
Port P2.5 mapping register
P2MAP5
05h
Port P2.6 mapping register
P2MAP6
06h
Port P2.7 mapping register
P2MAP7
07h
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Table 37. Port Mapping for Port P3 (Base Address: 01D8h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3.0 mapping register
P3MAP0
00h
Port P3.1 mapping register
P3MAP3
01h
Port P3.2 mapping register
P3MAP2
02h
Port P3.3 mapping register
P3MAP3
03h
Port P3.4 mapping register
P3MAP4
04h
Port P3.5 mapping register
P3MAP5
05h
Port P3.6 mapping register
P3MAP6
06h
Port P3.7 mapping register
P3MAP7
07h
Table 38. Port P1/P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
Table 39. Port P3/P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
P4SEL
0Bh
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Table 40. Port P5/P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pullup/pulldown enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pullup/pulldown enable
P6REN
07h
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
Table 41. Port P7/P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 pullup/pulldown enable
P7REN
06h
Port P7 drive strength
P7DS
08h
Port P7 selection
P7SEL
0Ah
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 pullup/pulldown enable
P8REN
07h
Port P8 drive strength
P8DS
09h
Port P8 selection
P8SEL
0Bh
Table 42. Port P9 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 pullup/pulldown enable
P9REN
06h
Port P9 drive strength
P9DS
08h
Port P9 selection
P9SEL
0Ah
Table 43. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Port PJ selection
PJSEL
0Ah
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Table 44. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0 counter register
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
TA0 expansion register 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 45. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
TA1 counter register
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
TA1 expansion register 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 46. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
TA2 counter register
TA2R
10h
Capture/compare register 0
TA2CCR0
12h
Capture/compare register 1
TA2CCR1
14h
TA2 expansion register 0
TA2EX0
20h
TA2 interrupt vector
TA2IV
2Eh
Table 47. TA3 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA3 control
TA3CTL
00h
Capture/compare control 0
TA3CCTL0
02h
Capture/compare control 1
TA3CCTL1
04h
TA3 counter register
TA3R
10h
Capture/compare register 0
TA3CCR0
12h
Capture/compare register 1
TA3CCR1
14h
TA3 expansion register 0
TA3EX0
20h
TA3 interrupt vector
TA3IV
2Eh
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Table 48. Backup Memory Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Backup Memory 0
BAKMEM0
00h
Backup Memory 1
BAKMEM1
02h
Backup Memory 2
BAKMEM2
04h
Backup Memory 3
BAKMEM3
06h
Table 49. RTC_C Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC password
RTCPWD
01h
RTC control 1
RTCCTL1
02h
RTC control 3
RTCCTL3
03h
RTC offset calibration
RTCOCAL
04h
RTC temperature compensation
RTCTCMP
06h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds
RTCSEC
10h
RTC minutes
RTCMIN
11h
RTC hours
RTCHOUR
12h
RTC day of week
RTCDOW
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year
RTCYEAR
16h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion register
BIN2BCD
1Ch
BCD-to-Binary conversion register
BCD2BIN
1Eh
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Table 50. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
Table 51. DMA General Control Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Eh
Table 52. DMA Channel 0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
10h
DMA channel 0 source address low
DMA0SAL
12h
DMA channel 0 source address high
DMA0SAH
14h
DMA channel 0 destination address low
DMA0DAL
16h
DMA channel 0 destination address high
DMA0DAH
18h
DMA channel 0 transfer size
DMA0SZ
1Ah
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Table 53. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 1 control
DMA1CTL
20h
DMA channel 1 source address low
DMA1SAL
22h
DMA channel 1 source address high
DMA1SAH
24h
DMA channel 1 destination address low
DMA1DAL
26h
DMA channel 1 destination address high
DMA1DAH
28h
DMA channel 1 transfer size
DMA1SZ
2Ah
Table 54. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 2 control
DMA2CTL
30h
DMA channel 2 source address low
DMA2SAL
32h
DMA channel 2 source address high
DMA2SAH
34h
DMA channel 2 destination address low
DMA2DAL
36h
DMA channel 2 destination address high
DMA2DAH
38h
DMA channel 2 transfer size
DMA2SZ
3Ah
Table 55. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI _A control word 1
UCA0CTLW1
02h
eUSCI_A baud rate 0
UCA0BR0
06h
eUSCI_A baud rate 1
UCA0BR1
07h
eUSCI_A modulation control
UCA0MCTLW
08h
eUSCI_A status
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
UCA0IRTCTL
12h
eUSCI_A IrDA receive control
UCA0IRRCTL
13h
eUSCI_A interrupt enable
UCA0IE
1Ah
eUSCI_A interrupt flags
UCA0IFG
1Ch
eUSCI_A interrupt vector word
UCA0IV
1Eh
Table 56. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA1CTLW0
00h
eUSCI _A control word 1
UCA1CTLW1
02h
eUSCI_A baud rate 0
UCA1BR0
06h
eUSCI_A baud rate 1
UCA1BR1
07h
eUSCI_A modulation control
UCA1MCTLW
08h
eUSCI_A status
UCA1STAT
0Ah
eUSCI_A receive buffer
UCA1RXBUF
0Ch
eUSCI_A transmit buffer
UCA1TXBUF
0Eh
eUSCI_A LIN control
UCA1ABCTL
10h
eUSCI_A IrDA transmit control
UCA1IRTCTL
12h
eUSCI_A IrDA receive control
UCA1IRRCTL
13h
eUSCI_A interrupt enable
UCA1IE
1Ah
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Table 56. eUSCI_A1 Registers (Base Address:05E0h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A interrupt flags
UCA1IFG
1Ch
eUSCI_A interrupt vector word
UCA1IV
1Eh
Table 57. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA2CTLW0
00h
eUSCI _A control word 1
UCA2CTLW1
02h
eUSCI_A baud rate 0
UCA2BR0
06h
eUSCI_A baud rate 1
UCA2BR1
07h
eUSCI_A modulation control
UCA2MCTLW
08h
eUSCI_A status
UCA2STAT
0Ah
eUSCI_A receive buffer
UCA2RXBUF
0Ch
eUSCI_A transmit buffer
UCA2TXBUF
0Eh
eUSCI_A LIN control
UCA2ABCTL
10h
eUSCI_A IrDA transmit control
UCA2IRTCTL
12h
eUSCI_A IrDA receive control
UCA2IRRCTL
13h
eUSCI_A interrupt enable
UCA2IE
1Ah
eUSCI_A interrupt flags
UCA2IFG
1Ch
eUSCI_A interrupt vector word
UCA2IV
1Eh
Table 58. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
eUSCI_B received address
UCB0ADDRX
1Ch
eUSCI_B address mask
UCB0ADDMASK
1Eh
eUSCI I2C slave address
UCB0I2CSA
20h
eUSCI interrupt enable
UCB0IE
2Ah
eUSCI interrupt flags
UCB0IFG
2Ch
eUSCI interrupt vector word
UCB0IV
2Eh
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Table 59. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_A Control register 0
ADC10CTL0
00h
ADC10_A Control register 1
ADC10CTL1
02h
ADC10_A Control register 2
ADC10CTL2
04h
ADC10_A Window Comparator Low Threshold
ADC10LO
06h
ADC10_A Window Comparator High Threshold
ADC10HI
08h
ADC10_A Memory Control Register 0
ADC10MCTL0
0Ah
ADC10_A Conversion Memory Register
ADC10MCTL0
12h
ADC10_A Interrupt Enable
ADC10IE
1Ah
ADC10_A Interrupt Flags
ADC10IGH
1Ch
ADC10_A Interrupt Vector Word
ADC10IV
1Eh
Table 60. SD24_B Registers (Base Address: 0800h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SD24_B Control 0 register
SD24BCTL0
00h
SD24_B Control 1 register
SD24BCTL1
02h
SD24_B Trigger Control register
SD24BTRGCTL
04h
SD24_B Trigger OSR Control register
SD24BTRGOSR
06h
SD24_B Trigger Preload register
SD24BTRGPRE
08h
SD24_B interrupt flag register
SD24BIFG
0Ah
SD24_B interrupt enable register
SD24BIE
0Ch
SD24_B Interrupt Vector register
SD24BIV
0Eh
SD24_B converter 0 Control register
SD24BCCTL0
10h
SD24_B converter 0 Input Control register
SD24BINCTL0
12h
SD24_B converter 0 OSR Control register
SD24BOSR0
14h
SD24_B converter 0 Preload register
SD24BPRE0
16h
SD24_B converter 1 Control register
SD24BCCTL1
18h
SD24_B Converter 1 Input Control register
SD24BINCTL1
1Ah
SD24_B Converter 1 OSR Control register
SD24BOSR1
1Ch
SD24_B Converter 1 Preload register
SD24BPRE1
1Eh
SD24_B Converter 2 Control register
SD24BCCTL2
20h
SD24_B Converter 2 Input Control register
SD24BINCTL2
22h
SD24_B Converter 2 OSR Control register
SD24BOSR2
24h
SD24_B Converter 2 Preload register
SD24BPRE2
26h
SD24_B Converter 0 Conversion Memory Low Word register
SD24BMEML0
50h
SD24_B Converter 0 Conversion Memory High Word regiser
SD24BMEMH0
52h
SD24_B Converter 1 Conversion Memory Low Word register
SD24BMEML1
54h
SD24_B Converter 1 Conversion Memory High Word regiser
SD24BMEMH1
56h
SD24_B Converter 2 Conversion Memory Low Word register
SD24BMEML2
58h
SD24_B Converter 2 Conversion Memory High Word regiser
SD24BMEMH2
5Ah
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Table 61. Auxiliary Supplies Registers (Base Address: 09E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Auxiliary Supply Control 0 register
AUXCTL0
00h
Auxiliary Supply Control 1 register
AUXCTL1
02h
Auxiliary Supply Control 2 register
AUXCTL2
04h
AUX2 Charger Control
AUX2CHCTL
12h
AUX3 Charger Control
AUX3CHCTL
14h
AUX ADC Control
AUXADCCTL
16h
AUX Interrupt Flag
AUXIFG
1Ah
AUX Interrupt Enable
AUXIE
1Ch
AUX Interrupt Vector Word
AUXIV
1Eh
Table 62. LCD_C Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
LCD_C control register 0
LCDCCTL0
000h
LCD_C control register 1
LCDCCTL1
002h
LCD_C blinking control register
LCDCBLKCTL
004h
LCD_C memory control register
LCDCMEMCTL
006h
LCD_C voltage control register
LCDCVCTL
008h
LCD_C port control 0
LCDCPCTL0
00Ah
LCD_C port control 1
LCDCPCTL1
00Ch
LCD_C port control 2
LCDCPCTL2
00Eh
LCD_C charge pump control register
LCDCCPCTL
012h
LCD_C interrupt vector
LCDCIV
01Eh
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
Static and 2 to 4 mux modes
⋮
⋮
⋮
LCD_C memory 20
LCDM20
033h
LCD_C blinking memory 1
LCDBM1
040h
LCD_C blinking memory 2
LCDBM2
041h
⋮
⋮
LCD_C blinking memory 20
⋮
LCDBM20
053h
LCD_C memory 1
LCDM1
020h
LCD_C memory 2
LCDM2
021h
5 to 8 mux modes
⋮
⋮
LCD_C memory 40
46
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LCDM40
047h
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC to DVSS
Voltage applied to any pin (excluding VCORE)
-0.3 V to 4.1 V
(2)
-0.3 V to VCC + 0.3 V
Diode current at any device pin
Storage temperature range, Tstg
±2 mA
(3)
–55°C to 150°C
Maximum junction temperature, TJ
(1)
(2)
(3)
95°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
MIN
Supply voltage during program execution and flash
programming. V(AVCC) = V(DVCC) = VCC (1)
VCC
NOM
MAX
1.8
3.6
V
PMMCOREVx = 0, 1
2.0
3.6
V
PMMCOREVx = 0, 1, 2
2.2
3.6
V
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
V
VSS
Supply voltage V(AVSS) = V(DVSS) = VSS
TA
Operating free-air temperature
I version
–40
85
TJ
Operating junction temperature
I version
–40
85
CVCORE
Recommended capacitor at VCORE
CDVCC/
CVCORE
Capacitor ratio of DVCC to VCORE
fSYSTEM
ILOAD,
DVCCD
ILOAD,
AUX1D
ILOAD,
AUX2D
ILOAD,
AVCCA
ILOAD,
AUX1A
ILOAD,
AUX2A
(1)
(2)
(3)
Processor frequency (maximum MCLK frequency) (2) (3)
(see Figure 1)
UNIT
PMMCOREVx = 0
0
V
470
°C
°C
nF
10
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V
0
12.0
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
0
20.0
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
25.0
MHz
Maximum load current that can be drawn from DVCC for
core and IO (ILOAD = ICORE + IIO)
20
mA
Maximum load current that can be drawn from AUXVCC1 for
core and IO (ILOAD = ICORE + IIO)
20
mA
Maximum load current that can be drawn from AUXVCC2 for
core and IO (ILOAD = ICORE + IIO)
20
mA
Maximum load current that can be drawn from AVCC for
analog modules (ILOAD = IModules)
10
mA
Maximum load current that can be drawn from AUXVCC1 for
analog modules (ILOAD = IModules)
5
mA
Maximum load current that can be drawn from AUXVCC2 for
analog modules (ILOAD = IModules)
5
mA
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC)
can be tolerated during power up and operation.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
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25
System Frequency - MHz
3
20
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 1. Maximum System Frequency
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
PMMCOREVx
1 MHz
TYP
IAM,
IAM,
(1)
(2)
(3)
(4)
(5)
48
Flash
RAM
(4)
(5)
Flash
RAM
3.0 V
3.0 V
8 MHz
MAX
0.36
TYP
2.10
12 MHz
MAX
TYP
20 MHz
MAX
TYP
0
0.32
1
0.36
2.39
3.54
2
0.39
2.65
3.94
6.54
3
0.42
4.20
6.96
0
0.20
1
0.22
1.30
1.90
2
0.24
1.45
2.15
3.55
3
0.26
1.55
2.30
3.80
1.10
TYP
UNIT
MAX
2.30
2.82
0.22
25 MHz
MAX
3.90
mA
7.23
8.65
9.54
1.22
2.10
mA
4.0
4.70
5.30
All inputs are tied to 0 or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
Active mode supply current when program executes in flash at a nominal supply voltage of 3.0V.
Active mode supply current when program executes in RAM at a nominal supply voltage of 3 V.
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MSP430F672x
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
-40°C
TYP
ILPM0,1MHz
Low-power mode 0 (3) (4)
ILPM2
Low-power mode 2 (5) (4)
ILPM3,XT1LF
Low-power mode 3, crystal
mode (6) (4)
ILPM3,XT1LF
ILPM3,VLO
ILPM4
Low-power mode 3, crystal
mode (6) (4)
Low-power mode 3,
VLO mode (7) (4)
ILPM4.5
MAX
MAX
TYP
TYP
UNIT
MAX
0
75
78
87
81
84
96
3
85
89
99
93
98
110
2.2 V
0
5.9
6.2
9
6.9
9.4
17
3.0 V
3
6.9
7.4
10
8.4
11
19
0
1.4
1.7
2.5
4.9
1
1.5
1.9
2.7
5.2
2
1.7
2.0
2.9
5.5
0
2.2
2.5
3.3
5.5
1
2.3
2.7
3.5
5.8
2
2.5
2.9
3.7
6.1
3
2.5
2.9
3.5
3.7
6.1
14.0
0
1.4
1.7
2.2
2.4
4.5
11.5
1
1.5
1.8
2.5
4.7
2
1.6
1.9
2.7
4.9
3
1.6
1.9
2.4
2.7
5.0
12.7
0
1.3
1.6
2.0
2.3
4.4
11.1
1
1.4
1.6
2.4
4.5
2
1.4
1.7
2.5
4.8
2.2 V
3.0 V
Low-power mode 4 (8) (4)
3.0 V
1.4
1.7
Low-power mode 3.5, RTC
active on AUXVCC3 (9)
2.2V
0.65
0.80
3.0V
1.16
1.24
3.0V
0.70
0.78
Low-power mode 4.5
85°C
MAX
3.0 V
3.0 V
(10)
60°C
TYP
2.2 V
3
ILPM3.5
25°C
3.1
2.2
µA
µA
µA
12.7
µA
µA
µA
2.5
4.8
0.90
1.30
12.2
2.05
1.43
1.87
2.71
1.05
0.90
1.20
1.85
µA
µA
(1)
(2)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL, SVML).
High side monitor disabled (SVMH). RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting
= 1 MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer clocked by ACLK included. RTC is disabled (RTCHOLD=1). ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply
(10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1
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Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
Temperature (TA)
PARAMETER
VCC
PMMCOREVx
-40°C
TYP
ILPM3
LCD,
int. bias
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
disabled (3) (4)
ILPM3
LCD,
int. bias
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
disabled (3) (4)
2.2 V
3.0 V
2.2 V
ILPM3
LCD,CP
(1)
(2)
(3)
(4)
(5)
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
enabled (3) (5)
3.0 V
MAX
25°C
TYP
0
2.4
2.9
1
2.5
3.1
2
2.6
3.3
0
2.8
3.2
1
2.9
2
3.1
3
3.1
3.6
60°C
MAX
TYP
TYP
UNIT
MAX
3.8
5.8
4.0
6.0
3.9
4.2
6.3
13.4
3.9
4.1
6.4
13.3
3.4
4.3
6.7
3.6
4.5
7.0
4.5
7.0
0
3.8
1
3.9
2
4.0
0
4.0
1
4.1
2
4.2
3
4.2
3.6
85°C
MAX
4.5
12.2
µA
µA
14.7
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. ACLK = low-frequency crystal operation (XTS = 0,
XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor and monitors disabled (SVSL, SVML).
High-side monitor disabled (SVMH). RAM retention enabled.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3V,typ.), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ... = 0 and odd segments S1, S3, ... = 1. No LCD panel load.
Schmitt-Trigger Inputs – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
50
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VCC
MIN
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.85
3V
0.4
1.0
20
TYP
35
5
MAX
50
UNIT
V
V
V
kΩ
pF
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430F673x
MSP430F672x
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Inputs – Ports P1 and P2 (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
t(int)
(1)
(2)
PARAMETER
TEST CONDITIONS
VCC
External interrupt timing (2)
Port P1, P2: P1.x to P2.x, External trigger pulse width to
set interrupt flag
2.2 V/3 V
MIN
MAX
20
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals shorter
than t(int).
Leakage Current – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
High-impedance leakage current
See
VCC
(1) (2)
MIN
1.8 V/3 V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs – General Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA (1)
VOH
High-level output voltage
I(OHmax) = –10 mA (1)
I(OHmax) = –5 mA
I(OLmax) = 3 mA (2)
Low-level output voltage
I(OLmax) = 10 mA (3)
I(OLmax) = 5 mA (2)
I(OLmax) = 15 mA (3)
(1)
(2)
(3)
1.8 V
(1)
I(OHmax) = –15 mA (1)
VOL
VCC
3V
1.8 V
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
UNIT
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Recommended Operating Conditions for more details.
The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.
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Typical Characteristics – General Purpose I/O (Full Drive Strength)
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
0
VCC = 3 V
Full Drive Strength
-10
-5
IOH – High-Level Output Current – mA
IOH – High-Level Output Current – mA
VCC = 1.8 V
Full Drive Strength
-10
-15
TA = 85°C
-20
-20
-30
-40
TA = 85°C
-50
TA = 25°C
TA = 25°C
-60
-25
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0
1.8
0.5
1.5
Figure 3.
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
2.5
3
60
50
IOL – Low-Level Output Current – mA
20
TA = 25°C
TA = 85°C
15
10
5
TA = 25°C
TA = 85°C
40
30
20
10
VCC = 1.8 V
Full Drive Strength
VCC = 3 V
Full Drive Strength
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VOL – Low-Level Output Voltage – V
Figure 4.
52
2
Figure 2.
25
IOL – Low-Level Output Current – mA
1
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
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1.6
1.8
0
0.5
1
1.5
2
2.5
3
VOL – Low-Level Output Voltage – V
Figure 5.
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430F673x
MSP430F672x
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Outputs – General Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA
VOH
High-level output voltage
I(OHmax) = –3 mA (2)
I(OHmax) = –2 mA (2)
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA
VOL
Low-level output voltage
(3)
(4)
1.8 V
3.0 V
(3)
I(OLmax) = 3 mA (4)
I(OLmax) = 2 mA (3)
I(OLmax) = 6 mA (4)
(1)
(2)
VCC
(2)
1.8 V
3.0 V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
UNIT
V
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
V
VSS VSS + 0.60
Selecting reduced drive strength may reduce EMI.
The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.
See Recommended Operating Conditions for more details.
The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.
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Typical Characteristics – General Purpose I/O (Reduced Drive Strength)
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
0
VCC = 1.8 V
Reduced Drive Strength
VCC = 3 V
Reduced Drive Strength
IOH – High-Level Output Current – mA
IOH – High-Level Output Current – mA
-1
-2
-3
-4
-5
TA = 85°C
-6
-5
-10
-15
TA = 85°C
-20
TA = 25°C
-7
TA = 25°C
-8
-25
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.5
VOH – High-Level Output Voltage – V
2
Figure 7.
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
2.5
3
20
18
7
TA = 25°C
TA = 25°C
IOL – Low-Level Output Current – mA
IOL – Low-Level Output Current – mA
1.5
Figure 6.
8
6
TA = 85°C
5
4
3
2
1
16
TA = 85°C
14
12
10
8
6
4
VCC = 3 V
Reduced Drive Strength
2
VCC = 1.8 V
Reduced Drive Strength
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VOL – Low-Level Output Voltage – V
Figure 8.
54
1
VOH – High-Level Output Voltage – V
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1.6
1.8
0
0.5
1
1.5
2
2.5
3
VOL – Low-Level Output Voltage – V
Figure 9.
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430F673x
MSP430F672x
www.ti.com
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Output Frequency – General Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPx.y
fPort_CLK
(1)
(2)
TEST CONDITIONS
Port output frequency
(with load)
See
Clock output frequency
ACLK
SMCLK
MCLK
CL = 20 pF (2)
(1) (2)
MIN
MAX
VCC = 1.8 V
PMMCOREVx = 0
16
VCC = 3 V
PMMCOREVx = 3
25
VCC = 1.8 V
PMMCOREVx = 0
16
VCC = 3 V
PMMCOREVx = 3
25
UNIT
MHz
MHz
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ΔIDVCC.LF
Differential XT1 oscillator
crystal current consumption
from lowest drive setting, LF
mode
TEST CONDITIONS
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 2, TA = 25°C
OALF
(5)
(6)
(3)
10
32.768
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
XTS = 0, XCAPx = 0 (6)
(3)
(4)
0.170
32768
Oscillation allowance for
LF crystals (4)
(2)
3.0 V
XTS = 0, XT1BYPASS = 0
XT1 oscillator logic-level
square-wave input frequency, XTS = 0, XT1BYPASS = 1 (2)
LF mode
MAX
UNIT
0.075
0.290
fXT1,LF,SW
(1)
TYP
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C
XT1 oscillator crystal
frequency, LF mode
Integrated effective load
capacitance, LF mode (5)
MIN
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 1, TA = 25°C
fXT1,LF0
CL,eff
VCC
µA
Hz
50
kHz
kΩ
2
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
pF
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this datasheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
(b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
(c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
(d) For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
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Crystal Oscillator, XT1, Low-Frequency Mode(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Duty cycle
LF mode
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
30
70
%
fFault,LF
Oscillator fault frequency,
LF mode (7)
XTS = 0 (8)
10
10000
Hz
tSTART,LF
(7)
(8)
Startup time, LF mode
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF
1000
3.0 V
ms
500
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
TEST CONDITIONS
Measured at ACLK
VCC
1.8 V to 3.6 V
MIN
TYP
MAX
6
9.4
15
(1)
1.8 V to 3.6 V
0.5
Measured at ACLK (2)
1.8 V to 3.6 V
4
Measured at ACLK
1.8 V to 3.6 V
Measured at ACLK
30
UNIT
kHz
%/°C
%/V
70
%
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
REFO oscillator current
consumption
TA = 25°C
1.8 V to 3.6 V
3
µA
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Hz
Full temperature range
1.8 V to 3.6 V
±3.5
3V
±1.5
REFO absolute tolerance calibrated
TA = 25°C
%
%
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK (1)
1.8 V to 3.6 V
0.01
%/°C
dfREFO/dVCC
REFO frequency supply voltage drift Measured at ACLK (2)
1.8 V to 3.6 V
1.0
%/V
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO startup time
40%/60% duty cycle
1.8 V to 3.6 V
tSTART
(1)
(2)
56
40
50
25
60
%
µs
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(85°C – (–40°C))
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fDCO(0,0)
DCO frequency (0, 0)
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
0.20
MHz
fDCO(0,31)
DCO frequency (0, 31)
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
fDCO(1,0)
DCO frequency (1, 0)
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
fDCO(1,31)
DCO frequency (1, 31)
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
fDCO(2,0)
DCO frequency (2, 0)
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2, 31)
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
fDCO(3,31)
DCO frequency (3, 31)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
fDCO(4,0)
DCO frequency (4, 0)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
fDCO(4,31)
DCO frequency (4, 31)
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
fDCO(5,0)
DCO frequency (5, 0)
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
fDCO(5,31)
DCO frequency (5, 31)
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
fDCO(6,0)
DCO frequency (6, 0)
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
fDCO(6,31)
DCO frequency (6, 31)
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
fDCO(7,0)
DCO frequency (7, 0)
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
40
50
60
%
dfDCO/dT
DCO frequency temperature drift
fDCO = 1 MHz
0.1
%/°C
dfDCO/dVCORE
DCO frequency voltage drift
fDCO = 1 MHz
1.9
%/V
Typical DCO Frequency, VCC = 3.0 V, TA = 25°C
100
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 10. Typical DCO Frequency
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PMM, Brown-Out Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage, DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage, DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
tRESET
(1)
(1)
MIN
TYP
0.80
1.30
60
Pulse length required at RST/NMI pin to
accept a reset
MAX
UNIT
1.45
V
1.50
V
250
mV
2
µs
Pulse much shorter than 2 µs might trigger reset.
PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.93
V
VCORE2(AM)
Core voltage, active mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.83
V
VCORE1(AM)
Core voltage, active mode, PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.62
V
VCORE0(AM)
Core voltage, active mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.42
V
VCORE3(LPM)
Core voltage, low-current mode, PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V
1.96
V
VCORE2(LPM)
Core voltage, low-current mode, PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
1.94
V
VCORE1(LPM)
Core voltage, low-current mode, PMMCOREV = 1
2.0 V ≤ DVCC ≤ 3.6 V
1.74
V
VCORE0(LPM)
Core voltage, low-current mode, PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V
1.54
V
PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT–)
V(SVSH_IT+)
SVSH on voltage level (1)
SVSH off voltage level (1)
tpd(SVSH)
SVSH propagation delay
t(SVSH)
SVSH on/off delay time
dVDVCC/dt
DVCC rise time
(1)
58
TYP
MAX
0
UNIT
nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
200
nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
1.5
µA
SVSHE = 1, SVSHRVL = 0
1.60
1.65
1.70
SVSHE = 1, SVSHRVL = 1
1.77
1.84
1.90
SVSHE = 1, SVSHRVL = 2
1.97
2.04
2.10
SVSHE = 1, SVSHRVL = 3
2.09
2.16
2.23
SVSHE = 1, SVSMHRRL = 0
1.68
1.74
1.80
SVSHE = 1, SVSMHRRL = 1
1.89
1.95
2.01
SVSHE = 1, SVSMHRRL = 2
2.08
2.14
2.21
SVSHE = 1, SVSMHRRL = 3
2.21
2.27
2.34
SVSHE = 1, SVSMHRRL = 4
2.35
2.41
2.49
SVSHE = 1, SVSMHRRL = 5
2.65
2.72
2.80
SVSHE = 1, SVSMHRRL = 6
2.96
3.04
3.13
SVSHE = 1, SVSMHRRL = 7
2.96
3.04
3.13
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
20
SVSHE = 0 → 1, SVSHFP = 1
12.5
SVSHE = 0 → 1, SVSHFP = 0
100
0
V
V
µs
µs
1000
V/s
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. Please refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.
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PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
V(SVMH)
SVMH current consumption
SVMH on/off voltage level
(1)
t(SVMH)
(1)
SVMH propagation delay
SVMH on/off delay time
MAX
UNIT
0
nA
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
200
nA
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
1.5
µA
SVMHE = 1, SVSMHRRL = 0
1.68
1.74
1.80
SVMHE = 1, SVSMHRRL = 1
1.89
1.95
2.01
SVMHE = 1, SVSMHRRL = 2
2.08
2.14
2.21
SVMHE = 1, SVSMHRRL = 3
2.21
2.27
2.34
SVMHE = 1, SVSMHRRL = 4
2.35
2.41
2.49
SVMHE = 1, SVSMHRRL = 5
2.65
2.72
2.80
SVMHE = 1, SVSMHRRL = 6
2.96
3.04
3.13
SVMHE = 1, SVSMHRRL = 7
2.96
3.04
3.13
SVMHE = 1, SVMHOVPE = 1
tpd(SVMH)
TYP
V
3.79
SVMHE = 1, dVDVCC/dt = 10 mV/µs,
SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs,
SVMHFP = 0
20
µs
SVMHE = 0 → 1,
SVMHFP = 1
12.5
SVMHE = 0 → 1,
SVMHFP = 0
100
µs
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. Refer to the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx Family User's Guide (SLAU208) on recommended settings and usage.
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PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
t(SVSL)
SVSL propagation delay
SVSL on/off delay time
MAX
UNIT
0
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
µA
SVSLE = 1, dVCORE/dt = 10 mV/µs,
SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs,
SVSLFP = 0
20
µs
SVSLE = 0 → 1, SVSLFP = 1
12.5
SVSLE = 0 → 1, SVSLFP = 0
100
µs
PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML)
SVML propagation delay
t(SVML)
SVML on/off delay time
MAX
UNIT
0
nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
1.5
µA
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
20
SVMLE = 0 → 1, SVMLFP = 1
12.5
SVMLE = 0 → 1, SVMLFP = 0
100
µs
µs
Wake-Up from Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tWAKE-UPFAST
tWAKE-UPSLOW
tWAKE-UPLPM4.5
tWAKE-UPRESET
(1)
(2)
(3)
60
TEST CONDITIONS
MIN
TYP MAX UNIT
fMCLK ≥ 4 MHz
3
5
1 MHz < fMCLK < 4
MHz
4
6
150
160
µs
Wake-up time from
LPM4.5 to active
mode (3)
2
3
ms
Wake-up time from RST
or BOR event to active
mode (3)
2
3
ms
Wake-up time from
LPM2, LPM3, or LPM4
to active mode (1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
Wake-up time from
PMMCOREV = SVSMLRRL = n (where n = 0, 1, 2, or 3),
LPM2, LPM3 or LPM4 to
SVSLFP = 0
active mode (2)
µs
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
Family User's Guide (SLAU208).
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx Family User's Guide
(SLAU208).
This value represents the time from the wakeup event to the reset vector execution.
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Auxiliary Supplies - Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
NOM
MAX
Supply voltage range for all supplies at pins DVCC, AVCC, AUX1, AUX2, AUX3
1.8
3.6
PMMCOREVx = 0
1.8
3.6
PMMCOREVx = 1
2.0
3.6
PMMCOREVx = 2
2.2
3.6
2.4
3.6
UNIT
V
VDSYS
Digital system supply voltage range,
VDSYS = VCC - RON×ILOAD
VASYS
Analog system supply voltage range, VASYS = VCC - RON × ILOAD
CVCC,CAUX1/2
Recommended capacitor at pins DVCC, AVCC, AUX1, AUX2
CVSYS
Recommended capacitor at pins VDSYS and VASYS
CVCORE
Recommended capacitance at pin VCORE
CAUX3
Recommended capacitor at pin AUX3
0.47
µF
PMMCOREVx = 3
Refer to modules
V
V
4.7
µF
4.7
µF
0.47
µF
Auxiliary Supplies - AUX3 (Backup-Sub-System) Currents
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IAUX3,RTCon
AUX3 current with RTC
enabled
RTC and 32-kHz oscillator in
backup-subsystem enabled
3V
IAUX3,RTCoff
AUX3 current with RTC
disabled
RTC and 32-kHz oscillator in
backup-subsystem disabled
3V
TA
MIN
TYP
MAX
25°C
0.83
85°C
0.95
25°C
110
85°C
165
UNIT
µA
nA
Auxiliary Supplies - Auxiliary Supply Monitor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ICC,Monitor
Average supply current for
monitoring circuitry drawn from
VDSYS
LOCKAUX = 0, AUXMRx = 0,
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
VDSYS = DVCC, VASYS = AVCC,
Current measured at VDSYS pin
IMeas,Monitor
Average current drawn from
monitored supply during
measurement cycle
LOCKAUX = 0, AUXMRx = 0,
AUX0MD = 0, AUX1MD = 0, AUX2MD = 1,
VDSYS = DVCC, VASYS = AVCC,
AUXVCC1 = 3 V,
Current measured at AUXVCC1 pin
VMonitor
Auxiliary supply threshold level
Copyright © 2011–2012, Texas Instruments Incorporated
VCC
MIN
TYP
3V
MAX
UNIT
0.70
µA
0.11
µA
AUXLVLx = 0
1.67
1.74
1.80
AUXLVLx = 1
1.87
1.95
2.01
AUXLVLx = 2
2.06
2.14
2.21
AUXLVLx = 3
2.19
2.27
2.33
AUXLVLx = 4
2.33
2.41
2.48
AUXLVLx = 5
2.63
2.72
2.79
AUXLVLx = 6
2.91
3.02
3.10
AUXLVLx = 7
2.91
3.02
3.10
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0.7
0.6
ICC, monitor – µA
0.5
0.4
0.3
0.2
0.1
0
1.8
2
2.2
2.4
2.6
2.8
VDSYS Voltage – V
3
3.2
3.4
3.6
3.2
3.4
3.6
Figure 11. VDSYS Voltage vs ICC,Monitor
120
Imeas, monitor – nA
100
80
60
40
20
0
1.8
2.0
2.2
2.4
2.6
2.8
AUXVCC1 Voltage – V
3.0
Figure 12. AUXVCC1 Voltage vs IMeas,Monitor
Auxiliary Supplies - Switch On-Resistance
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RON,DVCC
On-resistance of switch
between DVCC and VDSYS
ILOAD = ICORE + IIO = 10mA + 10mA = 20mA
5
Ω
RON,DAUX1
On-resistance of switch
between AUX1 and VDSYS
ILOAD = ICORE + IIO = 10mA + 10mA = 20mA
5
Ω
RON,DAUX2
On-resistance of switch
between AUX2 and VDSYS
ILOAD = ICORE + IIO = 10mA + 10mA = 20mA
5
Ω
RON,AVCC
On-resistance of switch
between AVCC and VASYS
ILOAD = IModules = 10mA
5
Ω
RON,AAUX1
On-resistance of switch
between AUX1 and VASYS
ILOAD = IModules = 5mA
20
Ω
RON,AAUX2
On-resistance of switch
between AUX2 and VASYS
ILOAD = IModules = 5mA
20
Ω
62
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Auxiliary Supplies - Switching Time
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tSwitch
Time from occurence of trigger (SVM or software) to
"new" supply connected to system supplies
tRecover
"Recovery time" after a switch over took place.
During that time no further switching takes place.
VCC
MIN
TYP
200
MAX
UNIT
100
ns
450
µs
Auxiliary Supplies - Switch Leakage
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ISW,Lkg
Current into DVCC, AVCC, AUX1 or AUX2 Per supply (but not the highest
if not selected
supply)
IVmax
Current drawn from highest supply
VCC
MIN
TYP
MAX
UNIT
50
100
nA
450
730
nA
UNIT
Auxiliary Supplies - Auxiliary Supplies to ADC10_A
over operating free-air temperature range (unless otherwise noted)
PARAMETER
V3
RV3
tSample,V3
TEST CONDITIONS
Supply voltage divider
V3 = VSupply/3
Load resistance
Sampling time required if V3
selected.
AUXADC = 1,
ADC10ON = 1,
INCH = 0Ch,
Error of conversion
result ≤ 1 LSB
VCC
MIN
TYP
MAX
1.8 V
0.58
0.60
0.62
3.0 V
0.98
1.00
1.02
3.6 V
1.18
1.20
1.22
V
AUXADCRx = 0
18
kΩ
AUXADCRx = 1
1.5
kΩ
AUXADCRx = 2
0.6
kΩ
AUXADCRx = 0
1000
ns
AUXADCRx = 1
1000
ns
AUXADCRx = 2
1000
ns
Auxiliary Supplies - Charge Limiting Resistor
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RCHARGE
Charge limiting resistor
Copyright © 2011–2012, Texas Instruments Incorporated
TEST CONDITIONS
VCC
MIN
TYP
MAX
CHCx = 1
3V
5
CHCx = 2
3V
10
CHCx = 3
3V
20
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kΩ
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Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
1.8 V/
3.0 V
tTA,cap
Timer_A capture timing
All capture inputs.
Minimum pulse width required for
capture.
1.8 V/
3.0 V
MIN
TYP
MAX
UNIT
25
MHz
20
ns
eUSCI (UART Mode) - Recommended Operating Conditions
PARAMETER
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
5
MHz
UNIT
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
UCGLITx = 0
UART receive deglitch time (1)
tt
UCGLITx = 1
2.0 V/3.0
V
UCGLITx = 2
UCGLITx = 3
(1)
MIN
TYP
MAX
10
15
25
30
50
85
50
80
150
70
120
200
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
eUSCI (SPI Master Mode) - Recommended Operating Conditions
PARAMETER
feUSCI
eUSCI input clock frequency
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
MAX
UNIT
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
MIN
tSTE,LEAD
STE lead time, STE
active to clock
UCSTEM = 0, UCMODEx = 01 or 10
TEST CONDITIONS
2.0 V/3.0 V
150
UCSTEM = 1, UCMODEx = 01 or 10
2.0 V/3.0 V
150
tSTE,LAG
STE lag time, Last clock
to STE inactive
UCSTEM = 0, UCMODEx = 01 or 10
2.0 V/3.0 V
200
UCSTEM = 1, UCMODEx = 01 or 10
2.0 V/3.0 V
200
UCSTEM = 0, UCMODEx = 01 or 10
tSTE,ACC
STE access time, STE
active to SIMO data out
UCSTEM = 1, UCMODEx = 01 or 10
tSTE,DIS
tSU,MI
(1)
64
STE disable time, STE
inactive to SIMO high
impedance
SOMI input data setup
time
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
TYP
ns
ns
2.0 V
50
3.0 V
30
2.0 V
50
3.0 V
30
2.0 V
40
3.0 V
25
2.0 V
40
3.0 V
25
2.0 V
50
3.0 V
30
ns
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
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eUSCI (SPI Master Mode) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
tHD,MI
SOMI input data hold
time
tVALID,MO
SIMO output data valid
time (2)
UCLK edge to SIMO valid, CL = 20 pF
tHD,MO
SIMO output data hold
time (3)
CL = 20 pF
(2)
(3)
MIN
2.0 V
0
3.0 V
0
TYP
MAX
ns
2.0 V
9
3.0 V
5
2.0 V
0
3.0 V
0
UNIT
ns
ns
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 15 and Figure 16.
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tSTE,ACC
tVALID,MO
tSTE,DIS
SIMO
Figure 13. SPI Master Mode, CKPH = 0
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 14. SPI Master Mode, CKPH = 1
66
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eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
VCC
MIN
2.0 V
4
3.0 V
3
2.0 V
0
3.0 V
0
TYP
MAX
ns
ns
2.0 V
46
3.0 V
24
2.0 V
38
3.0 V
25
2.0 V
2
3.0 V
1
2.0 V
2
3.0 V
2
55
32
24
16
ns
ns
3.0 V
3.0 V
ns
ns
2.0 V
2.0 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 15 and Figure 16.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams
inFigure 15 and Figure 16.
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 15. SPI Slave Mode, CKPH = 0
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 16. SPI Slave Mode, CKPH = 1
68
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eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
MIN
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
tSU,DAT
Data setup time
tSU,STO
Setup time for STOP
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
2 V/3 V
tHD,STA
fSCL = 100 kHz
0
fSCL = 100 kHz
fSCL = 100 kHz
2 V/3 V
5.0
fSCL > 100 kHz
2 V/3 V
1.3
kHz
µs
µs
µs
µs
µs
1.7
UCGLITx = 0
75
220
ns
UCGLITx = 1
35
120
ns
30
60
ns
20
35
2 V/3 V
UCGLITx = 2
UCCLTOx = 1
Clock low timeout
400
5.2
2 V/3 V
UCGLITx = 3
tTIMEOUT
MHz
1.4
0.4
fSCL > 100 kHz
fSYSTEM
5.1
2 V/3 V
fSCL = 100 kHz
UNIT
1.5
2 V/3 V
fSCL > 100 kHz
MAX
5.1
2 V/3 V
fSCL > 100 kHz
Pulse duration of spikes suppressed by input
filter
tSP
VCC
UCCLTOx = 2
2 V/3 V
UCCLTOx = 3
tSU,STA
tHD,STA
tHD,STA
ns
30
ms
33
ms
37
ms
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 17. I2C Mode Timing
LCD_C - Recommended Operating Conditions
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
VCC,LCD_C,CP en,3.6
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
VCC,LCD_C,CP en,3.3
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
VCC,LCD_C,int. bias
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,ext.
Supply voltage range, external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,VLCDEXT
Supply voltage range, external
LCD voltage, internal or external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.0
3.6
V
VLCDCAP/R33
External LCD voltage at
LCDCAP/R33, internal or external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
bias
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LCD_C - Recommended Operating Conditions (continued)
PARAMETER
CONDITIONS
MIN
CLCDCAP
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000
(charge pump enabled)
fFrame
LCD frame frequency range
fLCD = 2 × mux × fFRAME
with mux = 1 (static), 2, 3, 4 up to 8
fACLK,in
ACLK input frequency range
CPanel
Panel capacitance
100-Hz frame frequency
VR33
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
VR23,1/3bias
Analog input voltage at R23
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13
VR13,1/3bias
Analog input voltage at R13 with
1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13,1/2bias
Analog input voltage at R13 with
1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
Analog input voltage at R03
R0EXT = 1
VLCD-VR03
Voltage difference between VLCD
and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF/R13
External LCD reference voltage
applied at LCDREF/R13
VLCDREFx = 01
0.8
NOM
MAX
4.7
10
µF
100
Hz
0
30
32
UNIT
40
kHz
10000
pF
VCC+0
.2
V
VR03 +
2/3×(VR33VR03)
VR33
V
VR03
VR03 +
1/3×(VR33VR03)
VR23
V
VR03
VR03 +
1/2×(VR33VR03)
VR33
V
2.4
VSS
V
VCC+0
.2
V
1.2
1.5
V
TYP
MAX
LCD_C Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VLCD
LCD voltage
TEST CONDITIONS
VCC
MIN
VLCDx = 0000, VLCDEXT = 0
2.4 V to 3.6 V
VCC
LCDCPEN = 1, VLCDx = 0001
2 V to 3.6 V
2.58
LCDCPEN = 1, VLCDx = 0010
2 V to 3.6 V
2.64
LCDCPEN = 1, VLCDx = 0011
2 V to 3.6 V
2.71
LCDCPEN = 1, VLCDx = 0100
2 V to 3.6 V
2.78
LCDCPEN = 1, VLCDx = 0101
2 V to 3.6 V
2.83
LCDCPEN = 1, VLCDx = 0110
2 V to 3.6 V
2.90
LCDCPEN = 1, VLCDx = 0111
2 V to 3.6 V
2.96
LCDCPEN = 1, VLCDx = 1000
2 V to 3.6 V
3.02
LCDCPEN = 1, VLCDx = 1001
2 V to 3.6 V
3.07
LCDCPEN = 1, VLCDx = 1010
2 V to 3.6 V
3.14
LCDCPEN = 1, VLCDx = 1011
2 V to 3.6 V
3.21
LCDCPEN = 1, VLCDx = 1100
2 V to 3.6 V
3.27
LCDCPEN = 1, VLCDx = 1101
2.2 V to 3.6 V
3.32
LCDCPEN = 1, VLCDx = 1110
2.2 V to 3.6 V
3.38
LCDCPEN = 1, VLCDx = 1111
2.2 V to 3.6 V
3.44
UNIT
V
3.6
ICC,Peak,CP
Peak supply currents due to
charge pump activities
LCDCPEN = 1, VLCDx = 1111
2.2 V
400
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7µF, LCDCPEN = 0→1,
VLCDx = 1111
2.2 V
150
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
2.2 V
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10µA
2.2 V
10
kΩ
70
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µA
500
50
ms
µA
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MSP430F673x
MSP430F672x
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
SD24_B, Power Supply and Recommended Operating Conditions
MIN
AVCC
Analog supply voltage
fSD
AVCC = DVCC, AVSS = DVSS = 0 V
TYP
MAX
UNIT
2.4
3.6
V
Modulator clock frequency (1)
0.03
2.3
MHz
VI
Absolute input voltage range
AVSS - 1V
AVCC
V
VIC
Common-mode input voltage range
AVSS - 1V
AVCC
V
VID,FS
Differential full scale input voltage
-VREF/GAIN
+VREF/GAIN
Differential input voltage for specified
performance (2)
VID
VID = VI,A+ - VI,A-
SD24REFS = 1
SD24GAINx = 1
±910
±920
SD24GAINx = 2
±455
±460
SD24GAINx = 4
±227
±230
SD24GAINx = 8
±113
±115
SD24GAINx = 16
±57
±58
SD24GAINx = 32
±28
±29
SD24GAINx = 64
±14
±14.5
±7
±7.2
SD24GAINx =
128
CREF
(1)
(2)
(3)
VREF load capacitance
(3)
SD24REFS = 1
100
(1)
PARAMETER
Input capacitance
TEST CONDITIONS
VCC
MIN
ZID
(1)
Input impedance
(Pin A+ or A- to AVSS)
Differential input impedance
(Pin A+ to pin A-)
TYP
SD24GAINx = 1
5
SD24GAINx = 2
5
SD24GAINx = 4
5
SD24GAINx = 8
5
SD24GAINx = 16
5
SD24GAINx = 32, 64, 128
ZI
nF
Modulator clock frequency: MIN = 32.768 kHz - 10% ≈ 30 kHz. MAX = 32.768 kHz × 64 + 10% ≈ 2.3 MHz
The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS-= -VREF/GAIN: FSR = VFS+ - VFS-= 2*VREF/GAIN. If VREF is sourced
externally, the analog input range should not exceed 80% of VFS+ or VFS-; i.e., VID = 0.8 VFS- to 0.8 VFS+. If VREF is sourced internally,
the given VID ranges apply.
There is no capacitance required on VREF. However, a capacitance of 100nF is recommended to reduce any reference voltage noise.
SD24_B, Analog Input
CI
mV
fSD24 = 1MHz
fSD24 = 1MHz
MAX
UNIT
pF
5
SD24GAINx = 1
3V
200
SD24GAINx = 8
3V
200
SD24GAINx = 32
3V
200
SD24GAINx = 1
3V
SD24GAINx = 8
3V
SD24GAINx = 32
3V
300
400
400
300
kΩ
kΩ
400
All parameters pertain to each SD24_B converter.
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1600
Input Leakage Current – nA
1400
1200
1000
800
600
400
200
0
-200
-1
-0.5
0
0.5
1
Input Voltage – V
1.5
2
2.5
3
Figure 18. Input Leakage Current vs Input Voltage
(Modulator OFF)
SD24_B, Supply Currents
PARAMETER
ISD,256
ISD,512
TEST CONDITIONS
Analog plus digital supply current per
converter (reference not included)
Analog plus digital supply current per
converter (reference not included)
fSD24 = 1 MHz,
SD24OSR = 256
fSD24 = 2 MHz,
SD24OSR = 512
TYP
MAX
SD24GAIN: 1
VCC
3V
MIN
600
675
SD24GAIN: 2
3V
600
675
SD24GAIN: 4
3V
600
675
SD24GAIN: 8
3V
700
750
SD24GAIN: 16
3V
700
750
SD24GAIN: 32
3V
775
850
SD24GAIN: 64
3V
775
850
SD24GAIN: 128
3V
775
850
SD24GAIN: 1
3V
750
800
SD24GAIN: 8
3V
825
900
SD24GAIN: 32
3V
900
1000
UNIT
µA
µA
SD24_B, Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
INL
Gnom
72
TEST CONDITIONS
SD24GAIN: 1
Integral nonlinearity, endSD24GAIN: 8
point fit
SD24GAIN: 32
Nominal gain
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VCC
MIN
TYP
3V
-0.01
0.01
3V
-0.01
0.01
3V
-0.01
0.01
SD24GAIN: 1
3V
1
SD24GAIN: 2
3V
2
SD24GAIN: 4
3V
4
SD24GAIN: 8
3V
8
SD24GAIN: 16
3V
16
SD24GAIN: 32
3V
31.7
SD24GAIN: 64
3V
63.4
SD24GAIN: 128
3V
126.8
MAX
UNIT
% of
FSR
Copyright © 2011–2012, Texas Instruments Incorporated
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MSP430F672x
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SD24_B, Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
Gain error (1)
EG
ΔEG/ΔT
ΔEG/ΔVCC
EOS[V]
EOS[FS]
ΔEOS/ΔT
ΔEOS/ΔVCC
CMRR,DC
(1)
(2)
(3)
(4)
(5)
(6)
(7)
TEST CONDITIONS
Gain error temperature
coefficient (2), internal
reference
Gain error vs VCC
(3)
Offset error (4)
Offset error (4)
Offset error temperature
coefficient (5)
Offset error vs VCC
(6)
Common mode rejection
at DC (7)
VCC
MIN
TYP
MAX
SD24GAIN: 1, with external reference (1.2 V)
3V
-1
+1
SD24GAIN: 8, with external reference (1.2 V)
3V
-2
+2
SD24GAIN: 32, with external reference (1.2 V)
3V
-2
+2
SD24GAIN: 1/8/32 (with internal reference)
3V
UNIT
%
50 ppm/°C
SD24GAIN: 1
0.15
SD24GAIN: 8
0.15
SD24GAIN: 32
0.4
%/V
SD24GAIN: 1 (with Vdiff = 0V)
3V
2.3
SD24GAIN: 8
3V
0.73
SD24GAIN: 32
3V
SD24GAIN: 1 (with Vdiff = 0V)
3V
-0.2
0.2
SD24GAIN: 8
3V
-0.5
0.5
SD24GAIN: 32
3V
-0.5
SD24GAIN: 1
3V
1
SD24GAIN: 8
3V
0.15
SD24GAIN: 32
3V
mV
0.18
% FS
0.5
uV/°C
0.1
SD24GAIN: 1
600
SD24GAIN: 8
100
SD24GAIN: 32
50
SD24GAIN: 1
3V
-110
SD24GAIN: 8
3V
-110
SD24GAIN: 32
3V
-110
uV/V
dB
The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact - Gnom)/Gnom. It covers process,
temperature and supply voltage variations.
The gain error temperature coefficient ΔEG/ ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) Gnom)/Gnom) using the box method (i.e. min. and max. values):
ΔEG/ ΔT = (MAX(EG(T)) - MIN(EG(T) ) / (MAX(T) - MIN(T)) = (MAX(Gact(T)) - MIN(Gact(T)) / Gnom / (MAX(T) - MIN(T))
with T ranging from -40°C to +85°C.
The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) Gnom)/Gnom) using the box method (i.e. min. and max. values):
ΔEG/ ΔVCC = (MAX(EG(VCC)) - MIN(EG(VCC) ) / (MAX(VCC) - MIN(VCC)) = (MAX(Gact(VCC)) - MIN(Gact(VCC)) / Gnom / (MAX(VCC) MIN(VCC))
with VCC ranging from 2.4V to 3.6V.
The offset error EOS is measured with shorted inputs in 2's complement mode with +100% FS = VREF/G and -100% FS = -VREF/G.
Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V]×G/VREF; EOS [V] = EOS [FS]×VREF/G.
The offset error temperature coefficient ΔEOS/ ΔT specifies the variation of the offset error EOS over temperature using the box method
(i.e. min. and max. values):
ΔEOS/ ΔT = (MAX(EOS(T)) - MIN(EOS(T) ) / (MAX(T) - MIN(T))
with T ranging from -40°C to +85°C.
The offset error vs VCC ΔEOS/ ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (i.e. min.
and max. values):
ΔEOS/ ΔVCC = (MAX(EOS(VCC)) - MIN(EOS(VCC) ) / (MAX(VCC) - MIN(VCC))
with VCC ranging from 2.4V to 3.6V.
The DC CMRR specifies the change in the measured differential input voltage value when the common mode voltage varies:
DC CMRR = -20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured when
sweeping the common mode voltage (for example, calculating with 16-bits FSR = 65536 a maximum change by 1 LSB results in 20log(1/65536) ≈ -96 dB) .
The DC CMRR is measured with both inputs connected to the common mode voltage (i.e. no differential input signal is applied), and the
common mode voltage is swept from -1V to VCC.
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SD24_B, Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
CMRR,50Hz
AC PSRR,ext
AC PSRR,int
XT
Common mode rejection
at 50 Hz (8)
AC power supply
rejection ratio, external
reference (9)
AC power supply
rejection ratio, internal
reference (9)
Crosstalk between
converters (10)
TEST CONDITIONS
VCC
MIN
TYP
SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV
3V
-110
SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV
3V
-110
SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV
3V
-110
SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π ×
fVcc × t), fVcc = 50 Hz
-61
SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π ×
fVcc × t), fVcc = 50 Hz
-77
SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π ×
fVcc × t), fVcc = 50 Hz
-79
SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π ×
fVcc × t), fVcc = 50 Hz
-61
SD24GAIN: 8, VVCC = 3 V + 50 mV × sin(2π ×
fVcc × t), fVcc = 50 Hz
-77
SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π ×
fVcc × t), fVcc = 50 Hz
-79
Crosstalk source: SD24GAIN: 1, Sine-wave
with max. possible Vpp. fIN = 50 Hz, 100 Hz,
Converter under test: SD24GAIN: 1
3V
-120
Crosstalk source: SD24GAIN: 1, Sine-wave
with max. possible Vpp. fIN = 50 Hz, 100 Hz,
Converter under test: SD24GAIN: 8
3V
-115
Crosstalk source: SD24GAIN: 1, Sine-wave
with max. possible Vpp. fIN = 50 Hz, 100 Hz,
Converter under test: SD24GAIN: 32
3V
-100
MAX
UNIT
dB
dB
dB
dB
(8)
The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common mode ripple
applied to the inputs of the ADC and the actual common mode signal spur visible in the FFT spectrum:
AC CMRR = Error Spur [dBFS] - 20log(VCM/1.2V/G) [dBFS] with a common mode signal of VCM × sin(2π × fCM × t) applied to the analog
inputs.
The AC CMRR is measured with the both inputs connected to the common mode signal i.e. no differential input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
(9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple
applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum:
AC PSRR = Error Spur [dBFS] - 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × fVcc × t) added to VCC.
The AC PSRR is measured with the inputs grounded; that is, no analog input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = -27.6 dBFS
SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = -9.5 dBFS
SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS
(10) The crosstalk XT is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under
test. It is measured with the inputs of the converter under test being grounded.
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SD24_B, AC Performance
fSD24 = 1MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
SINAD
THD
Signal-to-noise +
distortion ratio
Total Harmonic
distiortion
TEST CONDITIONS
VCC
MIN
TYP
SD24GAIN: 1
3V
85
87
SD24GAIN: 2
3V
SD24GAIN: 4
3V
SD24GAIN: 8
3V
fIN = 50Hz (1)
SD24GAIN: 16
3V
84
dB
80
3V
3V
SD24GAIN: 128
3V
62
SD24GAIN: 1
3V
100
3V
90
3V
80
SD24GAIN: 32
(1)
85
82
SD24GAIN: 64
fIN = 50Hz (1)
UNIT
86
SD24GAIN: 32
SD24GAIN: 8
MAX
73
74
68
dB
The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A-(t) = 0 V - VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) - VI,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed
for a given range (according to SD24_B recommended operating conditions).
SD24_B, AC Performance
fSD24 = 2MHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER
SINAD
(1)
Signal-to-noise +
distortion ratio
TEST CONDITIONS
VCC
MIN
TYP
SD24GAIN: 1
3V
87
SD24GAIN: 2
3V
86
SD24GAIN: 4
3V
85
SD24GAIN: 8
3V
84
3V
81
SD24GAIN: 32
3V
76
SD24GAIN: 64
3V
71
SD24GAIN: 128
3V
65
SD24GAIN: 16
fIN = 50Hz (1)
MAX
UNIT
dB
The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A-(t) = 0 V - VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) - VI,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed
for a given range (according to SD24_B recommended operating conditions).
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SD24_B, AC Performance
fSD24 = 32 kHz, SD24OSRx = 512, SD24REFS = 1
PARAMETER
Signal-to-noise +
distortion ratio
SINAD
(1)
TEST CONDITIONS
VCC
MIN
TYP
SD24GAIN: 1
3V
89
SD24GAIN: 2
3V
85
SD24GAIN: 4
3V
84
SD24GAIN: 8
3V
86
3V
80
SD24GAIN: 32
3V
76
SD24GAIN: 64
3V
67
SD24GAIN: 128
3V
61
fIN = 12Hz (1)
SD24GAIN: 16
MAX
UNIT
dB
The following voltages were applied to the SD24_B inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A-(t) = 0 V - VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VI,A+(t) - VI,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed
for a given range (according to SD24_B recommended operating conditions).
95
90
SINAD – dB
85
80
75
70
65
60
55
32
64
128
256
512
1024
SD24OSRx
Figure 19. SINAD vs OSR
(fSD24 = 1 MHz, SD24REFS = 1, SD24GAIN = 1)
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90
85
SINAD – dB
80
75
70
65
60
0.1
0.2
0.3
0.4
0.5
0.6
Vpp/Vref/Gain
0.7
0.8
0.9
1
Figure 20. SINAD vs VPP
SD24_B, External Reference Input
ensure correct input voltage range according to VREF
VCC
MIN
TYP
MAX
VREF(I) Input voltage
PARAMETER
SD24REFS = 0
TEST CONDITIONS
3V
1.0
1.20
1.5
V
IREF(I)
SD24REFS = 0
3V
50
nA
Input current
UNIT
10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range (1)
All ADC10_A pins
Operating supply current into
AVCC terminal, REF module
and reference buffer off
fADC10CLK = 5 MHz, ADC10ON =1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF
= 00
Operating supply current into
AVCC terminal, REF module
on, reference buffer on
VCC
MIN
TYP
MAX
UNIT
1.8
3.6
V
0
AVCC
V
2.2 V
70
105
3V
80
115
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF
= 01
3V
130
185
µA
Operating supply current into
AVCC terminal, REF module
off, reference buffer on
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF
= 10, VEREF = 2.5 V
3V
108
160
µA
Operating supply current into
AVCC terminal, REF module
off, reference buffer off
fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF
= 11, VEREF = 2.5 V
3V
74
105
µA
CI
Input capacitance
Only one terminal Ax can be selected at one time
from the pad to the ADC10_A capacitor array
including wiring and pad.
2.2 V
3.5
RI
Input MUX ON resistance
IADC10_A
(1)
µA
pF
AVCC > 2 V, 0 V ≤ VAx ≤ AVCC
36
1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC
96
kΩ
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external
reference voltage requires decoupling capacitors. Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to
decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and
MSP430x6xx Family User's Guide (SLAU208).
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10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC10_A linearity
parameters
2.2 V, 3 V
0.45
5
5.5
MHz
Internal ADC10_A
oscillator (1)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
4.4
5.0
5.6
MHz
2.2 V, 3 V
2.4
Conversion time
REFON = 0, Internal oscillator, 12 ADC10CLK
cycles, 10-bit mode
fADC10OSC = 4 MHz to 5 MHz
fADC10CLK
fADC10OSC
tCONVERT
TEST CONDITIONS
µs
External fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSEL ≠ 0
tADC10ON
Turn on settling time of
the ADC
tSample
Sampling time
(1)
(2)
(3)
(4)
78
See
3.0
(2)
(3)
100
ns
RS = 1000 Ω, RI = 96 kΩ, CI = 3.5 pF (4)
1.8 V
3
µs
RS = 1000 Ω, RI = 36 kΩ, CI = 3.5 pF (4)
3V
1
µs
The ADC10OSC is sourced directly from MODOSC inside the UCS.
12 × ADC10DIV × 1/fADC10CLK
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately eight Tau (t) are needed to get an error of less than ±0.5 LSB
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10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral
linearity error
1.4 V ≤ (VeREF+ – VeREF–)min ≤ 1.6 V
ED
Differential
linearity error
(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–),
CVeREF+ = 20 pF
2.2 V, 3 V
±1.0
LSB
EO
Offset error
(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–),
Internal impedance of source RS < 100 Ω, CVREF+ = 20 pF
2.2 V, 3 V
±1.0
LSB
EG
Gain error
(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–),
CVeREF+ = 20 pF
2.2 V, 3 V
±1.0
LSB
ET
Total unadjusted
error
(VeREF+ – VeREF–)min ≤ (VeREF+ – VeREF–),
CVeREF+ = 20 pF
2.2 V, 3 V
±2.0
LSB
MAX
UNIT
1.6 V < (VeREF+ – VeREF–)min ≤ VAVCC
±1.0
2.2 V, 3 V
±1.0
±1.0
LSB
10-Bit ADC, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VeREF+
Positive external
reference voltage input
VeREF–
(VeREF+ –
VeREF–)
IVeREF+
IVeREF–
CVeREF+/(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
VCC
MIN
TYP
VeREF+ > VeREF–
(2)
1.4
AVCC
V
Negative external
reference voltage input
VeREF+ > VeREF–
(3)
0
1.2
V
Differential external
reference voltage input
VeREF+ > VeREF–
(4)
1.4
AVCC
V
±26
µA
±1
µA
Static input current
Capacitance at
VeREF+/- terminal
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
2.2 V, 3 V
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
2.2 V, 3 V
See
(5)
±8.5
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VeREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
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REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Positive built-in reference
voltage
VREF+
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
Operating supply current
into AVCC terminal (1)
IREF+
TEST CONDITIONS
VCC
MIN
TYP
MAX
REFVSEL = {2} for 2.5 V, REFON = 1
3V
2.47
2.51
2.55
REFVSEL = {1} for 2.0 V, REFON = 1
3V
1.95
1.99
2.03
REFVSEL = {0} for 1.5 V, REFON = 1
2.2 V, 3 V
1.46
1.50
1.54
REFVSEL = {0} for 1.5 V
1.8
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
UNIT
V
V
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
3V
23
30
µA
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2.0 V
3V
21
27
µA
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V
3V
19
25
µA
10
50
ppm/
°C
TCREF+
Temperature coefficient of
built-in reference (2)
REFVSEL = {0, 1, 2}, REFON = 1
ISENSOR
Operating supply current
into AVCC terminal
REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C
2.2 V
145
220
3V
170
245
VSENSOR
See
REFON = 1, ADC10ON = 1,
INCH = 0Ah, TA = 30°C
2.2 V
780
3V
780
VMID
AVCC divider at channel 11
ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC
2.2 V
1.08
1.1
1.12
3V
1.48
1.5
1.52
tSENSOR(sample)
Sample time required if
channel 10 is selected (4)
REFON = 1, ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
tVMID(sample)
Sample time required if
channel 11 is selected (5)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
PSRR_DC
Power supply rejection ratio
(dc)
AVCC = AVCC (min) - AVCC(max)
TA = 25 °C
REFVSEL = {0, 1, 2}, REFON = 1
120
PSRR_AC
Power supply rejection ratio
(ac)
AVCC = AVCC (min) - AVCC(max)
TA = 25 °C
f = 1 kHz, ΔVpp = 100 mV
REFVSEL = {0, 1, 2}, REFON = 1
1
mV/V
tSETTLE
Settling time of reference
voltage (6)
AVCC = AVCC (min) - AVCC(max)
REFVSEL = {0, 1, 2}, REFON = 0 → 1
75
µs
VSD24REF
SD24_B internal reference
voltage
SD24REFS = 1
3V
tON
SD24_B internal reference
turn-on time (7)
SD24REFS = 0->1, CREF = 100 nF
3V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
80
(3)
µA
mV
V
30
µs
1
µs
1.137
1.151
200
300
1.165
µV/V
V
µs
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended to minimize the offset error of the
built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
The condition is that the error in a conversion started after tREFON is ≤ 1 LSB.
The condition is that SD24_B conversion started after tON should guarantee specified SINAD values for the selected Gain, OSR and
fSD24.
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
DVCC(PGM/ERASE) Program and erase supply voltage
IPGM
Average supply current from DVCC during program
IERASE
Average supply current from DVCC during erase
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank erase
tCPT
Cumulative program time
MIN
TYP
1.8
3.6
3
See
MAX
(1)
104
V
5
mA
8
mA
5
mA
16
Program/erase endurance
UNIT
105
ms
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
64
85
µs
tBlock,
0
Block program time for first byte or word
See
(2)
49
65
µs
1–(N–1)
Block program time for each additional byte or word, except for last
byte or word
See
(2)
37
49
µs
Block program time for last byte or word
See
(2)
55
73
µs
tErase
Erase time for segment erase, mass erase, and bank erase when
available
See
(2)
23
32
ms
fMCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
0
1
MHz
tBlock,
tBlock,
(1)
(2)
N
100
years
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word- or byte-write and block-write modes.
These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V, 3 V
0.025
15
µs
tSBW,
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) (1)
2.2 V, 3 V
1
µs
100
µs
En
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency for 4-wire JTAG (2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
15
2.2 V
0
5
3V
0
10
2.2 V, 3 V
45
60
80
MHz
kΩ
Tools accessing the Spy-Bi-Wire interface need to wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 and P1.1, Input/Output With Schmitt Trigger (MSP430F67xxIPZ and
MSP430F67xxIPN)
Pad Logic
to/from Reference
To ADC10_A
INCHx = y
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
from Port Mapping
1
P1OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
to Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Table 63. Port P1 (P1.0 and P1.1) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x)
P1.0/PM_TA0.0/
VeREF-/A2
P1.1/PM_TA0.1/
VeREF+/A1
(1)
(2)
82
x
0
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
0
X
0
1
default
TA0.TA0
1
1
default
VeREF-/A2 (2)
X
1
= 31
I: 0; O: 1
0
X
0
1
default
TA0.TA1
1
1
default
VeREF+/A1 (2)
X
1
= 31
P1.0 (I/O)
TA0.CCI0A
1
CONTROL BITS/SIGNALS (1)
P1.1 (I/O)
TA0.CCI1A
P1MAPx
X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Port P1, P1.2, Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN)
Pad Logic
To ADC10_A
INCHx = y
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
from Port Mapping
1
P1OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
to Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Table 64. Port P1 (P1.2) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x)
x
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
2
(1)
(2)
FUNCTION
CONTROL BITS/SIGNALS (1)
P1DIR.x
P1SEL.x
P1MAPx
I: 0; O: 1
0
X
UCA0RXD/UCA0SOMI
X
1
default
A0 (2)
X
1
= 31
P1.2 (I/O)
X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
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Port P1, P1.3 to P1.5, Input/Output With Schmitt Trigger (MSP430F67xxIPZ and
MSP430F67xxIPN)
to LCD_C
Pad Logic
P1REN.x
P1MAP.x = PMAP_ANALOG
P1DIR.x
0
from Port Mapping
1
P1OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
P1IN.x
Bus
Keeper
EN
to Port Mapping
D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Table 65. Port P1 (P1.3 to P1.5) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
PIN NAME (P1.x)
x
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
3
FUNCTION
P1.3 (I/O)
UCA0TXD/UCA0SIMO
R03 (2)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
4
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
5
(1)
(2)
84
P1.4 (I/O)
UCA1RXD/UCA1SOMI
LCDREF/R13 (2)
CONTROL BITS/SIGNALS (1)
P1DIR.x
P1SEL.x
I: 0; O: 1
0
P1MAPx
X
X
1
default
= 31
X
1
I: 0; O: 1
0
X
X
1
default
= 31
X
1
I: 0; O: 1
0
X
UCA1TXD/UCA1SIMO
X
1
default
R23 (2)
X
1
= 31
P1.5 (I/O)
X = Don't care
Setting P1SEL.x bit together with P1MAPx = PM_ANALOG disables the output driver as well as the input Schmitt trigger.
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Port P1, P1.6 and P1.7 (MSP430F67xxIPZ and MSP430F67xxIPN),
Port P2, P2.0 and P2.1 (MSP430F67xxIPZ Only) Input/Output With Schmitt Trigger
COM4 to COM7
from LCD_C
Pad Logic
PyREN.x
PyMAP.x = PMAP_ANALOG
PyDIR.x
0
from Port Mapping
1
PyOUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
PyDS.x
0: Low drive
1: High drive
PySEL.x
P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
PyIN.x
Bus
Keeper
EN
to Port Mapping
D
PyIE.x
EN
PyIRQ.x
Q
PyIFG.x
PySEL.x
PyIES.x
Set
Interrupt
Edge
Select
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Table 66. Port P1 (P1.6 and P1.7) Pin Functions (MSP430F67xxIPZ and MSP430F67xxIPN)
CONTROL BITS/SIGNALS (1)
PIN NAME (P1.x)
P1.6/PM_UCA0CLK/COM4
x
6
FUNCTION
(1)
7
COM4,5
Enable Signal
0
X
0
1
default
0
X
1
= 31
0
P1SEL.x
P1.6 (I/O)
I: 0; O: 1
UCA0CLK
X
Output driver and input Schmitt
trigger disabled
COM4
P1.7/PM_UCB0CLK/COM5
P1MAPx
P1DIR.x
X
X
X
1
P1.7 (I/O)
I: 0; O: 1
0
X
0
UCB0CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM5
X
X
X
1
X = Don't care
Table 67. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxIPZ Only)
CONTROL BITS/SIGNALS (1)
PIN NAME (P2.x)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
x
0
FUNCTION
P2.0 (I/O)
(1)
86
1
P2SEL.x
P2MAPx
COM6,7
Enable Signal
I: 0; O: 1
0
X
0
UCB0SOMI/UCB0SCL
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM6
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
P2DIR.x
X
X
X
1
I: 0; O: 1
0
X
0
UCB0SIMO/UCB0SDA
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
COM7
X
X
X
1
P2.1 (I/O)
X = Don't care
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Port P2, P2.2 to P2.7, Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
P2.2/PM_UCA2RXD/PM_UCA2SOMI
P2.3/PM_UCA2TXD/PM_UCA2SIMO
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
P2.6/PM_TA1.0
P2.7/PM_TA1.1
Bus
Keeper
EN
to Port Mapping
1
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
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Table 68. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P2.x)
x
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
2
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
3
FUNCTION
P2.2 (I/O)
UCA2RXD/UCA2SOMI
Output driver and input Schmitt trigger disabled
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
P2.6/PM_TA1.0
4
5
6
(1)
88
7
P2DIR.x
P2SEL.x
P2MAPx
I: 0; O: 1
0
X
X
1
default
X
1
= 31
I: 0; O: 1
0
X
UCA2TXD/UCA2SIMO
X
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
P2.4 (I/O)
I: 0; O: 1
0
X
UCA1CLK
X
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
P2.5 (I/O)
I: 0; O: 1
0
X
UCA2CLK
X
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
I: 0; O: 1
0
X
0
1
default
TA1.TA0
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
I: 0; O: 1
0
X
TA1.CCI1A
0
1
default
TA1.TA1
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
P2.3 (I/O)
P2.6 (I/O)
TA1.CC10A
P2.7/PM_TA1.1
CONTROL BITS/SIGNALS (1)
P2.7 (I/O)
X = Don't care
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Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
from Port Mapping
1
P3OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.0/PM_TA2.0
P3.1/PM_TA2.1
P3.2/PM_TACLK/PM_RTCCLK
P3.3/PM_TA0.2
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
to Port Mapping
D
Table 69. Port P3 (P3.0 to P3.3) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P3.x)
P3.0/PM_TA2.0
x
0
FUNCTION
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
0
1
default
TA2.TA0
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
I: 0; O: 1
0
X
TA2.CCI1A
0
1
default
TA2.TA1
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
I: 0; O: 1
0
X
TACLK
0
1
default
RTCCLK
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
P3.0 (I/O)
TA2.CC10A
P3.1/PM_TA2.1
P3.2/PM_TACLK/
PM_RTCCLK
P3.3/PM_TA0.2
(1)
1
2
3
CONTROL BITS/SIGNALS (1)
P3.1 (I/O)
P3.2 (I/O)
P3.3 (I/O)
P3MAPx
I: 0; O: 1
0
X
TA0.CCI2A
0
1
default
TA0.TA2
1
1
default
Output driver and input Schmitt trigger disabled
X
1
= 31
X = Don't care
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Port P3, P3.4 to P3.7 , Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
S39 to S37
LCDS39 to LCDS37
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
from Port Mapping
1
P3OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P3.4/PM_SDCLK/S39
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
P3.7/PM_SD2DIO/S36
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
to Port Mapping
D
Table 70. Port P3 (P3.4 to P3.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P3.x)
P3.4/PM_SDCLK/S39
P3.5/PM_SD0DIO/S38
x
4
5
FUNCTION
P3DIR.x
P3SEL.x
P3MAPx
LCDS39...36
I: 0; O: 1
0
X
0
SDCLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S39
X
X
X
1
P3.4 (I/O)
P3.5 (I/O)
I: 0; O: 1
0
X
0
SD0DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S38
P3.6/PM_SD1DIO/S37
6
X
X
X
1
I: 0; O: 1
0
X
0
SD1DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.6 (I/O)
S37
P3.7/PM_SD2DIO/S36
(1)
90
7
CONTROL BITS/SIGNALS (1)
X
X
X
1
I: 0; O: 1
0
X
0
SD2DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S36
X
X
X
1
P3.7 (I/O)
X = Don't care
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Port P4, Port P5, Port P6, Port P7, Port P8, P8.0 to P8.3
Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Sz
LCDSz
Pad Logic
PyREN.x
PyDIR.x
0
0
DVSS
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
PyOUT.x
DVSS
PyDS.x
0: Low drive
1: High drive
PySEL.x
Py.x/Sz
PyIN.x
EN
Not Used
Bus
Keeper
D
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Table 71. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P4.x)
P4.0/S35
P4.1/S34
x
0
1
FUNCTION
P4.0 (I/O)
2
3
P4.5/S30
P4.6/S29
4
5
6
0
0
1
0
DVSS
1
1
0
S35
X
X
1
P4.1 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P4.2 (I/O)
7
92
X
1
0
0
0
1
0
1
1
0
S33
X
X
1
I: 0; O: 1
0
0
0
1
0
P4.3 (I/O)
DVSS
1
1
0
S32
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S31
X
X
1
P4.4 (I/O)
P4.5 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S30
X
X
1
P4.6 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P4.7 (I/O)
N/A
(1)
X
I: 0; O: 1
DVSS
S29
P4.7/S28
LCDS35...28
0
N/A
P4.4/S31
P4SEL.x
I: 0; O: 1
N/A
P4.3/S32
P4DIR.x
N/A
S34
P4.2/S33
CONTROL BITS/SIGNALS (1)
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S28
X
X
1
X = Don't care
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Table 72. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P5.x)
P5.0/S27
P5.1/S26
x
0
1
FUNCTION
P5.0 (I/O)
2
3
P5.5/S22
P5.6/S21
4
5
6
0
0
1
0
DVSS
1
1
0
S27
X
X
1
P5.1 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P5.2 (I/O)
7
X
1
0
0
0
1
0
1
1
0
S25
X
X
1
I: 0; O: 1
0
0
0
1
0
P5.3 (I/O)
DVSS
1
1
0
S24
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S23
X
X
1
P5.4 (I/O)
P5.5 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S22
X
X
1
P5.6 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P5.7 (I/O)
N/A
(1)
X
I: 0; O: 1
DVSS
S21
P5.7/S20
LCDS27...20
0
N/A
P5.4/S23
P5SEL.x
I: 0; O: 1
N/A
P5.3/S24
P5DIR.x
N/A
S26
P5.2/S25
CONTROL BITS/SIGNALS (1)
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S20
X
X
1
X = Don't care
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Table 73. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P6.x)
P6.0/S19
P6.1/S18
x
0
1
FUNCTION
P6.0 (I/O)
2
3
P6.5/S14
P6.6/S13
4
5
6
0
0
1
0
DVSS
1
1
0
S19
X
X
1
P6.1 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P6.2 (I/O)
7
94
X
1
0
0
0
1
0
1
1
0
S17
X
X
1
I: 0; O: 1
0
0
0
1
0
P6.3 (I/O)
DVSS
1
1
0
S16
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S15
X
X
1
P6.4 (I/O)
P6.5 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S14
X
X
1
P6.6 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P6.7 (I/O)
N/A
(1)
X
I: 0; O: 1
DVSS
S13
P6.7/S12
LCDS19...12
0
N/A
P6.4/S15
P6SEL.x
I: 0; O: 1
N/A
P6.3/S16
P6DIR.x
N/A
S18
P6.2/S17
CONTROL BITS/SIGNALS (1)
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S12
X
X
1
X = Don't care
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Table 74. Port P7 (P7.0 to P7.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P7.x)
P7.0/S11
P7.1/S10
x
0
1
FUNCTION
P7.0 (I/O)
2
3
P7.5/S6
P7.6/S5
4
5
6
0
0
1
0
DVSS
1
1
0
S11
X
X
1
P7.1 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P7.2 (I/O)
7
X
1
0
0
0
1
0
1
1
0
S9
X
X
1
I: 0; O: 1
0
0
0
1
0
P7.3 (I/O)
DVSS
1
1
0
S8
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S7
X
X
1
P7.4 (I/O)
P7.5 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S6
X
X
1
P7.6 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P7.7 (I/O)
N/A
(1)
X
I: 0; O: 1
DVSS
S5
P7.7/S4
LCDS11...4
0
N/A
P7.4/S7
P7SEL.x
I: 0; O: 1
N/A
P7.3/S8
P7DIR.x
N/A
S10
P7.2/S9
CONTROL BITS/SIGNALS (1)
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S4
X
X
1
X = Don't care
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Table 75. Port P8 (P8.0 to P8.3) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P8.x)
P8.0/S3
P8.1/S2
x
0
1
FUNCTION
P8.0 (I/O)
2
3
96
LCDS3...0
0
0
0
1
0
DVSS
1
1
0
S3
X
X
1
P8.1 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P8.2 (I/O)
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S1
X
X
1
I: 0; O: 1
0
0
0
1
0
P8.3 (I/O)
N/A
(1)
P8SEL.x
I: 0; O: 1
N/A
P8.3/S0
P8DIR.x
N/A
S2
P8.2/S1
CONTROL BITS/SIGNALS (1)
DVSS
1
1
0
S0
X
X
1
X = Don't care
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Port P8, P8.4 to P8.7, Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Pad Logic
P8REN.x
P8DIR.x
0
0
DVCC
1
1
Direction
0: Input
1: Output
1
P8OUT.x
DVSS
0
1
Module X OUT
P8.4/TA1.0
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
Module X IN
D
Table 76. Port P8 (P8.4 to P8.7) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P8.x)
P8.4/TA1.0
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1
x
4
5
6
7
FUNCTION
P8.4 (I/O)
CONTROL BITS/SIGNALS
P8DIR.x
P8SEL.x
I: 0; O: 1
0
TA1.CCI0A
0
1
TA1.TA0
1
1
P8.5 (I/O)
I: 0; O: 1
0
TA1.CCI1A
0
1
TA1.TA1
1
1
P8.6 (I/O)
I: 0; O: 1
0
TA2.CCI0A
0
1
TA2.TA0
1
1
P8.7 (I/O)
I: 0; O: 1
0
TA2.CCI1A
0
1
TA2.TA1
1
1
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Port P9, P9.0, Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Pad Logic
P9REN.x
P9DIR.x
0
Module X OUT
0
DVCC
1
1
Direction
0: Input
1: Output
1
P9OUT.x
DVSS
0
1
P9.0/TACLK/RTCCLK
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
EN
Module X IN
D
Table 77. Port P9 (P9.0) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P9.x)
P9.0/TACLK/RTCCLK
98
x
0
FUNCTION
CONTROL BITS/SIGNALS
P9DIR.x
P9SEL.x
I: 0; O: 1
0
TACLK
0
1
RTCCLK
1
1
P9.0 (I/O)
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Port P9, P9.1 to P9.3, Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
Pad Logic
To ADC10
INCHx = y
P9REN.x
DVSS
0
DVCC
1
1
P9DIR.x
P9OUT.x
P9.1/A5
P9.2/A4
P9.3/A3
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
Bus
Keeper
Table 78. Port P9 (P9.1 to P9.3) Pin Functions (MSP430F67xxIPZ Only)
PIN NAME (P9.x)
P9.1/A5
x
1
FUNCTION
P9.1 (I/O)
A5
P9.2/A4
2
(2)
P9.2 (I/O)
A4 (2)
P9.3/A3
3
P9.3 (I/O)
A3
(1)
(2)
(2)
CONTROL BITS/SIGNALS (1)
P9DIR.x
P9SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
Setting P9SEL.x bit disables the output driver as well as the input Schmitt trigger.
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Port P2, P2.0 and P2.1, Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
S39, S38
LCDS39, LCDS38
COM6, COM7
from LCD_C
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38
P2IN.x
Bus
Keeper
EN
to Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
100
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Interrupt
Edge
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Table 79. Port P2 (P2.0 and P2.1) Pin Functions (MSP430F67xxIPN Only)
CONTROL BITS/SIGNALS (1)
PIN NAME (P2.x)
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/
S39
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/
S38
(1)
x
0
1
FUNCTION
P2.0 (I/O)
P2DIR.x
P2SEL.x
P2MAPx
LCDS39,
LCDS38
COM6,7
Enable
Signal
I: 0; O: 1
0
X
0
0
UCB0SOMI/UCB0SCL
X
1
default
0
0
Output driver and input
Schmitt trigger disabled
X
1
= 31
0
0
COM6
X
X
X
X
1
S39
X
X
X
1
0
P2.1 (I/O)
I: 0; O: 1
0
X
0
0
UCB0SIMO/UCB0SDA
X
1
default
0
0
Output driver and input
Schmitt trigger disabled
X
1
= 31
0
0
COM7
X
X
X
X
1
S38
X
X
X
1
0
X = Don't care
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Port P2, P2.2 to P2.7 , Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
S37...S32
LCDS37...LCDS32
Pad Logic
P2REN.x
P2MAP.x = PMAP_ANALOG
P2DIR.x
0
from Port Mapping
1
P2OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37
P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0/S33
P2.7/PM_TA1.1/S32
Bus
Keeper
EN
to Port Mapping
1
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
102
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Interrupt
Edge
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 80. Port P2 (P2.2 to P2.7) Pin Functions (MSP430F67xxIPN Only)
PIN NAME (P2.x)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
x
2
FUNCTION
P2.2 (I/O)
3
4
5
6
X
0
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
X
X
X
1
I: 0; O: 1
0
X
0
UCA2TXD/UCA2SIMO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.3 (I/O)
X
X
X
1
P2.4 (I/O)
I: 0; O: 1
0
X
0
UCA1CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
X
X
X
1
P2.5 (I/O)
I: 0; O: 1
0
X
0
UCA2CLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
X
X
X
1
I: 0; O: 1
0
X
0
TA1.CCI0A
0
1
default
0
TA1.TA0
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P2.6 (I/O)
S33
P2.7/PM_TA1.1/S32
(1)
7
LCDS37...32
0
S34
P2.6/PM_TA1.0/S33
P2MAPx
X
S35
P2.5/PM_UCA2CLK/S34
P2SEL.x
I: 0; O: 1
S36
P2.4/PM_UCA1CLK/S35
P2DIR.x
UCA2RXD/UCA2SOMI
S37
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
CONTROL BITS/SIGNALS (1)
X
X
X
1
I: 0; O: 1
0
X
0
TA1.CCI1A
0
1
default
0
TA1.TA1
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S32
X
X
X
1
P2.7 (I/O)
X = Don't care
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Port P3, P3.0 to P3.7 , Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
S31 to S24
LCDS31 to LCDS24
Pad Logic
P3REN.x
P3MAP.x = PMAP_ANALOG
P3DIR.x
0
from Port Mapping
1
P3OUT.x
0
from Port Mapping
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
to Port Mapping
104
1
Bus
Keeper
P3.0/PM_TA2.0/S31
P3.1/PM_TA2.1/S30
P3.2/PM_TACLK/PM_RTCCLK/S29
P3.3/PM_TA0.2/S28
P3.4/PM_SDCLK/S27
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
P3.7/PM_SD2DIO/S24
D
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 81. Port P3 (P3.0 to P3.7) Pin Functions (MSP430F67xxIPN Only)
PIN NAME (P3.x)
P3.0/PM_TA2.0/S31
x
0
FUNCTION
P3.0 (I/O)
1
P3.3/PM_TA0.2/S28
P3.4/PM_SDCLK/S27
2
3
4
5
6
X
0
1
default
0
TA2.TA0
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
X
X
X
1
I: 0; O: 1
0
X
0
TA2.CCI1A
0
1
default
0
TA2.TA1
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.1 (I/O)
X
X
X
1
I: 0; O: 1
0
X
0
TACLK
0
1
default
0
RTCCLK
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S29
X
X
X
1
P3.2 (I/O)
P3.3 (I/O)
I: 0; O: 1
0
X
0
TA0.CCI2A
0
1
default
0
TA0.TA2
1
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S28
X
X
X
1
P3.4 (I/O)
I: 0; O: 1
0
X
0
SDCLK
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
X
X
X
1
I: 0; O: 1
0
X
0
SD0DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.5 (I/O)
X
X
X
1
I: 0; O: 1
0
X
0
SD1DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
P3.6 (I/O)
S25
P3.7/PM_SD2DIO/S24
(1)
7
LCDS31...24
0
S26
P3.6/PM_SD1DIO/S25
P3MAPx
0
S27
P3.5/PM_SD0DIO/S26
P3SEL.x
I: 0; O: 1
S30
P3.2/PM_TACLK/
PM_RTCCLK/S29
P3DIR.x
TA2.CCI0A
S31
P3.1/PM_TA2.1/S30
CONTROL BITS/SIGNALS (1)
X
X
X
1
I: 0; O: 1
0
X
0
SD2DIO
X
1
default
0
Output driver and input Schmitt
trigger disabled
X
1
= 31
0
S24
X
X
X
1
P3.7 (I/O)
X = Don't care
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Port P4, Port P5, Port P6, Input/Output With Schmitt Trigger (MSP430F67xxIPN Only)
Sz
LCDSz
Pad Logic
PyREN.x
PyDIR.x
0
0
DVSS
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
PyOUT.x
DVSS
PyDS.x
0: Low drive
1: High drive
PySEL.x
Py.x/Sz
PyIN.x
EN
Not Used
106
Bus
Keeper
D
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 82. Port P4 (P4.0 to P4.7) Pin Functions (MSP430F67xxIPN Only)
PIN NAME (P4.x)
P4.0/S23
P4.1/S22
x
0
1
FUNCTION
P4.0 (I/O)
2
3
P4.5/S18
P4.6/S17
4
5
6
0
0
1
0
DVSS
1
1
0
S23
X
X
1
P4.1 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P4.2 (I/O)
7
X
1
0
0
0
1
0
1
1
0
S21
X
X
1
I: 0; O: 1
0
0
0
1
0
P4.3 (I/O)
DVSS
1
1
0
S20
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S19
X
X
1
P4.4 (I/O)
P4.5 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S18
X
X
1
P4.6 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P4.7 (I/O)
N/A
(1)
X
I: 0; O: 1
DVSS
S17
P4.7/S16
LCDS23...16
0
N/A
P4.4/S19
P4SEL.x
I: 0; O: 1
N/A
P4.3/S20
P4DIR.x
N/A
S22
P4.2/S21
CONTROL BITS/SIGNALS (1)
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S16
X
X
1
X = Don't care
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Table 83. Port P5 (P5.0 to P5.7) Pin Functions (MSP430F67xxIPN Only)
PIN NAME (P5.x)
P5.0/S15
P5.1/S14
x
0
1
FUNCTION
P5.0 (I/O)
2
3
P5.5/S10
P5.6/S9
4
5
6
0
0
1
0
DVSS
1
1
0
S15
X
X
1
P5.1 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P5.2 (I/O)
7
108
X
1
0
0
0
1
0
1
1
0
S13
X
X
1
I: 0; O: 1
0
0
0
1
0
P5.3 (I/O)
DVSS
1
1
0
S12
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S11
X
X
1
P5.4 (I/O)
P5.5 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S10
X
X
1
P5.6 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P5.7 (I/O)
N/A
(1)
X
I: 0; O: 1
DVSS
S9
P5.7/S8
LCDS15...8
0
N/A
P5.4/S11
P5SEL.x
I: 0; O: 1
N/A
P5.3/S12
P5DIR.x
N/A
S14
P5.2/S13
CONTROL BITS/SIGNALS (1)
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S8
X
X
1
X = Don't care
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 84. Port P6 (P6.0 to P6.7) Pin Functions (MSP430F67xxIPN Only)
PIN NAME (P6.x)
P6.0/S7
P6.1/S6
x
0
1
FUNCTION
P6.0 (I/O)
2
3
P6.5/S2
P6.6/S1
4
5
6
0
0
1
0
DVSS
1
1
0
S7
X
X
1
P6.1 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P6.2 (I/O)
7
X
1
0
0
0
1
0
1
1
0
S5
X
X
1
I: 0; O: 1
0
0
0
1
0
P6.3 (I/O)
DVSS
1
1
0
S4
X
X
1
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S3
X
X
1
P6.4 (I/O)
P6.5 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
S2
X
X
1
P6.6 (I/O)
I: 0; O: 1
0
0
N/A
0
1
0
DVSS
1
1
0
P6.7 (I/O)
N/A
(1)
X
I: 0; O: 1
DVSS
S1
P6.7/S0
LCDS7...0
0
N/A
P6.4/S3
P6SEL.x
I: 0; O: 1
N/A
P6.3/S4
P6DIR.x
N/A
S6
P6.2/S5
CONTROL BITS/SIGNALS (1)
X
X
1
I: 0; O: 1
0
0
0
1
0
DVSS
1
1
0
S0
X
X
1
X = Don't care
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Port J, J.0, JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
PJDIR.x
0
DVCC
1
PJOUT.x
00
From JTAG
01
SMCLK
10
DVSS
0
DVCC
1
1
PJ.0/SMCLK/TDO
PJDS.0
0: Low drive
1: High drive
11
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
Port J, J.1 to J.3, JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
PJDIR.x
DVSS
PJOUT.x
DVSS
0
DVCC
1
1
0
1
00
From JTAG
01
MCLK/ADC10CLK/ACLK
10
PJDS.x
0: Low drive
1: High drive
11
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
PJSEL.x
From JTAG
PJIN.x
EN
To JTAG
110
Bus
Holder
D
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 85. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS/ SIGNALS (1)
PIN NAME (PJ.x)
PJ.0/SMCLK/TDO
PJDIR.x
PJSEL.x
JTAG
Mode
Signal
I: 0; O: 1
0
0
1
1
0
(3)
X
X
1
PJ.1 (I/O) (2)
I: 0; O: 1
0
0
1
1
0
x
0
FUNCTION
PJ.0 (I/O) (2)
SMCLK
TDO
PJ.1/MCLK/TDI/TCLK
1
MCLK
TDI/TCLK
PJ.2/ADC10CLK/TMS
2
X
X
1
PJ.2 (I/O) (2)
I: 0; O: 1
0
0
ADC10CLK
1
1
0
X
X
1
I: 0; O: 1
0
0
1
1
0
X
X
1
TMS
PJ.3/ACLK/TCK
3
(3) (4)
(3) (4)
PJ.3 (I/O)
(2)
ACLK
TCK
(1)
(2)
(3)
(4)
(3) (4)
X = Don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
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DEVICE DESCRIPTORS (TLV)
Table 86 and Table 87 list the complete contents of the device descriptor tag-length-value (TLV) structure for
each device type.
Table 86. MSP430F673x Device Descriptor Table
Info Block
Die Record
ADC10
Calibration
112
F6736PZ
F6736PN
F6735PZ
F6735PN
F6734PZ
F6734PN
F6733PZ
F6733PN
F6731PZ
F6731PN
F6730PZ
F6730PN
Value
Value
Value
Value
Value
Value
06h
06h
06h
06h
06h
06h
1
06h
06h
06h
06h
06h
06h
01A02h
2
per unit
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
1
6Ch
6Bh
6Ah
65h
63h
62h
Description
Address
Size
bytes
Info length
01A00h
1
CRC length
01A01h
CRC value
Device ID
01A05h
1
81h
81h
81h
80h
80h
80h
Hardware revision
01A06h
1
per unit
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC10 Calibration Tag
01A14h
1
13h
13h
13h
13h
13h
13h
ADC10 Calibration length
01A15h
1
10h
10h
10h
10h
10h
10h
ADC Gain Factor
01A16h
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC Offset
01A18h
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 30°C
01A1Ah
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 85°C
01A1Ch
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 30°C
01A1Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 85°C
01A20h
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 30°C
01A22h
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 85°C
01A24h
2
per unit
per unit
per unit
per unit
per unit
per unit
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SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Table 87. MSP430F672x Device Descriptor Table
Description
Info Block
Die Record
ADC10
Calibration
Address
Size
bytes
F6726PZ
F6726PN
F6725PZ
F6725PN
F6724PZ
F6724PN
F6723PZ
F6723PN
F6721PZ
F6721PN
F6720PZ
F6720PN
Value
Value
Value
Value
Value
Value
06h
Info length
01A00h
1
06h
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
06h
06h
CRC value
01A02h
2
per unit
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
1
6Fh
6Eh
6Dh
61h
59h
58h
Device ID
01A05h
1
81h
81h
81h
80h
80h
80h
Hardware revision
01A06h
1
per unit
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
1
per unit
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
1
08h
08h
08h
08h
08h
08h
Die Record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Lot/Wafer ID
01A0Ah
4
per unit
per unit
per unit
per unit
per unit
per unit
Die X position
01A0Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
Die Y position
01A10h
2
per unit
per unit
per unit
per unit
per unit
per unit
Test results
01A12h
2
per unit
per unit
per unit
per unit
per unit
per unit
13h
ADC10 Calibration Tag
01A14h
1
13h
13h
13h
13h
13h
ADC10 Calibration length
01A15h
1
10h
10h
10h
10h
10h
10h
ADC Gain Factor
01A16h
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC Offset
01A18h
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 30°C
01A1Ah
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 1.5-V Reference
Temp. Sensor 85°C
01A1Ch
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 30°C
01A1Eh
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V Reference
Temp. Sensor 85°C
01A20h
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 30°C
01A22h
2
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.5-V Reference
Temp. Sensor 85°C
01A24h
2
per unit
per unit
per unit
per unit
per unit
per unit
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REVISION HISTORY
REVISION
SLAS731
SLAS731A
114
COMMENTS
Production Data release
Changed the SYSRSTIV, System Reset Interrupt Event at offset 1Ch to Reserved in Table 16.
Changed LPM3 current in Features.
Changed limits for ILPM0,1MHz, ILPM2, and ILPM3,XT1LF in Low-Power Mode Supply Currents (Into VCC) Excluding External
Current.
Changed limits for ILPM3,LCD,int. bias in Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current.
Corrected values in "x" column in Table 70.
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PACKAGE OPTION ADDENDUM
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28-May-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F6720IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6720IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6720IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6720IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6721IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6721IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6721IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6721IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6723IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6723IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6723IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6723IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6724IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6724IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6724IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6724IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6725IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Addendum-Page 1
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
28-May-2012
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F6725IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6725IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6725IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6726IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6726IPNR
ACTIVE
LQFP
PN
80
1
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6726IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6726IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6730IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6730IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6730IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6730IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6731IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6731IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6731IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6731IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6733IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6733IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6733IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Addendum-Page 2
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
28-May-2012
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430F6733IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6734IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6734IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6734IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6734IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6735IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6735IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6735IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6735IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6736CY
PREVIEW
DIESALE
Y
0
1
TBD
MSP430F6736CYS
PREVIEW WAFERSALE
Call TI
Call TI
Call TI
Call TI
YS
0
1
TBD
MSP430F6736IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6736IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6736IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430F6736IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 3
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2012
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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