MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC DESCRIPTION The M62500 is a semiconductor integrated circuit designed and PIN CONFIGURATION (TOP VIEW) developed as a deflection control of the CRT display monitor. The built-in trigger mode oscillator allows stable PWM control to be gained against a wide range of change of external signals. GND 1 24 VCC VREF 2 23 DRIVE OUTPUT Tin 3 The M62500 provides a low supply voltage output malfunction preventive circuit (UVLO) and software start function optimum to Delay Adj 4 horizontal output correction of monitor, high voltage drive and high 5 CAGC1 22 Phase Adj 21 Duty Adj 20 DOUBLE SPEED SWITCH 19 RAGC DTC 6 voltage regulator. FEATURES PWM output in synchronization with external signals Wide range of PWM control frequency IN1 (+) 7 18 CAGC2 IN1 (-) 8 17 IN2 (+) FB1 9 16 IN2 (-) COLLECTOR1 10 15kHz to 150kHz 15 FB2 OUT1 11 The PWM output phase is adjustable against external signals 14 COLLECTOR2 P.GND 12 13 OUT2 Soft start Built-in low voltage output malfunction prevention circuit Outline 24P4D (P) 24P2V-A (FP) Start VCC>9V Stop VCC<6V APPLICATION CRT display monitor BLOCK DIAGRAM VCC DRIVE OUTPUT Phase Adj Duty Adj DOUBLE SPEED SWITCH RAGC CAGC2 IN2 (+) IN2 (-) 24 23 22 21 20 19 18 17 16 15 14 9 10 11 FB2 COLLECTOR2 OUT2 13 PHASE CONT WIND COMP EDGE DETECTION (SWITCH) DUTY CONT GEN AGC comp OUTPUT START START (VCC>9V) STOP (VCC<6V) GEN AGC VREF VCC DELAY 1 2 3 4 5 6 7 8 GND VREF Tin Delay Adj CAGC1 DTC IN1 (+) IN1 (-) ( 1 / 11 ) FB1 COLLECTOR1 OUT1 12 P. GND MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC ABSOLUTE MAXIMUM RATINGS (Ta=25˚C, unless otherwise noted) Symbol VCC VOUT IOUT Vd Id VICM VID Parameter Supply voltage Output voltage Output current Drive output voltage Drive output current Common mode input voltage range of error amplifier Common mode differential input voltage of error amplifier Pd Power dissipation K Thermal derating Topr Tstg Operating temperature Storage temperature Ratings 15 15 ±150 15 20 Unit V V mA V mA -0.3 to VCC V VCC V P FP 1400 1000 P FP 11.2 8 -20 to +75 -40 to +125 mW mW/°C °C °C Note. For the polarity of current, the direction in which current flows to the IC is specified positive (+), while the direction in which current flows out from the IC is specified to be negative (-). ( 2 / 11 ) MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC ELECTRICAL CHARACTERISTICS (VCC=12V, fIN=40kHz, Ta=25˚C, unless otherwise noted) Block Symbol VCC ICC VCC ON VCC OFF VIO IIb IIO VICM AV SR VOR Isink Isource VsatL VsatH VREF Reg-in Reg-L TCVREF IREF MAX IS IIN VIN L VIN H IDelay TD min TD max IDTC Vth U Vth L TDuty IDuty Duty min Duty max Duty IPhase T2 min T2 max T2 Vsat D ILD Ifh Vfh Parameter Range of power supply voltage Dissipation current Activation start voltage Activation stop voltage Input offset voltage Input bias voltage Input offset current Common mode input range Open loop gain Through rate Output voltage range 1) Output sink current Output source current Output saturation voltage L Output saturation voltage H Reference voltage Input stability Load voltage Temperature coefficient of reference voltage Maximum reference current Short-circuit current Input current "L" input voltage "H" input voltage Input current Minimum delay time Maximum delay time Input current Test conditions Without signal -100 -100 -0.3 70 IO=100mA IO=-100mA IREF=-5mA VCC=7 to 14V IREF=-5mA IREF=0 to -5mA Ta=-20 to +75°C VIN=5V VDelay adj=0V VDelay adj=3.0V 40 9 6.0 9.5 4.80 — — 2.0 -0.6 — 10 — Max. 14 70 10 6.6 7 100 VCC-2 110 4 VREF-1.5 0.7 10.5 5.00 1 2 0.01 -40 -70 140 — — -0.1 0.8 15 0.5 -10 1.4 5.20 10 20 200 0.6 — — 1 — 2.0 0.65VREF 0.7VREF 0.75VREF Lower limit voltage of saw tooth wave 0.28VREF 0.3VREF 0.32VREF VDTC=2.5V VDuty adj=2.5V VDuty adj=2.5V VPhase adj=2.5V Minimum leading time of drive output Minimum leading time of drive output Leading time of drive output Output saturation voltage Output leak current fh pin current fh switching voltage Limits Typ. 0.3 10 Upper limit voltage of saw tooth wave PWM output duty Input current Minimum duty Maximum duty Duty Input current Min. VCC off 20 8 5.4 VPhase adj=1.0V Id=10mA VDO=12V Vfh=5V 45 -6.5 — 80 45 -3.5 — 9 4.5 50 -1.3 10 95 50 -0.7 0.7 9.4 5.5 — 330 0.4VREF 0.5VREF Note 1. Output must not be reversed with input of 0. ( 3 / 11 ) 55 — 20 — 55 — 1.6 — 7.0 0.4 1 430 0.6VREF Unit V mA V V mV nA nA V dB V/µs V mA mA V V V mV mV %/°C mA mA µA V V µA µs µs µA V V % µA % % % µA µs µs µs V µA µA V MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC EXPLANATION OF TERMINALS Pin No. 1 Symbol GND Function and peripheral circuit of pins GND VCC 2 VREF 5.0V reference voltage External load of about 5mA can be taken out. 2 VREF 3 Tin Trigger input Read at the rising edge S 3 Tin Q FF R VREF 4 Delay Adj Delay adjustment Delay of read trigger signal VDelay : 0 to 3.0V TDelay : 1µ to 10µsec 4 VREF 5 18 CAGC1 CAGC2 AGC capacitance Connects capacitance between each pin and GND and sets up AGC sensitivity 5 18 ( 4 / 11 ) MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC EXPLANATION OF TERMINALS (Cont.) Pin No. 6 Symbol DTC Function and peripheral circuit of pins 6 Dead time control (PWM comparator + pin) VCC 7 8 16 17 IN1 (+) IN1 (-) IN2 (-) IN2 (+) 17 Air amplifier input pin 7 8 16 VCC 9 15 9 15 FB1 FB2 Air amplifier output (PWM comparator + input pin) 10 14 10 11 12 13 14 COLLECTOR1 OUT1 P.GND OUT2 COLLECTOR2 PWM output section 11 13 12 VREF 19 RAGC AGC current setup Connects resistance between pin 19 and GND and sets up AGC current on the OUT2 side. 19 ( 5 / 11 ) MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC EXPLANATION OF TERMINALS (Cont.) Pin No. Symbol Function and peripheral circuit of pins VREF 20 fh/2fh Double speed switch Switches frequency of OUT2 and drive output to the double frequency. OPEN, GND fh VREF 2fh 20 VREF 21 Duty Adj Duty adjustment of drive output 21 Phase adjustment of drive output against OUT2 (T2) VREF 22 Phase Adj DRIVE OUT 22 OUT2 T2 VREF 23 DRIVE OUTPUT Open collector output 24 VCC Supply terminal 23 ( 6 / 11 ) MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC APPLICATION EXAMPLE VCC VR2 D1 C4 VR4 VR3 VR1 C1 R1 Tin C2 1 24 2 23 3 22 4 21 5 20 C10 R12 DOUT C9 C8 C7 Ragc Cagc1 +IN1 -IN1 R4 C4 R3 R5 C3 R6 OUT1 C1, C10 VR 1, 2, 3, 4 C2, C8, C9 6 19 7 18 8 17 9 16 R2 10 15 11 14 12 13 : Is required for stabilization of Vcc and VREF. C5 R7 C6 R8 R11 -IN2 OUT2 R4, R5, R8, R9 assure the stability of feedback, R4 and R8 µF. C3, C4, C5, C6 shall be set to several kΩ to tens of kΩ to set : Is determined taking into account the load the gain to approx. 20dB to 40dB with f=1 capability of VREF. (External load capability kHz. If the gain is too low, jitter may take of approx. 5mA) Shall be normally set to place. It is therefore recommended to set C3 approx. 10kΩ. and C5 to tens of pF to hundreds of pF, C4 : Is added to high impedance pin of voltage and C6 to thousands of pF to tens of thousands of pF, and R5 and R9 to tens of kΩ to hundreds of kΩ. environment. Shall be normally set to approx. Ragc 0.1µF. : Resistance for setting AGC on the OUT2 side. Is set with Ragc=27kΩ. : Is added for the execution of software start. C7 : If f to be input into Tin suddenly changes, Set a time constant, taking into account the addition of C7 shortens non-control time of set value of VR2. Dout (output of "H"). As a capacitance value, : Is added to reduce interference by Tin and it is recommended to adopt 2.2µF. In the outputs. With VIN=approx. 2.5V to 5V, the case of adding C7, however, resistance value of approx. 22kΩ is Cagc2≥0.68µF is recommended. recommended. Cagc 1, 2 R9 +IN2 R2, R3, R10, R11 : A gain setup constant of error Amp. To Depends on the device installation R1 R10 Is normally set to tens of µF to hundreds of control for improvement in noise margin. C4, D1 Cagc2 R6, R7 : Current limit resistance of OUT1/2. Is normally set to several Ω. Insertion of direct : Capacitance necessary for stabilization of AGC. As the capacitance is larger, the limit resistance into OUT1/2 pin is also stability is larger, but the characteristic of answering becomes worse. The capacitance effective. R12 value of 1µF is recommended. : Pull-up resistance of DOUT output. DOUT is an open collector output and requires R12. Is normally set to several kΩ. * Note: To reduce interference in the signal system, pins 1 GND and 12 P.GND shall be grounded at a point in the power supply block. ( 7 / 11 ) MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC SETUP OF VOLTAGE CONTROL BLOCK TD vs. VDELAY Adj CHARACTERISTICS (f=40kHz) 20 Applying a voltage to the DELAY Adj pin can control the delay time of OUT1 to TIN. 10 TIN TD TD OUT1 0 0 2.0 4.0 VDELAY Adj (V) PWM OUTPUT MINIMUM DUTY vs. VDTC CHARACTERISTICS (f=40kHz) 100 Applying a voltage to the DTC pin can control the dead time of PWM output. 80 60 TH 40 OUT1, 2 T 20 PWM output minimum duty 0 0 1 2 3 TDUTY= TH X100 (%) T 4 VDTC (V) T2 vs. VPhase CHARACTERISTICS (f=40kHz) 10 Applying a voltage to the Phase Adj pin can control a leading time of drive output to OUT2. 8 6 OUT2 4 T2 2 DRIVE OUT 0 0 1 2 3 4 5 VPhase (V) ( 8 / 11 ) T2 MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC T2 vs. f CHARACTERISTICS 10 VPhase=2300mV 8 VPhase=1350mV 6 VPhase=650mV 4 VPhase=250mV 2 0 50 0 100 150 TIN f (kHz) DRIVE OUTPUT DUTY vs. VDUTY CHARACTERISTICS (f=40kHz) 100 Applying a voltage to the DUTY Adj pin can control drive output duty. 80 60 TH Drive output T 40 20 0 Drive output duty 0 1 2 3 TDUTY= TH X100 (%) T 4 VDUTY (V) ( 9 / 11 ) MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC TIME CHART VCC DRIVE OUTPUT PHASE ADJ DUTY ADJ DOUBLE SPEED SWITCH 24 23 22 21 20 RAGC CAGC2 IN2 (+) IN2 (-) FB2 COLLECTOR2 OUT2 19 18 17 16 15 14 9 10 11 13 PHASE CONT WIND COMP EDGE DETECTION (SWITCH) DUTY CONT D E GEN AGC F comp C B OUTPUT START START (VCC>9V) STOP (VCC<6V) GEN AGC VREF A VCC DELAY 1 2 3 4 5 6 7 8 GND VREF Tin Delay Adj CAGC1 DTC IN1 (+) IN1 (-) FB1 COLLECTOR1 OUT1 12 P. GND PIN WAVE PIN 3 TIN FB1 PIN 9 A POINT B POINT C POINT PIN 11 OUT1 TD D POINT ( 10 / 11 ) MITSUBISHI (Dig./Ana. INTERFACE) M62500P/FP SYNCHRONIZATION DEFLECTION SYSTEM CONTROL PWM IC PIN WAVE (Cont.) D POINT E POINT PIN 20 F POINT Low FB2 PIN 15 PIN 13 OUT2 PIN 23 D.OUT T1 T2 TL TH E POINT F POINT PIN 20 PIN 13 High OUT2 PIN 23 D.OUT PWM OUT NON-CONTROL STATUS With trigger input at pin 3 3.5V 1.5V FB>3.5V, FB>DTC High OUT1, 2 FB<1.5V, FB>DTC Without trigger at pin 3 (in case of GND) OUT1, 2 Low (GND) ( 11 / 11 )