IRF IRF1324S-7PPBF Hexfet power mosfet Datasheet

PD - 97263
IRF1324S-7PPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
S
VDSS
RDS(on) typ.
max.
ID
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
24V
0.8m:
1.0m:
429A
D
S
G
S
S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current d
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery f
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Max.
Units
429c
303c
1640
300
2.0
± 20
1.6
-55 to + 175
A
W
W/°C
V
V/ns
°C
300
10lbxin (1.1Nxm)
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy e
Avalanche Currentc
Repetitive Avalanche Energy g
230
See Fig. 14, 15, 22a, 22b,
mJ
A
mJ
Thermal Resistance
Symbol
RθJC
RθJA
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Parameter
Junction-to-Case k
2
Junction-to-Ambient (PCB Mount) , D Pak jk
Typ.
Max.
Units
–––
–––
0.50
40
°C/W
1
10/10/06
IRF1324S-7PPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
RG
Min. Typ. Max. Units
24
–––
–––
2.0
–––
–––
–––
–––
–––
––– –––
0.023 –––
0.80 1.0
–––
4.0
–––
20
––– 250
––– 200
––– -200
3.0
–––
Conditions
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 5mAd
mΩ VGS = 10V, ID = 160A g
V VDS = VGS, ID = 250µA
µA VDS = 24V, VGS = 0V
VDS = 19V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
270
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Effective Output Capacitance (Energy Related) –––
Effective Output Capacitance (Time Related)h –––
–––
180
47
58
122
19
240
86
93
7700
3380
1930
4780
4970
–––
252
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
ns
pF
Conditions
VDS = 50V, ID = 160A
ID = 75A
VDS =12V
VGS = 10V g
ID = 75A, VDS =0V, VGS = 10V g
VDD = 16V
ID = 160A
RG =2.7Ω
VGS = 10V g
VGS = 0V
VDS = 19V
ƒ = 1.0MHz, See Fig.5
VGS = 0V, VDS = 0V to 19V i, See Fig.11
VGS = 0V, VDS = 0V to 19V h
Diode Characteristics
Symbol
IS
Parameter
Min. Typ. Max. Units
Continuous Source Current
VSD
trr
(Body Diode)
Pulsed Source Current
(Body Diode)d
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
––– 429c
A
MOSFET symbol
–––
–––
A
showing the
integral reverse
1636
D
G
p-n junction diode.
––– –––
1.3
V TJ = 25°C, IS = 160A, VGS = 0V g
VR = 20V,
–––
71
107
ns TJ = 25°C
T
=
125°C
I
–––
74
110
J
F = 160A
di/dt
= 100A/µs g
–––
83
120
nC TJ = 25°C
TJ = 125°C
–––
92
140
–––
2.0
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 160A.
‚ Repetitive rating; pulse width limited by max. junction
temperature.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.018mH
RG = 25Ω, IAS = 160A, VGS =10V. Part not recommended for use
above this value.
„ ISD ≤ 160A, di/dt ≤ 600A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
Conditions
–––
S
† Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
‰ Rθ is measured at TJ approximately 90°C
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IRF1324S-7PPbF
1000
1000
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
BOTTOM
100
100
4.5V
10
0.1
≤60µs PULSE WIDTH
Tj = 175°C
≤60µs PULSE WIDTH
Tj = 25°C
1
10
4.5V
10
0.1
100
Fig 1. Typical Output Characteristics
10
100
Fig 2. Typical Output Characteristics
1000
1.8
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
T J = 175°C
10
T J = 25°C
1
VDS = 15V
≤60µs PULSE WIDTH
0.1
ID = 160A
VGS = 10V
1.6
1.4
1.2
1.0
0.8
0.6
2
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
12.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 75A
C oss = C ds + C gd
C, Capacitance (pF)
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
Ciss
Coss
10000
Crss
1000
10.0
VDS= 19V
VDS= 12V
8.0
6.0
4.0
2.0
0.0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
50
100
150
200
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRF1324S-7PPbF
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 175°C
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100
1msec
100
T J = 25°C
10
10msec
10
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
1.0
0.5
1.0
1.5
2.0
2.5
0
VSD, Source-to-Drain Voltage (V)
300
250
200
150
100
50
0
50
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Limited By Package
350
25
100
32
Id = 5mA
31
30
29
28
27
26
25
24
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs.
Case Temperature
1.4
EAS , Single Pulse Avalanche Energy (mJ)
1000
1.2
1.0
Energy (µJ)
10
Fig 8. Maximum Safe Operating Area
450
400
1
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
0.8
0.6
0.4
0.2
0.0
ID
TOP
45A
80A
BOTTOM 160A
900
800
700
600
500
400
300
200
100
0
-5
0
5
10
15
20
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
DC
1
0.0
ID, Drain Current (A)
100µsec
25
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRF1324S-7PPbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
0.05
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
τ2
τ1
R3
R3
τC
τ
τ2
τ3
τ3
τ4
τ4
Ci= τi/Ri
Ci i/Ri
1E-005
0.02070
0.000010
0.08624
0.000070
0.24491
0.001406
0.15005
0.009080
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
τi (sec)
Ri (°C/W)
R4
R4
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆ Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
100
0.05
0.10
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
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5
IRF1324S-7PPbF
EAR , Avalanche Energy (mJ)
250
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 160A
200
150
100
50
0
25
50
75
100
125
150
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
175
Starting T J , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
VGS(th) , Gate threshold Voltage (V)
4.5
4.0
3.5
3.0
2.5
ID = 250µA
ID = 1.0mA
ID = 1.0A
2.0
1.5
1.0
-75 -50 -25 0
25 50 75 100 125 150 175 200
T J , Temperature ( °C )
Fig 16. Threshold Voltage Vs. Temperature
6
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IRF1324S-7PPbF
Driver Gate Drive
D.U.T
ƒ
-
‚
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
tp
15V
DRIVER
L
VDS
D.U.T
RG
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD
Fig 22b. Unclamped Inductive Waveforms
VGS
VDS
90%
+
VDD D.U.T
10%
VGS
VDS
Second Pulse Width < 1µs
Duty Factor < 0.1%
td(off)
Fig 23a. Switching Time Test Circuit
tf
td(on)
tr
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
1K
20K
VCC
Vgs(th)
S
Qgodr
Fig 24a. Gate Charge Test Circuit
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Qgd
Qgs2 Qgs1
Fig 24b. Gate Charge Waveform
7
IRF1324S-7PPbF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
8
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IRF1324S-7PPbF
D2Pak - 7 Pin Part Marking Information
14
D2Pak - 7 Pin Tape and Reel
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/06
9