IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 16 x 16 parallel multiplier-accumulator with selectable accumulation and subtraction • High-speed: 20ns multiply-accumulate time • IDT7210 features selectable accumulation, subtraction, rounding and preloading with 35-bit result • IDT7210 is pin and function compatible with the TRW TDC1010J, TMC2210, Cypress CY7C510, and AMD AM29510 • Performs subtraction and double precision addition and multiplication • Produced using advanced CMOS high-performance technology • TTL-compatible • Available in topbraze DIP, PLCC, Flatpack and Pin Grid Array • Military product compliant to MIL-STD-883, Class B • Standard Military Drawing #5962-88733 is listed on this function • Speeds available: Commercial: L20/25/35/45/55/65 Military: L25/30/40/55/65/75 The IDT7210 is a high-speed, low-power 16 x 16-bit parallel multiplier-accumulator that is ideally suited for real-time digital signal processing applications. Fabricated using CMOS silicon gate technology, this device offers a very low-power alternative to existing bipolar and NMOS counterparts, with only 1/7 to 1/10 the power dissipation and exceptional speed (25ns maximum) performance. A pin and functional replacement for TRW’s TDC1010J the IDT7210 operates from a single 5 volt supply and is compatible with standard TTL logic levels. The architecture of the IDT7210 is fairly straightforward, featuring individual input and output registers with clocked D-type flip-flop, a preload capability which enables input data to be preloaded into the output registers, individual three-state output ports for the Extended Product (XTP) and Most Significant Product (MSP) and a Least Significant Product output (LSP) which is multiplexed with the Y input. The XIN and YIN data input registers may be specified through the use of the Two’s Complement input (TC) as either a two’s complement or an unsigned magnitude, yielding a fullprecision 32-bit result that may be accumulated to a full 35-bit result. The three output registers – Extended Product (XTP), Most Most Significant Product (MSP) and Least Significant Product (LSP) – are controlled by the respective TSX, TSM and TSL input lines. The LSP output can be routed through YIN ports. FUNCTIONAL BLOCK DIAGRAM ACC, SUB, RND, TC XIN (X15-X0) CLKX 16 CLKY YIN (Y15-Y0/P15-P0) 4 16 CONTROL REGISTER XREGISTER YREGISTER MULTIPLIER ARRAY 32 +/– + TSL ACCUMULATOR PREL 35 35 XTP REGISTER CLKP MSP REGISTER LSP REGISTER 16 3 TSM TSX 3 XTPOUT (P34-P32) PREL 16 MSPOUT (P31-P16) IDT7210 MILITARY AND COMMERCIAL TEMPERATURE RANGES 1995 Integrated Device Technology, Inc. 11.2 2577 drw 01 AUGUST 1995 DSC-2018/7 1 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES DESCRIPTION (Continued) The Accumulate input (ACC) enables the device to perform either a multiply or a multiply-accumulate function. In the multiply-accumulate mode, output data can be added to or subtracted from previous results. When the Subtraction (SUB) input is active simultaneously with an active ACC, a subtraction can be performed. The double precision accumulated result is rounded down to either a single precision or single precision plus 3-bit extended result. In the multiply mode, the Extended Product output (XTP) is sign extended in the two’s complement mode or set to zero in the unsigned mode. The Round (RND) control rounds up the Most Significant Product (MSP) and the 3-bit Extended Product (XTP) outputs. When Preload input (PREL) is active, all the output buffers are forced into a highimpedance state (see Preload truth table) and external data can be loaded into the output register by using the TSX, TSL and TSM signals as input controls. X7 X8 X9 X10 X11 X12 X13 X14 X15 TSL RND SUB ACC CLKX CLKY VCC TC TSX PREL TSM CLKP P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 60 59 58 5756 55 54 53 5251 50 4948 47 46 45 44 P1, Y1 61 P0, Y0 62 X0 63 X1 64 X2 65 X3 66 X4 67 X5 68 X6 1 X7 2 X8 3 X9 4 X10 5 X11 6 X12 7 X13 8 X14 9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 J68-1, L68-1 J68-1 10 11 1213 14 1516 17 18 19 20 21 22 23 24 25 26 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 2577 drw 03 X15 TSL RND SUB ACC CLKX CLKY VCC VCC VCC VCC TC TSX PREL TSM CLKP P34 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 C64-2 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PLCC TOP VIEW P1, Y1 P2, Y2 P3, Y3 P4, Y4 P5, Y5 P6, Y6 P7, Y7 GND P8, Y8 P9, Y9 P10, Y10 P11, Y11 P12, Y12 P13, Y13 P14, Y14 P15, Y15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2577 drw 02 DIP TOP VIEW 64636261 605958575655 545352 515049 P0, Y0 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 F64-1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 17181920 212223242526 272829 303132 2577 drw 04 X15 TSL RND SUB ACC CLKX CLKY VCC TC TSX PREL TSM CLKP P34 P33 P32 X6 X5 X4 X3 X2 X1 X0 P 0, P 1, P 2, P 3, P 4, P 5, P 6, P 7, GND P 8, P 9, P10, P11, P12, P13, P14, P15, P16 P17 P18 P19 P20 P21 P22 P23 P2, Y2 P3, Y3 P4, Y4 P5, Y5 P6, Y6 P7, Y7 GND GND P8, Y8 P9, Y9 P10, Y10 P11, Y11 P12, Y12 P13, Y13 P14, Y14 P15, Y15 P16 PIN CONFIGURATIONS FLATPACK TOP VIEW 11.2 2 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR 11 MILITARY AND COMMERCIAL TEMPERATURE RANGES NC X15 RND ACC CLKY TSL SUB CLKX VCC 10 X13 X14 09 X11 08 TC PREL CLKP P33 P32 NC X12 P30 P31 X9 X10 P28 P29 07 X7 X8 P26 P27 06 X5 X6 P24 P25 05 X3 X4 P22 P23 04 X1 X2 P20 P21 03 Y0, P0 X0 P18 P19 02 NC Y1, P1 Y3, P3 Y5, P5 Y7, P7 Y8, P8 Y10, P10 Y12, P12 Y14, P14 P16 P17 Y2, P2 Y4, P4 Y6, P6 GND Y9, P9 Y11, P11 Y13, P13 Y15, P15 NC B C D E F G H J K 01 Pin 1 Designator A TSX TSM P34 G68-2 PGA TOP VIEW L 2577 drw 05 PIN DESCRIPTIONS Pin Name X0 - 15 I/O I Y0 - 15/ P0 - 15 I/O P16 - 31 I/O P32 - 34 I/O Description Data Inputs Multiplexed I/O port. Y0 - 15 are data inputs and can be used to preload LSP register on PREL = 1. P0 - 15 are LSP register outputs - enabled by TSL. MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1. CLKX I XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when PREL = 1. Input data X0 - 15 loaded in X input register on CLKX rising edge. CLKY I Input data Y0 - 15 loaded in Y input register on CLKY rising edge. CLKP I Output data loaded into output register on rising edge of CLKP. TSX I TSX = 0 enables XTP outputs, TSX = 1 tristates P32 - 34 lines. TSM I TSM = 0 enables MSP outputs, TSM = 1 tristates P16 - 31 lines. TSL I TSL = 0 enables LSP outputs, TSL = 1 tristates P0 - 15 lines. PREL I When PREL= 1 data is input on P0 - 15 lines. When PREL = 0, inputs on these lines are ignored. ACC I SUB I TC I RND I This input is loaded into the control register on the rising edge of (CLKX + CLKY). When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a simple multipler with no accumulation This input is loaded into the control register on the rising edge of (CLKX + CLKY). This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted from the result and stored back in the output register. When SUB = 0 the contents of the output register are added to the result and stored back in the output register This input is loaded into the control register on the rising edge of (CLKX + CLKY). When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y inputs are assumed to be in unsigned magnitude form This input is loaded into the control register on the rising edge of (CLKX + CLKY). RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and XTP data 2577 tbl 01 11.2 3 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES NOTES ON TWO'S COMPLEMENT FORMATS PRELOAD TRUTH TABLE PREL TSX TSM TSL XTP MSP LSP 0 0 0 0 Q Q Q 0 0 0 1 Q Q Hi Z 0 0 1 0 Q Hi Z Q 0 0 1 1 Q Hi Z Hi Z 0 1 0 0 Hi Z Q Q 0 1 0 1 Hi Z Q Hi Z 0 1 1 0 Hi Z Hi Z Q 0 1 1 1 Hi Z Hi Z Hi Z 1 0 0 0 Hi Z Hi Z Hi Z 1 0 0 1 Hi Z Hi Z PL 1 0 1 0 Hi Z PL Hi Z 1 0 1 1 Hi Z PL PL 1 1 0 0 PL Hi Z Hi Z 1 1 0 1 PL Hi Z PL 1 1 1 0 PL PL Hi Z 1 1 1 1 PL PL PL 1. In two's complement notation, the location of the binary point that signifies the separation of the fractional and integer fileds is just after the sign, between the sign bit (-2°) and the next significant bit for the multiplier inputs. This same format is carried over to the output format, except that the extended significance of the integer filed is provided to extend the utility of the accumulator. In the case of the output rotation, the output binary point is located between the2° and 21 bit positions. The location of the binary point is arbitrary, as long as there is consistency with both the input and output formats. The number filed can be considered entirely integer with the binary point just to the right of the least significant bit for the input, product and the accumulated sum. 2. When in the non-accumulating mode, the first four bits (P34 to P31) will all indicate the sign of the product. Additionally, the P30 term will also indicate the sign with one exception, when multiplying -1 x -1. With the additional bits that are available in this multiplier, the –1 x –1 is a valid operation that yields a +1 product. 3. In operations that require the accumulation of single products or sum of products, there is no change in format. To allow for a valid summation beyond that available for a single multiplication product, three additional significant bits (guard bits) are provided. This is the same as if the product was accumulated off-chip in a separate 35-bit wide adder. Taking the sign at the most significant bit position will guarantee that the largest number field will be used. When the accumulated sum only occupies the right hand portion of the accumulator, the sign will be extended into the lesser significant bit positions. NOTES: 2577 tbl 02 Hi Z = Output buffers at high impedance (output disabled) Q = Output buffers at low impedance. Contents of output register will be transferred to output pins. PL = Output buffers at high impedance or output disabled. Preload data supplied externally at output pins will be loaded into the output register at the rising edge of CLKP. ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating VCC Power Supply Voltage VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature IOUT DC Output Current CAPACITANCE (TA = +25°C, f = 1.0MHz) Commercial -0.5 to +7.0 Military -0.5 to +7.0 Unit V –0.5 to VCC +0.5V –0.5 to VCC +0.5V V 0 to +70 –55 to +125 °C –55 to +125 –65 to +135 °C –55 to +125 –65 to +150 °C 50 50 mA Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V Max. 10 Unit pF VOUT = 0V 12 pF NOTE: 2577 tbl 04 1. This parameter is measured at characterization and not 100%tested. NOTE: 2577 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 11.2 4 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) Commercial Typ.(1) — Max. — Unit — Min. 2.0 — 0.8 — — 0.8 V — — 10 — — 10 µA — — 10 — — 10 µA 2.4 — — 2.4 — — V VCC = Min., IOL = 4mA — — 0.4 — — 0.4 V VCC = Max., V0 GND -20 — -100 -20 — -100 mA VCC = Max., Outputs Enabled f= 10MHz(2) CL = 50 pF VIN ≥ VIH, VIN ≤ VIL — 45 90 — 45 110 mA — 20 30 — 20 30 mA — 4 10 — 4 12 mA — — 6 — — 8 mA/ MHz Symbol Parameter VIH Input High Voltage Test Guaranteed Logic HIGH Level Min. 2.0 Typ.(1) VIL Input Low Voltage Guaranteed Logic LOW Level — |ILI| Input Leakage Current VCC = Max., VIN = 0V to VCC |ILO| Output Leakage Current VOH Output HIGH Voltage VCC = Max., Outputs Disabled VOUT = 0 to VCC VCC = Min., IOH = –2.0mA VOL(4) Output LOW Voltage IOS Output Short Circuit Current ICC (2) Operating Power Supply Current ICCQ1 Quiescent Power Supply Current ICCQ2 Quiescent Power Supply Current ICC/f (2,3) Increase in Power Supply Current MHz Military Max. — Conditions(5) VIN ≥ VCC –0.2V, V IN ≤ 0.2V VCC = Max., Outputs Disabled V 2577 tbl 05 NOTES: 1. Typical implies VCC = 5V and TA = +25°C. 2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range: ICC = 90+ 6(f –10)mA, where f = operating frequency in MHz. For the military range, ICC = 110 + 8(f –10). f = operating frequency in MHz, f = 1/tMA. 3. For frequencies greater than 10MHz, guaranteed by design, not production tested. 4. IOL = 4mA for tMA > 55ns. 5. For conditions shown as Max. or Min., use appropriate value specified under electrical characteristics. AC ELECTRICAL CHARACTERISTICS COMMERCIAL (VCC = 5V ± 10%, TA = 0° to +70°C) Symbol t MA tD t ENA t DIS tS tH t PW t HCL Parameter Multiply-Accumulate Time(2) Output Delay (2) 3-State Enable Time 3-State Disable Time(1) Input Register Set-up Time Input Register Hold Time Clock Pulse Width Relative Hold Time 7210L20 Min. Max. 2.0 20 2.0 18 — 18 — 18 10 — 3 — 9 — 0 — 7210L25 Min. Max. 2.0 25 2.0 20 – 20 – 20 12 – 3 – 10 – 0 – 7210L35 Min. Max. 2.0 35 2.0 25 – 25 – 25 12 – 3 – 10 – 0 – 7210L45 Min. Max. 2.0 45 2.0 25 – 25 – 25 15 – 3 – 15 – 0 – 7210L55 Min. Max. 2.0 55 2.0 30 – 30 – 30 20 – 3 – 20 – 0 – NOTES: 1. Transition is measured ±500mV from steady state voltage. 2. Minimum delays guaranteed but not tested 7210L65 Min. Max. Unit 2.0 65 ns 2.0 35 ns – 30 ns – 30 ns 25 – ns 3 – ns 25 – ns 0 – ns 2577 tbl 06 AC ELECTRICAL CHARACTERISTICS MILITARY (VCC = 5V ± 10%, TA = –55° to +125°C) Symbol t MA tD t ENA t DIS tS tH t PW t HCL Parameter Multiply-Accumulate Time(2) Output Delay (2) 3-State Enable Time 3-State Disable Time(1) Input Register Set-up Time Input Register Hold Time Clock Pulse Width Relative Hold Time 7210L25 Min. Max. 2.0 25 2.0 20 — 20 — 20 12 — 3 — 10 — 0 — 7210L30 Min. Max. 2.0 30 2.0 20 – 20 – 20 12 – 3 – 10 – 0 – NOTES: 1. Transition is measured ±500mV from steady state voltage. 2. Minimum delays guaranteed but not tested 7210L40 Min. Max. 2.0 40 2.0 25 – 25 – 25 15 – 3 – 15 – 0 – 7210L55 Min. Max. 2.0 55 2.0 30 – 30 – 25 20 – 3 – 20 – 0 – 7210L65 Min. Max. 2.0 65 2.0 35 – 30 – 30 25 – 3 – 25 – 0 – 7210L75 Min. Max. Unit 2.0 75 ns 2.0 35 ns – 35 ns – 30 ns 25 – ns 3 – ns 25 – ns 0 – ns 2577 tbl 07 11.2 5 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES CONTROL AND DATAIN INPUT tS INPUT CLOCK tH tPW tHCL tMA OUTPUT CLOCK tPW PRELOAD THREE-STATE CONTROL tDIS OUTPUT tENA tDIS DATAOUT HIGH IMPEDANCE tS tH PRELOAD IN DATA tENA DATAOUT tD Figure 1. Timing Diagram 11.2 6 = = –20 2 –1 2–2 2 –3 2–4 2 –5 2–6 2 –7 Y8 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y 9 2–8 Y7 2–8 X7 2 –9 Y6 2 –9 X6 X4 X3 X2 X1 X0 Y4 Y3 Y2 Y1 Y0 2–10 2 –11 2–12 2 –13 2–14 2 –15 Y5 2–10 2 –11 2–12 2 –13 2–14 2 –15 X5 DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL 22 21 20 11.2 2 –2 2 –3 2 –4 2 –5 –1 2 2 –2 2 –3 2 –4 2 –4 2 2 –5 –5 2 –6 2 –6 –7 2 2 –8 Y8 –3 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y 9 2 –8 2 –2 –7 2 –1 X8 –6 2 2 –9 Y7 –9 X7 2 2 –8 2 –9 X5 X4 X3 X2 X1 X0 Y5 Y4 Y3 Y2 Y1 Y0 2 –10 2–11 2 –12 2–13 2 –14 2–15 2 –16 Y6 2 –10 2–11 2 –12 2–13 2 –14 2–15 2 –16 X6 22 XTP 1 2 20 –1 2 2 –2 2 –3 2 –4 2 –5 2 –6 –7 2 2 –8 –9 DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL P7 P6 P5 P4 P3 P2 P1 P0 SIGNAL P8 P7 LSP P6 P5 P4 P3 P2 P1 P0 SIGNAL 2577 drw 10 LSP 2577 drw 11 DIGIT 2 –10 2–11 2 –12 2–13 2 –14 2–15 2 –16 2–17 2 –18 2–19 2 –20 2–21 2 –22 2–23 2 –24 2–25 2 –26 2–27 2 –28 2–29 2 –30 2–31 2 –32 VALUE Figure 3. Fractional Unsigned Mgnitude Notation MSP 2 P8 DIGIT 2–10 2 –11 2–12 2 –13 2–14 2 –15 2–16 2 –17 2–18 2 –19 2–20 2 –21 2–22 2 –23 2–24 2 –25 2–26 2 –27 2–28 2 –29 2–30 VALUE Figure 2. Fractional Two’s Complement Notation. MSP 2 –7 P 34 P 33 P 32 P 31 P 30 P 29 P 28 P 27 P 26 P 25 P 24 P 23 P 22 P 21 P 20 P 19 P 18 P 17 P 16 P 15 P 14 P 13 P 12 P 11 P 10 P 9 X 2 –1 X 15 X 14 X 13 X 12 X 11 X 10 X 9 BINARY POINT XTP –24 2 3 P 34 P 33 P 32 P 31 P 30 P 29 P 28 P 27 P 26 P 25 P 24 P 23 P 22 P 21 P 20 P 19 P 18 P 17 P 16 P 15 P 14 P 13 P 12 P 11 P 10 P 9 X 2 –5 2 –7 2–4 2–6 2 –3 –20 2 –1 2–2 X8 X 15 X 14 X 13 X 12 X 11 X 10 X 9 BINARY POINT IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES 7 = = 211 210 11.2 2 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 MSP 23 2 2 21 2 20 2 19 2 18 2 17 2 16 2 15 2 14 2 13 X 215 214 213 212 211 211 210 210 Y8 212 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y 9 213 28 214 XTP 234 233 2 32 231 30 2 229 2 28 227 2 26 2 25 24 2 MSP 2 23 2 21 20 2 2 19 18 2 2 17 2 16 215 2 14 213 2 12 Figure 5. Integer Unsigned Magnitude Notation 22 2 211 2 10 29 2 8 8 2 29 2 9 215 2 10 X8 2 11 X 15 X 14 X 13 X 12 X 11 X 10 X 9 12 2 Figure 4. Integer Two's Complement Notation 22 P8 2 31 P 34 P 33 P 32 P 31 P 30 P 29 P 28 P 27 P 26 P 25 P 24 P 23 P 22 P 21 P 20 P 19 P 18 P 17 P 16 P 15 P 14 P 13 P 12 P 11 P 10 P 9 2 32 28 XTP 33 29 –2 34 P8 212 P 34 P33 P 32 P31 P 30 P29 P 28 P 27 P 26 P 25 P 24 P23 P 22 P21 P 20 P19 P 18 P 17 P 16 P 15 P 14 P13 P 12 P11 P 10 P 9 213 28 –215 214 Y8 Y 15 Y 14 Y13 Y 12 Y11 Y 10 Y 9 29 X 210 28 211 29 212 –215 214 213 X8 X 15 X 14 X13 X 12 X11 X 10 X 9 2 LSP 27 P7 27 Y7 27 X7 LSP 7 P7 27 Y7 27 X7 2 6 P6 26 Y6 26 X6 2 6 P6 26 Y6 26 X6 25 P5 25 Y5 25 X5 2 5 P5 25 Y5 25 X5 2 4 P4 24 Y4 24 X4 2 4 P4 24 Y4 24 X4 23 P3 23 Y3 23 X3 2 3 P3 23 Y3 23 X3 2 2 P2 22 Y2 22 X2 2 2 P2 22 Y2 22 X2 2 0 P0 20 Y0 20 X0 DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL 21 2 0 P0 20 Y0 20 X0 DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL 2577 drw 13 P1 21 Y1 21 X1 BINARY POINT 2577 drw 12 2 1 P1 21 Y1 21 X1 BINARY POINT IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES 8 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS V CC SWITCH POSITION 500Ω V OUT VIN Pulse Generator Test Switch Open Drain Disable Low Closed 7.0V Enable Low Open All Other Tests D.U.T. 50pF RT 2577 lnk 09 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 2577 drw 06 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 2577 drw 08 2577 drw 07 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V CONTROL INPUT 1.5V tPZL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED 2577 drw 09 SWITCH OPEN 3.5V 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 0V tPLZ 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V 2577 drw 10 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 11.2 9 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXX Device Type A Power 999 Speed A Package X Process/ Temperature Range Blank B Commercial (0°C to +70°C) Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B C J F G Topbraze DIP Plastic Leaded Chip Carrier Flatpack Pin Grid Array Com'l. 20 25 35 45 55 65 Mil. 25 30 40 55 65 75 Speed in Nanoseconds L Low Power 7210 16 x 16 Parallel Multiplier Accumulator 2577 drw 11 11.2 10