PD - 94758
IRF540Z
IRF540ZS
IRF540ZL
AUTOMOTIVE MOSFET
Features
●
●
●
●
●
HEXFET® Power MOSFET
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
D
VDSS = 100V
RDS(on) = 26.5mΩ
G
Description
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low onresistance per silicon area. Additional features of
this design are a 175°C junction operating temperature, fast switching speed and improved repetitive
avalanche rating . These features combine to make
this design an extremely efficient and reliable device
for use in Automotive applications and a wide variety
of other applications.
ID = 36A
S
D2Pak
IRF540ZS
TO-220AB
IRF540Z
TO-262
IRF540ZL
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
IDM
140
PD @TC = 25°C Power Dissipation
92
W
0.61
± 20
W/°C
V
83
mJ
36
Linear Derating Factor
VGS
Gate-to-Source Voltage
EAS (Thermally limited) Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
EAS (Tested )
d
c
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
120
A
mJ
-55 to + 175
°C
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
Thermal Resistance
i
Parameter
RθJC
Junction-to-Case
RθCS
Case-to-Sink, Flat Greased Surface
RθJA
Junction-to-Ambient
RθJA
Junction-to-Ambient (PCB Mount)
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h
See Fig.12a, 12b, 15, 16
g
i
A
25
c
j
i
300 (1.6mm from case )
y
y
10 lbf in (1.1N m)
Typ.
Max.
Units
–––
1.64
°C/W
0.50
–––
–––
62
–––
40
1
10/31/03
IRF540Z/S/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
100
–––
∆V(BR)DSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.093
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
21
26.5
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
gfs
IDSS
Forward Transconductance
36
–––
Drain-to-Source Leakage Current
–––
–––
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
200
Gate-to-Source Reverse Leakage
–––
–––
-200
Qg
Total Gate Charge
–––
42
63
Qgs
Gate-to-Source Charge
–––
9.7
–––
Qgd
Gate-to-Drain ("Miller") Charge
–––
15
–––
VGS = 10V
td(on)
Turn-On Delay Time
–––
15
–––
VDD = 50V
tr
Rise Time
–––
51
–––
td(off)
Turn-Off Delay Time
–––
43
–––
tf
Fall Time
–––
39
–––
VGS = 10V
LD
Internal Drain Inductance
–––
4.5
–––
Between lead,
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
and center of die contact
VGS = 0V
IGSS
–––
V
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 22A
e
V
VDS = VGS, ID = 250µA
–––
V
VDS = 25V, ID = 22A
20
µA
VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
ID = 22A
nC
VDS = 80V
e
ID = 22A
ns
nH
RG = 12 Ω
e
D
G
S
Ciss
Input Capacitance
–––
1770
–––
Coss
Output Capacitance
–––
180
–––
Crss
Reverse Transfer Capacitance
–––
100
–––
Coss
Output Capacitance
–––
730
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
110
–––
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
170
–––
VGS = 0V, VDS = 0V to 80V
VDS = 25V
pF
ƒ = 1.0MHz
f
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
36
ISM
(Body Diode)
Pulsed Source Current
–––
–––
140
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
V
trr
Reverse Recovery Time
–––
33
50
ns
Qrr
Reverse Recovery Charge
–––
41
62
nC
ton
Forward Turn-On Time
2
c
Conditions
MOSFET symbol
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 22A, VGS = 0V
e
TJ = 25°C, IF = 22A, VDD = 50V
di/dt = 100A/µs
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRF540Z/S/L
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
10
4.5V
100
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
4.5V
10
60µs PULSE WIDTH
Tj = 175°C
60µs PULSE WIDTH
Tj = 25°C
1
1
0.1
1
10
100
0.1
0
VDS, Drain-to-Source Voltage (V)
10
100
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
80
Gfs, Forward Transconductance (S)
1000
ID, Drain-to-Source Current (Α)
1
100
T J = 175°C
10
T J = 25°C
VDS = 25V
60µs PULSE WIDTH
1
4.0
5.0
6.0
7.0
T J = 175°C
60
40
T J = 25°C
20
VDS = 10V
380µs PULSE WIDTH
0
0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
20
30
40
50
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
3
IRF540Z/S/L
3000
20
2500
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C, Capacitance (pF)
C oss = C ds + C gd
2000
Ciss
1500
1000
500
Coss
ID= 22A
VDS= 80V
VDS= 50V
VDS= 20V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
Crss
0
0
1
10
0
100
10
20
30
40
50
60
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000.0
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100.0
100
T J = 175°C
10.0
1.0
T J = 25°C
10
1
VGS = 0V
0.1
0.1
0.2
0.4
0.6
0.8
1.0
1.2
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1.4
100µsec
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
1
10msec
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF540Z/S/L
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID , Drain Current (A)
40
30
20
10
ID = 22A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
0
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
T J , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF540Z/S/L
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
VGS
20V
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
180
15V
ID
8.3A
14A
BOTTOM 20A
160
TOP
140
120
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGD
4.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
L
VGS(th) Gate threshold Voltage (V)
QGS
3.5
ID = 250µA
3.0
2.5
2.0
VCC
DUT
0
1K
1.5
-75
-50
-25
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRF540Z/S/L
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
0.01
10
0.05
0.10
1
0.1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
100
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 20A
EAR , Avalanche Energy (mJ)
90
80
70
60
50
40
30
20
10
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
www.irf.com
175
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRF540Z/S/L
D.U.T
Driver Gate Drive
+
+
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
D=
Period
P.W.
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
VDS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRF540Z/S/L
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045)
MIN
1
2
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
3
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
3X
1.40 (.055)
3X
1.15 (.045)
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
AS S EMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
INTERNATIONAL
RECTIFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
For GB Production
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
AS S EMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
INTERNATIONAL
RECT IFIER
LOGO
LOT CODE
www.irf.com
PART NUMBER
DAT E CODE
9
IRF540Z/S/L
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
F530S
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
AS S EMBLY
LOT CODE
For GB Production
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
LOT CODE
10
PART NUMBER
F530S
DAT E CODE
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IRF540Z/S/L
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
IGBT
1- GATE
2- COLLECTOR
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
INT ERNAT IONAL
RECTIFIER
LOGO
AS SEMBLY
LOT CODE
www.irf.com
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
11
IRF540Z/S/L
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Notes:
Repetitive rating; pulse width limited by
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
max. junction temperature. (See fig. 11).
avalanche performance.
Limited by TJmax, starting TJ = 25°C, L = 0.46mH This value determined from sample failure population. 100%
RG = 25Ω, IAS = 20A, VGS =10V. Part not
tested to this value in production.
recommended for use above this value.
This is only applied to TO-220AB pakcage.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
This is applied to D2Pak, when mounted on 1" square PCB (FR Coss eff. is a fixed capacitance that gives the
4 or G-10 Material). For recommended footprint and soldering
same charging time as Coss while VDS is rising
techniques refer to application note #AN-994.
from 0 to 80% VDSS .
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101]market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/03
12
www.irf.com
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/