TI1 DAC8228SRTQR Octal, 14-bit, low-power, high-voltage output, parallel input digital-to-analog converter Datasheet

DA
C8
228
DAC8228
DA
C8
228
www.ti.com
SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
Octal, 14-Bit, Low-Power, High-Voltage Output, Parallel Input
DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC8228
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
The DAC8228 is a low-power, octal, 14-bit
digital-to-analog converter (DAC). With a 5V
reference, the output can either be a bipolar ±15V
voltage when operating from a dual ±15.5V (or
higher) power supply, or a unipolar 0V to +30V
voltage when operating from a +30.5V power supply.
With a 5.5V reference, the output can be ±16.5V for a
dual ±17V (or higher) power supply, or a unipolar 0V
to +33V voltage when operating from a +33.5V (or
higher) power supply. This DAC provides low-power
operation, good linearity, and low glitch over the
specified temperature range of –40°C to +105°C. This
device is trimmed in manufacturing and has very low
zero and full-scale error. In addition, user calibration
can be performed to achieve ±1 LSB bipolar
zero/full-scale error for a bipolar supply, or ±1 LSB
zero-code/full-scale error for a unipolar supply over
the entire signal chain. The output range can be
offset by using the DAC Offset Register.
1
2
•
•
•
•
•
•
•
Bipolar Output: ±3V, up to ±16.5V
Unipolar Output: 0V to +33V
14-Bit Resolution
Low Power: 13.5mW/Ch
Relative Accuracy: 1LSB Max
Flexible User Calibration
Low Zero/Full-Scale Error
– Before User Calibration: ±2.5 LSB Max
– After User Calibration: ±1 LSB
Low Glitch: 4nV-s
Settling Time: 15μs
Channel Monitor Output
Programmable Gain: x4, x6
Programmable Offset
14-Bit Parallel Interface:
50MHz (Write Operation)
Packages: QFN-56 (8mm x 8mm),
TQFP-64 (10mm x 10mm)
The DAC8228 features a standard, high-speed, 14-bit
parallel interface that operates at up to 50MHz and is
1.8V, 3V, and 5V logic compatible, to communicate
with a DSP or microprocessor. The eight DACs and
the auxiliary registers are addressed with five address
lines. The device features double-buffered interface
logic. An asynchronous load input (LDAC) transfers
data from the DAC data register to the DAC latch.
The asynchronous CLR input sets the output of all
eight DACs to AGND. The VMON pin is a monitor
output that connects to the individual analog outputs,
the offset DAC, and the reference buffer outputs
through a multiplexer (mux).
APPLICATIONS
•
•
•
Automatic Test Equipment
PLC and Industrial Process Control
Communications
IOVDD
DGND
DVDD
AVDD
AVSS
REF-A
DAC8228
Analog Monitor
A4
R/W
CS
D0
Reference
Buffer A
To DAC-0, DAC-1,
DAC-2, DAC-3
(When Correction Engine Disabled)
Input Data
Register 0
Correction
Engine
Control Logic
User Calibration:
Zero Register 0
Gain Regsiter 0
VOUT-7
Ref Buffer A
Ref Buffer B
OFFSET-B
VMON
The DAC8228 is pin-to-pin compatible with the
DAC8728 (16-bit) and the DAC7728 (12-bit).
OFFSET-A
DAC-0
DAC-0
Data
VOUT-0
Latch-0
D13
RST
RSTSEL
LDAC
CLR
USB/BTC
BUSY
GPIO
OFFSET
DAC A
Command
Registers
Mux
A0
Parallel Bus Interface
VOUT-0
To DAC-0, DAC-1,
DAC-2, DAC-3
Internal Trimming
Zero/Gain; INL
LDAC
AGND-A
To DAC-4, DAC-5, DAC-6, DAC-7
OFFSET-B
(Same Function Blocks
for All Channels)
Reference
Buffer B
OFFSET
DAC B
Power-Up/
Power-Down
Control
VOUT-7
AGND-B
REF-B
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
DAC8228
SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
LINEARITY
(LSB)
±1
±1
DAC8228
(1)
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
±1
QFN-56
RTQ
–40°C to +105°C
DAC8228
±1
TQFP-64
PAG
–40°C to +105°C
DAC8228
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
DAC8228
UNIT
AVDD to AVSS
–0.3 to 38
V
AVDD to AGND
–0.3 to 38
V
AVSS to AGND, DGND
–19 to 0.3
V
DVDD to DGND
–0.3 to 6
V
IOVDD to DGND
–0.3 to DVDD + 0.3
V
AGND to DGND
–0.3 to 0.3
V
Digital input voltage to DGND
–0.3 to IOVDD + 0.3
V
VOUT-x, VMON to AVSS
–0.3 to AVDD + 0.3
V
–0.3 to DVDD
V
–0.3 to IOVDD + 0.3
V
Maximum current from VMON
3
mA
Operating temperature range
–40 to +105
°C
Storage temperature range
–65 to +150
°C
REF-A, REF-B to AGND
BUSY, GPIO to DGND
Maximum junction temperature (TJ max)
+150
°C
4
kV
TQFP
1000
V
QFN
500
Human body model (HBM)
ESD ratings
Charged device model (CDM)
Machine model (MM)
Junction-to-ambient, θJA
Thermal impedance
Junction-to-case, θJC
200
V
TQFP
55
°C/W
QFN
21.7
°C/W
TQFP
21
°C/W
QFN
20.4
°C/W
(TJ max – TA) / θJA
W
Power dissipation
(1)
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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DAC8228
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
ELECTRICAL CHARACTERISTICS: Dual-Supply
All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
DAC8228
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
±1
LSB
STATIC PERFORMANCE
Resolution
14
Bits
Linearity error
Measured by line passing through codes 0000h and 3FFFh
Differential linearity error
Measured by line passing through codes 0000h and 3FFFh
±1
LSB
TA = +25°C, before user calibration, gain = 6, code = 2000h
±2.5
LSB
TA = +25°C, before user calibration, gain = 4, code = 2000h
±4
LSB
±2
ppm FSR/°C
Bipolar zero error
TA = +25°C, after user calib., gain = 4 or 6, code = 2000h
Bipolar zero error TC
Zero-code error
Zero-code error TC
Gain error
Gain error TC
Full-scale error
Gain = 4 or 6, code = 2000h
±1
±0.5
TA = +25°C, gain = 6, code = 0000h
±2.5
TA = +25°C, gain = 4, code = 0000h
±4
LSB
±3
ppm FSR/°C
Gain = 4 or 6, code = 0000h
±0.5
±2.5
TA = +25°C, gain = 4
±4
LSB
±3
ppm FSR/°C
Gain = 4 or 6
±1
LSB
TA = +25°C, before user calibration, gain = 6, code = 3FFFh
±2.5
LSB
TA = +25°C, before user calibration, gain = 4, code = 3FFFh
±4
LSB
±3
ppm FSR/°C
±1
Full-scale error TC
Gain = 4 or 6, code = 3FFFh
±0.5
DC crosstalk (2)
Measured channel at code = 2000h, full-scale change on any
other channel
0.05
(2)
LSB
TA = +25°C, gain = 6
TA = +25°C, after user calib., gain = 4 or 6, code = 3FFFh
(1)
LSB
LSB
LSB
Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±3 LSB from the nominal number listed in Table 8. These pins are not intended to drive an external load, and must not be
connected during dual-supply operation.
The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc
change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With
high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk.
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DAC8228
SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
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ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
DAC8228
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
V
ANALOG OUTPUT (VOUT-0 to VOUT-7) (3)
Voltage output (4)
Output impedance
VREF = +5V
–15
+15
VREF = +1.5V
–4.5
+4.5
V
0.5
Ω
Code = 2000h
Short-circuit current (5)
Load current
Output voltage drift vs time
±10
±3
mA
TA = +25°C, device operating for 500 hours, full-scale output
3.4
ppm of FSR
TA = +25°C, device operating for 1000 hours, full-scale output
4.3
Capacitive load stability
Settling time
Slew rate
ppm of FSR
500
pF
To 0.03% of FSR, CL = 200pF, RL= 10kΩ, code from 0000h
to 3FFFh and 3FFFh to 0000h
10
μs
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 0000h to
3FFFh and 3FFFh to 0000h
15
μs
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 1F00h to
2100h and 2100h to 1F00h
6
μs
6
V/μs
(6)
Power-on delay (7)
mA
See Figure 37
From IOVDD ≥ +1.8V and DVDD ≥ +2.7V to CS low
Power-down recovery time
200
μs
50
μs
4
nV-s
5
mV
Digital-to-analog glitch (8)
Code from 1FFFh to 2000h and 2000h to 1FFFh
Glitch impulse peak amplitude
Code from 1FFFh to 2000h and 2000h to 1FFFh
Channel-to-channel isolation (9)
VREF = 4VPP, f = 1kHz
88
dB
DACs in the same group
10
nV-s
DAC-to-DAC crosstalk (10)
1
nV-s
Digital crosstalk (11)
1
nV-s
Digital feedthrough (12)
1
Output noise
DACs among different groups
200
nV/√Hz
TA = +25°C at 10kHz, gain = 4
130
nV/√Hz
20
μVPP
0.05
LSB
0.1Hz to 10Hz, gain = 6
Power-supply rejection (13)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
4
nV-s
TA = +25°C at 10kHz, gain = 6
AVDD = ±15.5V to ±16.5V
Specified by design.
The analog output range of VOUT-0 to VOUT-7 is equal to (6 × VREF – 5 × OUTPUT_OFFSET_DAC) for gain = 6. The maximum value of
the analog output must not be greater than (AVDD – 0.5V), and the minimum value must not be less than (AVSS + 0.5V). All
specifications are for a ±16.5V power supply and a ±15V output, unless otherwise noted.
When the output current is greater than the specification, the current is clamped at the specified maximum value.
Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 1FFFh and 2000h in straight binary format.
Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and
subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s.
Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input
register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s.
Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of
the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s.
The output must not be greater than (AVDD – 0.5V) and not less than (AVSS + 0.5V).
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DAC8228
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
DAC8228
PARAMETER
OFFSET DAC OUTPUT (14)
CONDITIONS
MIN
TYP
MAX
UNIT
(15)
Voltage output
VREF = +5V
Full-scale error
TA = +25°C
0
±1
LSB
Zero-code error
TA = +25°C
±0.5
LSB
Linearity error
5
±1.5
Differential linearity error
V
LSB
±1
LSB
ANALOG MONITOR PIN (VMON)
Output impedance (16)
TA = +25°C
Three-state leakage current
2000
Ω
100
nA
REFERENCE INPUT
Reference input voltage range (17)
1.0
5.5
V
Reference input dc impedance
10
MΩ
Reference input capacitance
10
pF
DIGITAL INPUT (14)
High-level input voltage, VIH
Low-level input voltage, VIL
Input current
IOVDD = +4.5V to +5.5V
3.8
0.3 + IOVDD
V
IOVDD = +2.7V to +3.3V
2.3
0.3 + IOVDD
V
IOVDD = +1.7V to +2.0V
1.5
0.3 + IOVDD
V
IOVDD = +4.5V to +5.5V
–0.3
0.8
V
IOVDD = +2.7V to +3.3V
–0.3
0.6
V
IOVDD = +1.7V to +2.0V
–0.3
0.3
V
±1
μA
±5
μA
CLR, LDAC, RST, A0 to A4, R/W, and CS
USB/BTC, RSTSEL, and D0 to D13
CLR, LDAC, RST, A0 to A4, R/W, and CS
Input capacitance
5
pF
USB/BTC, RSTSEL, and D0 to D13
12
pF
GPIO
14
pF
DIGITAL OUTPUT (14)
High-level output voltage, VOH
(D0 to D13)
IOVDD = +2.7V to +5.5V, sourcing 1mA
IOVDD – 0.4
IOVDD
V
1.6
IOVDD
V
Low-level output voltage, VOL (D0
to D13, BUSY, and GPIO)
IOVDD = +2.7V to +5.5V, sinking 1mA
0
0.4
V
IOVDD = +1.8V, sinking 200μA
0
0.2
V
High-impedance leakage current
D0 to D13, BUSY, and GPIO
±5
μA
High-impedance output
capacitance
BUSY and GPIO
14
pF
IOVDD = +1.8V, sourcing 200μA
(14) Specified by design.
(15) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±3 LSB from the nominal number listed in Table 8. These pins are not intended to drive an external load, and must not be
connected during dual-supply operation.
(16) 8000Ω when VMON is connected to Reference Buffer A or B.
(17) Reference input voltage ≤ DVDD.
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DAC8228
SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
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ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted.
DAC8228
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD
+4.5
+18
V
AVSS
–18
–4.5
V
DVDD
+2.7
+5.5
V
IOVDD
+1.7
DVDD
Normal operation, midscale code, output unloaded
AIDD
4
Power down, output unloaded
Normal operation, midscale code, output unloaded
AISS
–4
IOIDD
Power dissipation
V
mA
35
μA
–2.5
mA
–35
μA
Normal operation
75
μA
Power down
35
μA
Normal operation, VIH = IOVDD, VIL = DGND
5
μA
Power down, VIH = IOVDD, VIL = DGND
5
Power down, output unloaded
DIDD
6
Normal operation, ±16.5V supplies, midscale code
107
μA
165
mW
+105
°C
TEMPERATURE RANGE
Specified performance
6
–40
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DAC8228
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
ELECTRICAL CHARACTERISTICS: Single-Supply
All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x =
DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8228
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
±1
LSB
STATIC PERFORMANCE
Resolution
14
Bits
Linearity error
Measured by line passing through codes 0040h and 3FFFh
Differential linearity error
Measured by line passing through codes 0040h and 3FFFh
±1
LSB
TA = +25°C, before user calibration, gain = 6, code = 0040h
±2.5
LSB
TA = +25°C, before user calibration, gain = 4, code = 0040h
±4
LSB
±3
ppm FSR/°C
Unipolar zero error
TA = +25°C, after user calib., gain = 4 or 6, code = 0040h
Unipolar zero error TC
Gain error
Gain error TC
Full-scale error
±1
Gain = 4 or 6, code = 0040h
±0.5
TA = +25°C, gain = 6
±2.5
TA = +25°C, gain = 4
±4
LSB
±3
ppm FSR/°C
Gain = 4 or 6
±1
±2.5
LSB
TA = +25°C, before user calibration, gain = 4, code = 3FFFh
±4
LSB
±3
ppm FSR/°C
±1
Full-scale error TC
Gain = 4 or 6, code = 3FFFh
±0.5
DC crosstalk (1)
Measured channel at code = 2000h, full-scale change on any
other channel
0.05
ANALOG OUTPUT (VOUT-0 to VOUT-7)
Output impedance
Output drift vs time
0
+30
VREF = +1.5V
0
+9
V
0.5
Ω
Code = 2000h
±10
V
mA
See Figure 89 and Figure 90
±3
mA
TA = +25°C, Device operating for 500 hours, full-scale output
3.4
ppm of FSR
TA = +25°C, Device operating for 1000 hours, full-scale output
4.3
ppm of FSR
500
pF
To 0.03% of FSR, CL = 200pF, RL= 10kΩ, code from 0040h to
3FFFh and 3FFFh to 0040h
10
μs
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 0040h to 3FFFh
and 3FFFh to 0040h
15
μs
To 1 LSB, CL = 200pF, RL = 10kΩ, code from 1F00h to 2100h
and 2100h to 1F00h
6
μs
6
V/μs
Slew rate (5)
Power-on delay (6)
LSB
VREF = +5V
Capacitive load stability
Settling time
LSB
(2)
Short-circuit current (4)
Load current
LSB
TA = +25°C, before user calibration, gain = 6, code = 3FFFh
TA = +25°C, after user calib., gain = 4 or 6, code = 3FFFh
Voltage output (3)
LSB
From IOVDD ≥ +1.8V and DVDD ≥ +2.7V to CS low
Power-down recovery time
μs
200
50
μs
Digital-to-analog glitch (7)
Code from 1FFFh to 2000h and 2000h to 1FFFh
4
nV-s
Glitch impulse peak amplitude
Code from 1FFFh to 2000h and 2000h to 1FFFh
5
mV
(1)
(2)
(3)
(4)
(5)
(6)
(7)
The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. DC crosstalk indicates how much dc
change in one or more channel outputs may occur when the dc load current changes in one channel (because of an update). With
high-impedance loads, the effect is virtually immeasurable. Multiple AVDD and AVSS terminals are provided to minimize dc crosstalk.
Specified by design.
The analog output range of VOUT-0 to VOUT-7 is equal to (6 × VREF) for gain = 6. The maximum value of the analog output must not be
greater than (AVDD – 0.5V). All specifications are for a +32V power supply and a 0V to +30V output, unless otherwise noted.
When the output current is greater than the specification, the current is clamped at the specified maximum value.
Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 1FFFh and 2000h in straight binary format.
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DAC8228
SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: Single-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x =
DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8228
PARAMETER
Channel-to-channel isolation (8)
DAC-to-DAC crosstalk (9)
CONDITIONS
MIN
TYP
MAX
UNIT
VREF = 4VPP, f = 1kHz
88
dB
DACs in the same group
10
nV-s
1
nV-s
Digital crosstalk (10)
1
nV-s
Digital feedthrough (11)
1
Output noise
DACs among different groups
200
nV/√Hz
TA = +25°C at 10kHz, gain = 4
130
nV/√Hz
20
μVPP
AVDD = +33V to +36V
0.05
LSB
TA = +25°C
2000
Ω
100
nA
0.1Hz to 10Hz, gain = 6
Power-supply rejection (12)
nV-s
TA = +25°C at 10kHz, gain = 6
ANALOG MONITOR PIN (VMON)
Output impedance (13)
Three-state leakage current
REFERENCE INPUT
Reference input voltage
range (14)
1.0
5.5
V
Reference input dc impedance
10
MΩ
Reference input capacitance
10
pF
DIGITAL INPUT (15)
High-level input voltage, VIH
Low-level input voltage, VIL
Input current
IOVDD = +4.5V to +5.5V
3.8
0.3 + IOVDD
V
IOVDD = +2.7V to +3.3V
2.3
0.3 + IOVDD
V
IOVDD = +1.7V to +2.0V
1.5
0.3 + IOVDD
V
IOVDD = +4.5V to +5.5V
–0.3
0.8
V
IOVDD = +2.7V to +3.3V
–0.3
0.6
V
IOVDD = +1.7V to +2.0V
–0.3
0.3
V
±1
μA
±5
μA
CLR, LDAC, RST, A0 to A4, R/W, and CS
USB/BTC, RSTSEL, and D0 to D13
CLR, LDAC, RST, A0 to A4, R/W, and CS
Input capacitance
5
pF
USB/BTC, RSTSEL, and D0 to D13
12
pF
GPIO
14
pF
DIGITAL OUTPUT (15)
High-level output voltage, VOH
(D0 to D13)
IOVDD = +2.7V to +5.5V, sourcing 1mA
IOVDD – 0.4
IOVDD
V
1.6
IOVDD
V
IOVDD = +2.7V to +5.5V, sinking 1mA
0
0.4
Low-level output voltage, VOL
(D0 to D13, BUSY, and GPIO)
V
IOVDD = +1.8V, sinking 200μA
0
0.2
V
High-impedance leakage current D0 to D13, BUSY, and GPIO
±5
μA
High-impedance output
capacitance
14
pF
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
8
IOVDD = +1.8V, sourcing 200μA
BUSY and GPIO
Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and
subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s.
Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input
register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s.
Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of
the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s.
The analog output must not be greater than (AVDD – 0.5V).
8000Ω when VMON is connected to Reference Buffer A or B.
Reference input voltage ≤ DVDD.
Specified by design.
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ELECTRICAL CHARACTERISTICS: Single-Supply (continued)
All specifications at TA = TMIN to TMAX, AVDD = +32V, AVSS = 0V, DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x =
DGND = 0V, and OFFSET-A = OFFSET-B = AGND, unless otherwise noted.
DAC8228
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD
+9
+36
V
DVDD
+2.7
+5.5
V
IOVDD
+1.7
DVDD
AIDD
DIDD
IOIDD
Power dissipation
4.5
Power down, output unloaded
35
µA
Normal operation
75
μA
Power down
35
μA
Normal operation, VIH = IOVDD, VIL = DGND
5
μA
Power down, VIH = IOVDD, VIL = DGND
5
Normal operation
7
V
Normal operation, midscale code, output unloaded
mA
μA
144
224
mW
+105
°C
TEMPERATURE RANGE
Specified performance
–40
FUNCTIONAL BLOCK DIAGRAM
IOVDD
DGND
DVDD
AVDD
AVSS
REF-A
DAC8228
Analog Monitor
A4
R/W
CS
D0
Reference
Buffer A
Command
Registers
To DAC-0, DAC-1,
DAC-2, DAC-3
(When Correction Engine Disabled)
Input Data
Register 0
Correction
Engine
Control Logic
VOUT-7
Ref Buffer A
Ref Buffer B
OFFSET-B
DAC-0
Data
VMON
OFFSET-A
DAC-0
VOUT-0
Latch-0
D13
RST
RSTSEL
LDAC
CLR
USB/BTC
BUSY
GPIO
OFFSET
DAC A
Mux
A0
Parallel Bus Interface
VOUT-0
To DAC-0, DAC-1,
DAC-2, DAC-3
Internal Trimming
Zero/Gain; INL
LDAC
User Calibration:
Zero Register 0
Gain Regsiter 0
AGND-A
To DAC-4, DAC-5, DAC-6, DAC-7
OFFSET-B
(Same Function Blocks
for All Channels)
Reference
Buffer B
OFFSET
DAC B
Power-Up/
Power-Down
Control
VOUT-7
AGND-B
REF-B
Figure 1. Functional Block Diagram
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PIN CONFIGURATIONS
DGND
D4
D3
D2
46
45
44
43
DVDD
IOVDD
48
47
CS
R/W
50
49
D6
D5
52
51
D8
D7
54
53
D10
D9
56
55
50 D2
49 D1
52 D4
51 D3
54 DGND
RTQ PACKAGE
QFN-56
(TOP VIEW)
53 NC
56 DVDD
55 IOVDD
58 CS
57 R/W
60 D6
59 D5
62 D8
61 D7
64 D10
63 D9
PAG PACKAGE
TQFP-64
(TOP VIEW)
D11
1
48 D0
D12
2
47 NC
D11
1
42
D1
D13
3
46 NC
D12
2
41
D0
VMON
4
45 NC
D13
3
40
NC
VOUT-3
5
44 VOUT-4
VMON
4
39
NC
REF-A
6
43 REF-B
VOUT-3
5
38
NC
VOUT-2
7
42 VOUT-5
REF-A
6
37
VOUT-4
AVDD
8
41 AVDD
VOUT-2
7
36
REF-B
AGND-A
9
AVDD
8
35
VOUT-5
AGND-A
9
34
AVDD
VOUT-1
10
33
AGND-B
AVSS
11
32
VOUT-6
OFFSET-A
12
31
AVSS
VOUT-0
13
30
OFFSET-B
USB/BTC
14
29
VOUT-7
DAC8228
40 AGND-B
39 VOUT-6
VOUT-1 10
38 AVSS
AVSS 11
DAC8228
37 OFFSET-B
OFFSET-A 12
36 VOUT-7
VOUT-0 13
(1)
25
26
27
28
A4
DGND
GPIO
RSTSEL
23
24
A2
A3
21
22
DVDD
DGND
19
20
A0
RST
A1
17
18
LDAC
BUSY
NC 31
NC 32
A4 29
DGND 30
A3 27
NC 28
A2 26
DGND 25
NC 23
DVDD 24
NC 22
A1 21
A0 20
RST 19
CLR 17
LDAC 18
15
33 GPIO
BUSY 16
16
34 RSTSEL
USB/BTC 15
CLR
35 NC
NC 14
The thermal pad is internally connected to
the substrate. This pad can be connected
to AVSS or left floating. Keep the thermal
pad separate from the digital ground, if
possible.
PIN DESCRIPTIONS
(1)
10
PIN NO.
PIN
NAME
QFN-56
TQFP-64
I/O
D11
1
1
I/O
Data bit 11
D12
2
2
I/O
Data bit 12
D13
3
3
I/O
Data bit 13
VMON
4
4
O
Analog monitor output. This pin is either in Hi-Z status, or connected to one of the DAC outputs,
reference buffer outputs, or offset DAC outputs, depending on the content of the Monitor Register.
VOUT-3
5
5
O
DAC-3 output
REF-A
6
6
I
Group A (1) reference input
VOUT-2
7
7
O
DAC-2 output
AVDD
8
8
I
Positive analog power supply
AGND-A
9
9
I
Group A (1) analog ground and the ground of REF-A. This pin must be tied to AGND-B and DGND.
VOUT-1
10
10
O
DAC-1 output
AVSS
11
11
I
Negative analog power supply. Connect to AGND in single-supply operation.
OFFSET-A
12
12
O
OFFSET DAC-A analog output. Must be connected to AGND-A during single power-supply operation
(AVSS = 0V). This pin is not intended to drive an external load.
VOUT-0
13
13
O
DAC-0 output
USB/BTC
14
15
I
Input data format selection. Input data are in straight binary format when connected to DGND or in
twos complement format when connected to IOVDD. Command data are always in straight binary
format.
BUSY
15
16
O
This pin is an open drain and requires an external pullup resistor. BUSY goes low when the correction
engine is running; see the Busy Pin section for details.
CLR
16
17
I
Level trigger. When the CLR pin is logic '0', all VOUT-X pins connect to AGND-x through switches and
an internal 15kΩ resistor. When the CLR pin is logic '1' and LDAC is logic '0', all VOUT-X pins connect
to the amplifier outputs.
DESCRIPTION
Group A consists of DAC-0, DAC-1, DAC-2, and DAC-3. Group B consists of DAC-4, DAC-5, DAC-6, and DAC-7.
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PIN DESCRIPTIONS (continued)
PIN
NAME
(2)
PIN NO.
QFN-56
TQFP-64
I/O
DESCRIPTION
LDAC
17
18
I
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the
contents of the DAC Data Register are transferred to it. The DAC output changes to the corresponding
level simultaneously when the DAC latch is updated. See the DAC Output Update section for details. If
asynchronous mode is desired, LDAC must be permanently tied low before power is applied to the
device. If synchronous mode is desired, LDAC must be logic high during power-on.
RST
18
19
I
Reset input (active low). Logic low on this pin resets the DAC registers and DACs to the values defined
by the RSTSEL pin. CS must be at logic high when RST is used.
A0
19
20
I
Address bit A0 to specify the internal registers.
A1
20
21
I
Address bit A1 to specify the internal registers.
DVDD
21
24
I
Digital power supply
DGND
22
25
I
Digital ground
A2
23
26
I
Address bit A2 to specify the internal registers.
A3
24
27
I
Address bit A3 to specify the internal registers.
A4
25
29
I
Address bit A4 to specify the internal registers.
DGND
26
30
I
Digital ground
GPIO
27
33
I/O
General-purpose digital input/output. This pin is a bidirectional, open-drain, digital input/output, and
requires an external pullup resistor. See the GPIO Pin section for details.
RSTSEL
28
34
I
Output reset selection. Selects the output voltage on the VOUT pin after power-on or hardware reset.
Refer to the Power-On Reset section for details.
VOUT-7
29
36
O
DAC-7 output
OFFSET-B
30
37
O
OFFSET DAC-B analog output. Must be connected to AGND-B during single-supply operation
(AVSS = 0V). This pin is not intended to drive an external load.
AVSS
31
38
I
Negative analog power supply. Connect to AGND in single-supply operation.
VOUT-6
32
39
O
DAC-6 output
AGND-B
33
40
I
Group B (2) analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.
AVDD
34
41
I
Positive analog power supply
VOUT-5
35
42
O
DAC-5 output
REF-B
36
43
I
Group B (2) reference input
VOUT-4
37
44
O
DAC-4 output
NC
38-40
14, 22, 23,
28, 31, 32,
35, 45-47, 53
—
Not connected
D0
41
48
I/O
Data bit 0
D1
42
49
I/O
Data bit 1
D2
43
50
I/O
Data bit 2
D3
44
51
I/O
Data bit 3
D4
45
52
I/O
Data bit 4
DGND
46
54
I
Digital ground
IOVDD
47
55
I
Digital interface power supply
DVDD
48
56
I
Digital power supply
R/W
49
57
I
Read and write signal. High for reading operation; low for writing operation.
CS
50
58
I
Chip select input (active low)
D5
51
59
I/O
Data bit 5
D6
52
60
I/O
Data bit 6
D7
53
61
I/O
Data bit 7
D8
54
62
I/O
Data bit 8
D9
55
63
I/O
Data bit 9
D10
56
64
I/O
Data bit 10
Group A consists of DAC-0, DAC-1, DAC-2, and DAC-3. Group B consists of DAC-4, DAC-5, DAC-6, and DAC-7.
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TIMING DIAGRAMS
t8
t1
CS
t9
CS
t10
t2
t3
R/W
R/W
t12
t11
t13
D13:D0
t5
t4
A4:A0
A4:A0
t14
Hi-Z
Hi-Z
Hi-Z
D13:D0
Hi-Z
t6
Figure 2. Read Operation
t7
Write Operation 1:
1. Writing to the Configuration Register, Offset Register,
Monitor Register, GPIO Register.
2. Writing to the DAC Input Registers, Zero Registers, and
Gain Registers in Asynchronous mode (LDAC pin is tied low).
Figure 3. Write Operation 1
space
t1
CS
t2
t3
R/W
t5
t4
A4:A0
D13:D0
Hi-Z
Hi-Z
t7
t6
t15
t16
LDAC
LD bit can be set to replace LDAC
to update the DAC output
Write Operation 2:
Writing to the DAC Input Data Registers, Zero Registers, and
Gain Registers when the correction engine is disabled and
DAC outputs are updated in Synchronous mode.
Figure 4. Write Operation 2
CS
BUSY
t18
t17
t16
LDAC
LD bit can be set to replace LDAC
to update the DAC output
Write Operation 3:
Writing to the DAC Input Data Registers, Zero Registers, and Gain Registers when the correction engine is
enabled (SCE = 1) and the DAC outputs are updated in Synchronous mode. The update trigger (either LDAC
or the LD bit) activates after the correction completes.
Figure 5. Write Operation 3
12
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
TIMING CHARACTERISTICS (1)
(2) (3) (4) (5)
At –40°C to +105°C, DVDD = +5V to +5.5V, and IOVDD = +5V, unless otherwise noted.
PARAMETER
t1
CS width for write operation
t2
MIN
MAX
UNIT
15
ns
Delay from R/W falling edge to CS falling edge
2
ns
t3
Delay from CS rising edge to R/W rising edge
2
ns
t4
Delay from address valid to CS falling edge
0
ns
t5
Delay from CS rising edge to address change
0
ns
t6
Delay from data valid to CS rising edge
15
ns
t7
Delay from CS rising to data change
t8
CS width for read operation
t9
5
ns
30
ns
Delay from R/W rising edge to CS falling edge
2
ns
t10
Delay from CS rising edge to R/W falling edge
2
ns
t11
Delay from address valid to CS falling edge
0
ns
t12
Delay from CS rising to address change
0
t13
Delay from CS falling edge to data valid
t14
Delay from CS rising to data bus off (Hi-Z)
2
ns
t15
Delay from CS rising edge to LDAC falling edge
0
ns
t16
LDAC pulse width
10
ns
t17
Delay from LDAC rising edge to next CS rising edge
20
ns
t18
Delay from BUSY rising edge to next LDAC falling edge
0
ns
t19
Delay from CS rising edge to next LDAC falling edge
30
ns
t20
Delay from CS rising edge to BUSY falling edge
t21
Delay from LDAC falling edge to BUSY rising edge
(1)
(2)
(3)
(4)
(5)
ns
25
20
50
ns
ns
ns
Specified by design; not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
Rise and fall times of all digital input signals are 3ns.
Rise and fall times of all digital outputs are 3ns for a 10pF capacitor load.
For sequential writes to the same address, there must be a minimum of 30ns between the CS rising edges.
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TIMING CHARACTERISTICS (1)
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(2) (3) (4) (5)
At –40°C to +105°C, DVDD = +3V to +5V, and IOVDD = +3V, unless otherwise noted.
PARAMETER
t1
CS width for write operation
t2
MIN
MAX
UNIT
25
ns
Delay from R/W falling edge to CS falling edge
2
ns
t3
Delay from CS rising edge to R/W rising edge
2
ns
t4
Delay from address valid to CS falling edge
6
ns
t5
Delay from CS rising edge to address change
0
ns
t6
Delay from data valid to CS rising edge
25
ns
t7
Delay from CS rising to data change
t8
CS width for read operation
t9
5
ns
50
ns
Delay from R/W rising edge to CS falling edge
2
ns
t10
Delay from CS rising edge to R/W falling edge
2
ns
t11
Delay from address valid to CS falling edge
6
ns
t12
Delay from CS rising to address change
0
t13
Delay from CS falling edge to data valid
t14
Delay from CS rising to data bus off (Hi-Z)
2
ns
t15
Delay from CS rising edge to LDAC falling edge
5
ns
t16
LDAC pulse width
10
ns
t17
Delay from LDAC rising edge to next CS rising edge
20
ns
t18
Delay from BUSY rising edge to next LDAC falling edge
0
ns
t19
Delay from CS rising edge to next LDAC falling edge
30
ns
t20
Delay from CS rising edge to BUSY falling edge
t21
Delay from LDAC falling edge to BUSY rising edge
(1)
(2)
(3)
(4)
(5)
14
ns
40
20
50
ns
ns
ns
Specified by design; not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
Rise and fall times of all digital input signals are 5ns.
Rise and fall times of all digital outputs are 5ns for a 10pF capacitor load.
For sequential writes to the same address, there must be a minimum of 50ns between the CS rising edges.
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
TIMING CHARACTERISTICS (1)
(2) (3) (4) (5)
At –40°C to +105°C, DVDD = +3V to +5V, and IOVDD = +1.8V, unless otherwise noted.
PARAMETER
t1
CS width for write operation
t2
MIN
MAX
UNIT
35
ns
Delay from R/W falling edge to CS falling edge
2
ns
t3
Delay from CS rising edge to R/W rising edge
2
ns
t4
Delay from address valid to CS falling edge
12
ns
t5
Delay from CS rising edge to address change
0
ns
t6
Delay from data valid to CS rising edge
35
ns
t7
Delay from CS rising to data change
t8
CS width for read operation
t9
Delay from R/W rising edge to CS falling edge
t10
Delay from CS rising edge to R/W falling edge
t11
Delay from address valid to CS falling edge
t12
Delay from CS rising to address change
t13
Delay from CS falling edge to data valid
t14
Delay from CS rising to data bus off (Hi-Z)
2
ns
t15
Delay from CS rising edge to LDAC falling edge
5
ns
t16
LDAC pulse width
10
ns
t17
Delay from LDAC rising edge to next CS rising edge
30
ns
t18
Delay from BUSY rising edge to next LDAC falling edge
0
ns
t19
Delay from CS rising edge to next LDAC falling edge
50
ns
t20
Delay from CS rising edge to BUSY falling edge
t21
Delay from LDAC falling edge to BUSY rising edge
(1)
(2)
(3)
(4)
(5)
5
ns
60
ns
2
ns
2
ns
12
ns
0
ns
50
30
50
ns
ns
ns
Specified by design; not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
Rise and fall times of all digital input signals are 8ns.
Rise and fall times of all digital outputs are 12ns for a 10pF capacitor load.
For sequential writes to the same address, there must be a minimum of 50ns between the CS rising edges.
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TYPICAL CHARACTERISTICS: Dual-Supply
At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25°C
0.75
0.50
DNL Error (LSB)
INL Error (LSB)
0.50
0.25
0
-0.25
DAC0
DAC1
DAC2
DAC3
-0.50
-0.75
-1.00
0
2048
4096
DAC4
DAC5
DAC6
DAC7
0.25
0
-0.25
DAC0
DAC1
DAC2
DAC3
-0.50
-0.75
-1.00
6144 8192 10240 12288 14336 16384
Digital Input Code
0
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 7.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
TA = +25°C
Gain = 4
0.75
TA = +25°C
Gain = 4
0.75
0.50
DNL Error (LSB)
0.50
0.25
0
-0.25
0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
0
Figure 8.
16
2048
DAC4
DAC5
DAC6
DAC7
Figure 6.
1.00
INL Error (LSB)
TA = +25°C
0.75
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 9.
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: Dual-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = -40°C
0.75
0.50
DNL Error (LSB)
INL Error (LSB)
0.50
0.25
0
-0.25
0
-0.25
-0.50
-0.75
-0.75
-1.00
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 10.
Figure 11.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25°C
0.75
TA = +25°C
0.75
0.50
DNL Error (LSB)
0.50
INL Error (LSB)
0.25
-0.50
-1.00
0.25
0
-0.25
0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 12.
Figure 13.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +105°C
0.75
TA = +105°C
0.75
0.50
DNL Error (LSB)
0.50
INL Error (LSB)
TA = -40°C
0.75
0.25
0
-0.25
0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
0
Figure 14.
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 15.
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TYPICAL CHARACTERISTICS: Dual-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
LINEARITY ERROR
vs TEMPERATURE
1.00
1.00
0.75
0.75
0.50
0.50
INL Max
DNL Error (LSB)
INL Error (LSB)
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
0.25
0
-0.25
INL Min
-0.50
0.25
DNL Max
0
DNL Min
-0.25
-0.50
-0.75
-0.75
-1.00
-1.00
-55
-35
5
-15
25
45
65
Temperature (°C)
85
105
125
-55
-35
5
-15
25
45
65
Temperature (°C)
85
Figure 16.
Figure 17.
LINEARITY ERROR
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
1.00
Gain = 4
0.75
0.75
0.50
DNL Error (LSB)
INL Max
0.25
0
-0.25
INL Min
-0.50
0.25
DNL Max
0
-0.25
DNL Min
-0.50
-0.75
-0.75
-1.00
-1.00
-55
-35
5
-15
25
45
65
Temperature (°C)
85
105
125
-55
25
45
65
Temperature (°C)
BIPOLAR ZERO ERROR
vs TEMPERATURE
BIPOLAR ZERO ERROR
vs TEMPERATURE
5
LSB = 1.83mV
4
3
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
-35
5
-15
Figure 19.
5
-55
-35
Figure 18.
-15
5
25
45
65
Temperature (°C)
DAC4
DAC5
DAC6
DAC7
85
105
125
85
105
125
LSB = 1.22mV
Gain = 4
4
Bipolar Zero Error (mV)
INL Error (LSB)
0.50
Bipolar Zero Error (mV)
125
1.00
Gain = 4
3
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
-55
-35
Figure 20.
18
105
-15
5
25
45
65
Temperature (°C)
DAC4
DAC5
DAC6
DAC7
85
105
125
Figure 21.
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: Dual-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
GAIN ERROR
vs TEMPERATURE
GAIN ERROR
vs TEMPERATURE
5
5
LSB = 1.83mV
4
Bipolar Zero Error (mV)
Gain Error (mV)
3
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
-55
-35
-15
5
25
45
65
Temperature (°C)
DAC4
DAC5
DAC6
DAC7
85
105
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-5
125
-55
-35
-15
5
25
45
65
Temperature (°C)
DAC4
DAC5
DAC6
DAC7
85
Figure 22.
Figure 23.
LINEARITY ERROR
vs AVDD AND AVSS
DIFFERENTIAL LINEARITY ERROR
vs AVDD AND AVSS
105
125
1.00
VREF = 2.048V
Gain = 4
0.75
VREF = 2.048V
Gain = 4
0.75
0.50
0.50
INL Max
DNL Error (LSB)
INL Error (LSB)
3
-4
1.00
0.25
0
INL Min
-0.25
0.25
DNL Max
0
DNL Min
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
4
6
8
10
12
AVDD = -AVSS (V)
14
16
18
4
6
8
10
12
AVDD = -AVSS (V)
14
16
Figure 24.
Figure 25.
LINEARITY ERROR
vs REFERENCE VOLTAGE
DIFFERENTIAL LINEARITY ERROR
vs REFERENCE VOLTAGE
1.00
18
1.00
AVDD = +18V
AVSS = -18V
0.75
AVDD = +18V
AVSS = -18V
0.75
0.50
0.50
INL Max
DNL Error (LSB)
INL Error (LSB)
LSB = 1.22mV
Gain = 4
4
0.25
0
-0.25
INL Min
0.25
DNL Max
0
-0.50
-0.50
-0.75
-0.75
-1.00
DNL Min
-0.25
-1.00
0
1
2
3
4
5
6
0
VREF (V)
Figure 26.
1
2
3
VREF (V)
4
5
6
Figure 27.
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TYPICAL CHARACTERISTICS: Dual-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
BIPOLAR ZERO ERROR
vs AVDD AND AVSS
GAIN ERROR
vs AVDD AND AVSS
5
5
VREF = 2.048V
Gain = 4
3
3
2
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
1
0
-1
-2
DAC4
DAC5
DAC6
DAC7
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
6
8
10
12
AVDD = -AVSS (V)
14
16
18
4
6
8
10
12
AVDD = -AVSS (V)
Figure 29.
BIPOLAR ZERO ERROR
vs REFERENCE VOLTAGE
BIPOLAR ZERO ERROR
vs REFERENCE VOLTAGE
16
18
5
AVDD = +18V
AVSS = -18V
4
Bipolar Zero Error (mV)
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-4
AVDD = +18V
AVSS = -18V
Gain = 4
4
3
-3
DAC4
DAC5
DAC6
DAC7
3
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
DAC4
DAC5
DAC6
DAC7
-5
0
1
2
3
4
5
6
0
1
2
VREF (V)
3
VREF (V)
4
Figure 30.
Figure 31.
GAIN ERROR
vs REFERENCE VOLTAGE
GAIN ERROR
vs REFERENCE VOLTAGE
5
5
6
5
AVDD = +18V
AVSS = -18V
4
3
3
2
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
AVDD = +18V
AVSS = -18V
Gain = 4
4
Gain Error (mV)
Gain Error (mV)
14
Figure 28.
5
1
0
-1
-2
DAC4
DAC5
DAC6
DAC7
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
DAC4
DAC5
DAC6
DAC7
-5
0
1
2
3
4
5
6
0
VREF (V)
Figure 32.
20
DAC4
DAC5
DAC6
DAC7
-5
4
Bipolar Zero Error (mV)
VREF = 2.048V
Gain = 4
4
Gain Error (mV)
Bipolar Zero Error (mV)
4
1
2
3
VREF (V)
4
5
6
Figure 33.
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: Dual-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
QUIESCENT CURRENTS
vs TEMPERATURE
QUIESCENT CURRENTS
vs DIGITAL INPUT CODE
8
8
Code = 2000h
6
6
IAVDD
IAVDD, IAVSS (mA)
IAVDD, IAVSS (mA)
2
0
IAVSS
-2
2
0
-2
IAVSS
-4
-4
-6
-6
-8
-8
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 34.
Figure 35.
QUIESCENT CURRENTS
vs REFERENCE VOLTAGE
DELTA OUTPUT VOLTAGE
vs SOURCE/SINK CURRENTS
6
8
0000h
6
4
IAVDD
4
2
DVOUT (mV)
IAVDD, IAVSS (mA)
IAVDD
4
4
0
-2
-4
-6
-4
1000h
-6
-8
2
3
VREF (V)
3FFFh
3000h
AVDD = +18V
AVSS = -18V
Code = 2000h
1
2000h
0
-2
IAVSS
0
2
4
5
6
-12 -10 -8
-6
-4
-2 0
2
IOUT (mA)
4
Figure 36.
Figure 37.
SETTLING TIME
–15V TO +15V TRANSITION
SETTLING TIME
+15V TO –15V TRANSITION
5V/div
Large-Signal Output
6
10
12
Code Change: 3FFFh to 0000h
Output Loaded with 10kW and
240pF to AGND
Small-Signal Error
Small-Signal Error
1 LSB/div
1 LSB/div
Code change: 0000h to 3FFFh
Output loaded with 10kW and
240pF to AGND
5V/div
8
Large-Signal Output
5V/div
LDAC
5V/div
LDAC
Time (10ms/div)
Time (10ms/div)
Figure 38.
Figure 39.
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TYPICAL CHARACTERISTICS: Dual-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
SETTLING TIME
1/4 TO 3/4 FULL-SCALE TRANSITION
SETTLING TIME
3/4 TO 1/4 FULL-SCALE TRANSITION
Code change: 3000h to 1000h
Output loaded with 10kW and
240pF to AGND
Large-Signal Output
5V/div
Small-Signal Error
Small-Signal Error
1 LSB/div
LDAC
5V/div
1 LSB/div
Large-Signal Output
Code change: 1000h to 3000h
Output loaded with 10kW and
240pF to AGND
5V/div
LDAC
5V/div
Time (10ms/div)
Time (10ms/div)
Figure 40.
Figure 41.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
Code change: 1FFFh to 2000h
Output loaded with 10kW and
240pF to AGND
Code change: 2000h to 1FFFh
Output loaded with 10kW and
240pF to AGND
Integrated Glitch Energy (3.5nV-s)
VOUT
2mV/div
2mV/div
VOUT
Integrated Glitch Energy (0.5nV-s)
5V/div
5V/div
LDAC
LDAC
Time (2ms/div)
Time (2ms/div)
Figure 42.
Figure 43.
0.1Hz TO 10Hz NOISE
FOR MIDSCALE CODE
0.1Hz TO 10Hz NOISE
FOR MIDSCALE CODE
TA = +25°C
Gain = 4
5mV/div
5mV/div
TA = +25°C
Time (2s/div)
Time (2s/div)
Figure 44.
22
Figure 45.
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: Dual-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +16.5V, AVSS = –16.5V, and gain = 6, unless otherwise noted.
IOVDD SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
3.0
2000
Code = 2000h
1800
IOVDD Supply Current (mA)
Output Voltage Noise Density (nV/ÖHz)
OUTPUT NOISE SPECTRAL DENSITY
vs FREQUENCY
1600
1400
1200
Gain = 6
1000
800
Gain = 4
600
400
IOVDD Values are Shown
for Logic Level Change
on D0 to D13.
2.5
TA = +25°C
2.0
1.5
IOVDD = 5V
1.0
IOVDD = 2.7V
0.5
200
IOVDD = 1.8V
0
0
1
10
100
1k
10k
0
100k
0.5
Frequency (Hz)
1.0
1.5 2.0 2.5 3.0 3.5
Logic Input Voltage (V)
4.0
4.5
5.0
Figure 46.
Figure 47.
BIPOLAR ZERO ERROR PRODUCTION DISTRIBUTION
BIPOLAR ZERO ERROR PRODUCTION DISTRIBUTION
45
45
TA = +25°C
Gain = 6
35
30
30
20
15
25
20
15
10
10
5
5
0
0
-2.50
-2.25
-2.00
-1.75
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
Population (%)
35
25
TA = +25°C
Gain = 4
40
-2.50
-2.25
-2.00
-1.75
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
Population (%)
40
Bipolar Zero Error (LSB)
Bipolar Zero Error (LSB)
Figure 48.
Figure 49.
GAIN ERROR PRODUCTION DISTRIBUTION
GAIN ERROR PRODUCTION DISTRIBUTION
30
35
TA = +25°C
Gain = 6
TA = +25°C
Gain = 4
30
25
Population (%)
20
15
10
20
15
5
5
0
0
-2.50
-2.25
-2.00
-1.75
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
10
-2.50
-2.25
-2.00
-1.75
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
Population (%)
25
Gain Error (LSB)
Gain Error (LSB)
Figure 50.
Figure 51.
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TYPICAL CHARACTERISTICS: Single-Supply
At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25°C
0.75
0.50
DNL Error (LSB)
INL Error (LSB)
0.50
0.25
0
-0.25
DAC0
DAC1
DAC2
DAC3
-0.50
-0.75
-1.00
0
2048
4096
DAC4
DAC5
DAC6
DAC7
0.25
0
-0.25
DAC0
DAC1
DAC2
DAC3
-0.50
-0.75
-1.00
6144 8192 10240 12288 14336 16384
Digital Input Code
0
4096
DAC4
DAC5
DAC6
DAC7
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 53.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
TA = +25°C
Gain = 4
0.75
TA = +25°C
Gain = 4
0.75
0.50
DNL Error (LSB)
0.50
0.25
0
-0.25
0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
0
Figure 54.
24
2048
Figure 52.
1.00
INL Error (LSB)
TA = +25°C
0.75
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 55.
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS: Single-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = -40°C
0.75
0.50
DNL Error (LSB)
INL Error (LSB)
0.50
0.25
0
-0.25
0
-0.25
-0.50
-0.75
-0.75
-1.00
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 56.
Figure 57.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25°C
0.75
TA = +25°C
0.75
0.50
DNL Error (LSB)
0.50
INL Error (LSB)
0.25
-0.50
-1.00
0.25
0
-0.25
0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 58.
Figure 59.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +105°C
0.75
0.75
0.50
DNL Error (LSB)
0.50
INL Error (LSB)
TA = -40°C
0.75
0.25
0
-0.25
0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
0
Figure 60.
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 61.
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
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TYPICAL CHARACTERISTICS: Single-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
1.00
1.00
0.75
0.75
0.50
0.50
DNL Error (LSB)
INL Error (LSB)
LINEARITY ERROR
vs TEMPERATURE
INL Max
0.25
0
-0.25
INL Min
-0.50
0.25
DNL Max
0
DNL Min
-0.25
-0.50
-0.75
-0.75
-1.00
-1.00
-55
-35
5
-15
25
45
65
Temperature (°C)
85
105
125
-55
-35
5
-15
25
45
65
Temperature (°C)
85
Figure 62.
Figure 63.
LINEARITY ERROR
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
1.00
Gain = 4
0.75
0.75
0.50
DNL Error (LSB)
INL Error (LSB)
0.50
INL Max
0.25
0
-0.25
INL Min
-0.50
0.25
DNL Max
0
-0.25
DNL Min
-0.50
-0.75
-0.75
-1.00
-1.00
-55
-35
5
-15
25
45
65
Temperature (°C)
85
105
125
-55
-35
5
-15
25
45
65
Temperature (°C)
Figure 64.
Figure 65.
ZERO-SCALE ERROR
vs TEMPERATURE
ZERO-SCALE ERROR
vs TEMPERATURE
5
85
105
125
5
LSB = 1.83mV
Code = 0040h
4
3
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
-55
-35
-15
DAC4
DAC5
DAC6
DAC7
5
25
45
65
Temperature (°C)
LSB = 1.22mV
Code = 0040h
Gain = 4
4
Zero-Scale Error (mV)
Zero-Scale Error (mV)
125
1.00
Gain = 4
3
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
85
105
125
-55
-35
Figure 66.
26
105
-15
5
25
45
65
Temperature (°C)
85
DAC4
DAC5
DAC6
DAC7
105
125
Figure 67.
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TYPICAL CHARACTERISTICS: Single-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
GAIN ERROR
vs TEMPERATURE
5
DAC0
DAC1
DAC2
DAC3
LSB = 1.83mV
4
3
2
5
DAC4
DAC5
DAC6
DAC7
3
1
0
-1
-2
2
1
0
-1
-2
-3
-3
-4
-4
-5
DAC0
DAC1
DAC2
DAC3
-5
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
Figure 69.
LINEARITY ERROR
vs AVDD
DIFFERENTIAL LINEARITY ERROR
vs AVDD
125
1.00
VREF = 2.048V
Gain = 4
0.75
VREF = 2.048V
Gain = 4
0.75
0.50
0.25
DNL Error (LSB)
0.50
INL Max
0
-0.25
INL Min
0.25
DNL Max
0
DNL Min
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
8
12
16
20
24
AVDD (V)
28
32
36
8
12
16
20
24
AVDD (V)
28
32
Figure 70.
Figure 71.
LINEARITY ERROR
vs REFERENCE VOLTAGE
DIFFERENTIAL LINEARITY ERROR
vs REFERENCE VOLTAGE
1.00
36
1.00
AVDD = +36V
AVDD = +36V
0.75
0.75
0.50
0.50
DNL Error (LSB)
INL Error (LSB)
DAC4
DAC5
DAC6
DAC7
Figure 68.
1.00
INL Error (LSB)
LSB = 1.22mV
Gain = 4
4
Gain Error (mV)
Gain Error (mV)
GAIN ERROR
vs TEMPERATURE
INL Max
0.25
0
-0.25
INL Min
0.25
DNL Max
0
-0.50
-0.50
-0.75
-0.75
-1.00
DNL Min
-0.25
-1.00
0
1
2
3
4
5
6
0
VREF (V)
Figure 72.
1
2
3
VREF (V)
4
5
6
Figure 73.
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TYPICAL CHARACTERISTICS: Single-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
ZERO-SCALE ERROR
vs AVDD
GAIN ERROR
vs AVDD
5
5
VREF = 2.048V
Code = 0040h
Gain = 4
3
3
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
2
1
0
-1
-2
DAC4
DAC5
DAC6
DAC7
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
12
16
20
24
AVDD (V)
28
32
36
8
12
16
20
24
AVDD (V)
Figure 75.
ZERO-SCALE ERROR
vs REFERENCE VOLTAGE
ZERO-SCALE ERROR
vs REFERENCE VOLTAGE
32
36
5
AVDD = 36V
Code = 0040h
4
Zero-Scale Error (mV)
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-4
AVDD = 36V
Code = 0040h
Gain = 4
4
3
-3
DAC4
DAC5
DAC6
DAC7
3
2
1
0
-1
-2
DAC0
DAC1
DAC2
DAC3
-3
-4
-5
DAC4
DAC5
DAC6
DAC7
-5
0
1
2
3
4
5
6
0
1
2
VREF (V)
5
3
VREF (V)
4
Figure 76.
Figure 77.
GAIN ERROR
vs REFERENCE VOLTAGE
GAIN ERROR
vs REFERENCE VOLTAGE
DAC0
DAC1
DAC2
DAC3
AVDD = +36V
4
3
2
5
DAC4
DAC5
DAC6
DAC7
5
6
AVDD = +36V
Gain = 4
4
3
Gain Error (mV)
Gain Error (mV)
28
Figure 74.
5
1
0
-1
2
1
0
-1
-2
-2
-3
-3
-4
-4
-5
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
-5
0
1
2
3
4
5
6
0
VREF (V)
Figure 78.
28
DAC4
DAC5
DAC6
DAC7
-5
8
Zero-Scale Error (mV)
VREF = 2.048V
Gain = 4
4
Gain Error (mV)
Zero-Scale Error (mV)
4
1
2
3
VREF (V)
4
5
6
Figure 79.
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TYPICAL CHARACTERISTICS: Single-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
QUIESCENT CURRENT
vs TEMPERATURE
QUIESCENT CURRENT
vs DIGITAL INPUT CODE
8
8
7
7
6
6
5
5
IAVDD (mA)
IAVDD (mA)
Code = 2000h
4
3
4
3
2
2
1
1
0
0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
0
125
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 80.
Figure 81.
QUIESCENT CURRENT
vs REFERENCE VOLTAGE
8
AVDD = 36V
Code = 2000h
7
IAVDD (mA)
6
5
4
3
2
1
0
0
1
2
3
VREF (V)
4
5
6
Figure 82.
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TYPICAL CHARACTERISTICS: Single-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
SETTLING TIME
0V TO 30V TRANSITION
SETTLING TIME
30V TO 0V TRANSITION
Large-Signal Output
Code change: 3FFFh to 0040h
Output loaded with 10kW and
240pF to AGND
5V/div
Small-Signal Error
Small-Signal Error
1 LSB/div
5V/div
LDAC
Code change: 0040h to 3FFFh
Output loaded with 10kW and
240pF to AGND
1 LSB/div
5V/div
Large-Signal Output
LDAC
5V/div
Time (10ms/div)
Time (10ms/div)
Figure 83.
Figure 84.
SETTLING TIME
1/4 TO 3/4 FULL-SCALE TRANSITION
SETTLING TIME
3/4 TO 1/4 FULL-SCALE TRANSITION
Code change: 3000h to 1000h
Output loaded with 10kW and
240pF to AGND
Large-Signal Output
5V/div
Small-Signal Error
Small-Signal Error
1 LSB/div
1 LSB/div
Large-Signal Output
5V/div
5V/div
LDAC
Code change: 1000h to 3000h
Output loaded with 10kW and
240pF to AGND
5V/div
LDAC
Time (10ms/div)
Time (10ms/div)
Figure 85.
Figure 86.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
Code change: 2000h to 1FFFh
Output loaded with 10kW and
240pF to AGND
VOUT
Integrated Glitch Energy (2.45nV-s)
2mV/div
Integrated Glitch Energy (3nV-s)
5V/div
LDAC
2mV/div
Code change: 1FFFh to 2000h
Output loaded with 10kW and
240pF to AGND
5V/div
VOUT
LDAC
Time (2ms/div)
Time (2ms/div)
Figure 87.
30
Figure 88.
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TYPICAL CHARACTERISTICS: Single-Supply (continued)
At TA = +25°C, VREF = +5V, AVDD = +32V, and gain = 6, unless otherwise noted.
OUTPUT VOLTAGE
vs SINK CURRENT CAPABILITY
OUTPUT VOLTAGE
vs SOURCE CURRENT CAPABILITY
2.5
30.5
2.0
30.0
3FFFh
3F80h
29.5
1.5
0200h
0100h
0080h
VOUT (V)
VOUT (V)
3FC0h
1.0
3F00h
29.0
3E00h
28.5
0.5
28.0
0
Operation Near AGND Rail
Operation Near AVDD Rail
0040h 0000h
27.5
-0.5
-10
-9
-8
-7
-6
-5
-4
ISINK (mA)
-3
-2
-1
0
0
1
2
3
4
5
6
ISOURCE (mA)
7
8
9
Figure 89.
Figure 90.
ZERO-SCALE ERROR PRODUCTION DISTRIBUTION
ZERO-SCALE ERROR PRODUCTION DISTRIBUTION
25
35
TA = +25°C
Code = 0040h
Gain = 6
20
10
TA = +25°C
Code = 0040h
Gain = 4
30
Population (%)
Population (%)
25
15
10
20
15
10
5
0
-2.50
-2.25
-2.00
-1.75
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
0
-2.50
-2.25
-2.00
-1.75
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
5
Zero-Scale Error (LSB)
Zero-Scale Error (LSB)
Figure 91.
Figure 92.
GAIN ERROR PRODUCTION DISTRIBUTION
GAIN ERROR PRODUCTION DISTRIBUTION
25
35
TA = +25°C
Gain = 6
TA = +25°C
Gain = 4
30
20
Population (%)
Population (%)
25
15
10
20
15
10
5
0
-2.50
-2.25
-2.00
-1.75
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
0
-2.50
-2.25
-2.00
-1.75
-1.50
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
5
Gain Error (LSB)
Gain Error (LSB)
Figure 93.
Figure 94.
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THEORY OF OPERATION
GENERAL DESCRIPTION
The DAC8228 contains eight DAC channels and eight output amplifiers in a single package. Each channel
consists of a resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a
string of resistors, each with a value of R, from REF to AGND, as shown in Figure 95. This type of architecture
provides DAC monotonicity. The 14-bit binary digital code loaded to the DAC register determines at which node
on the string the voltage is tapped off before being fed into the output amplifier. The output amplifier multiplies
the DAC output voltage by a gain of six or four. The output span is 9V with a 1.5V reference, 18V with a 3V
reference, and 30V for a 5V reference when using dual power supplies of ±16.5V and a gain of 6.
REF
R
R
R
To Output
Amplifier
R
R
Figure 95. Resistor String
CHANNEL GROUPS
The eight DAC channels and two Offset DACs are arranged into two groups (A and B) with four channels and
one Offset DAC per group. Group A consists of DAC-0, DAC-1, DAC-2, DAC-3, and Offset DAC-A. Group B
consists of DAC-4, DAC-5, DAC-6, DAC-7, and Offset DAC-B. Group A derives its reference voltage from
REF-A, and Group B derives its reference voltage from REF-B.
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USER-CALIBRATION FOR ZERO ERROR AND GAIN ERROR
The DAC8228 implements a digital user-calibration function that allows for trimming gain and zero errors on the
entire signal chain. This function can eliminate the need for external adjustment circuits. Each DAC channel has
a Zero Register and Gain Register. Using the correction engine, the data from the Input Data Register are
operated on by a digital adder and multiplier controlled by the contents of Zero and Gain registers, respectively.
The calibrated DAC data are then stored in the DAC Data Register where they are finally transferred into the
DAC latch and set the DAC output. Each time the data are written to the Input Data Register (or to the Gain or
Zero registers), the data in the Input Data Register are corrected, and the results automatically transferred to
DAC Data Register.
The range of the gain adjustment coefficient is 0.5 to 1.5. The range of the zero adjustment is –8192 LSB to
+8191 LSB, or ±50% of full scale.
There is only one correction engine in the DAC8228, which is shared among all channels. Each channel has an
individual busy flag (BF-x) in the Busy Flag register. When the channel is accessed, the respective BF-x bit is set
if either the Input Data Register, Zero Register, or Gain Register are written to. When the DAC data are adjusted
by the correction engine and transferred into DAC Data Register, the BF-x bit is cleared. It takes approximately
500ns per channel for the correction to complete.
The correction engine calibrates the individual channels according to priority. DAC-0 has the highest priority,
while DAC-7 has the lowest. Correction of lower-priority channels is not performed until correction of
higher-priority channels completes. Repeatedly accessing higher-priority channels may block the correction of
lower-priority channels. Table 1 lists the correction engine channel priority.
Table 1. Correction Engine Priority
CHANNEL
PRIORITY
DAC-0
1 (highest)
DAC-1
2
DAC-2
3
DAC-3
4
DAC-4
5
DAC-5
6
DAC-6
7
DAC-7
8 (lowest)
The device also provides a global busy flag (GBF) and a logic output from the BUSY pin to indicate the
correction engine status. When the correction engine is running, the GBF bit is set ('1'), and the BUSY pin is low.
When the engine stops, GBF is cleared ('0'), and the BUSY pin goes high (or Hi-Z if no pull-up resistor is used).
Note that when the correction engine is disabled, the GBF bit is always cleared, and the BUSY pin is always in a
Hi-Z state.
To avoid any potential conflicts caused by the correction process, the input data must be written properly. Either
one of the following approaches can be used to update the DAC Input Data Register, Zero Register, or Gain
Register:
1. Writing to any channel when the BUSY pin is high or when the GBF bit = '0'.
2. Writing to an individual channel when the corresponding BF-x bit = '0'.
3. Tracking the correction time. It takes approximately 500ns to correct one channel for each input data, zero or
gain change.
The individual channel can be rewritten only if the corrections are completed for that channel and for all other
channels that have higher priority. For example, if DAC-0, DAC-1, and DAC-2 are written to first, and then DAC-1
is written to again, the second writing to DAC-1 is not permitted until the correction of the first DAC-1 writing is
complete (that is, approximately 1000ns after writing to DAC-0, or 500ns after the first writing to DAC-1).
However, if writing to DAC-0, DAC-1, DAC-2, and then DAC-2 again, the second writing of DAC-2 is prohibited
until the correction for the first writing to DAC-2 is complete (that is, approximately 1500ns after writing to DAC-0,
or 500ns after the first writing to DAC-2).
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If the user-calibration function is not needed, the correction engine can be turned off to speed up the device.
Setting the SCE bit in the Configuration Register to '0' turns off the correction engine. Setting SCE to '1' enables
the correction engine. When SCE = '0' (default), the data are directly transferred to the DAC Data Register. In
this case, writing to the Gain Register or Zero Register updates the Gain and Zero registers but does not start a
math engine calculation. Reading these registers returns the written values.
ANALOG OUTPUTS (VOUT-0 to VOUT-7, with reference to the ground of REF-x)
When the correction engine is off (SCE = '0'):
VOUT = VREF ´ Gain ´
INPUT_CODE
OFFSETDAC_CODE
- VREF ´ (Gain - 1) ´
16384
16384
(1)
BLANKSPACE
When the correction engine is on (SCE = '1'):
VOUT = VREF ´ Gain ´
DAC_DATA_CODE
16384
- VREF ´ (Gain - 1) ´
OFFSETDAC_CODE
16384
(2)
BLANKSPACE
Where:
DAC_DATA_CODE =
INPUT_CODE ´ (USER_GAIN + 213)
214
+ USER_ZERO
Gain = the DAC gain defined by the GAIN bit in the Configuration Register.
INPUT_CODE = the data written into the Input Data Register.
OFFSETDAC_CODE = the data written into the Offset DAC Register.
USER_GAIN = the code of the Gain Register.
USER_ZERO = the code of the Zero Register.
For single-supply operation, the OFFSET-A pin must be connected to the AGND-A pin and the OFFSET-B pin
must be connected to the AGND-B pin. Offset DAC-A and Offset DAC-B are in a power-down state.
For dual-supply operation, the OFFSET-A and OFFSET-B default code for a gain of 6 is 9830 with a ±3 LSB
variation, depending on the linearity of the Offset DACs. The default code for a gain of 4 is 10923 with a ±3 LSB
variation. The default code of OFFSET-A and OFFSET-B are independently factory trimmed for both gains of 6
and 4.
The power-on default value of the Gain Register is 8192, and the default value of the Zero Register is '0'. The
DAC input registers are set to a default value of 0000h.
Note that the maximum output voltage must not be greater than (AVDD – 0.5V) and the minimum output voltage
must not be less than (AVSS + 0.5V); otherwise, the output may be saturated.
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INPUT DATA FORMAT
The USB/BTC pin defines the input data format and the Offset DAC format. When this pin connects to DGND,
the Input DAC data and Offset DAC data are straight binary, as shown in Table 2 and Table 4. When this pin is
connected to IOVDD, the Input DAC data and Offset DAC data are twos complement, as shown in Table 3 and
Table 5.
Table 2. Bipolar Output vs Straight Binary Code Using Dual Power Supplies with Gain = 6
USB CODE
NOMINAL OUTPUT
DESCRIPTION
3FFFh
+3 × VREF × (8191/8192)
+Full-Scale – 1 LSB
••• •••
••• •••
••• •••
2001h
+3 × VREF × (1/8192)
+1 LSB
2000h
0
Zero
1FFFh
–3 × VREF × (1/8192)
–1 LSB
••• •••
••• •••
••• •••
0000h
–3 × VREF × (8192/8192)
–Full-Scale
Table 3. Bipolar Output vs Twos Complement Code Using Dual Power Supplies with Gain = 6
BTC CODE
NOMINAL OUTPUT
DESCRIPTION
1FFFh
+3 × VREF × (8191/8192)
+Full-Scale – 1 LSB
••• •••
••• •••
••• •••
0001h
+3 × VREF × (1/8192)
+1 LSB
0000h
0
Zero
3FFFh
–3 × VREF × (1/8192)
–1 LSB
••• •••
••• •••
••• •••
2000h
–3 × VREF × (8192/8192)
–Full-Scale
Table 4. Unipolar Output vs Straight Binary Code Using Single Power Supply with Gain = 6
USB CODE
NOMINAL OUTPUT
DESCRIPTION
3FFFh
+6 × VREF × (16383/16384)
+Full-Scale – 1 LSB
••• •••
••• •••
••• •••
2001h
+6 × VREF × (8193/16384)
Midscale + 1 LSB
2000h
+6 × VREF × (8192/16384)
Midscale
1FFFh
+6 × VREF × (8191/16384)
Midscale – 1 LSB
••• •••
••• •••
••• •••
0000h
0
0
Table 5. Unipolar Output vs Twos Complement Code Using Single Power Supply with Gain = 6
BTC CODE
NOMINAL OUTPUT
DESCRIPTION
1FFFh
+6 × VREF × (16383/16384)
+Full-Scale – 1 LSB
••• •••
••• •••
••• •••
0001h
+6 × VREF × (8193/16384)
Midscale + 1 LSB
0000h
+6 × VREF × (8192/16384)
Midscale
3FFFh
+6 × VREF × (8191/16384)
Midscale – 1 LSB
••• •••
••• •••
••• •••
2000h
0
0
The data written to the Gain Register are always in straight binary, data to the Zero Register are in twos
complement, and data to all other control registers are as specified in the definitions, regardless of the USB/BTC
pin status.
In reading operation, the read-back data are in the same format as written.
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OFFSET DACS
There are two 14-bit Offset DACs: one for Group A, and one for Group B. The Offset DACs allow the entire
output curve of the associated DAC groups to be shifted by introducing a programmable offset. This offset allows
for asymmetric bipolar operation of the DACs or unipolar operation with bipolar supplies. Thus, subject to the
limitations of headroom, it is possible to set the output range of Group A and/or Group B to be unipolar positive,
unipolar negative, symmetrical bipolar, or asymmetrical bipolar, as shown in Table 6 and Table 7. Increasing the
digital input codes for the offset DAC shifts the outputs of the associated channels in the negative direction. The
default codes for the Offset DACs in the DAC8228 are factory trimmed to provide optimal offset and gain
performance for the default output range and span of symmetric bipolar operation. When the output range is
adjusted by changing the value of the Offset DAC, an extra offset is introduced as a result of the linearity and
offset errors of the Offset DAC. Therefore, the actual shift in the output span may vary slightly from the ideal
calculations. For optimal offset and gain performance in the default symmetric bipolar operation, the Offset DAC
input codes should not be changed from the default power-on values. The allowed maximum offset depends on
the reference and the power supply. If INPUT_CODE from Equation 1 or DAC_DATA_CODE from Equation 2 is
set to 0, then these equations simplify to Equation 3:
VOUT = -VREF ´ (Gain - 1) ´
OFFSETDAC_CODE
16384
(3)
This equation shows the transfer function of the Offset DAC to the output of the DAC channels. In any case, the
analog output must not go beyond the specified range shown in the Analog Outputs section. After power-on or
reset, the Offset DAC is set to the value defined by the selected data format and the selected analog output
voltage. If the DAC gain setting is changed, the offset DAC code is reset to the default value corresponding to
the new DAC gain setting. Refer to the Power-On Reset and Hardware Reset sections for details.
For single-supply operation (AVSS = 0V), the Offset DAC is turned off, and the output amplifier is in a Hi-Z state.
The OFFSET-x pin must be connected to the AGND-x pin through a low-impedance connection. For dual-supply
operation, this pin provides the output of the Offset DAC. The OFFSET-x pin is not intended to drive an external
load. See Figure 96 for the internal Offset DAC and output amplifier configuration.
Table 6. Example of Offset DAC Codes and Output Ranges with Gain = 6 and VREF = 5V
(1)
OFFSET DAC
CODE
OFFSET DAC
VOLTAGE
DAC CHANNELS MFS
VOLTAGE
DAC CHANNELS PFS
VOLTAGE
2666h (1)
3.0V
–15V
+15V – 1 LSB
0000h
0V
0V
+30V – 1 LSB
3FFFh
~5.0V
–25V
+5V – 1 LSB
199Ah
~2.0V
–10V
+20V – 1 LSB
3333h
~4.0V
–20V
+10V – 1 LSB
This is the default code for symmetric bipolar operation; actual codes may vary ±3 LSB. Codes are in straight binary format.
Table 7. Example of Offset DAC Codes and Output Ranges with Gain = 4 and VREF = 5V
(1)
36
OFFSET DAC
CODE
OFFSET DAC
VOLTAGE
DAC CHANNELS MFS
VOLTAGE
DAC CHANNELS PFS
VOLTAGE
2AABh (1)
~3.33333V
–10V
+10V – 1 LSB
0000h
0V
0V
+20V – 1 LSB
3FFFh
~5.0V
–15V
+5V – 1 LSB
1555h
~1.666V
–5V
+15V – 1 LSB
2000h
2.5V
–7.5V
+12.5V – 1 LSB
3555h
~4.1666V
–12.5V
+7.5V – 1 LSB
This is the default code for symmetric bipolar operation; actual codes may vary ±3 LSB. Codes are in straight binary format.
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VOUT = GAIN x V1 - (GAIN - 1) x VOFF
DAC
Channel
V1
VOUT
AGND-x
Offset
DAC
VOFF
OFFSET
Figure 96. Output Amplifier and Offset DAC
OUTPUT AMPLIFIERS
The output amplifiers can swing to 0.5V below the positive supply and 0.5V above the negative supply. This
condition limits how much the output can be offset for a given reference voltage. The maximum range of the
output for ±17V power and a +5.5V reference is –16.5V to +16.5V for gain = 6.
Each output amplifier is implemented with individual over-current protection. The amplifier is clamped at 10mA,
even if the output current goes over 10mA.
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GENERAL-PURPOSE INPUT/OUTPUT PIN (GPIO)
The GPIO pin is a general-purpose, bidirectional, digital input/output, as shown in Figure 97. When the GPIO pin
acts as an output, the pin status is determined by the corresponding GPIO bit in the GPIO Register. The pin
output is high-impedance when the GPIO bit is set to '1', and is logic low when the GPIO bit is cleared to '0'.
Note that a pull-up resistor to IOVDD is required when using the GPIO pin as an output. When the GPIO pin acts
as an input, the digital value on the pin is acquired by reading the GPIO bit. After power-on reset, or any forced
hardware or software reset, the GPIO bit is set to '1', and is in a high-impedance state. If not used, the GPIO pin
must be tied to either DGND or to IOVDD through a pull-up resistor. Leaving the GPIO pin floating can cause high
IOVDD supply currents.
+IOVDD
GPIO
Enable
Bit GPIO (when writing)
Bit GPIO (when reading)
Figure 97. GPIO Pin
BUSY Pin
The BUSY pin is an open-drain output. When the correction engine runs, the GBF bit in the Configuration
Register is set and the BUSY pin is low. When multiple DAC8228 devices may be used in one system, the BUSY
pins can be tied together. When each device has finished updating the DAC Data Register, the respective BUSY
pin is released. If another device has not finished updating the DAC Data Register, it will hold BUSY low. This
configuration is useful when it is required that no DAC in any device is updated until all other DACs are ready.
ANALOG OUTPUT PIN (CLR)
The CLR pin is an active low input that should be high for normal operation. When this pin is in logic '0', all VOUT
outputs connect to AGND-x through internal 15kΩ resistors and are cleared to 0 V, and the output buffer is in a
Hi-Z state. While CLR is low, all LDAC pulses are ignored. When CLR is taken high again while the LDAC is
high, the DAC outputs remain cleared until LDAC is taken low. However, if LDAC is tied low, taking CLR back to
high sets the DAC output to the level defined by the value of the DAC latch. The contents of the Zero Registers,
Gain Registers, Input Data Registers, DAC Data Registers, and DAC latches are not affected by taking CLR low.
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POWER-ON RESET
The DAC8228 contains a power-on reset circuit that controls the output during power-on and power down. This
feature is useful in applications where the known state of the DAC output during power-on is important. The
Offset DAC Registers, DAC Data Registers, and DAC latches are loaded with the value defined by the RSTSEL
pin, as shown in Table 8. The Gain Registers and Zero Registers are loaded with default values. The Input Data
Register is reset to 0000h, independent of the RSTSEL state.
Table 8. Bipolar Output Reset Values for Dual Power-Supply Operation
(1)
RSTSEL PIN
USB/BTC PIN
INPUT FORMAT
VALUE OF DAC
DATA REGISTER
AND DAC LATCH
VALUE OF OFFSET
DAC REGISTER
FOR GAIN = 6 (1)
DGND
DGND
Straight Binary
0000h
2666h
–Full-Scale
VOUT
IOVDD
DGND
Straight Binary
2000h
2666h
0V
DGND
IOVDD
Twos Complement
2000h
0666h
–Full-Scale
IOVDD
IOVDD
Twos Complement
0000h
0666h
0V
Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±3 LSB from the nominal number listed in this table.
In single-supply operation, the Offset DAC is turned off and the output is unipolar. The power-on reset is defined
as shown in Table 9.
Table 9. Unipolar Output Reset Values for Single Power-Supply Operation
RSTSEL PIN
USB/BTC PIN
INPUT FORMAT
VALUE OF DAC DATA
REGISTER AND DAC
LATCH
DGND
DGND
Straight Binary
0000h
0V
IOVDD
DGND
Straight Binary
2000h
Midscale
DGND
IOVDD
Twos Complement
2000h
0V
IOVDD
IOVDD
Twos Complement
0000h
Midscale
VOUT
HARDWARE RESET
When the RST pin is low, the device is in hardware reset. All the analog outputs (VOUT-0 to VOUT-7), the DAC
registers, and the DAC latches are set to the reset values defined by the RSTSEL pin as shown in Table 8 and
Table 9. In addition, the Gain and Zero registers are loaded with default values, communication is disabled, and
the signals on R/W, CS , [D0:D13], and [A0:A4] are ignored (note that [D0:D13] are in a high-impedance state).
The Input Data Register is reset to 0000h, independent of the RSTSEL state. On the rising edge of RST, the
analog outputs (VOUT-0 to VOUT-7) maintain the reset value as defined by the RSTSEL pin until a new value is
programmed. After RST goes high, the parallel interface returns to normal operation. CS must be set to a logic
high whenever RST is used.
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UPDATING THE DAC OUTPUTS
Depending on the status of both CS and LDAC, and after data have been transferred into the DAC Data
registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode. This update
mode is established at power-on. If asynchronous mode is desired, the LDAC pin must be permanently tied low
before power is applied to the device. If synchronous mode is desired, LDAC must be logic high before and
during power-on.
The DAC8228 updates a DAC latch only if it has been accessed since the last time LDAC was brought low or if
the LD bit is set to '1', thereby eliminating any unnecessary glitch. Any DAC channels that were not accessed are
not loaded again. When the DAC latch is updated, the corresponding output changes to the new level
immediately.
Asynchronous Mode
In this mode, the LDAC pin is set low at power-up. This action places the DAC8228 into Asynchronous mode,
and the LD bit and LDAC signal are ignored. When the correction engine is off (SCE bit = '0'), the DAC Data
Registers and DAC latches are updated immediately when CS goes high. When the correction engine is on (SCE
bit = '1'), each DAC latch is updated individually when the correction engine updates the corresponding DAC
Data Register.
Synchronous Mode
To activate this mode, take LDAC low or set the LD bit to '1' after CS goes high. If LDAC goes low or if the LD bit
is set to '1' when SCE = '0', all DAC latches are updated simultaneously. If LDAC goes low or if the LD bit is set
to '1' when SCE = '1' and the BUSY pin is high (GBF bit = '0'), all DAC latches are updated simultaneously. If
LDAC goes low or the LD bit is set to '1' when SCE = '1' and the BUSY pin is low (GBF bit = '1'), the DAC
latches are not updated immediately because the correction engine is still running. Instead, all DAC latches are
updated simultaneously when the GBF bit is cleared to '0'. At that time, the correction engine is finished.
In this mode, when LDAC stays high, the DAC latch is not updated; therefore, the DAC output does not change.
The DAC latch is updated by taking LDAC low (or by setting the LD bit in the Configuration Register to '1') any
time after the delay of t15 from the rising edge of CS (when the correction engine is disabled), or after the delay
of t18 from the rising edge of BUSY (when the correction engine is enabled). If the timing requirement of t15 or t18
is not satisfied, invalid data are loaded. Refer to the Timing Diagrams and the Configuration Register (Table 11)
for details.
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MONITOR OUTPUT PIN (VMON)
The VMON pin is the channel monitor output. It monitors either of the DAC outputs, offset DAC outputs, or
reference buffer outputs. The channel monitor function consists of an analog multiplexer addressed via the
parallel interface, allowing any channel output, reference buffer output, or offset DAC output to be routed to the
VMON pin for monitoring using an external ADC. The monitor function is controlled by the Monitor Register, which
allows the monitor output to be enabled or disabled. When disabled, the monitor output is high-impedance;
therefore, several monitor outputs may be connected in parallel with only one enabled at a time.
Note that the multiplexer is implemented as a series of analog switches. Care should be taken to ensure the
maximum current from the VMON pin must not be greater than the given specification because this could
conceivably cause a large amount of current to flow from the input of the multiplexer (that is, from VOUT-X) to the
output of the multiplexer (VMON). Refer to the Monitor Register section and Table 12 for more details.
POWER-DOWN MODE
The DAC8228 is implemented with a power-down function to reduce power consumption. Either the entire device
or each individual group can be put into power-down mode. If the proper power-down bit (PD-x) in the
Configuration Register is set to '1', the individual group is put into power down mode. During power-down mode,
the analog outputs (VOUT-0 to VOUT-7) connect to AGND-X through an internal 15kΩ resistor, and the output
buffer is in Hi-Z status. When the entire device is in power-down, the bus interface remains active in order to
continue communication and receive commands from the host controller, but all other circuits are powered down.
The host controller can wake the device from power-down mode and return to normal operation by clearing the
PD-x bit; it takes 200μs or less for recovery to complete.
POWER-ON RESET SEQUENCING
The DAC8228 permanently latches the status of some of the digital pins at power-on. These digital levels should
be well-defined before or while the digital supply voltages are applied. Therefore, it is advised to have a pull up
resistor to IOVDD or DGND for the digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL) to ensure that
these levels are set correctly while the digital supplies are raised.
For proper power-on initialization of the device, IOVDD and the digital pins must be applied before or at the same
time as DVDD. If possible, it is preferred that IOVDD and DVDD can be connected together in order to simplify the
supply sequencing requirements. Pull-up resistors should go to either supply. AVDD should be applied after the
digital supplies (IOVDD and DVDD) and digital initialization pins (LDAC, CLR, RST, CS, and RSTSEL). AVSS can
be applied at the same time as or after AVDD. The REF-x pins must be applied last.
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PARALLEL INTERFACE
The DAC8228 interfaces with microprocessors using a 14-bit data bus. The interface is double-buffered, allowing
simultaneous updating of all DACs. Each DAC has an input data register, DAC data register, user-calibration
zero register, user-calibration gain register, and DAC latch. When user calibration is enabled, the input data
register receives data from the data bus, the DAC Data Register stores the data after internal calibration, and the
DAC latch sets the analog output level. When user calibration is disabled (default), the DAC Data Register stores
data from the data bus, and the DAC latch sets the analog output level. Five address lines (A0:A4) select which
DAC or auxiliary register is addressed. Table 10 shows the register map.
Table 10. Register Map
ADDRESS BITS
DATA BITS
A4 A3 A2 A1 A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
REGISTER
Configuration
Register
0
0
0
0
0
A/B
LD
RST
PD-A
PD-B
SCE
GBF
GAIN-A
GAIN-B
0
0
0
0
1
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC-0
Offset
DAC-A
0
0
0
1
0
GPIO
0
0
0
1
1
D13:D0, default = 9830 (2666h)
Offset DAC-A
Data Register
0
0
1
0
0
D13:D0 , default = 9830 (2666h)
Offset DAC-B
Data Register
0
0
1
0
1
0
0
1
1
0
Reserved (2)
Reserved
0
0
1
1
1
Reserved (2)
Reserved
0
1
0
0
0
DB13:DB0
DAC-0
0
1
0
0
1
DB13:DB0
DAC-1
0
1
0
1
0
DB13:DB0
DAC-2
0
1
0
1
1
DB13:DB0
DAC-3
0
1
1
0
0
DB13:DB0
DAC-4
0
1
1
0
1
DB13:DB0
DAC-5
0
1
1
1
0
DB13:DB0
DAC-6
0
1
1
1
1
DB13:DB0
DAC-7
1
0
0
0
0
Z13:Z0, default = 0 (0000h), twos complement
Zero Register-0
1
1
0
0
0
G13:G0, default = 8192 (2000h), straight binary
Gain Register-0
1
0
0
0
1
Z13:Z0, default = 0 (0000h), twos complement
Zero Register-1
1
1
0
0
1
G13:G0, default = 8192 (2000h), straight binary
Gain Register-1
1
0
0
1
0
Z13:Z0, default = 0 (0000h), twos complement
Zero Register-2
1
1
0
1
0
G13:G0, default = 8192 (2000h), straight binary
Gain Register-2
1
0
0
1
1
Z13:Z0, default = 0 (0000h), twos complement
Zero Register-3
1
1
0
1
1
G13:G0, default = 8192 (2000h), straight binary
Gain Register-3
1
0
1
0
0
Z13:Z0, default = 0 (0000h), twos complement
Zero Register-4
1
1
1
0
0
G13:G0, default = 8192 (2000h), straight binary
Gain Register-4
1
0
1
0
1
Z13:Z0, default = 0 (0000h), twos complement
Zero Register-5
1
1
1
0
1
G13:G0, default = 8192 (2000h), straight binary
Gain Register-5
1
0
1
1
0
Z13:Z0, default = 0 (0000h), twos complement
Zero Register-6
1
1
1
1
0
G13:G0, default = 8192 (2000h), straight binary
Gain Register-6
1
0
1
1
1
Z13:Z0, default = 0 (0000h), twos complement
Zero Register-7
1
1
1
1
1
G13:G0, default = 8192 (2000h), straight binary
Gain Register-7
(1)
(2)
42
BF-7
Don't Care
D1:D0
(1)
Offset
DAC-B
Ref
Buffer
-A
Ref
Buffer
-B
Don't Care (1)
BF-6
BF-5
BF-4
BF-3
BF-2
BF-1
BF-0
Don't
Care (1)
Monitor Register
GPIO Register
Don't Care (1)
Busy Flag
Register
Writing to a Don't Care bit has no effect; reading the bit returns '0'.
Writing to a reserved bit has no effect; reading the bit returns '0'.
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INTERNAL REGISTERS
The DAC8228 internal registers consist of the Configuration Register, the Monitor Register, the DAC Input Data
Registers, the Zero Registers, the Gain Registers, the DAC Data Registers, and the Busy Flag Register, and are
described in the following section.
The Configuration Register specifies which actions are performed by the device. Table 11 shows the details.
Table 11. Configuration Register (Default = 2000h)
BIT
D13
NAME
A/B
DEFAULT
VALUE
DESCRIPTION
1
A/B bit.
When A/B = '0', reading DAC-x returns the value in the Input Data Register.
When A/B = '1', reading DAC-x returns the value in the DAC Data Register.
When the correction engine is enabled, the data returned from the Input Data Register are the original data written to the
bus, and the value in the DAC Data Register is the corrected data.
D12
LD
0
Synchronously update DAC bits.
When LDAC is tied high, setting LD = '1' at any time after the write operation and the correction process complete
synchronously updates all DAC latches with the content of the corresponding DAC Data Register, and sets VOUT to a new
level. The DAC8228 updates the DAC latch only if it has been accessed since the last time LDAC was brought low or the
LD bit was set to '1', thereby eliminating unnecessary glitch. Any DACs that were not accessed are not reloaded. After
updating, the bit returns to '0'. When the LDAC pin is tied low, this bit is ignored. When the correction engine is off, the LD
bit can be issued any time after the write operation is finished, and the DAC latch is immediately updated when CS goes
high.
D11
RST
0
Software reset bit.
Set the RST bit to '1' to reset the device; functions the same as a hardware reset. After reset completes, the RST bit
returns to '0'.
D10
PD-A
0
Power-down bit for Group A.
Setting the PD-A bit to '1' places Group A (DAC-0, DAC-1, DAC-2, and DAC-3) into power-down mode. All output buffers
are in Hi-Z and all analog outputs (VOUT-X) connect to AGND-A through an internal 15kΩ resistor.
Setting the PD-A bit to '0' returns group A to normal operation.
D9
PD-B
0
Power-down bit for Group B.
Setting the PD-B bit to '1' places Group B (DAC-4, DAC-5, DAC-6, and DAC-7) into power-down operation. All output
buffers are in Hi-Z and all analog outputs (VOUT-X) connect to AGND-B through an internal 15kΩ resistor.
Setting the PD-B bit to '0' returns group B to normal operation.
D8
SCE
0
System-calibration enable bit.
Set the SCE bit to '1' to enable the correction engine. When the engine is enabled, the input data are adjusted by the
correction engine according to the contents of the corresponding Gain Register and Zero Register. The results are
transferred to the corresponding DAC Data Register, and finally loaded into the DAC latch, which sets the VOUT-x pin
output level.
Set the SCE bit to '0' to turn off the correction engine. When the engine is turned off, the input data are transferred to the
corresponding DAC Data Register, and then loaded into the DAC latch, which sets the output voltage. Refer to the User
Calibration for Zero-Code Error and Gain Error section for details.
D7
(Read
Only)
GBF
0
Global correction engine busy flag.
GBF = '1' when the correction engine is running, indicating that at least one channel has not been corrected.
GBF = 0' 'when the correction engine stops, indicating that no more correction is needed.
When the SCE bit = '0', GBF is always cleared ('0').
0
Gain bit for Group A (DAC-0, DAC-1, DAC-2, and DAC-3).
Set the GAIN-A bit to '0' for an output span = 6 × REF-A.
Set the GAIN-A bit to '1' for an output span = 4 × REF-A.
Updating this bit to a new value automatically resets the Offset DAC-A Register to its factory-trimmed value for the new
gain setting.
D6
GAIN-A
D5
GAIN-B
0
Gain bit for Group B (DAC-4, DAC-5, DAC-6, and DAC-7).
Set the GAIN-B bit to '0' for an output span = 6 × REF-B.
Set the GAIN-B bit to '1' for an output span = 4 × REF-B.
Updating this bit to a new value automatically resets the Offset DAC-B Register to its factory-trimmed value for the new
gain setting.
D4:D0
—
0
Don't care. Writing to these bits has no effect; reading these bits returns '0'.
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Monitor Register (default = 0000h).
The Monitor Register selects one of the DAC outputs, reference buffer outputs, or offset DAC outputs to be
monitored through the VMON pin. Only one bit at a time can be set to '1'. When bits [D13:D2] = '0', the monitor is
disabled and VMON is in a Hi-Z state.
Note that if any value is written other than those specified in Table 12, the Monitor Register stores the invalid
value; however, the VMON pin is forced into a Hi-Z state.
Table 12. Monitor Register (Default = 0000h)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1:D0
VMON CONNECTS TO
0
0
0
0
0
0
0
0
0
0
0
1
X (1)
Reference buffer B output
0
0
0
0
0
0
0
0
0
0
1
0
X
Reference buffer A output
0
0
0
0
0
0
0
0
0
1
0
0
X
Offset DAC B output
0
0
0
0
0
0
0
0
1
0
0
0
X
Offset DAC A output
0
0
0
0
0
0
0
1
0
0
0
0
X
DAC-0
0
0
0
0
0
0
1
0
0
0
0
0
X
DAC-1
0
0
0
0
0
1
0
0
0
0
0
0
X
DAC-2
0
0
0
0
1
0
0
0
0
0
0
0
X
DAC-4
0
0
0
1
0
0
0
0
0
0
0
0
X
DAC-4
0
0
1
0
0
0
0
0
0
0
0
0
X
DAC-5
0
1
0
0
0
0
0
0
0
0
0
0
X
DAC-6
1
0
0
0
0
0
0
0
0
0
0
0
X
DAC-7
0
0
0
0
0
0
0
0
0
0
0
0
X
Monitor function disabled, Hi-Z (default)
All other codes
(1)
Monitor function disabled, Hi-Z
X = don't care. Writing to this bit has no effect; reading the bit returns '0'.
Input Data Register for DAC-n (where n = 0 to 7). Default = 0000h.
This register stores the DAC data written to the device when the SCE bit = '1'. When the SCE bit = '0' (default),
the DAC Data Register stores the DAC data written to the device. When the data are loaded into the
corresponding DAC latch, the DAC output changes to the new level defined by the DAC data. The default value
after power-on or reset is 0000h.
Table 13. DAC-n (1) Input Data Register
MSB
LSB
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB13 (2)
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
(1)
(2)
44
n = 0, 1, 2, 3, 4, 5, 6, or 7.
DB13:DB0 are the DAC data bits
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Zero Register n (where n = 0 to 7). Default = 0000h.
The Zero Register stores the user-calibration data that are used to eliminate the offset error, as shown in
Table 14. The data are 14 bits wide, 1 LSB/step, and the total adjustment is –8192 LSB to +8191 LSB, or ±50%
of full-scale range. The Zero Register uses a twos complement data format.
Table 14. Zero Register
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Z13
Z12
Z11
Z10
Z9
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
Z13:Z0—OFFSET BITS
ZERO ADJUSTMENT
1FFFh
+8191 LSB
1FFEh
+8190 LSB
••• ••• •••
••• ••• •••
0001h
+1 LSB
0000h
0 LSB (default)
3FFFh
–1 LSB
••• ••• •••
••• ••• •••
2001h
–8191 LSB
2000h
–8192 LSB
Gain Register n (where n = 0 to 7). Default = 2000h.
The Gain Register stores the user-calibration data that are used to eliminate the gain error, as shown in
Table 15. The data are 14 bits wide, 0.0061% FSR/step, and the total adjustment range is 0.5 to 1.5. The Gain
Register uses a straight binary data format.
Table 15. Gain Register
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
G0
G13:G0—GAIN-CODE BITS
GAIN ADJUSTMENT
3FFFh
1.499939
3FFEh
1.499878
••• ••• •••
••• ••• •••
2001h
1.000061
2000h
1 (default)
1FFFh
0.999939
••• ••• •••
••• ••• •••
0001h
0.500061
0000h
0.5
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GPIO Register. Default = 2000h.
The GPIO Register determines the status of the GPIO pin.
D13
D12
GPIO
(1)
X
(1)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
X
X = don't care. Writing to this bit has no effect; reading the bit returns '0'.
GPIO
For write operations, the GPIO pin operates as an output. Writing a '1' to the GPIO bit sets the GPIO pin to high
impedance, and writing a '0' sets the GPIO pin to logic low. An external pull-up resistor is required when using
the GPIO pin as an output.
For read operations, the GPIO pin operates as an input. Read the GPIO bit to receive the status of the GPIO
pin. Reading a '0' indicates that the GPIO pin is low, and reading a '1' indicates that the GPIO pin is high.
After power-on reset, or any forced hardware or software reset, the GPIO bit is set to '1', and is in a
high-impedance state.
Busy Flag Register (read-only). Default = 0000h.
Busy flag bit of DAC-x. The Busy Flag Register Each channel has an individual busy flag (BF-x) in the Busy Flag
register. When the channel is accessed and the correction engine is enabled, the respective BF-x bit is set if
either the Input Data Register, Zero Register, or Gain Register are written to. When the DAC data is adjusted by
the correction engine and transferred into the DAC Data Register, the BF-x bit is cleared. It takes approximately
500ns per channel for the correction to complete.
(1)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BF-7
BF-6
BF-5
BF-4
BF-3
BF-2
BF-1
BF-0
X (1)
X
X
X
X
X
X = don't care. Writing to this bit has no effect; reading the bit returns '0'.
BF-7:0
BF-x = '1' if the input data of DAC-x has not been corrected or if the correction engine is not finished.
BF-x = '0' when the input data has been corrected or the correction engine is turned off.
46
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SBAS462A – JUNE 2009 – REVISED NOVEMBER 2009
APPLICATION INFORMATION
PRECISION VOLTAGE REFERENCE SELECTION
To achieve the optimum performance from the DAC8228 over the full operating temperature range, a precision
voltage reference must be used. Careful consideration should be given to the selection of a precision voltage
reference. The DAC8228 has two reference inputs, REF-A and REF-B. The voltages applied to the reference
inputs are used to provide a buffered positive reference for the DAC cores. Therefore, any error in the voltage
reference is reflected in the outputs of the device. There are four possible sources of error to consider when
choosing a voltage reference for high-accuracy applications: initial accuracy, temperature coefficient of the output
voltage, long-term drift, and output voltage noise. Initial accuracy error on the output voltage of an external
reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low
initial accuracy error specification is preferred. Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight, long-term drift specification ensures that the overall solution
remains relatively stable over its entire lifetime. The temperature coefficient of a reference output voltage affects
the output drift when the temperature changes. Choose a reference with a tight temperature coefficient
specification to reduce the dependence of the DAC output voltage on ambient conditions. In high-accuracy
applications, which have a relatively low noise budget, the reference output voltage noise also must be
considered. Choosing a reference with as low an output noise voltage as practical for the required system
resolution is important. Precision voltage references such as TI's REF50xx (2V to 5V) and REF32xx (1.25V to
4V) provide a low-drift, high-accuracy reference voltage.
POWER-SUPPLY NOISE
The DAC8228 must have ample supply bypassing of 1μF to 10μF in parallel with 0.1μF on each supply, located
as close to the package as possible; ideally, immediately next to the device. The 1μF to 10μF capacitors must be
the tantalum-bead type. The 0.1μF capacitor must have low effective series resistance (ESR) and low effective
series inductance (ESI), such as common ceramic types, which provide a low-impedance path to ground at high
frequencies to handle transient currents because of internal logic switching. The power-supply lines must be as
large a trace as possible to provide low-impedance paths and reduce the effects of glitches on the power-supply
line. Apart from these considerations, the wideband noise on the AVDD, AVSS, DVDD and IOVDD supplies should
be filtered before feeding to the DAC to obtain the best possible noise performance.
LAYOUT
Precision analog circuits require careful layout, adequate bypassing, and a clean, well-regulated power supply to
obtain the best possible dc and ac performance. Careful consideration of the power-supply and ground-return
layout helps to meet the rated performance. DGND is the return path for digital currents and AGND is the power
ground for the DAC. For the best ac performance, care should be taken to connect DGND and AGND with very
low resistance back to the supply ground. The printed circuit board (PCB) must be designed so that the analog
and digital sections are separated and confined to certain areas of the board. If multiple devices require an
AGND-to-DGND connection, the connection is to be made at one point only. The star ground point is established
as close as possible to the device.
The power-supply lines must be as large a trace as possible to provide low impedance paths and reduce the
effects of glitches on the power-supply line. Fast switching signals must never be run near the reference inputs. It
is essential to minimize noise on the reference inputs because it couples through to the DAC output. Avoid
crossover of digital and analog signals. Traces on opposite sides of the board must run at right angles to each
other. This configuration reduces the effects of feedthrough on the board. A microstrip technique may be
considered, but is not always possible with a double-sided board. In this technique, the component side of the
board is dedicated to the ground plane, and signal traces are placed on the solder-side.
Each DAC group has a ground pin, AGND-x, which is the ground of the output from the DACs in the group. It
must be connected directly to the corresponding reference ground in low-impedance paths to get the best
performance. AGND-A must be connected with REFGND-A and AGND-B must be connected with REFGND-B.
AGND-A and AGND-B must be tied together and connected to the analog power ground and DGND.
During single-supply operation, the OFFSET-x pins must be connected to AGND-x with a low-impedance path
because these pins carry DAC-code-dependent current. Any resistance from OFFSET-x to AGND-x causes a
voltage drop by this code-dependent current. Therefore, it is very important to minimize routing resistance to
AGND-x or to any ground plane that AGND-x is connected to.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DAC8228SPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 105
DAC8228
DAC8228SPAGR
ACTIVE
TQFP
PAG
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 105
DAC8228
DAC8228SRTQR
ACTIVE
QFN
RTQ
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
DAC8228
DAC8228SRTQT
ACTIVE
QFN
RTQ
56
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
DAC8228
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC8228SPAGR
TQFP
PAG
64
1500
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
DAC8228SRTQR
QFN
RTQ
56
2000
330.0
16.4
8.3
8.3
2.25
12.0
16.0
Q2
DAC8228SRTQT
QFN
RTQ
56
250
180.0
16.4
8.3
8.3
2.25
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Mar-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8228SPAGR
TQFP
PAG
64
1500
367.0
367.0
45.0
DAC8228SRTQR
QFN
RTQ
56
2000
336.6
336.6
28.6
DAC8228SRTQT
QFN
RTQ
56
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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