Maxim MAX5510 1.8v to 5.5v, ultra-low-power, 8-bit, voltage-output dac Datasheet

19-3120; Rev 0; 1/04
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
The MAX5510/MAX5511 are single, 8-bit, ultra-lowpower, voltage-output, digital-to-analog converters
(DACs) offering Rail-to-Rail® buffered voltage outputs.
The DACs operate from a 1.8V to 5.5V supply and consume less than 6µA, making them desirable for lowpower and low-voltage applications. A shutdown mode
reduces overall current, including the reference input
current, to just 0.18µA. The MAX5510/MAX5511 use a
3-wire serial interface that is compatible with SPI™,
QSPI™, and MICROWIRE™.
At power-up, the MAX5510/MAX5511 outputs are driven to zero scale, providing additional safety for applications that drive valves or for other transducers that
must be off during power-up. The zero-scale outputs
enable glitch-free power-up.
The MAX5510 accepts an external reference input. The
MAX5511 contains an internal reference and provides
an external reference output. Both devices have forcesense-configured output buffers.
The MAX5510/MAX5511 are available in a 4mm x 4mm
x 0.8mm, 12-pin, thin QFN package and are guaranteed
over the extended -40°C to +85°C temperature range.
For 12-bit compatible devices, refer to the MAX5530/
MAX5531 data sheet. For 10-bit compatible devices,
refer to the MAX5520/MAX5521 data sheet.
Applications
Features
♦ Single +1.8V to +5.5V Supply
♦ Ultra-Low 6µA Supply Current
♦ Shutdown Mode Reduces Supply Current to
0.18µA (max)
♦ Small 4mm x 4mm x 0.8mm Thin QFN Package
♦ Flexible Force-Sense-Configured Rail-to-Rail
Output Buffers
♦ Internal Reference Sources 8mA of Current
(MAX5511)
♦ Fast 16MHz 3-Wire SPI-/QSPI-/MICROWIRECompatible Serial Interface
♦ TTL- and CMOS-Compatible Digital Inputs
with Hysteresis
♦ Glitch-Free Outputs During Power-Up
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX5510ETC
PART
-40°C to +85°C
12 Thin QFN-EP*
MAX5511ETC
-40°C to +85°C
12 Thin QFN-EP*
*EP = Exposed paddle (internally connected to GND).
Portable Battery-Powered Devices
Instrumentation
Pin Configuration
Automatic Trimming and Calibration in Factory
or Field
Programmable Voltage and Current Sources
TOP VIEW
Industrial Process Control and Remote
Industrial Devices
Remote Data Conversion and Monitoring
CS
1
Programmable Liquid Crystal Display (LCD) Bias
SCLK
2
Selector Guide
DIN
3
FB
N.C.
OUT
12
11
10
9
GND
8
VDD
7
N.C.
Chemical Sensor Cell Bias for Gas Monitors
PART
REFERENCE
TOP MARK
MAX5510ETC
External
AACO
MAX5511ETC
Internal
AACP
MAX5510
MAX5511
4
5
REFIN (MAX5510) N.C.
REFOUT(MAX5511)
6
N.C.
THIN QFN
Rail-to-Rail is a registered trademark of Nippon Motorola, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5510/MAX5511
General Description
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
OUT to GND ...............................................-0.3V to (VDD + 0.3V)
FB to GND ..................................................-0.3V to (VDD + 0.3V)
SCLK, DIN, CS to GND ..............................-0.3V to (VDD + 0.3V)
REFIN, REFOUT to GND ............................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
Thin QFN (derate 16.9mW/°C above +70°C).............1349mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ..................................................... +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +1.8V to +5.5V, OUT unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
STATIC ACCURACY (MAX5510 EXTERNAL REFERENCE)
Resolution
N
Integral Nonlinearity (Note 1)
Differential Nonlinearity (Note 1)
Offset Error (Note 2)
INL
DNL
VOS
MIN
±0.25
±1
VDD = 1.8V, VREF = 1.024V
±0.25
±1
Guaranteed monotonic,
VDD = 5V, VREF = 4.096V
±0.2
±1
Guaranteed monotonic,
VDD = 1.8V, VREF = 1.024V
±0.2
PSRR
LSB
LSB
±1
VDD = 5V, VREF = 4.096V
±1
±20
VDD = 1.8V, VREF = 1.024V
±1
±20
VDD = 5V, VREF = 4.096V
±0.5
±1
VDD = 1.8V, VREF = 1.024V
±0.5
±1
1.8V ≤ VDD ≤ 5.5V
mV
µV/°C
±2
GE
UNITS
Bits
VDD = 5V, VREF = 4.096V
Gain-Error Temperature
Coefficient
Power-Supply Rejection Ratio
MAX
8
Offset-Error Temperature Drift
Gain Error (Note 3)
TYP
LSB
±4
ppm/°C
85
dB
STATIC ACCURACY (MAX5511 INTERNAL REFERENCE)
Resolution
Integral Nonlinearity (Note 1)
Differential Nonlinearity (Note 1)
Offset Error (Note 2)
N
INL
DNL
VOS
8
VDD = 5V, VREF = 3.9V
±0.25
±1
VDD = 1.8V, VREF = 1.2V
±0.25
±1
Guaranteed monotonic,
VDD = 5V, VREF = 3.9V
±0.2
±1
Guaranteed monotonic,
VDD = 1.8V, VREF = 1.2V
±0.2
Gain-Error Temperature
Coefficient
2
±1
±1
±20
VDD = 1.8V, VREF = 1.2V
±1
±20
VDD = 5V, VREF = 3.9V
±0.5
±1
VDD = 1.8V, VREF = 1.2V
±0.5
±1
±4
_______________________________________________________________________________________
mV
µV/°C
±2
GE
LSB
LSB
VDD = 5V, VREF = 3.9V
Offset-Error Temperature Drift
Gain Error (Note 3)
Bits
LSB
ppm/°C
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
(VDD = +1.8V to +5.5V, OUT unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Power-Supply Rejection Ratio
SYMBOL
PSRR
CONDITIONS
MIN
1.8V ≤ VDD ≤ 5.5V
TYP
MAX
85
UNITS
dB
REFERENCE INPUT (MAX5510)
Reference-Input Voltage Range
Reference-Input Impedance
VREFIN
RREFIN
0
Normal operation
VDD
4.1
In shutdown
V
MΩ
2.5
GΩ
REFERENCE OUTPUT (MAX5511)
Initial Accuracy
VREFOUT
Output-Voltage Temperature
Coefficient
VTEMPCO
Line Regulation
Load Regulation
Output Noise Voltage
Short-Circuit Current (Note 6)
No external load, VDD = 1.8V
1.197
1.214
1.231
No external load, VDD = 2.5V
1.913
1.940
1.967
No external load, VDD = 3V
2.391
2.425
2.459
No external load, VDD = 5V
3.828
3.885
3.941
TA = -40°C to +85°C (Note 4)
12
30
ppm/°C
VREFOUT < VDD - 200mV (Note 5)
2
200
µV/V
0 ≤ IREFOUT ≤ 1mA, sourcing, VDD = 1.8V,
VREF = 1.2V
0.3
2
0 ≤ IREFOUT ≤ 8mA, sourcing, VDD = 5V,
VREF = 3.9V
0.3
2
-150µA ≤ IREFOUT ≤ 0, sinking
0.2
0.1Hz to 10Hz, VREFOUT = 3.9V
150
10Hz to 10kHz, VREFOUT = 3.9V
600
0.1Hz to 10Hz, VREFOUT = 1.2V
50
10Hz to 10kHz, VREFOUT = 1.2V
450
VDD = 5V
30
VDD = 1.8V
14
V
µV/µA
µVP-P
mA
Capacitive Load Stability Range
(Note 7)
0 to 10
nF
Thermal Hysteresis
(Note 8)
200
ppm
Reference Power-Up Time (from
Shutdown)
REFOUT unloaded, VDD = 5V
5.4
REFOUT unloaded, VDD = 1.8V
4.4
Long-Term Stability
ms
200
ppm/
1khrs
1000
pF
DAC OUTPUT (OUT)
Capacitive Driving Capability
Short-Circuit Current (Note 6)
CL
VDD = 5V, VOUT set to full scale, OUT
shorted to GND, source current
65
VDD = 5V, VOUT set to 0V, OUT shorted to
VDD, sink current
65
VDD = 1.8V, VOUT set to full scale, OUT
shorted to GND, source current
14
VDD = 1.8V, VOUT set to 0V, OUT shorted to
VDD, sink current
14
mA
_______________________________________________________________________________________
3
MAX5510/MAX5511
ELECTRICAL CHARACTERISTICS (continued)
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.8V to +5.5V, OUT unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
TYP
Coming out of shutdown
(MAX5510)
VDD = 5V
VDD = 1.8V
3.8
Coming out of standby
(MAX5511)
VDD = 1.8V
to 5.5V
0.4
DAC Power-Up Time
Output Power-Up Glitch
MIN
MAX
UNITS
3
CL = 100pF
FB_ Input Current
ms
10
mV
10
pA
DIGITAL INPUTS (SCLK, DIN, CS)
Input High Voltage
VIH
4.5V ≤ VDD ≤ 5.5V
2.4
2.7V < VDD ≤ 3.6V
2.0
1.8V ≤ VDD ≤ 2.7V
Input Low Voltage
VIL
4.5V ≤ VDD ≤ 5.5V
2.7V < VDD ≤ 3.6V
1.8V ≤ VDD ≤ 2.7V
Input Leakage Current
IIN
(Note 9)
Input Capacitance
CIN
V
0.7 x VDD
0.8
0.6
0.3 x VDD
±0.05
±0.5
V
µA
10
pF
Positive and negative (Note 10)
10
V/ms
0.1 to 0.9 of full scale to within 0.5 LSB
(Note 10)
660
µs
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
Voltage-Output Settling Time
0.1Hz to 10Hz
Output Noise Voltage
10Hz to 10kHz
VDD = 5V
80
VDD = 1.8V
55
VDD = 5V
620
VDD = 1.8V
476
µVP-P
POWER REQUIREMENTS
Supply Voltage Range
VDD
1.8
MAX5510
Supply Current (Note 9)
IDD
MAX5511
Standby Supply Current
IDDSD
(Note 9)
Shutdown Supply Current
IDDPD
(Note 9)
2.6
4
VDD = 3V
2.6
4
VDD = 1.8V
3.6
5
VDD = 5V
5.3
6.5
VDD = 3V
4.8
6.0
VDD = 1.8V
5.4
7.0
VDD = 5V
3.3
4.0
VDD = 3V
2.8
3.4
VDD = 1.8V
4
5.5
VDD = 5V
2.4
3.0
0.05
0.18
_______________________________________________________________________________________
V
µA
µA
µA
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
16.7
MHz
TIMING CHARACTERISTICS (VDD = 4.5V TO 5.5V)
Serial Clock Frequency
fSCLK
0
DIN to SCLK Rise Setup Time
tDS
15
ns
DIN to SCLK Rise Hold Time
tDH
0
ns
SCLK Pulse-Width High
tCH
24
ns
SCLK Pulse-Width Low
tCL
24
ns
CS Pulse-Width High
tCSW
100
ns
SCLK Rise to CS Rise Hold Time
tCSH
0
ns
CS Fall to SCLK Rise Setup Time
tCSS
20
ns
SCLK Fall to CS Fall Setup
tCSO
0
ns
CS Rise to SCK Rise Hold Time
tCS1
20
ns
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
MHz
TIMING CHARACTERISTICS (VDD = 1.8V TO 5.5V)
Serial Clock Frequency
fSCLK
0
DIN to SCLK Rise Setup Time
tDS
24
DIN to SCLK Rise Hold Time
tDH
0
ns
SCLK Pulse-Width High
tCH
40
ns
SCLK Pulse-Width Low
tCL
40
ns
CS Pulse-Width High
tCSW
150
ns
SCLK Rise to CS Rise Hold Time
tCSH
0
ns
CS Fall to SCLK Rise Setup Time
tCSS
30
ns
SCLK Fall to CS Fall Setup
tCSO
0
ns
CS Rise to SCK Rise Hold Time
tCS1
30
ns
ns
Note 1: Linearity is tested within codes 6 to 255.
Note 2: Offset is tested at code 6.
Note 3: Gain is tested at code 250. FB is connected to OUT.
Note 4: Guaranteed by design. Not production tested.
Note 5: VDD must be a minimum of 1.8V.
Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that the package power dissipation is not exceeded.
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN.
Note 9: All digital inputs at VDD or GND.
Note 10: Load = 10kΩ in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5510) or VREF = 3.9V (MAX5511).
_______________________________________________________________________________________
5
MAX5510/MAX5511
TIMING CHARACTERISTICS
Typical Operating Characteristics
(VDD = 5.0V, VREF = 4.096V (MAX5510) or VREF = 3.9V (MAX5511), TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5511)
6
5
4
3
7
6
5
4
3
2
2
1
1
0
35
60
-40
85
-15
10
35
60
SUPPLY CURRENT
vs. LOGIC INPUT VOLTAGE
CS = LOGIC LOW
CODE = 0
VREF = 1.2V
1.5
VDD = 5V
100
10
VDD = 1.8V
ALL DIGITAL INPUTS
SHORTED TOGETHER
4.5
4.0
SUPPLY CURRENT (mA)
SUPPLY CURRENT (µA)
VREF = 1.9V
5.0
MAX5510 toc05
1000
MAX5510 toc04
85
3.5
3.0
2.5
2.0
1.5
1.0
1.0
0.5
0.5
0
1
0
-15
10
35
60
0.01
85
0.1
1
10
100
0
1000 10000 100000
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE (°C)
FREQUENCY (kHz)
LOGIC INPUT VOLTAGE (V)
INL vs. INPUT CODE
(VDD = VREF = 1.8V)
INL vs. INPUT CODE
(VDD = VREF = 5V)
DNL vs. INPUT CODE
(VDD = VREF = 1.8V)
0.10
MAX5510 toc07
0.05
0.05
0
-0.05
-0.05
INL (LSB)
0
-0.10
0.014
0.012
0.010
0.008
DNL (LSB)
0.10
MAX5510 toc08
-40
MAX5510 toc09
STANDBY SUPPLY CURRENT (µA)
10
SUPPLY CURRENT
vs. CLOCK FREQUENCY
2.5
2.0
-15
STANDBY SUPPLY CURRENT
vs. TEMPERATURE (MAX5511)
VREF = 2.4V
3.0
-40
TEMPERATURE (°C)
VREF = 3.9V
3.5
1
TEMPERATURE (°C)
VDD = 5V
4.0
10
SUPPLY VOLTAGE (V)
5.0
4.5
100
0.1
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
MAX5510 toc03
8
MAX5510 toc06
7
1000
SHUTDOWN SUPPLY CURRENT (nA)
9
SUPPLY CURRENT (µA)
8
SUPPLY CURRENT (µA)
10
MAX5510 toc02
9
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5511)
SUPPLY CURRENT vs. TEMPERATURE
(MAX5511)
MAX5510 toc01
10
INL (LSB)
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
-0.10
0.006
0.004
0.002
-0.15
-0.15
-0.20
-0.20
-0.25
-0.25
-0.004
-0.30
-0.30
-0.006
0
0
50
100
150
200
DIGITAL INPUT CODE
6
250
300
-0.002
0
50
100
150
200
DIGITAL INPUT CODE
250
300
0
50
100
150
200
DIGITAL INPUT CODE
_______________________________________________________________________________________
250
300
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
OFFSET VOLTAGE
vs. TEMPERATURE
0.01
0
-0.01
MAX5510 toc11
0.025
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.02
-0.03
50
100
150
200
250
0
-0.005
-0.010
-0.020
-1.0
-0.025
-40
300
-15
10
35
60
85
-40
-15
10
35
85
60
TEMPERATURE (°C)
TEMPERATURE (°C)
DIGITAL FEEDTHROUGH RESPONSE
(DAC OUTPUT SET TO 0)
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
DIN
5V/div
VDD = 1.8V
DAC CODE = MIDSCALE
VREF = 1.2V
0.6046
0.6044
0.6042
OUT
50mV/div
DAC OUTPUT CURRENT (µA)
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
3
VDD = 5V
2
VDD = 3V
VDD = 1.8V
1
0.1
1.9415
1.9410
1.9400
-10 -8
-6
-4
-2
0
2
4
6
8
4.0
3.5
OUTPUT LARGE-SIGNAL STEP RESPONSE
(VDD = 1.8V, VREF = 1.219V)
VDD = 5V
3.0
2.5
10
MAX5510 toc17
4.5
VREF = VDD
CODE = MIDSCALE
VOUT
200mV/div
VDD = 3V
2.0
1.5
1.0
0.5
0.01
1.9420
MAX5510 toc18
5.0
DAC OUTPUT VOLTAGE (V)
4
1.9425
DAC OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX5510 toc16
VREF = VDD
CODE = MIDSCALE
1.9430
VDD = 5.0V
DAC CODE = MIDSCALE
VREF = 3.9V
1.9405
0.6040
-1000-800 -600 -400 -200 0 200 400 600 800 1000
20µs/div
1.9435
MAX5510 toc15
DAC OUTPUT VOLTAGE (V)
SCLK
5V/div
0.6048
1.9440
MAX5510 toc14
0.6050
CS
5V/div
OUTPUT VOLTAGE (V)
0.005
DIGITAL INPUT CODE
MAX5510 toc13
0
0.001
0.010
-0.015
ZERO SCALE
5
0.015
-0.8
DAC OUTPUT VOLTAGE (V)
0
VDD = 5V
VREF = 3.9V
0.020
GAIN-ERROR CHANGE (LSB)
0.02
VDD = 5V
VREF = 3.9V
0.8
OFFSET VOLTAGE (mV)
0.03
DNL (LSB)
1.0
MAX5510 toc10
0.04
GAIN-ERROR CHANGE
vs. TEMPERATURE
MAX5510 toc12
DNL vs. INPUT CODE
(VDD = VREF = 5V)
1
10
OUTPUT SOURCE CURRENT (mA)
100
MAX5510/MAX5511
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5510) or VREF = 3.9V (MAX5511), TA = +25°C, unless otherwise noted.)
0
0.001
VDD = 1.8V
0.01
0.1
1
10
100
100µs/div
OUTPUT SINK CURRENT (mA)
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5510) or VREF = 3.9V (MAX5511), TA = +25°C, unless otherwise noted.)
OUTPUT LARGE-SIGNAL STEP RESPONSE
(VDD = 5V, VREF = 3.9V)
OUTPUT MINIMUM SERIES RESISTANCE
vs. LOAD CAPACITANCE
MAX5510 toc19
MAX5510 toc20
FOR NO OVERSHOOT
VOUT
500mV/div
500
VDD
2V/div
400
300
200
VOUT
10mV/div
100
0
0.0001 0.001
200µs/div
POWER-UP OUTPUT VOLTAGE GLITCH
MAX5510 toc21
600
MINIMUM SERIES RESISTANCE (Ω)
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
0.01
0.1
1
10
100
20ms/div
CAPACITANCE (µF)
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX5510 toc23
3.940
VOUT
AC-COUPLED
5mV/div
REFERENCE OUTPUT VOLTAGE (V)
VDD = 5V
3.935
3.930
3.925
3.920
3.915
3.910
3.905
3.900
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
3.91
3.90
3.89
1.21748
1.218
1.217
1.216
1.215
10
35
60
85
-500
1500
3500
REFERENCE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
REFERENCE LINE-TRANSIENT RESPONSE
(VREF = 1.2V)
NO LOAD
MAX5510 toc27
1.21746
2.8V
VDD
1.21744
1.21742
1.8V
1.21740
VREF
500mV/div
1.21738
1.21736
1.21734
1.21730
-500
2000
4500
7000
9500 12,000 14,500
REFERENCE OUTPUT CURRENT (µA)
8
7500
REFERENCE OUTPUT CURRENT (µA)
1.21732
3.88
5500
TEMPERATURE (°C)
MAX5510 toc26
REFERENCE OUTPUT VOLTAGE (V)
VDD = 5V
-15
1.21750
REFERENCE OUTPUT VOLTAGE (V)
MAX5510 toc25
3.92
VDD = 1.8V
1.219
1.214
-40
100µs/div
1.220
REFERENCE OUTPUT VOLTAGE (V)
MAX5510 toc22
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
MAX5510 toc24
MAJOR CARRY OUTPUT VOLTAGE GLITCH
(CODE 7FFh TO 800h)
(VDD = 5V, VREF = 3.9V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
100µs/div
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
REFERENCE LINE-TRANSIENT RESPONSE
(VREF = 3.9V)
REFERENCE LOAD TRANSIENT
(VDD = 1.8V)
MAX5510 toc28
REFERENCE LOAD TRANSIENT
(VDD = 5V)
MAX5510 toc29
MAX5510 toc30
5.5V
VDD
REFOUT
SOURCE
CURRENT
0.5mA/div
REFOUT
SOURCE
CURRENT
0.5mA/div
4.5V
VREF
500mV/div
VREFOUT
500mV/div
3.9V
VREFOUT
500mV/div
3.9V
100µs/div
200µs/div
200µs/div
REFERENCE LOAD TRANSIENT
(VDD = 1.8V)
REFERENCE LOAD TRANSIENT
(VDD = 5V)
REFERENCE PSRR
vs. FREQUENCY
MAX5510 toc32
REFOUT
SINK
CURRENT
50µA/div
REFOUT
SINK
CURRENT
100µA/div
VREFOUT
500mV/div
VREFOUT
500mV/div
3.9V
MAX5510 toc33
80
POWER-SUPPLY REJECTION RATIO (dB)
MAX5510 toc31
VDD = 1.8V
70
MAX5510/MAX5511
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5510) or VREF = 3.9V (MAX5511), TA = +25°C, unless otherwise noted.)
60
50
40
30
20
10
0
200µs/div
0.01
200µs/div
0.1
1
10
100
1000
FREQUENCY (kHz)
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (VDD = 1.8V, VREF = 1.2V)
REFERENCE PSRR
vs. FREQUENCY
MAX5510 toc35
VDD = 5V
70
MAX5510 toc36
MAX5510 toc34
80
POWER-SUPPLY REJECTION RATIO (dB)
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (VDD = 5V, VREF = 3.9V)
60
50
40
100µV/div
100µV/div
30
20
10
0
0.01
0.1
1
10
FREQUENCY (kHz)
100
1000
1s/div
1s/div
_______________________________________________________________________________________
9
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
Pin Description
PIN
NAME
MAX5510
MAX5511
1
1
CS
2
2
SCLK
3
3
DIN
4
—
REFIN
FUNCTION
Active-Low Digital-Input Chip Select
Serial-Interface Clock
Serial-Interface Data Input
Reference Input
—
4
REFOUT
5, 6, 7, 11
5, 6, 7, 11
N.C.
No Connection. Leave N.C. inputs unconnected (floating), or connect to GND.
Reference Output
8
8
VDD
Power Input. Connect VDD to a 1.8V to 5.5V power supply. Bypass VDD to GND with a
0.1µF capacitor.
9
9
GND
Ground
10
10
OUT
Analog Voltage Output
12
12
FB
EP
Exposed
Paddle
EP
Feedback Input
Exposed Paddle. Connect EP to GND.
MAX5510 Functional Diagram
VDD
REFIN
POWERDOWN
CONTROL
DAC
REGISTER
INPUT
REGISTER
SCLK
DIN
CS
CONTROL
LOGIC
AND
SHIFT
REGISTER
8-BIT DAC
OUT
MAX5510
FB
GND
10
______________________________________________________________________________________
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
VDD
POWERDOWN
CONTROL
2-BIT
PROGRAMMABLE
REFERENCE
INPUT
REGISTER
SCLK
DIN
CS
REF
BUF
DAC
REGISTER
CONTROL
LOGIC
AND
SHIFT
REGISTER
REFOUT
8-BIT DAC
OUT
MAX5511
FB
GND
Detailed Description
The MAX5510/MAX5511 single, 8-bit, ultra-low-power,
voltage-output DACs offer Rail-to-Rail buffered voltage
outputs. The DACs operate from a 1.8V to 5.5V supply
and require only 6µA (max) supply current. These
devices feature a shutdown mode that reduces overall
current, including the reference input current, to just
0.18µA. The MAX5511 includes an internal reference
that saves additional board space and can source up
to 8mA, making it functional as a system reference. The
16MHz, 3-wire serial interface is compatible with SPI,
QSPI, and MICROWIRE protocols. When V DD is
applied, all DAC outputs are driven to zero scale with
virtually no output glitch. The MAX5510/MAX5511 output buffers are configured in force sense allowing users
to externally set voltage gains on the output (an outputamplifier inverting input is available). These devices
come in a 4mm x 4mm thin QFN package.
Digital Interface
The MAX5510/MAX5511 use a 3-wire serial interface
compatible with SPI, QSPI, and MICROWIRE protocols
(Figures 1 and 2).
The MAX5510/MAX5511 include a single, 16-bit, input
shift register. Data loads into the shift register through
the serial interface. CS must remain low until all 16 bits
are clocked in. Data loads MSB first, D9–D0. The 16
bits consist of 4 control bits (C3–C0), 8 data bits
(D7–D0), and 4 sub-bits. (see Table 1). D7–D0 are the
DAC data bits and S3–S0 are the sub-bits. The sub-bits
must be set to zero for proper operation. The control
bits C3–C0 control the MAX5510/MAX5511, as outlined
in Table 2.
Each DAC channel includes two registers: an input register and a DAC register. The input register holds input
data. The DAC register contains the data updated to
the DAC output.
The double-buffered register configuration allows any
of the following:
• Loading the input registers without updating the DAC
registers
• Updating the DAC registers from the input registers
• Updating all the input and DAC registers simultaneously
______________________________________________________________________________________
11
MAX5510/MAX5511
MAX5511 Functional Diagram
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
Table 1. Serial Write Data Format
CONTROL
DATA BITS
MSB
C3
LSB
C2
C1
C0
D7
D6
D5
D4
D3
D2
D1
D0
S3
S2
S1
Sub-bits S3—S0 must be set to zero for proper operation.
tCH
SCLK
tCL
tDS
C3
DIN
tCS0
C2
C1
S0
tDH
tCSS
tCSH
CS
tCSW
tCS1
Figure 1. Timing Diagram
SCLK
DIN
1
C3
2
C2
3
C1
CONTROL BITS
4
C0
5
D7
6
D6
7
D5
8
D4
9
D3
DATA BITS
10
D2
11
D1
12
D0
13
S3
14
S2
15
S1
S0
SUB-BITS
CS
Figure 2. Register Loading Diagram
12
16
______________________________________________________________________________________
COMMAND
EXECUTED
S0
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
CONTROL BITS
INPUT DATA
SUB-BITS
FUNCTION
C3
C2
C1
C0
D7–D0
S3–S0
0
0
0
0
XXXXXXXX
0000
No operation; command is ignored.
0
0
0
1
8-bit data
0000
Load input register from shift register; DAC register
unchanged; DAC output unchanged.
0
0
1
0
—
—
Command reserved; do not use.
0
0
1
1
—
—
Command reserved; do not use.
0
1
0
0
—
—
Command reserved; do not use.
0
1
0
1
—
—
Command reserved; do not use.
0
1
1
0
—
—
Command reserved; do not use.
0
1
1
1
—
—
Command reserved; do not use.
1
0
0
0
8-bit data
MAX5510/MAX5511
Table 2. Serial-Interface Programming Commands
0000
Load DAC register from input register; DAC output
updated; MAX5510 enters normal operation if in
shutdown; MAX5511 enters normal operation if in
standby or shutdown.
Load input register and DAC register from shift register;
DAC output updated; MAX5510 enters normal operation
if in shutdown; MAX5511 enters normal operation if in
standby or shutdown.
1
0
0
1
8-bit data
0000
1
0
1
0
—
—
Command reserved; do not use.
1
0
1
1
—
—
Command reserved; do not use.
1
1
0
0
D7, D6,
XXXXXX
0000
MAX5510 enters shutdown; MAX5511 enters standby*.
For the MAX5511, D7 and D6 configure the internal
reference voltage (Table 3).
0000
MAX5510/MAX5511 enter normal operation; DAC output
reflects existing contents of DAC register. For the
MAX5511, D7 and D6 configure the internal reference
voltage (Table 3).
0000
MAX5510/MAX5511 enter shutdown; DAC output set to
high impedance. For the MAX5511, D7 and D6 configure
the internal reference voltage (Table 3).
0000
Load input register and DAC register from shift register;
DAC output updated; MAX5510 enters normal operation
if in shutdown; MAX5511 enters normal operation if in
standby or shutdown.
1
1
0
1
D7, D6,
XXXXXX
1
1
1
0
D7, D6,
XXXXXX
1
1
1
1
8-bit data
X = Don’t care.
*Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown.
______________________________________________________________________________________
13
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
Power Modes
The MAX5510/MAX5511 feature two power modes to
conserve power during idle periods. In normal operation, the device is fully operational. In shutdown mode,
the device is completely powered down, including the
internal voltage reference in the MAX5511. The
MAX5511 also offers a standby mode where all circuitry
is powered down except the internal voltage reference.
Standby mode keeps the reference powered up while
the remaining circuitry is shut down, allowing it to be
used as a system reference. Standby mode also helps
reduce the wake-up delay by not requiring the reference to power up when returning to normal operation.
Shutdown Mode
The MAX5510/MAX5511 feature a software-programmable shutdown mode that reduces the typical supply
current and the reference input current to 0.18µA
(max). Writing an input control word with control bits
C[3:0] = 1110 places the device in shutdown mode
(Table 2). In shutdown, the MAX5510 reference input
and DAC output buffers go high impedance. Placing
the MAX5511 into shutdown turns off the internal reference, and the DAC output buffers go high impedance.
The serial interface remains active for all devices.
Table 2 shows several commands that bring the
MAX5510/MAX5511 back to normal operation. The
power-up time from shutdown is required before the
DAC outputs are valid.
Note: For the MAX5511, standby mode cannot be
entered directly from shutdown mode. The device must
be brought into normal operation before entering standby mode.
Standby Mode (MAX5511 Only)
The MAX5511 features a software-programmable
standby mode that reduces the typical supply current
to 6µA. Standby mode powers down all circuitry except
the internal voltage reference. Place the device in
standby mode by writing an input control word with
control bits C[3:0] = 1100 (Table 2). The internal reference and serial interface remain active while the DAC
output buffers go high impedance. If the MAX5511 is
coming out of standby, the power-up time from standby
is required before the DAC outputs are valid.
directly from shutdown mode. The device must be
brought into normal operation before entering standby
mode. To enter standby from shutdown, issue the command to return to normal operation, followed immediately by the command to go into standby.
Table 2 shows several commands that bring the MAX5511
back to normal operation. When transitioning from standby
mode to normal operation, only the DAC power-up time is
required before the DAC outputs are valid.
Reference Input
The MAX5510 accepts a reference with a voltage range
extending from 0 to VDD. The output voltage (VOUT) is
represented by a digitally programmable voltage
source as:
VOUT = (VREF x N / 256) x gain
where N is the numeric value of the DAC’s binary input
code (0 to 255), VREF is the reference voltage and gain
is the externally set voltage gain for the MAX5510/
MAX5511.
In shutdown mode, the reference input enters a highimpedance state with an input impedance of 2.5GΩ (typ).
Reference Output
The MAX5511 internal voltage reference is software
configurable to one of four voltages. Upon power-up,
the default reference voltage is 1.214V. Configure the
reference voltage using the D6 and D7 data bits (Table
3) when the control bits are as follows: C[3:0] = 1100,
1101, or 1110 (Table 2). VDD must be kept at a minimum of 200mV above VREF for proper operation.
Table 3. Reference Output Voltage
Programming
D7
D6
REFERENCE VOLTAGE (V)
0
0
1.214
0
1
1.940
1
0
2.425
1
1
3.885
For the MAX5511, standby mode cannot be entered
14
______________________________________________________________________________________
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
1-Cell and 2-Cell Circuit
See Figure 3 for an illustration of how to power the
MAX5510/MAX5511 with either one lithium-ion battery
or two alkaline batteries. The low current consumption
of the devices makes the MAX5510/MAX5511 ideal for
battery-powered applications.
See the circuit in Figure 5 for an illustration of how to configure the MAX5510 to bias a current-output transducer.
In Figure 5, the output voltage of the MAX5510 is a function of the voltage drop across the transducer added to
the voltage drop across the feedback resistor R.
Self-Biased Two-Electrode
Potentiostat Application
Programmable Current Source
See the circuit in Figure 4 for an illustration of how to
configure the MAX5510 as a programmable current
source for driving an LED. The MAX5510 drives a standard NPN transistor to program the current source. The
current source (I LED ) is defined in the equation in
Figure 4.
See the circuit in Figure 6 for an illustration of how to
use the MAX5511 to bias a two-electrode potentiostat
on the input of an ADC.
VDD
536kΩ
1.8V ≤ VALKALINE ≤ 3.3V
2.2V ≤ VLITHIUM ≤ 3.3V
+1.25V
REFIN
DAC
VOUT
0.1µF
0.01µF
MAX6006
(1µA, 1.25V
SHUNT
REFERENCE)
VOUT (4.88mV / LSB)
V
× NDAC
VOUT = REFIN
256
MAX5510
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
GND
Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell
V+
LED
REFIN
DAC
VOUT
ILED
REFIN
DAC
VOUT
MAX5510
2N3904
R
FB
MAX5510
FB
TRANSDUCER
V
× NDAC
ILED = REFIN
256 × R
VOUT
VOUT = VBIAS + (IT × R)
R
VBIAS
IT
V
× NDAC
VBIAS = REFIN
256
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
Figure 4. Programmable Current Source Driving an LED
Figure 5. Transimpedance Configuration for a Voltage-Biased
Current-Output Transducer
______________________________________________________________________________________
15
MAX5510/MAX5511
Voltage Biasing a Current-Output
Transducer
Applications Information
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
MAX5510/MAX5511
Unipolar Output
Figure 7 shows the MAX5510 in a unipolar output configuration with unity gain. Table 4 lists the unipolar output codes.
REF
OUT
DAC
IF
TO ADC
Bipolar Output
TO ADC
The MAX5510 output can be configured for bipolar
operation, as shown in Figure 8. The output voltage is
given by the following equation:
RF
FB
VOUT = VREF x [(NA - 128) / 128]
where NA represents the numeric value of the DAC’s
binary input code. Table 5 shows digital codes (offset
binary) and the corresponding output voltage for the
circuit in Figure 4.
WE
MAX5511
SENSOR
CE
Configurable Output Gain
BAND
GAP
REFOUT
TO ADC
CL
Figure 6. Self-Biased Two-Electrode Potentiostat Application
REFIN
DAC
The MAX5510/MAX5511 have a force-sense output,
which provides a connection directly to the inverting terminal of the output op amp, yielding the most flexibility.
The advantage of the force-sense output is that specific
gains can be set externally for a given application. The
gain error for the MAX5510/MAX5511 is specified in a
unity-gain configuration (op-amp output and inverting terminals connected), and additional gain error results from
external resistor tolerances. Another advantage of the
force-sense DAC is that it allows many useful circuits to
be created with only a few simple external components.
OUT
Table 4. Unipolar Code Table (Gain = +1)
MAX5510
FB
VOUT =
DAC CONTENTS
VREFIN × NA
256
MSB
NA IS THE DAC INPUT CODE
(0 TO 255 DECIMAL).
Figure 7. Unipolar Output Circuit
10kΩ
10kΩ
VOUT
V-
MAX5510
Figure 8. Bipolar Output Circuit
16
FB
1111
1111
0000
+VREF (255/256)
1000
0001
0000
+VREF (129/256)
1000
0000
0000
+VREF (128/256) = +VREF/2
0111
1111
0000
+VREF (127/256)
0000
0001
0000
+VREF (1/256)
0000
0000
0000
0V
DAC CONTENTS
MSB
OUT
REFIN
ANALOG OUTPUT
Table 5. Bipolar Code Table (Gain = +1)
V+
DAC
LSB
LSB
ANALOG OUTPUT
1111
1111
0000
+VREF (127/128)
1000
0001
0000
+VREF (1/128)
1000
0000
0000
0V
0111
1111
0000
-VREF (1/128)
0000
0001
0000
-VREF (127/128)
0000
0000
0000
-VREF (128/128) = -VREF
______________________________________________________________________________________
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
Power Supply and Bypassing
Considerations
Bypass the power supply with a 0.1µF capacitor to GND.
Minimize lengths to reduce lead inductance. If noise
becomes an issue, use shielding and/or ferrite beads to
increase isolation. For the thin QFN package, connect
the exposed paddle to ground.
where NA represents the numeric value of the DAC
input code.
Layout Considerations
Digital and AC transient signals coupling to GND can
create noise at the output. Use proper grounding techniques, such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are not
recommended. For optimum system performance, use
printed circuit (PC) boards. Good PC board ground layout minimizes crosstalk between DAC outputs, reference
inputs, and digital inputs. Reduce crosstalk by keeping
analog lines away from digital lines.
MAX5510
REFIN
DAC
OUT
VOUT
R2
FB
R1
Figure 9. Separate Force-Sense Outputs Create Unity and
Greater-than-Unity DAC Gains Using the Same Reference
1.8V ≤ VDD ≤ 5.5V
REFIN
DAC
VOUT
VOUT
H
CS1
MAX5510
FB
MAX5401
SOT-POT
100kΩ
W
SCLK
V
255 - NPOT
× NDAC
VOUT = REFIN
1+
256
255
(
)
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE.
5PPM/°C
RATIOMETRIC
TEMPCO
DIN
CS2
L
Figure 10. Software-Configurable Output Gain
Chip Information
TRANSISTOR COUNT: 10,688
PROCESS: BiCMOS
______________________________________________________________________________________
17
MAX5510/MAX5511
An example of a custom fixed gain using the force-sense
output of the MAX5510/MAX5511 is shown in Figure 9. In
this example R1 and R2 set the gain for VOUT.
VOUT = [(VREFIN x NA) / 256] x [1 + (R2 / R1)]
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
B
1
2
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
B
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.