ON MC10E195 5v ecl programmable delay chip Datasheet

MC10E195, MC100E195
5VECL Programmable
Delay Chip
Description
The MC10E/100E195 is a programmable delay chip (PDC)
designed primarily for clock de-skewing and timing adjustment. It
provides variable delay of a differential ECL input transition.
The delay section consists of a chain of gates organized as shown in
the logic symbol. The first two delay elements feature gates that have
been modified to have delays 1.25 and 1.5 times the basic gate delay of
approximately 80 ps. These two elements provide the E195 with a
digitally-selectable resolution of approximately 20 ps. The required
device delay is selected by the seven address inputs D[0:6], which are
latched on chip by a high signal on the latch enable (LEN) control.
Because the delay programmability of the E195 is achieved by
purely differential ECL gate delays the device will operate at
frequencies of > 1.0 GHz while maintaining over 600 mV of output
swing.
The E195 thus offers very fine resolution, at very high frequencies,
that is selectable entirely from a digital input allowing for very
accurate system clock timing.
An eighth latched input, D7, is provided for cascading multiple
PDC’s for increased programmable range. The cascade logic allows
full control of multiple PDC’s, at the expense of only a single added
line to the data bus for each additional PDC, without the need for any
external gating.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE195FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Features
•
•
•
•
•
•
•
•
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
2.0 ns Worst Case Delay Range
≈20 ps/Delay Step Resolution
>1.0 GHz Bandwidth
On Chip Cascade Circuitry
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
•
•
•
•
Latchup Test
Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 368 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 10
1
Publication Order Number:
MC10E195/D
MC10E195, MC100E195
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D2
D3
D4
D5
D6
D7
NC
25
24
23
22
21
20
19
Table 1. PIN DESCRIPTION
PIN
D1
26
18
NC
D0
27
17
NC
LEN
28
16
VCC
VEE
1
15
VCCO
IN
2
14
Q
IN
3
13
Q
VBB
4
12
VCCO
MC10E195
MC100E195
NC
EN
9
10
ECL Signal Input
ECL Input Enable
ECL MUX Select Inputs
ECL Signal Output
ECL Latch Enable
ECL Min Delay Set
ECL Max Delay Set
ECL Cascade Signal
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Table 2. TRUTH TABLE
11
CASCADE
NC
8
CASCADE
7
SET MAX
6
SET MIN
5
FUNCTION
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE, CASCADE
VBB
VCC, VCCO
VEE
NC
*All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: 28-Lead PLCC
(Top View)
EN.
L
Q = IN
EN
H
Q Logic Low
LEN
L
Pass Through D[0:10]
LEN
H
Latch D[0:10]
SETMIN
L
Normal Mode
SETMIN
H
Min Delay Path
SETMAX
L
Normal Mode
SETMAX
H
Max Delay Path
VBB
11
IN
IN
EN
* 1.25
0
0
1
1
0
1
1
0
1
1
0
4 GATES
1
8 GATES
1
0
16 GATES
1
0
1
* 1.5
0
1
VEE
1
Q
Q
CASCADE
LEN
LEN
SET MIN
SET MAX
7 BIT LATCH
Q
LATCH
D
CASCADE
CASCADE
D0
* delays are 25% or 50% longer than
* standard (standard ≈ 80 ps)
D1
D2
D3
D4
D5
D6
Figure 2. Logic Diagram − Simplified
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2
D7
MC10E195, MC100E195
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
VEE
PECL Operating Range
NECL Operating Range
Tsol
Wave Solder
Pb
Pb−Free
Condition 2
VI v VCC
VI w VEE
22 to 26
°C/W
4.2 to 5.7
−5.7 to −4.2
V
V
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10E195, MC100E195
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
130
156
Min
85°C
Typ
Max
130
156
Min
Typ
Max
Unit
130
156
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
4070
4160
4020
4105
4190
4090
4185
4280
mV
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage (Single−Ended)
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage (Single−Ended)
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
VBB
Output Voltage Reference
3.62
3.74
3.65
3.75
3.69
3.81
V
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 3)
2.2
4.6
2.2
4.6
2.2
4.6
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
130
156
Min
85°C
Typ
Max
130
156
Min
Typ
Max
Unit
130
156
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 5)
−1020
−930
−840
−980
−895
−810
−910
−815
−720
mV
VOL
Output LOW Voltage (Note 5)
−1950
−1790
−1630
−1950
−1790
−1630
−1950
−1773
−1595
mV
VIH
Input HIGH Voltage (Single−Ended)
−1170
−1005
−840
−1130
−970
−810
−1060
−890
−720
mV
VIL
Input LOW Voltage (Single−Ended)
−1950
−1715
−1480
−1950
−1715
−1480
−1950
−1698
−1445
mV
VBB
Output Voltage Reference
−1.38
−1.27
−1.35
−1.25
−1.31
−1.19
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 6)
−2.8
−0.4
−2.8
−0.4
−2.8
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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4
MC10E195, MC100E195
Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 7)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
130
156
Min
85°C
Typ
Max
130
156
Min
Typ
Max
Unit
150
179
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 8)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage (Single−Ended)
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage (Single−Ended)
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
VBB
Output Voltage Reference
3.62
3.74
3.62
3.74
3.62
3.74
V
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
2.2
4.6
2.2
4.6
2.2
4.6
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 10)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
130
156
Min
85°C
Typ
Max
130
156
Min
Typ
Max
Unit
150
179
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 11)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 11)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 12)
−2.8
−0.4
−2.8
−0.4
−2.8
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
11. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
12. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC10E195, MC100E195
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 13)
0°C
Symbol
Min
Characteristic
Typ
fMAX
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay
IN to Q; Tap = 0
IN to Q; Tap = 127
EN to Q; Tap = 0
D7 to CASCADE
1210
3200
1250
300
1360
3570
1450
450
tRANGE
Programmable Range
tPD (max) − tPD (min)
2000
2175
Dt
Step Delay (Note 14)
55
115
250
505
1000
17
34
68
136
272
544
1088
D1
D0
Lin
Linearity (Note 15)
tSKEW
Duty Cycle Skew
tJITTER
Random Clock Jitter (RMS)
ts
Setup Time
th
Hold Time
tR
Release Time
tjit
Jitter
tr
tf
Output Rise/Fall Time
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
> 1.0
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
1510
3970
1650
700
105
180
325
620
1190
1240
3270
1275
300
1390
3630
1475
450
2050
2240
55
115
250
515
1030
17.5
35
70
140
280
560
1120
D1
D0
1540
4030
1675
700
105
180
325
620
1220
1440
3885
1350
300
1590
4270
1650
450
2375
2580
65
140
305
620
1240
21
42
84
168
336
672
1344
D1
D0
1765
4710
1950
700
ps
ps
ps
120
205
380
740
1450
ps
tPHL−tPLH (Note 16)
±30
±30
±30
<5
<5
<5
D to LEN
D to IN (Note 17)
EN to IN (Note 18)
200
800
200
0
200
800
200
0
200
800
200
0
LEN to D
IN to EN (Note 19)
500
0
250
500
0
250
500
0
250
EN to IN (Note 20)
SET MAX to LEN
SET MIN to LEN
300
800
800
300
800
800
<5
20−80% (Q)
20−80% (CASCADE)
Unit
GHz
125
300
225
450
125
300
ps
ps
ps
300
800
800
<5
325
650
ps
225
450
<5
325
650
125
300
225
450
ps
325
650
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
14. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
15. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for
increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions
and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the
Least Significant Bit (LSB), the device is guaranteed to be monotonic over all specified environmental conditions and process variation.
16. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
17. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
18. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75 mV to that IN/IN transition.
19. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than ±75 mV to that IN/IN transition.
20. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
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MC10E195, MC100E195
ADDRESS BUS (A0−A6)
D1
D7
D6
D5
D4
D1
D0
D0
E195
Chip #1
LEN
VEE
VCC
LEN
VCCO
VEE
E195
Chip #2
VCC
VCCO
CASCADE
VBB
CASCADE
VCCO
EN
EN
VBB
SET MAX
Q
SET MIN
Q
IN
CASCADE
IN
Q
CASCADE
Q
IN
SET MAX
IN
SET MIN
INPUT
D3
D2
D7
D6
D5
D4
D3
D2
A7
OUTPUT
VCCO
Figure 3. Cascading Interconnect Architecture
Cascading Multiple E195’s
Chip #1 on the other hand will have both SET MIN and
SET MAX de-asserted so that its delay will be controlled
entirely by the address bus A0−A6. If the delay needed is
greater than can be achieved with 31.75 gate delays
(1111111 on the A0−A6 address bus) D7 will be asserted to
signal the need to cascade the delay to the next E195 device.
When D7 is asserted the SET MIN pin of chip #2 will be
de-asserted and the delay will be controlled by the A0−A6
address bus. Chip #1 on the other hand will have its SET
MAX pin asserted resulting in the device delay to be
independent of the A0−A6 address bus.
When the SET MAX pin of chip #1 is asserted the D0 and
D1 latches will be reset while the rest of the latches will be
set. In addition, to maintain monotonicity an additional gate
delay is selected in the cascade circuitry. As a result when D7
of chip #1 is asserted the delay increases from 31.75 gates
to 32 gates. A 32 gate delay is the maximum delay setting for
the E195.
To expand this cascading scheme to more devices one
simply needs to connect the D7 input and CASCADE
outputs of the current most significant E195 to the new most
significant E195 in the same manner as pictured in Figure 3.
The only addition to the logic is the increase of one line to
the address bus for cascade control of the second PDC.
To increase the programmable range of the E195 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E195’s without the need for any
external gating. Furthermore this capability requires only
one more address line per added E195. Obviously cascading
multiple PDC’s will result in a larger programmable range
however this increase is at the expense of a longer minimum
delay.
Figure 3 illustrates the interconnect scheme for cascading
two E195’s. As can be seen, this scheme can easily be
expanded for larger E195 chains. The D7 input of the E195
is the cascade control pin. With the interconnect scheme of
Figure 3 when D7 is asserted it signals the need for a larger
programmable range than is achievable with a single device.
An expansion of the latch section of the block diagram is
pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D7
of chip #1 above is low the cascade output will also be low
while the cascade bar output will be a logical high. In this
condition the SET MIN pin of chip #2 will be asserted and
thus all of the latches of chip #2 will be reset and the device
will be set at its minimum delay. Since the RESET and SET
inputs of the latches are overriding any changes on the
A0−A6 address bus will not affect the operation of chip #2.
TO SELECT MULTIPLEXERS
BIT 0
D0
BIT 1
Q0
D1
BIT 2
Q1
D2
BIT 3
Q2
D3
BIT 4
Q3
D4
BIT 5
Q4
D5
BIT 6
Q5
D6
BIT 7
Q6
D7
Q7
LEN
LEN
LEN
LEN
LEN
LEN
LEN
LEN
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
Reset Reset
SET MIN
SET MAX
Figure 4. Expansion of the Latch Section of the E195 Block Diagram
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7
CASCADE
CASCADE
MC10E195, MC100E195
1600
30
DELAY VARIATION (ps)
25
20
PROPAGATION DELAY (ps)
Note:
All Taps Selected
SET = H, Temp. = 0°C
15
10
5
0
−5
−10
−15
−5.5
−5.3
−5.1
−4.9
−4.7
−4.5
1575
1550
1525
1500
1475
1450
1425
1400
1375
1350
1325
1300
−4.3
0
10
20
30
40
50
60
70
80
90
VEE, (V)
Temperature (°C)
Figure 5. Change in Delay vs. Change in
Supply Voltage
Figure 6. Delay vs. Temperature (Fixed Path)
100
4400
PROPAGATION DELAY (ps)
PROPAGATION DELAY (ps)
4300
4200
4100
4000
3900
3800
3700
3600
3600
85°C
2800
0°C
2000
3500
3400
0
10
20
30
40
50
60
70
80
90
100
1200
0
64
32
Temperature (°C)
Figure 7. Delay vs. Temperature (Max. Delay).
Figure 8. 100E195 Temperature Effects on
Delay.
3900
84
3400
80
DELAY (ps)
PROPAGATION DELAY (ps)
88
76
72
2900
2400
1900
68
64
128
96
Tap Delay
0
10
20
30
40
50
60
70
80
90
1400
100
0
20
40
60
80
100
Temperature (°C)
Tap Selection
Figure 9. Delay vs. Temperature (Per Gate).
Figure 10. E195 Delay Linearity.
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8
120
MC10E195, MC100E195
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 11. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10E195FN
PLCC−28
37 Units / Rail
MC10E195FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E195FNR2
PLCC−28
500 / Tape & Reel
MC10E195FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E195FN
PLCC−28
37 Units / Rail
MC100E195FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E195FNR2
PLCC−28
500 / Tape & Reel
MC100E195FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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9
MC10E195, MC100E195
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
0.007 (0.180)
B
Y BRK
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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10
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E195, MC100E195
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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Phone: 81−3−5773−3850
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC10E195/D