Anpec APW7063KC-TRL Synchronous buck pwm and linear controller Datasheet

APW7063
Synchronous Buck PWM and Linear Controller
Features
General Description
•
The APW7063 integrates PWM and linear controller,
Provide Two Regulated Voltages
as well as the monitoring and protection functions into
- Synchronous Rectified Buck PWM Controller
a single package. The synchronous PWM cont roller
- Linear Controller
•
which drives dual N-channel MOSFETs, which provides
Fast Transient Response
one controlled power outputs with under-voltage and
- 0~85% Duty Ratio
•
over-current protect ions . Linear cont roller drives an
ext ernal N-c hannel MOS FE T with under-volt age
Excellent Output Voltage Regulation
protection.
- 0.8V Internal Reference
- ±1% Over Line Voltage and Temperature
•
APW7063 provides excellent regulation for output load
variation. An internal 0.8V temperature-compensated
Over Current Protection
reference voltage is designed to meet the various low
- Sense Low-Side MOSFET’s RDS(ON)
•
•
•
•
output voltage applications . A PW 7063 inc ludes a
Under Voltage Lockout
250kHz free-running t riangle-wave osc illator that is
Small Converter Size
adjust able from below 70KHz to over 800KHz.
- 250KHz Free-Running Oscillator
A power-on-reset (POR) circuit limits the VCC minimum
- Programmable From 70kHz to 800kHz
opearting s upply voltage to ass ure the c ontroller
working well. Over current protec tion is achieved by
14-Lead SOIC Package
monit oring t he volt age drop ac ros s the low s ide
Lead Free Available (RoHS Compliant)
MOSFET, eliminating the need for a current sensing
resistor and short circuit condition is detected through
Applications
the FB pin. The over-current protection t riggers the
soft -start function until the fault events be removed,
•
•
•
•
•
Graphic Cards
but Under-voltage protection will shutdown IC directly.
Memory Power Supplies
Pull the COMP pin below 0.4V will shutdown t he
DSL or Cable MODEMs
controller, and both gate drive signals will be low.
Set Top Boxes
Pinouts
Low-Voltage Distributed Power Supplies
RT
1
14
FBL
SS
2
13
DRIVE
VREG
3
12
VCC
FB
4
11
LGATE
COMP
5
10
PGND
GND
6
9
BOOT
PHASE
7
8
UGATE
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
1
www.anpec.com.tw
APW7063
Ordering and Marking Information
Package Code
K : SOP - 14
Operating Ambient Temp. Range
C : 0 to 70 ° C
Handling Code
TU : Tube
TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Original Device
APW7063
Lead Free Code
Handling Code
Temp. Range
Package Code
APW7063
XXXXX
APW7063 K :
XXXXX - Date Code
No te : ANPEC lea d-fre e p ro ducts co ntain mo ld ing comp oun ds /di e attach m ate ri als and 100 % matte ti n p la te
te rmin atio n fi nish ; wh ich are full y compl iant with Ro HS and compa tibl e wi th both SnPb an d le ad-free sold ieri ng
op era tio ns. AN PEC le ad-free produ cts me et or exceed th e l ead -free req uireme nts of IPC /JEDEC J STD -02 0C
fo r MSL classi ficati on at lea d-fre e p eak re flo w temp era ture.
Block Diagram
SS
VCC
BOOT
vcc
Power-On
Reset
ISS
10uA
5.8V
Gate Control
UGATE
vcc
Soft Start
and
Fault Logic
GND
IOCSET
250uA
PHASE
VCC
50%V REF
:2
U.V.P
Comparator
O.C.P
Comparator
LGATE
PGND
FBL
50%V REF
PWM
Comparator
Error Amp
:2
VCC
VCC
DRIVE
VREF
Oscillator
Regulator
V REF
Triangle
Wave
FB
COMP
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
RT
VREG
2
www.anpec.com.tw
APW7063
Application Circuit
1. Boot-Strap - Use Internal Regulator
C1
12V
D1
5V
12V
1uF
1N4148
L1
VIN
R1
2R2
VIN R2
NC
R3
NC
1
2
3
4
5
6
7
C4
0.1uF
Q1
APM3055L
1
14
RT
FBL 13
SS
DRIVE 12
VREG
VCC 11
FB
LGATE 10
COMP
PGND 9
GND
BOOT 8
PHASE UGATE
R4
C11
/SHDN
C10
4.7uF
R6
R5
3.125KF
1%
C16
56pF
+ C6
470uF
16V
25mR
+ C7
470uF
16V
25mR
1
2
3
0R
2.5V
L2
0.1uF
2.2uH
8
7
6
5
R9
C15
0.01uF
+ C5
470uF
16V
25mR
Q2
APM4220
4
820R
R8
1KF
1%
C3
4.7uF
8
7
6
5
C8
1uF
3
3V3
+ C9
470uF
6.3V
25mR
1uH
U1
APW7063
2
+ C2
470uF
6.3V
25mR
Q3
APM4220
4
R7
100R
D2
SR24
2A/40V
+ C13
1000uF
6.3V
30mR
C14
4.7uF
R10
2.32KF
1%
1
2
3
0R
+ C12
1000uF
6.3V
30mR
C17
0.1uF
R11
20K
R12
1.07KF
1%
2. Boot-Strap - Use External Power
12V
C1
5V
C2
1uF
1uF
12V
L1
R2
2R2
VIN R1
NC
R3
NC
1
2
3
4
5
6
7
C7
0.1uF
Q1
APM3055L
1
RT
FBL
SS
DRIVE
VREG
VCC
FB
LGATE
COMP
PGND
GND
BOOT
PHASE UGATE
14
13
12
11
10
9
8
R4
C12
/SHDN
+ C10
470uF
6.3V
25mR
C11
4.7uF
R6
R5
3.125KF
1%
C17
56pF
+ C6
470uF
16V
25mR
2.5V
L2
2.2uH
8
7
6
5
R9
0R
R11
20K
+ C9
470uF
16V
25mR
1
2
3
0.1uF
C16
0.01uF
+ C5
470uF
16V
25mR
Q2
APM4220
4
0R
620R
R7
1KF
1%
C4
4.7uF
8
7
6
5
C8
1uF
3
3V3
1uH
D1
1N4148
U1
APW7063
2
+ C3
470uF
6.3V
25mR
VIN
Q3
APM4220
4
1
2
3
D2
SR24
2A/40V
R8
100R
+ C13
1000uF
6.3V
30mR
+ C14
1000uF
6.3V
30mR
C15
4.7uF
R10
2.32KF
1%
C18
0.1uF
R12
1.07KF
1%
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
3
www.anpec.com.tw
APW7063
Absolute Maximum Ratings
Symbol
Rating
Unit
VCC to GND
30
V
LGATE
LGATE to GND
30
V
DRIVE
DRIVE to GND
30
V
UGATE
UGATE to GND
30
V
VBOOT
BOOT to GND
30
V
PHASE to GND
30
VCC
Parameter
Operating Junction Temperature
T STG
Storage Temperature
TSDR
Soldering Temperature (10 Seconds)
VESD
Minimum ESD Rating
V
0~150
o
C
-65 ~ 150
o
C
300
o
C
±2
KV
Recommended Operating Conditions
Symbol
VCC
VBOOT
Parameter
Min.
Nom.
Max.
Unit
7
12
19
V
26
V
Supply Voltage
Boot Voltage
Thermal Characteristics
Symbol
θJA
Parameter
Value
Junction to Ambient Resistance in free air (SOP-14)
Unit
o
160
C/W
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V, RT = OPE N and
TA = 0 ~ 70oC. Typlcal values are at TA = 25oC.
Symbol
Parameter
Test Conditions
APW7063
Min
Typ
Max
Unit
SUPPLY CURRENT
ICC
VCC Nominal Supply
UGATE and LGATE Open
3
mA
POWER-ON-RESET
Rising VCC Threshold
7.0
7.2
7.4
V
Falling VCC Threshold
6.6
6.8
7.0
V
250
280
kHz
+15
%
OSCILLATOR
Free Running Frequency
R T = OPEN, VCC = 12V
220
Total Variation
6KΩ < RT to GND < 200KΩ
-15
Ramp Amplitude
R T = OPEN
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
4
1.7
VP-P
www.anpec.com.tw
APW7063
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V, RT = OPE N and
TA = 0 ~ 70oC. Typlcal values are at TA = 25oC.
Symbol
Parameter
Test Conditions
APW7063
Min
Typ
Max
Unit
REFERENCE
VREF
Reference Voltage
0.80
Reference Voltage Tolerance
-1
V
+1
%
PWM EEEOR AMPLIFIER
DC Gain
75
UGATE Duty Range
0
FB Input Current
dB
85
%
0.1
uA
GATE DRIVERS
IUGATE
Upper Gate Source
VBOOT = 12V, VUGATE = 6V
RUGATE
Upper Gate Sink
IUGATE = 0.3A
ILGATE
Lower Gate Source
VCC = 12V, VLGATE = 6V
RLGATE
Lower Gate Sink
ILGATE = 0.3A
TD
650
800
4
550
8
700
4
Dead Time
mA
Ω
mA
8
Ω
50
nS
0.8
V
2
%
LINEAR REGULATOR
Reference Voltage
Regulation
Output Drive Current
VDRIVE = 4V
8
10
12
mA
PROTECTION
FB Under Voltage Level
50
%
FBL Under Voltage Level
50
%
250
µA
OCSET Source Current
VREG
VREG
Output Voltage Accuracy
VCC > 12V
5.5
6
6.5
V
IOUT
Output Current Capacity
VCC = 12V
20
mA
C SS = 0uF
2
mS
SOFT START and SHUTDOWN
T SS
Internal Soft-Start Interval
ISS
Soft-Start Charge Current
Shutdown Threshold
8
COMP Falling
Shutdown Hysteresis
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
5
10
12
uA
0.4
V
50
mV
www.anpec.com.tw
APW7063
Functional Pin Description
RT (Pin 1)
VOLTAGE
V SOFT
This pin can adjust the switching frequency. Connect
START
a resistor from RT to VCC for decreasing the switching
frequency, Conversely, connect a resistor from RT to
GND for increasing the s witc hing frequency (see
V OUT2
Ty pical Characteristics).
V OUT1
SS (Pin 2)
Connect a capacitor from this pin t o GND to set the
soft -start interval of t he converter. An internal 10µA
current source charges this capacitor to 5.2V. The SS
FB
FBL
voltage clamps the reference voltage to the SS voltage,
t0
and Figure1 shows the soft-start interval. At t0, the
internal sourc e current starts to charge the capacitor
t1
t2
TIME
t3
Figure 1. Soft-Start Interval
and the internal 0.8V reference also starts to rise and
follows the SS. Until the internal reference reaches to
VREG (Pin 3)
0.8V at t2, the soft-st art interval is completed. This
An internal regulator will s upply 6V for boost voltage,
method provides a rapid and controlled output voltage
a 1uF capacitor to GND is recommended for stability.
ris e. The way of the Soft-Start of the output 2 is the
If the VREG voltage has variation by other interference,
same as the output1, but it starts from the SS at 2.2V
the IC can not work normally. W hen the VCC< 8V,
to 3.0V. The A PW 7063 als o provides t he int ernal
don’t use the VREG for BOOST voltage.
S oft-S tart whic h is fix ed to 2ms (t 0 t o t 1). If the
ex ternal Soft-Start interval is slower than the internal
FB (Pin 4)
S oft -S t art int erval (C SS < 0. 025uF) or no ex ternal
FB pin is the inverting input of the error amplifier, and it
capacitor, the Soft-S tart will follow t he internal Soft-
receives the feedback voltage from an external resistive
St art.
divider across the output (VOUT). The output voltage is
C SS
× 0.8V
TSoft-Start = t1 - t0 =
ISS
C SS
× 0.8V
t3 = t2 +
I SS
determined by :


VOUT = 0.8V × 1+
ROUT 

RGND 
where ROUT is the resistor connected from VOUT to FB,
Where:
and RGND is the resistor connected from FB to GND.
CSS = external Soft-Start capacitor
When the FB voltage is under 50% Vref, it will cause
ISS = Soft-Start current = 10µA
t2 =
C SS
ISS
the under voltage protection, and shutdown the device.
× 2.2V
Remove the condition and restart the V CC voltage or
pull the COMP from low to high once, will enable the
device again.
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
6
www.anpec.com.tw
APW7063
Functional Pin Description (Cont.)
COMP (Pin 5)
PGND (Pin 10)
This pin is t he output of t he error amplifier. Add an
Power ground for t he gate diver. Connect t he lower
external resis tor and capacitor network to provide the
MOSFET source to this pin.
loop compens ation for t he P W M c onvert er (see
A pplic at ion Information).
LGATE (Pin 11)
Pull this pin below 0.4V will shutdown the controller,
This pin provides the gate drive signal for the low side
forcing the UGATE and LGATE signals to be 0V. A soft
MOSFET.
start cycle will be initiated upon the release of this pin.
VCC (Pin 12)
GND (Pin 6)
This pin provides a supply voltage for the device, when
VCC is above the rising threshold 4.2V, It turns on the
Signal ground for the IC.
device is turned on, and conversely, VCC is below the
PHASE (Pin 7)
falling threshold 3.9V, the device is turned off. A 1uF
A resistor (ROCSET) is connected bet ween this pin and
decoupling capacitor to GND is recommended.
the drain of the low-side MOSFET will determine the
over current limit. An internally generated 250uA current
DRIVE (Pin 13)
source will flow through this resistor, creating a voltage
Connect this pin to the gate of an external N-channel
drop. This voltage will be compared with the voltage
MOS FET transis tor. This pin provides the gate volt-
ac ross the low-side MOSFET. The threshold of t he
age for the linear regulator pass transistor. It also pro-
over current limit is therefore given by :
vides a means of compensating the linear controller
R OCSET =
for applications where the user needs to optimize the
ILIMIT × R DS(ON)
regulator transient response.
250uA
FBL (Pin 14)
An over current condit ion will c yc le t he s oft st art
func tion unt il the over current condition is removed.
Connec t this pin to the out put of the linear regulator
Because of the comparator delay time, so the on time
via a proper s ized resistor divider. The voltage at this
of the low-side MOSFET must be longer than 800ns to
pin is regulat ed to 0.8V and the output voltage is de-
have the over current protection work.
termined using the following formula :


UGATE (Pin 8)
VOUT = 0.8V × 1 +
This pin provides gate drive for the high-side MOSFET.
ROUT 

RGND 
where ROUT is the resistor connected from VOUT to FBL,
BOOT (Pin 9)
and RGND is the resistor connected from FBL to GND.
This pin provides the supply voltage to the high side
MOS FE T driver. For driving logic level N-channel
This pin also monitores the under-voltage events, if
MOSEFT, a boots trap circuit can be use to create a
the linear regulator is not used, tie the FBL to VREG.
suitable driver’s supply.
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
7
www.anpec.com.tw
APW7063
Typical Characteristics
Power Up
Power Down
V CC=VIN1=12V
V IN2=5V, CSS=0.1µF
VCC(10V/div)
VCC=VIN1 =12V
VIN2=5V, CSS=0.1µF
VCC(10V/div)
SS(5V/div)
SS(5V/div)
VOUT1(2V/div)
VOUT1(2V/div)
VOUT2(2V/div)
VOUT2(2V/div)
Time (10ms/div)
Time (10ms/div)
Enable (COMP is left open)
Shutdown (COMP is pulled to GND)
V CC=VIN1=12V
V IN2=5V, CSS=0.1µF
VCC =VIN1=12V
VIN2 =5V, CSS=0.1µF
VOUT2(2V/div)
VOUT2(2V/div)
VOUT1(2V/div)
VOUT1(2V/div)
COMP(1V/div)
COMP(1V/div)
SS(5V/div)
SS(5V/div)
Time (2ms/div)
Time (10ms/div)
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
8
www.anpec.com.tw
APW7063
Typical Characteristics (Cont.)
UGATE Falling
UGATE Rising
VCC=2V, VIN=12V
VCC=2V, VI N=12V
LGATE(10V/div)
LGATE(10V/div)
PHASE(10V/div)
PHASE(10V/div)
UGATE(10V/div)
UGATE(10V/div)
Time (50ns/div)
Time (50ns/div)
Under Voltage Protection (PWM)
Under Voltage Protection (Linear)
VCC=12,VIN=12V
VOUT=3.3V, L=2.2mH
IL(10A/div)
SS(5V/div)
VCC=12V, VIN=5V
VOUT2=2.5V
SS(5V/div)
VOUT2(2V/div)
VOUT1 (2V/div)
UGATE (10V/div)
DRV(5V/div)
Time (5us/div)
Time (5us/div)
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
9
www.anpec.com.tw
APW7063
Typical Characteristics (Cont.)
PWM Load Transient
Linear Load Transient
VCC=12V
VIN=12V
VOUT=3.3V
COUT =470mFx2
ESR=22.5mW
L=1.5mH
f=400kHz
VCC=12V
VIN=12V
VOUT=2.5V
COUT=470mF
VOUT2(100mV/div)
VOUT1(100mV/div)
IOUT2(1A/div)
IOUT1(5A/div)
Time (20us/div)
Time (10us/div)
UGATE Sink Current vs. UGATE Voltage
UGATE Source Current vs. UGATE Voltage
1.2
VBOOT=12V
VBOOT=12V
1.2
UGATE Sink Current (A)
UGATE Source Current (A)
1.4
1
0.8
0.6
0.4
0.2
1
0.8
0.6
0.4
0.2
0
0
0
2
4
6
8
10
0
12
4
6
8
10
12
UGATE Voltage (V)
UGATE Voltage (V)
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
2
10
www.anpec.com.tw
APW7063
Typical Characteristics (Cont.)
LGATE Source Current vs. LGATE Voltage
LGATE Sink Current vs. LGATE Voltage
1.2
VCC=12V
VCC=12V
1.2
LGATE Sink Current (A)
LGATE Source Current (A)
1.4
1
0.8
0.6
0.4
0.2
1
0.8
0.6
0.4
0.2
0
0
0
2
4
6
8
10
12
0
LGATE Voltage (V)
2
4
6
8
10
12
LGATE Voltage (V)
Over Current Protection
VCC=12V,VIN=12V, VOUT=2.5V, ROCSET=1kW
RDS(ON)=16mW, L=2.2mH, IOUT=15A
Switching Frequence vs. RT Resistance
10000
RT Resistance (kΩ)
IL(10A/div)
SS(5V/div)
UGATE(20V/div)
RT pull up to 12V
1000
100
RT pull down to GND
10
1
VOUT1(2V/div)
10
Time (5us/div)
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
100
1000
Switching Frequency (kHz)
11
www.anpec.com.tw
APW7063
Typical Characteristics (Cont.)
Comp Source Current vs. Comp Voltage
Comp Sink Current vs. Comp Voltage
150
150
VCC=12V
VCC=12V
125
Source Current (µA)
Sink Current (µA)
125
100
75
50
25
100
75
50
25
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
1
1.5
Comp Voltage (V)
2
2.5
3
4
Comp Voltage (V)
Drive Source Current vs. Drive Voltage
Drive Sink Current vs. Drive Voltage
40
10
VCC=12V
VCC=12V
Source Current (mA)
8
Sink Current (mA)
3.5
6
4
2
30
20
10
0
0
0
2
4
6
8
10
0
12
Drive Voltage (V)
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
2
4
6
8
10
12
Drive Voltage (V)
12
www.anpec.com.tw
APW7063
Typical Characteristics (Cont.)
VREG Voltage vs. Supply Voltage
VREG Voltage vs. Load Current
6.5
6
5.5
VREG Voltage (V)
VREG Voltage (V)
VCC=12V
5
4.5
4
6.25
6
5.75
5.5
0
2
4
6
8
10
12
14
16
18
0
5
Supply Voltage (V)
10
15
20
Load Current (mA)
Supply Current vs. Supply Voltage
Reference Voltage vs. Temperature
4
0.8
Reference Voltage (V)
Supply Current (mA)
3.5
ICC
3
2.5
2
ICC(SHDN)
1.5
1
0.798
0.796
0.794
0.792
0.5
0.79
-40
0
0
2
4
6
8
10
12
Supply Voltage (V)
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
-20
0
20
40
60
80
100 120
Temperature (°C)
13
www.anpec.com.tw
APW7063
Application Information
Component Selection Guidelines
There is a tradeoff exists between the inductor’s ripple
Output Capacitor Selection
The select ion of COUT is determined by the required
effective series resistanc e (ES R) and voltage rat ing
rat her t han the ac t ual c apac it anc e requirement .
current and the regulator load transient response time
A smaller inductor will give the regulator a faster load
trans ient res ponse at the expens e of higher ripple
current and vice versa. The maximum ripple current
Therefore select high performance low ESR capacitors
occurs at the maximum input voltage. A good starting
that are intended for switching regulator applications.
In some applications, multiple capacitors have to be
paralled to achieve the desired ESR value. If tantalum
point is to choose the ripple current to be approximately
30% of the maximum output current.
capacitors are used, make sure they are surge tested
Once the induct ance value has been chosen, s elect
by the manufactures. If in doubt, consult the capacitors
an inductor that is capable of carrying the required
manufac turer.
peak current without going into s aturation. In s ome
ty pe of induc tors, es pec ially core that is make of
Input Capacitor Selection
ferrite, the ripple current will increase abruptly when it
The input capacitor is chosen based on the volt age
saturates. This will result in a larger output ripple
rating and the RMS current rating. For reliable operation,
voltage.
select the capacitor voltage rating to be at least 1.3
times higher than t he maximum input voltage. The
Compensation
maximum RMS current rating requirement is approximately
The output LC filter of a step down converter introduces
IOUT/2 , where IOUT is the load current. During power up,
a double pole, which contributes with –40dB/decade
the input capacitors have to handle large amount of
gain slope and 180 degrees phase shift in the control
surge current. If tantalum capacitors are used, make
loop. A compensation network between COMP pin and
sure they are surge tested by the manufactures. If in
ground should be added. The simplest loop compensation
doubt, consult the capacitors manufacturer.
network is shown in Fig. 5.
For high frequency decoupling, a ceramic c apacitor
The out put LC filter consist s of the output induc tor
between 0.1uF to 1uF can be connected between VCC
and output capacitors. The transfer function of the LC
and ground pin.
filter is given by:
GAINLC
Inductor Selection
The inductance of the inductor is determined by the
FLC
=
into lower output ripple voltage. The ripple current and
ripple voltage can be approximated by:
VIN - VOUT
VOUT
IRIPPLE =
x
VIN
Fs x L
where Fs is the switching frequency of the regulator.
1+ s× ESR× COUT
2
s × L × COUT + s × ESR× COUT + 1
The poles and zero of this transfer function are:
output voltage requirement. The larger the inductance,
the lower the inductor’s current ripple. This will translate
=
FESR
=
1
2 × π × L × COUT
1
2 × π × ESR × COUT
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
∆VOUT = IRIPPLE x ESR
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
14
www.anpec.com.tw
APW7063
Application Information (Cont.)
Compensation (Cont.)
The compens ation circuit is shown in Figure 5. R3
and C1 introduce a zero and C2 introduces a pole to
L
PHASE
Output
reduce t he switching noise. The transfer function of
error amplifier is given by:
COUT

GAINAMP = gm × Zo = gm ×  R3 +
ESR

= gm ×
Figure 2. The Output LC Filter
1


s +

R3
×
C1




s× s +
FLC
-40dB/dec
1 
1 
//

sC1  sC2 
C1 + C2

 × C2
R3 × C1 × C2 
The pole and zero of the compensation network are:
1
FP =
C1× C2
2 × π × R3 ×
C1+ C2
1
FZ =
2 × π × R3 × C1
FESR
Gain
-20dB/dec
V OUT
Frequency
Error
Amplifier
R1
Figure 3. The LC Filter Gain & Frequency
FB
-
The PWM modulator is shown in Figure. 4. The input
is the output of the error amplifier and the output is the
R2
P HA SE node. The trans fer func tion of t he PW M
COMP
+
R3
V REF
C2
modulator is given by:
GAINPWM =
C1
V IN
∆ V OSC
VIN
Figure 5. Compensation Network
Driver
The c losed loop gain of the converter c an be written
PWM
Comparator
as:
GAINLC x GAINPWM x
VOSC
R2
R1+ R2
x GAINAMP
Figure 6 shows the converter gain and the following
Output of
Error
Amplifier
PHASE
guidelines will help t o des ign the c ompens at ion
network.
1.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) x FS >FO>FZ
Driver
Use the following equation to calculate R3:
Figure 4. The PWM Modulator
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
15
www.anpec.com.tw
APW7063
Application Information (Cont.)
losses in the MOSFETs have two components: conduction
Compensation (Cont.)
R3 =
∆V OSC
V IN
×
F ESR
F LC
2
×
R1 + R2
R2
×
loss and t rans it ion loss. For t he upper and lower
FO
MOSFET, t he losses are approximately given by the
gm
following :
Where:
PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
gm = 900uA/V
2
2.Place the zero FZ before the LC filter double poles
FLC:
PLOWER = Iout (1+ TC)(RDS(ON))(1-D)
2
where IOUT is the load current
FZ = 0.75 x FLC
TC is the temperature dependency of RDS(ON)
Calculate the C1 by the equation:
C1 =
FS is the switching frequency
tsw is the switching interval
1
D is the duty cycle
2 × π × R1 × 0.75 × FLC
Note that both MOSFETs have conduction losses while
3. Set the pole at the half the switching frequency:
the upper MOSFET include an additional transition loss.
FP = 0.5xFS
The switching internal, tsw, is a function of the reverse
Calculate the C2 by the equation:
C2 =
transfer capac it anc e CRSS. Figure 7 illustrat es t he
switching waveform internal of the MOSFET.
C1
π × R3 × C1 × F S − 1
The (1+TC) term is to factor in the temperature dependency
of the RDS(ON) and can be extracted from the “RDS(ON) vs
Temperature” curve of the power MOSFET.
FZ =0.75FLC
20 ⋅log(gm⋅R3)
FP=0.5FS
Linear Regulator Input/Output Capacitor Selection
The input capacitor is chos en based on it s voltage
Compensation Gain
rating. Under load transient condition, the input capacitor
Gain
will momentarily supply the required transient current.
FLC
20 ⋅ log
A 1uF ceramic c apac it or will be sufficient inmost
FO
VIN
? VOSC
applications.
FESR
Converter
Gain
PWM &
Filter Gain
The output capacitor for the linear regulator is chosen
to minimize any droop during load transient condition.
Frequency
In addition, the capacitor is chosen based on its voltage
rating.
Figure 6. Converter Gain & Frequency
Linear Regulator MOSFET Selection
MOSFET Selection
The maximum DRIVE voltage is determined by the VCC.
The selection of the N-channel power MOSFETs are
Since this pin drives an external N-channel MOSFET,
determined by the RDS(ON), reverse transfer capacitance
therefore t he max imum output volt age of the linear
(CRSS) and maximum out put current requirement.The
regulator is dependent upon the VGS.
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
16
www.anpec.com.tw
APW7063
Application Information (Cont.)
MOSFET Selection (Cont.)
VOUT2MAX = VCC- VGS
VDS
Another criteria is its efficiency of heat removal. The
Voltage across
drain and source of MOSFET
power dissipated by the MOSFET is given by:
Pdiss = Iout * (VIN - VOUT2)
where Iout is the maximum load current
Vout2 is the nominal output voltage
In some applications, heatsink maybe required to help
maint ain the junction temperature of the MOSFET
below its maximum rating.
t sw
Layout Considerations
Time
Figure 7. Switching waveform across MOSFET
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, int erconnec ting impedanc es should be
VIN
minimized by using short, wide printed circuit traces.
Signal and power grounds are to be kept separate and
finally combined using ground plane cons truction or
C IN
APW7063
single point grounding. Figure 8 illustrates the layout,
PGND
with bold lines indicating high current paths. Components
along the bold lines should be placed close together.
11
+
LGATE 12
Below is a checklist for your layout:
U
9
1 UGATE
• Keep t he switching nodes (UGATE, LGATE and
PHASE 8
PHA SE) away from s ensit ive small signal nodes
C OUT
Q1
Q2
+
L1
since these nodes are fast moving signals. Therefore
keep traces to these nodes as short as possible.
L
O
A
D
VO U T
Figure 8. Recommended Layout Diagram
• The ground return of CIN must return to the combine
COUT (-) terminal.
• Capacitor CBOOT should be connected as close to
the BOOT and PHASE pins as possible.
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
17
www.anpec.com.tw
APW7063
Package Information
0 .0 1 5 x4 5
H
E
SOP – 14 (150mil)
A
0 .0 1 0
A1
A
D
Ee
B
L
Dim
A
A1
B
C
D
E
e
H
L
θ°
Millimeters
Min.
1.477
0.102
0.331
0.191
8.558
3.82
Inches
Max.
1.732
0.255
0.509
0.2496
8.762
3.999
Min.
0.058
0.004
0.013
0.0075
0.336
0.150
1.274
5.808
0.382
0°
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
Max.
0.068
0.010
0.020
0.0098
0.344
0.157
0.050
6.215
1.274
8°
18
0.228
0.015
0°
0.244
0.050
8°
www.anpec.com.tw
APW7063
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Average ramp-up rate
3°C/second max.
3°C/second max.
(TL to T P)
Preheat
100°C
150°C
- Temperature Min (Tsmin)
°C
150
200°C
- Temperature Max (Tsmax)
60-120
seconds
60-180
seconds
- Time (min to max) (ts)
Time maintained above:
183°C
217°C
- Temperature (TL)
60-150
seconds
60-150
seconds
- Time (t L)
Peak/Classificatioon Temperature (Tp)
See table 1
See table 2
Time within 5 °C of actual
10-30 seconds
20-40 seconds
Peak Temperature (tp)
Ramp-down Rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25 °C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
19
www.anpec.com.tw
APW7063
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
<2.5 mm
240 +0/-5° C
≥2.5 mm
225 +0/-5° C
Volume mm3
≥350
225 +0/-5° C
225 +0/-5° C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Package Thickness
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 mm
°
°
260 +0 C*
260 +0 C*
260 +0 °C*
1.6 mm – 2.5 mm
260 +0° C*
250 +0 °C*
245 +0 °C*
≥ 2.5 mm
°
°
250 +0 C*
245 +0 C*
245 +0 °C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the
stated classification temperature (this means Peak reflow temperature +0° C. For example 260° C+0° C)
at the rated MSL level.
Reliability Test Program
Test item
Method
SOLDERABILITY
HOLT
PCT
TST
Description
MIL-STD-883D-2003
MIL-STD 883D-1005.7
JESD-22-B, A102
MIL-STD 883D-1011.9
245°C,5 SEC
1000 Hrs Bias @ 125°C
168 Hrs, 100% RH, 121°C
-65°C ~ 150°C, 200 Cycles
Carrier Tape & Reel Dimensions
t
E
P
Po
D
P1
Bo
F
W
Ao
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
D1
20
Ko
www.anpec.com.tw
APW7063
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
Application
SOP-14
(150mil)
A
B
330REF
100REF
F
D
φ0.50 +
0.1
7.5
C
13.0 + 0.5
- 0.2
D1
φ1.50
(MIN)
J
T1
2 ± 0.5
T2
16.5REF 2.5 ± 025
W
16.0 ± 0.3
P
E
8
1.75
Po
P1
Ao
Ko
t
4.0
2.0
6.5
2.10
0.3 ± 0.05
(mm)
Cover Tape Dimensions
Application
SOP- 14
Carrier Width
24
Cover Tape Width
21.3
Devices Per Reel
2500
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
C opyright  ANPEC Electronics C orp.
Rev. A.7 - Nov., 2005
21
www.anpec.com.tw
Similar pages