Mitel MT9041B T1/e1 system synchronizer Datasheet

MT9041B
T1/E1 System Synchronizer
Advance Information
DS5059
Features
•
•
•
•
•
•
Supports AT&T TR62411 and Bellcore
GR-1244-CORE Stratum 4 Enhanced and
Stratum 4 timing for DS1 Interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12
and TBR 13 timing for E1 Interfaces
Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
Provides C1.5, C2, C3, C4, C8 and C16 output
clock signals
Provides 3 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9 Hz
ISSUE 3
Septemner 1999
Ordering Information
MT9041BP
28 Pin PLCC
-40 to +85 °C
Description
The MT9041B T1/E1 System Synchronizer contains
a digital phase-locked loop (DPLL), which provides
timing and synchronization signals for multitrunk T1
and E1 primary rate transmission links.
The MT9041B generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.
Applications
•
•
Synchronization and timing control for
multitrunk T1 and E1 systems
ST-BUS clock and frame pulse sources
VDD
The MT9041B is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE Stratum 4 Enhanced,
Stratum 4, and ETSI ETS 300 011. It will meet the
jitter tolerance, jitter transfer, intrinsic jitter, frequency
accuracy, capture range and phase change slope
requirements for these specifications.
VSS
OSCi
OSCo
C1.5o
REF
Loop
Filter
Phase
Detector
C3o
DCO
C2o
Output
Interface
Circuit
C4o
C8o
C16o
F0o
F8o
F16o
Mode Select
MS
Divider
RST
FS1
FS2
Figure 1 - Functional Block Diagram
1
MT9041B
4
VDD
OSCo
OSCi
F16o
F0o
F8o
C1.5o
5
6
7
8
9
10
11
IC0
VSS
RST
FS1
FS2
REF
NC
Advance Information
3 2 1 28 27 26
25
24
23
22
21
20
19
MT9041B
IC0
IC0
MS
IC0
IC0
IC1
IC0
C3o
C2o
C4o
VSS
C8o
C16o
VDD
12 13 14 15 16 17 18
Figure 2 - Pin Connections
Pin Description
2
Pin #
Name
Description
1
VSS
Ground. 0 Volts.
2
IC0
Internal Connect. Connect to Vss
3
NC
No Connect. Connect to Vss
4
REF
Reference (TTL Input). PLL reference clock.
5
VDD
Positive Supply Voltage. +5VDC nominal.
6
OSCo
Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is
connected from this pin to OSCi, see Figure 6. For clock oscillator operation, this pin is left
unconnected, see Figure 5.
7
OSCi
Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is
connected from this pin to OSCo, see Figure 6. For clock oscillator operation, this pin is
connected to a clock source, see Figure 5.
8
F16o
Frame Pulse ST-BUS 16.384Mb/s (CMO7S Output). This is an 8kHz 61ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 16.384Mb/s. See Figure 11.
9
F0o
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 11.
10
F8o
Frame Pulse ST-BUS 8.192Mb/s (CMOS Output). This is an 8kHz 122ns active high
framing pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS
operation at 8.192Mb/s. See Figure 11.
11
C1.5o
12
C3o
Clock 3.088MHz (CMOS Output). This optional output is used in T1 applications.
13
C2o
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.
14
C4o
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
15
VSS
Ground. 0 Volts.
16
C8o
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.
17
C16o
Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation at 16.384Mb/
s.
18
VDD
Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
Positive Supply Voltage. +5VDC nominal.
MT9041B
Advance Information
Pin Description (continued)
Pin #
Name
Description
19
IC0
Internal Connect. Connect to Vss
20
IC1
Internal Connect. Leave open Circuit
21
IC0
Internal Connect. Connect to Vss
22
IC0
Internal Connect. Connect to Vss
23
MS
Mode/Control Select (TTL Input). This pin, determines the device’s state (Normal, or
Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See
Table 3.
24
IC0
Internal Connect. Connect to Vss
25
IC0
Internal Connect. Connect to Vss
26
FS2
Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects which of three
possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input to the REF input. See
Table 1.
27
FS1
Frequency Select 1 (TTL Input). See pin description for FS2.
28
RST
Reset (Schmitt Input). A logic low at this input resets the MT9041B. To ensure proper
operation, the device must be reset after reference signal frequency changes and power-up.
The RST pin should be held low for a minimum of 300ns. While the RST pin is low, all frame
and clock outputs are at logic high. Following a reset, the input reference source and output
clocks and frame pulses are phase aligned as shown in Figure 10.
Functional Description
The MT9041B is a System Synchronizer, providing
timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital
Transmission links.
Figure 1 is a functional block diagram which is
described in the following sections.
FS2
FS1
Input Frequency
0
0
Reserved
0
1
8kHz
1
0
1.544MHz
1
1
2.048MHz
Table 1 - Input Frequency Selection
Digital Phase Lock Loop (DPLL)
Frequency Select MUX Circuit
The MT9041B operates on the falling edges of one
of three possible input reference frequencies (8kHz,
1.544MHz or 2.048MHz). The frequency select
inputs (FS1 and FS2) determine which of the three
frequencies may be used at the reference input
(REF). A reset (RST) must be performed after every
frequency select input change. Operation with FS1
and FS2 both at logic low is reserved and must not
be used. See Table 1.
The DPLL of the MT9041B consists of a Phase
Detector, Limiter, Loop Filter, Digitally Controlled
Oscillator, and a Control Circuit (see Figure 3).
Phase Detector - the Phase Detector compares the
primary reference signal (REF) with the feedback
signal from the Frequency Select MUX circuit, and
provides an error signal corresponding to the phase
difference between the two. This error signal is
passed to the Limiter circuit. The Frequency Select
MUX allows the proper feedback signal to be
externally selected (e.g., 8kHz, 1.544MHz or
2.048MHz).
Limiter - the Limiter receives the error signal from
the Phase Detector and ensures that the DPLL
responds to all input transient conditions with a
maximum output phase slope of 5ns per 125us. This
3
MT9041B
Advance Information
REF Reference
Phase
Detector
Limiter
Digitally
Controlled
Oscillator
Loop Filter
DPLL Reference
to
Output Interface Circuit
Control
Circuit
Feedback Signal
from
Frequency Select MUX
Figure 3 - DPLL Block Diagram
is well within the maximum phase slope of 7.6ns per
125us or 81ns per 1.326ms specified by Bellcore
GR-1244-CORE Stratum 4E.
Loop Filter - the Loop Filter is similar to a first order
low pass filter with a 1.9 Hz cutoff frequency for all
three reference frequency selections (8kHz,
1.544MHz or 2.048MHz). This filter ensures that the
jitter transfer requirements in ETS 300 011 and AT&T
TR62411 are met.
outputs. The C8o, C4o and C2o clocks are
generated by simply dividing the C16o clock by two,
four and eight respectively. These outputs have a
nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal to
generate two clock outputs. C1.5o and C3o are
generated by dividing the internal C12 clock by four
and eight respectively. These outputs have a nominal
50% duty cycle.
Control Circuit - the Control Circuit sets the mode
of the DPLL. The two possible modes are Normal
and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO
receives the limited and filtered signal from the Loop
FIlter, and based on its value, generates a
corresponding
digital
output
signal.
The
synchronization method of the DCO is dependent on
the state of the MT9041B.
T1 Divider
Tapped
Delay
Line
12MHz
C3o
From
DPLL
In Normal Mode, the DCO provides an output signal
which is frequency and phase locked to the selected
input reference signal.
In Freerun Mode, the DCO is free running with an
accuracy equal to the accuracy of the OSCi 20MHz
source.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output
Interface Circuit to provide the output signals shown
in Figure 4. The Output Interface Circuit uses two
Tapped Delay Lines followed by a T1 Divider Circuit
and an E1 Divider Circuit to generate the required
output signals.
Two tapped delay lines are used to generate a
16.384MHz and a 12.352MHz signals.
The E1 Divider Circuit uses the 16.384MHz signal to
generate four clock outputs and three frame pulse
4
C1.5o
E1 Divider
Tapped
Delay
Line
16MHz
C2o
C4o
C8o
C16o
F0o
F8o
F16o
Figure 4 - Output Interface Circuit Block
Diagram
The frame pulse outputs (F0o, F8o, F16o) are
generated directly from the C16 clock.
The T1 and E1 signals are generated from a
common DPLL signal. Consequently, the clock
outputs C1.5o, C3o, C2o, C4o, C8o, C16o, F0o and
F16o are locked to one another for all operating
states, and are also locked to the selected input
reference in Normal Mode. See Figures 11 and 12.
MT9041B
Advance Information
All frame pulse and clock outputs have limited driving
capability, and should be buffered when driving high
capacitance (e.g. 30pF) loads.
Master Clock
The MT9041B can use either a clock or crystal as
the master timing source. For recommended master
timing circuits, see the Applications - Master Clock
section.
Freerun Mode
Freerun Mode is typically used when a master clock
source is required, or immediately following system
power-up before network synchronization is
achieved.
In Freerun Mode, the MT9041B provides timing and
synchronization signals which are based on the
master clock frequency (OSCi) only, and are not
synchronized to the reference signal (REF).
Control and Modes of Operation
The MT9041B can operate either in Normal or
Freerun modes.
As shown in Table 2, pin MS selects between
NORMAL and FREERUN modes.
MS
Description of Operation
0
NORMAL
1
FREERUN
Table 2 - Operating Modes
Normal Mode
Normal Mode is typically used when a slave clock
source synchronized to the network is required.
In Normal Mode, the MT9041B provides timing
(C1.5o, C2o, C3o, C4o, C8o and C16o) and frame
synchronization (F0o, F8o, F16o) signals, which are
synchronized to reference input (REF). The input
reference signal may have a nominal frequency of
8kHz, 1.544MHz or 2.048MHz.
From a reset condition, the MT9041B will take up to
25 seconds for the output signal to be phase locked
to the reference.
The reference frequencies are selected by the
frequency control pins FS2 and FS1 as shown in
Table 1.
The accuracy of the output clock is equal to the
accuracy of the master clock (OSCi). So if a ±32ppm
output clock is required, the master clock must also
be ±32ppm. See Applications - Crystal and Clock
Oscillator sections.
MT9041B Measures of Performance
The following are some synchronizer performance
indicators and their corresponding definitions.
Intrinsic Jitter
Intrinsic jitter is the jitter produced by the
synchronizing circuit and is measured at its output. It
is measured by applying a reference signal with no
jitter to the input of the device, and measuring its
output jitter. Intrinsic jitter may also be measured
when the device is in a non-synchronizing mode, i.e.
free running mode, by measuring the output jitter of
the device. Intrinsic jitter is usually measured with
various bandlimiting filters depending on the
applicable standards.
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to
operate properly (i.e., remain in lock and or regain
lock), in the presence of large jitter magnitudes at
various jitter frequencies applied to its reference.
The applied jitter magnitude and jitter frequency
depends on the applicable standards.
Jitter Transfer
Jitter transfer or jitter attenuation refers to the
magnitude of jitter at the output of a device for a
given amount of jitter at the input of the device. Input
jitter is applied at various amplitudes and
frequencies, and output jitter is measured with
various filters depending on the applicable
standards.
5
MT9041B
Advance Information
For the MT9041B, two internal elements determine
the jitter attenuation. This includes the internal 1.9Hz
low pass loop filter and the phase slope limiter. The
phase slope limiter limits the output phase slope to
5ns/125us. Therefore, if the input signal exceeds this
rate, such as for very large amplitude low frequency
input jitter, the maximum output phase slope will be
limited (i.e., attenuated) to 5ns/125us.
The MT9041B has nine outputs with three possible
input frequencies for a total of 27 possible jitter
transfer functions. However, the data sheet section
on AC Electrical Characteristics - Jitter Transfer
specifies transfer values for only three cases, 8kHz
to 8kHz, 1.544MHz to 1.544MHz and 2.048MHz to
2.048MHz. Since all outputs are derived from the
same signal, these transfer values apply to all
outputs.
It should be noted that 1UI at 1.544MHz is 644ns,
which is not equal to 1UI at 2.048MHz, which is
488ns. Consequently, a transfer value using different
input and output frequencies must be calculated in
common units (e.g. seconds) as shown in the
following example.
What is the T1 and E1 output jitter when the T1 input
jitter is 20UI (T1 UI Units) and the T1 to T1 jitter
attenuation is 18dB?
A
 –----- 20 
usually made with large input jitter signals (e.g. 75%
of the specified maximum jitter tolerance).
Frequency Accuracy
Frequency accuracy is defined as the absolute
tolerance of an output clock signal when it is not
locked to an external reference, but is operating in a
free running mode. For the MT9041B, the Freerun
accuracy is equal to the Master Clock (OSCi)
accuracy.
Capture Range
Also referred to as pull-in range. This is the input
frequency range over which the synchronizer must
be able to pull into synchronization. The MT9041B
capture range is equal to ±230ppm minus the
accuracy of the master clock (OSCi). For example, a
±32ppm master clock results in a capture range of
±198ppm.
Lock Range
This is the input frequency range over which the
synchronizer
must
be
able
to
maintain
synchronization. The lock range is equal to the
capture range for the MT9041B.
Phase Slope
OutputT 1 = InputT 1 ×10
18
 –------- 20 
OutputT 1 = 20 ×10
= 2.5UI ( T 1 )
( 1UIT 1 )
OutputE1 = OutputT 1 × ---------------------( 1UIE1 )
( 644ns )
OutputE1 = OutputT 1 × ------------------- = 3.3UI ( T 1 )
( 488ns )
Using the above method, the jitter attenuation can be
calculated for all combinations of inputs and outputs
based on the three jitter transfer functions provided.
Phase slope is measured in seconds per second and
is the rate at which a given signal changes phase
with respect to an ideal signal. The given signal is
typically the output signal. The ideal signal is of
constant frequency and is nominally equal to the
value of the final output signal or final input signal.
Phase Continuity
Note that the resulting jitter transfer functions for all
combinations of inputs (8kHz, 1.544MHz, 2.048MHz)
and
outputs
(8kHz,
1.544MHz,
2.048MHz,
4.096MHz, 8.192MHz, 16.384MHz) for a given input
signal (jitter frequency and jitter amplitude) are the
same.
Phase continuity is the phase difference between a
given timing signal and an ideal timing signal at the
end of a particular observation period. Usually, the
given timing signal and the ideal timing signal are of
the same frequency. Phase continuity applies to the
output of the synchronizer after a signal disturbance
due to a reference switch or a mode change. The
observation period is usually the time from the
disturbance, to just after the synchronizer has settled
to a steady state.
Since intrinsic jitter
attenuation will appear
jitter signals than for
accurate jitter transfer
In the case of the MT9041B, the output signal phase
continuity is maintained to within ±5ns at the
instance (over one frame) of mode changes. The
total phase shift may accumulate up to ±200ns over
6
is always present, jitter
to be lower for small input
large ones. Consequently,
function measurements are
MT9041B
Advance Information
many frames. The rate of change of the ±200ns
phase shift is limited to a maximum phase slope of
approximately 5ns/125us. This meets the Bellcore
GR-1244-CORE maximum phase slope requirement
of 7.6ns/125us (81ns/1.326ms).
Phase Lock Time
Applications
This section contains MT9041B application specific
details for clock and crystal operation, reset
operation and power supply decoupling.
Master Clock
This is the time it takes the synchronizer to phase
lock to the input signal. Phase lock occurs when the
input signal and output signal are not changing in
phase with respect to each other (not including jitter).
The MT9041B can use either a clock or crystal as
the master timing source.
Lock time is very difficult to determine because it is
affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) synchronizer loop filter
iv) synchronizer limiter
In Freerun Mode, the frequency tolerance at the
clock outputs is identical to the frequency tolerance
of the source at the OSCi pin. For applications not
requiring an accurate Freerun Mode, tolerance of the
master timing source may be ±100ppm. For
applications requiring an accurate Freerun Mode,
such as Bellcore GR-1244-CORE, the tolerance of
the master timing source must be no greater than
±32ppm.
Although a short lock time is desirable, it is not
always possible to achieve due to other synchronizer
requirements. For instance, better jitter transfer
performance is achieved with a lower frequency loop
filter which increases lock time. And better (smaller)
phase slope performance (limiter) results in longer
lock times. The MT9041B loop filter and limiter were
optimized to meet the AT&T TR62411 jitter transfer
and phase slope requirements. Consequently, phase
lock time, which is not a standards requirement, may
be longer than in other applications. See AC
Electrical Characteristics - Performance for
maximum phase lock time.
Another consideration in determining the accuracy of
the master timing source is the desired capture
range. The sum of the accuracy of the master timing
source and the capture range of the MT9041B will
always equal ±230ppm. For example, if the master
timing source is ±100ppm, then the capture range
will be ±130ppm.
Clock Oscillator - when selecting a Clock Oscillator,
numerous parameters must be considered. These
include absolute frequency, frequency change over
temperature, output rise and fall times, output levels
and duty cycle. See AC Electrical Characteristics.
MT9041B and Network Specifications
MT9041B
The MT9041B fully meets all applicable PLL
requirements (intrinsic jitter, jitter tolerance, jitter
transfer, frequency accuracy, capture range and
phase change slope) for the following specifications.
1. Bellcore GR-1244-CORE Issue 1, June 1995 for
Stratum 4 Enhanced and Stratum 4
2. AT&T TR62411 (DS1) December 1990 for Stratum
4 Enhanced and Stratum 4
3. ANSI T1.101 (DS1) February 1994 for Stratum 4
Enhanced and Stratum 4
4. ETSI 300 011 (E1) April 1992 forSingle Access
and Multi Access
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. ITU-T I.431 March 1993
OSCi
+5V
+5V
20MHz OUT
GND
0.1uF
OSCo
No Connection
Figure 5 - Clock Oscillator Circuit
7
MT9041B
Advance Information
For applications requiring ±32ppm clock accuracy,
the following clock oscillator module may be used.
CTS CXO-65-HG-5-C-20.0MHz
Frequency:
20MHz
Tolerance:
25ppm 0C to 70C
Rise & Fall Time:
8ns (0.5V 4.5V 50pF)
Duty Cycle:
45% to 55%
The output clock should be connected directly (not
AC coupled) to the OSCi input of the MT9041B, and
the OSCo output should be left open as shown in
Figure 5.
Crystal Oscillator - Alternatively, a Crystal
Oscillator may be used. A complete oscillator circuit
made up of a crystal, resistor and capacitors is
shown in Figure 6.
Frequency:
20MHz
Tolerance:
As required
Oscillation Mode:
Fundamental
Resonance Mode:
Parallel
Load Capacitance:
32pF
Maximum Series Resistance:
35Ω
Approximate Drive Level:
1mW
e.g., CTS R1027-2BB-20.0MHZ
(±20ppm absolute, ±6ppm 0C to 50C, 32pF, 25Ω)
Reset Circuit
A simple power up reset circuit with about a 50us
reset low time is shown in Figure 7. Resistor RP is for
protection only and limits current into the RST pin
during power down conditions. The reset low time is
not critical but should be greater than 300ns.
MT9041B
MT9041B
+5V
OSCi
R
10kΩ
20MHz
1MΩ
RST
56pF
39pF
3-50pF
RP
1kΩ
OSCo
100Ω
C
10nF
1uH
1uH inductor: may improve stability and is optional
Figure 6 - Crystal Oscillator Circuit
Power Supply Decoupling
The MT9041B has two VDD (+5V) pins and two VSS
(GND) pins. Power and decoupling capacitors should
be included as shown in Figure 8.
C1
0.1uF
+
The accuracy of a crystal oscillator depends on the
crystal tolerance as well as the load capacitance
tolerance. Typically, for a 20MHz crystal specified
with a 32pF load capacitance, each 1pF change in
load capacitance contributes approximately 9ppm to
the frequency deviation. Consequently, capacitor
tolerances, and stray capacitances have a major
effect on the accuracy of the oscillator frequency.
Figure 7 - Power-Up Reset Circuit
18
The trimmer capacitor shown in Figure 6 may be
used to compensate for capacitive effects. If
accuracy is not a concern, then the trimmer may be
removed, the 39pF capacitor may be increased to
56pF, and a wider tolerance crystal may be
substituted.
The crystal should be a fundamental mode type - not
an overtone. The fundamental mode crystal permits
a simpler oscillator circuit with no additional filter
components and is less likely to generate spurious
responses. The crystal specification is as follows.
8
15
+
MT9041B
1
5
C2
0.1uF
Figure 8 - Power Supply Decoupling
MT9041B
Advance Information
MT9041B
MT9074
Link 0
TTIP
F0o
F0i
C4b
OUT
RTIP
E1.5o
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
RRING
LOS
+ 5V
C4o
TRING
To Controller
Interrupt
REF
20MHz
OSCi
CLOCK
Out
20MHz ±32ppm
FS1
FS2
MS
RST
1kΩ
10kΩ
+ 5V
10nF
MT9074
Links 1-7
TTIP
TRING
RTIP
1 TO 8
MUX
F0i
C4b
E1.5o
RRING
LOS
To Controller
Interrupt
Figure 9 - Multiple E1 Reference Sources with MT9041B
Multiple E1 Reference Sources with MT9041B
In this example 8 E1 link framers (MT9074) are
connected to a common system backplane clock
using the MT9041B. Each of the extracted clocks
E1.5o go to a mux which selects one of the eight
input clocks as the reference to the MT9041B. The
clock choice is made by a controller using the loss of
signal pin LOS from the MT9074s to qualify potential
references. In the event of loss of signal by one of
the framers, an interrupt signals the controller to
choose a different reference clock. Disturbances in
the generated system backplane clocks C4b and F0b
are minimized by the phase slope limitations of the
MT9041B PLL. This ensures system integrity and
minimizes the effect of clock switchover on
downstream trunks.
9
MT9041B
Advance Information
Absolute Maximum Ratings* - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
Supply voltage
VDD
-0.3
7.0
V
2
Voltage on any pin
VPIN
-0.3
VDD+0.3
V
3
Current on any pin
IPIN
20
mA
4
Storage temperature
TST
125
°C
5
PLCC package power dissipation
PPD
900
mW
-55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
Supply voltage
2
Operating temperature
Sym
Min
Typ
Max
Units
VDD
4.5
5.0
5.5
V
TA
-40
25
85
°C
DC Electrical Characteristics* - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
2
Supply current with:OSCi = 0V
OSCi = Clock
Sym
Min
Max
Units
IDDS
0.5
mA
Outputs unloaded
IDD
60
mA
Outputs unloaded
3
TTL high-level input voltage
VIH
2.0
4
TTL low-level input voltage
VIL
5
CMOS high-level input voltage
VCIH
6
CMOS low-level input voltage
VCIL
7
Schmitt high-level input voltage
VSIH
8
Schmitt low-level input voltage
VSIL
9
Schmitt hysteresis voltage
VHYS
0.4
10
Input leakage current
IIL
-50
11
High-level output voltage
VOH
0.8VDD
12
Low-level output voltage
VOL
V
0.8
0.7VDD
0.3VDD
2.3
0.8
+50
0.2VDD
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
10
Conditions/Notes
V
V
OSCi
V
OSCi
V
RST
V
RST
V
RST
uA
VI=VDD or 0V
V
IOH=4mA
V
IOL=4mA
MT9041B
Advance Information
AC Electrical Characteristics - Performance
Characteristics
1
Sym
Freerun Mode accuracy with OSCi at: 0ppm
Min
Max
Units
Conditions/Notes†
-0
+0
ppm
2-5
2
±32ppm
-32
+32
ppm
2-5
3
±100ppm
-100
+100
ppm
2-5
0ppm
-230
+230
ppm
1,3-5,37
5
±32ppm
-198
+198
ppm
1,3-5, 37
6
±100ppm
-130
+130
ppm
1,3-5,37
30
s
1, 3-11
4
Capture range with OSCi at:
7
Phase lock time
8
Output phase continuity with:
9
mode switch to Normal
200
ns
1-11
10
mode switch to Freerun
200
ns
1, 3-11
45
us/s
1-11, 24
11
Output phase slope
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are
with respect to ground (V SS) unless otherwise stated.
Characteristics
1
Threshold Voltage
2
Rise and Fall Threshold Voltage High
Sym
Schmitt
TTL
CMOS
Units
VT
1.5
1.5
0.5VDD
V
VHM
2.3
2.0
0.7VDD
V
3 Rise and Fall Threshold Voltage Low
VLM
0.8
0.8
0.3VDD
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
* Timing for input and output signals is based on the worst Chislehurst of the combination of TTL and CMOS thresholds.
* See Figure 10.
V
Timing Reference Points
V HM
VT
VLM
ALL SIGNALS
tIRF, tORF
tIRF, tORF
Figure 10 - Timing Parameter Measurement Voltage Levels
11
MT9041B
Advance Information
AC Electrical Characteristics - Input/Output Timing
Characteristics
Min
100
1
Reference input pulse width high or low
tRW
2
Reference input rise or fall time
tIRF
3
8kHz reference input to F8o delay
tR8D
4
1.544MHz reference input to F8o delay
5
Max
Units
ns
10
ns
-21
6
ns
tR15D
337
363
ns
2.048MHz reference input to F8o delay
tR2D
222
238
ns
6
F8o to F0o delay
tF0D
110
134
ns
7
F16o setup to C16o falling
tF16S
11
35
ns
8
F16o hold from C16o rising
tF16H
0
20
ns
9
F8o to C1.5o delay
tC15D
-51
-37
ns
10
F8o to C3o delay
tC3D
-51
-37
ns
11
F8o to C2o delay
tC2D
-13
2
ns
12
F8o to C4o delay
tC4D
-13
2
ns
13
F8o to C8o delay
tC8D
-13
2
ns
14
F8o to C16o delay
tC16D
-13
2
ns
15
C1.5o pulse width high or low
tC15W
309
339
ns
16
C3o pulse width high or low
tC3W
149
175
ns
17
C2o pulse width high or low
tC2W
230
258
ns
18
C4o pulse width high or low
tC4W
111
133
ns
19
C8o pulse width high or low
tC8W
52
70
ns
20
C16o pulse width high or low
tC16WL
24
35
ns
21
F0o pulse width low
tF0WL
230
258
ns
22
F8o pulse width high
tF8WH
111
133
ns
23
F16o pulse width low
tF16WL
52
70
ns
24
Output clock and frame pulse rise or fall time
9
ns
25
Input Controls Setup Time
tS
100
ns
26
Input Controls Hold Time
tH
100
ns
† See "Notes" following AC Electrical Characteristics tables.
12
Sym
tORF
MT9041B
Advance Information
tR8D
REF
8kHz
VT
tRW
tR15D
REF
1.544MHz
tR2D
REF
2.048MHz
tRW
VT
tRW
VT
VT
F8o
NOTES:
1. Input to output delay values
are valid after a TRST or RST
with no further state changes
Figure 11 - Input to Output Timing (Normal Mode)
tF8WH
VT
F8o
tF0D
tF0WL
VT
F0o
tF16WL
VT
F16o
tF16S
tC16WL
tF16H
tC16D
VT
C16o
tC8W
tC8W
tC8D
VT
C8o
tC4W
tC4W
tC4D
VT
C4o
tC2D
tC2W
VT
C2o
tC3W
tC3W
tC3D
VT
C3o
tC15W
tC15D
VT
C1.5o
Figure 12 - Output Timing 1
13
MT9041B
Advance Information
VT
F8o
tS
tH
VT
MS
Figure 13 - Input Controls Setup and Hold Timing
AC Electrical Characteristics - Intrinsic Jitter Unfiltered
Characteristics
Sym
Min
Max
Units
Conditions/Notes†
1
Intrinsic jitter at F8o (8kHz)
0.0002
UIpp
1-11,18-21,25
2
Intrinsic jitter at F0o (8kHz)
0.0002
UIpp
1-11,18-21,25
3
Intrinsic jitter at F16o (8kHz)
0.0002
UIpp
1-11,18-21,25
4
Intrinsic jitter at C1.5o (1.544MHz)
0.030
UIpp
1-11,18-21,26
5
Intrinsic jitter at C2o (2.048MHz)
0.040
UIpp
1-11,18-21,27
6
Intrinsic jitter at C3o (3.088MHz)
0.060
UIpp
1-11,18-21,28
7
Intrinsic jitter at C4o (4.096MHz)
0.080
UIpp
1-11,18-21,29
8
Intrinsic jitter at C8o (8.192MHz)
0.160
UIpp
1-11,18-21,30
9
Intrinsic jitter at C16o (16.384MHz)
0.320
UIpp
1-11,18-21,33
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - C1.5o (1.544MHz) Intrinsic Jitter Filtered
Characteristics
Sym
Min
Max
Units
Conditions/Notes†
1
Intrinsic jitter (4Hz to 100kHz filter)
0.015
UIpp
1-11,18-21,26
2
Intrinsic jitter (10Hz to 40kHz filter)
0.010
UIpp
1-11,18-21,26
3
Intrinsic jitter (8kHz to 40kHz filter)
0.010
UIpp
1-11,18-21,26
4
Intrinsic jitter (10Hz to 8kHz filter)
0.005
UIpp
1-11,18-21,26
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - C2o (2.048MHz) Intrinsic Jitter Filtered
Characteristics
Sym
Min
Max
Units
Conditions/Notes†
1
Intrinsic jitter (4Hz to 100kHz filter)
0.015
UIpp
1-11, 18-21, 27
2
Intrinsic jitter (10Hz to 40kHz filter)
0.010
UIpp
1-11, 18-21, 27
3
Intrinsic jitter (8kHz to 40kHz filter)
0.010
UIpp
1-11, 18-21, 27
4
Intrinsic jitter (10Hz to 8kHz filter)
0.005
UIpp
1-11, 18-21, 27
† See "Notes" following AC Electrical Characteristics tables.
14
MT9041B
Advance Information
AC Electrical Characteristics - 8kHz Input to 8kHz Output Jitter Transfer
Characteristics
Sym
Min
Max
Units
Conditions/Notes†
1
Jitter attenuation for [email protected] input
0
6
dB
1,3,6-11,18-19,21,25,32
2
Jitter attenuation for [email protected] input
6
16
dB
1,3,6-11,18-19,21,25,32
3
Jitter attenuation for [email protected]
input
12
22
dB
1,3,6-11,18-19,21,25,32
4
Jitter attenuation for [email protected]
input
28
38
dB
1,3,6-11,18-19,21,25,32
5
Jitter attenuation for [email protected]
input
42
dB
1,3,6-11,18-19,21,25,32
6
Jitter attenuation for [email protected]
input
45
dB
1,3,6-11,18-19,21,25,32
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 1.544MHz Input to 1.544MHz Output Jitter Transfer
Characteristics
Sym
Min
Max
Units
Conditions/Notes†
1
Jitter attenuation for 1Hz@20UIpp input
0
6
dB
1,4,6-11,18-19,21,26,32
2
Jitter attenuation for 1Hz@104UIpp input
6
16
dB
1,4,6-11,18-19,21,26,32
3
Jitter attenuation for 10Hz@20UIpp input
12
22
dB
1,4,6-11,18-19,21,26,32
4
Jitter attenuation for 60Hz@20UIpp input
28
38
dB
1,4,6-11,18-19,21,26,32
5
Jitter attenuation for 300Hz@20UIpp input
42
dB
1,4,6-11,18-19,21,26,32
6
Jitter attenuation for [email protected] input
45
dB
1,4,6-11,18-19,21,26,32
7
Jitter attenuation for [email protected]
input
45
dB
1,4,6-11,18-19,21,26,32
† See "Notes" following AC Electrical Characteristics tables.
15
MT9041B
Advance Information
AC Electrical Characteristics - 2.048MHz Input to 2.048MHz Output Jitter Transfer
Characteristics
Sym
Min
Max
Units
Conditions/Notes†
1
Jitter at output for [email protected] input
2.9
UIpp
1,5,6-11,18-19,21,27,32
2
with 40Hz to 100kHz filter
0.09
UIpp
1-5,6-11,18-19, 21,27,33
3
Jitter at output for [email protected] input
1.3
UIpp
1,5,6-11,18-19,21,27,32
4
with 40Hz to 100kHz filter
0.10
UIpp
1-5,6-11,18-19,21,2733
5
Jitter at output for [email protected] input
0.80
UIpp
1,5,6-11,18-19,21,27,32
6
with 40Hz to 100kHz filter
0.10
UIpp
1-5,6-11,18-19, 21,27,33
7
Jitter at output for [email protected] input
0.40
UIpp
1,5,6-11,18-19,21,27,32
8
with 40Hz to 100kHz filter
0.10
UIpp
1-5,6-11,18-19, 21,27,33
9
Jitter at output for [email protected] input
0.06
UIpp
1,5,6-11,18-19,21,27,32
10
with 40Hz to 100kHz filter
0.05
UIpp
1-5,6-11,18-19, 21,27,33
11
Jitter at output for [email protected] input
0.04
UIpp
1,5,6-11,18-19,21,27,32
12
with 40Hz to 100kHz filter
0.03
UIpp
1-5,6-11,18-19,21,27,33
13
Jitter at output for [email protected] input
0.04
UIpp
1,5,6-11,18-19,21,27,32
14
with 40Hz to 100kHz filter
0.02
UIpp
1-5,6-11,18-19,21,27,33
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 8kHz Input Jitter Tolerance
Characteristics
Sym
Min
Max
Units
Conditions/Notes†
1
Jitter tolerance for 1Hz input
0.80
UIpp
1,3,6-11,18-19,21-23,25
2
Jitter tolerance for 5Hz input
0.70
UIpp
1,3,6-11,18-19,21-23,25
3
Jitter tolerance for 20Hz input
0.60
UIpp
1,3,6-11,18-19,21-23,25
4
Jitter tolerance for 300Hz input
0.20
UIpp
1,3,6-11,18-19,21-23,25
5
Jitter tolerance for 400Hz input
0.15
UIpp
1,3,6-11,18-19,21-23,25
6
Jitter tolerance for 700Hz input
0.08
UIpp
1,3,6-11,18-19,21-23,25
7
Jitter tolerance for 2400Hz input
0.02
UIpp
1,3,6-11,18-19,21-23,25
8
Jitter tolerance for 3600Hz input
0.01
UIpp
1,3,6-11,18-19,21-23,25
† See "Notes" following AC Electrical Characteristics tables.
16
MT9041B
Advance Information
AC Electrical Characteristics - 1.544MHz Input Jitter Tolerance
Characteristics
Sym
Min
Max
Units
Conditions/Notes†
1
Jitter tolerance for 1Hz input
150
UIpp
1,4,6-11,18-19,21-23,26
2
Jitter tolerance for 5Hz input
140
UIpp
1,4,6-11,18-19,21-23,26
3
Jitter tolerance for 20Hz input
130
UIpp
1,4,6-11,18-19,21-23,26
4
Jitter tolerance for 300Hz input
35
UIpp
1,4,6-11,18-19,21-23,26
5
Jitter tolerance for 400Hz input
25
UIpp
1,4,6-11,18-19,21-23,26
6
Jitter tolerance for 700Hz input
15
UIpp
1,4,6-11,18-19,21-23,26
7
Jitter tolerance for 2400Hz input
4
UIpp
1,4,6-11,18-19,21-23,26
8
Jitter tolerance for 10kHz input
1
UIpp
1,4,6-11,18-19,21-23,26
9
Jitter tolerance for 100kHz input
0.5
UIpp
1,4,6-11,18-19,21-23,26
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 2.048MHz Input Jitter Tolerance
Characteristics
Sym
Min
Max
Units
Conditions/Notes†
1
Jitter tolerance for 1Hz input
150
UIpp
1,5,6-11,18-19,21-23,27
2
Jitter tolerance for 5Hz input
140
UIpp
1,5,6-11,18-19,21-23,27
3
Jitter tolerance for 20Hz input
130
UIpp
1,5,6-11,18-19,21-23,27
4
Jitter tolerance for 300Hz input
50
UIpp
1,5,6-11,18-19,21-23,27
5
Jitter tolerance for 400Hz input
40
UIpp
1,5,6-11,18-19,21-23,27
6
Jitter tolerance for 700Hz input
20
UIpp
1,5,6-11,18-19,21-23,27
7
Jitter tolerance for 2400Hz input
5
UIpp
1,5,6-11,18-19,21-23,27
8
Jitter tolerance for 10kHz input
1
UIpp
1,5,6-11,18-19,21-23,27
9
Jitter tolerance for 100kHz input
1
UIpp
1,5,6-11,18-19,21-23,27
† See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - OSCi 20MHz Master Clock Input
Characteristics
1
2
Sym
Frequency accuracy
(20 MHz nominal)
3
Min
Typ
Max
Units
Conditions/Notes†
-0
0
+0
ppm
15,18
-32
0
+32
ppm
16,19
-100
0
+100
ppm
17,20
40
50
60
%
4
Duty cycle
5
Rise time
10
ns
6
Fall time
10
ns
† See "Notes" following AC Electrical Characteristics tables.
17
MT9041B
Advance Information
† Notes:
Voltages are with respect to ground (VSS) unless otherwise stated.
Supply voltage and operating temperature are as per Recommended Operating Conditions.
Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
1. Normal Mode selected.
2. Freerun Mode selected.
3. 8kHz Frequency Mode selected.
4. 1.544MHz Frequency Mode selected.
5. 2.048MHz Frequency Mode selected.
6. Master clock input OSCi at 20MHz ±0ppm.
7. Master clock input OSCi at 20MHz ±32ppm.
8. Master clock input OSCi at 20MHz ±100ppm.
9. Selected reference input at ±0ppm.
10. Selected reference input at ±32ppm.
11. Selected reference input at ±100ppm.
12. For Freerun Mode of ±0ppm.
13. For Freerun Mode of ±32ppm.
14. For Freerun Mode of ±100ppm.
15. For capture range of ±230ppm.
16. For capture range of ±198ppm.
17. For capture range of ±130ppm.
18. 25pF capacitive load.
19. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp
where1UIpp=1/20MHz.
20. Jitter on reference input is less than 7nspp.
21. Applied jitter is sinusoidal.
22. Minimum applied input jitter magnitude to regain synchronization.
23. Loss of synchronization is obtained at slightly higher input
jitter amplitudes.
24. Within 10ms of the state, reference or input change.
25. 1UIpp = 125us for 8kHz signals.
26. 1UIpp = 648ns for 1.544MHz signals.
27. 1UIpp = 488ns for 2.048MHz signals.
28. 1UIpp = 323ns for 3.088MHz signals.
29. 1UIpp = 244ns for 4.096MHz signals.
30. 1UIpp = 122ns for 8.192MHz signals.
31. 1UIpp = 61ns for 16.384MHz signals.
32. No filter.
33. 40Hz to 100kHz bandpass filter.
34. With respect to reference input signal frequency.
35. After a RST or TRST.
36. Master clock duty cycle 40% to 60%.
18
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