AKM AK4115VQ High feature 192khz 24bit digital audio interface transceiver Datasheet

ASAHI KASEI
[AK4115]
AK4115
High Feature 192kHz 24bit Digital Audio Interface Transceiver
GENERAL DESCRIPTION
The AK4115 is a 24-bit stereo digital audio transceiver that supports sampling rates up to 216kHz. The
channel status bit decoder supports both consumer and professional modes and can automatically
detect Non-PCM bit streams such as Dolby Digital or MPEG. The AK4115 supports a wide array of
features a couple of them being; differential cable driver and receiver support, and an internal PLL that
can support clock sources such as bi-phase and “word clock”. Control of AK4115 is achieved though a
µP or pin-strapping (parallel mode) and it is packaged in a space- saving 64pin-LQFP.
* Dolby Digital is a trademark of Dolby Laboratories.
FEATURES
† AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
† Very Low Jitter Analog PLL
† Synchronous / Asynchronous Mode
† Include Two X’tal Oscillators
† Clock Source: PLL or External Clock
- Reference Clock for PLL:
• Biphase signal: 22kHz to 216kHz
• External Clock (ELRCK pin): 22kHz to 216kHz
† 8-channel Receiver input
- One channel supports Differential Input
† 2-channel Transmission output (Through output or DIT)
- One channel supports Differential Output (RS422 Line Output Buffer)
† Auxiliary Digital Input
† De-emphasis for 32kHz, 44.1kHz and 48kHz
† Detection Functions
- Non-PCM Bit Stream Detection
- DTS-CD Bit Stream Detection
- Sampling Frequency Detection:
(22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz,
176.4kHz and 192kHz)
- Unlock & Parity Error Detection
- DAT Start ID Detection
† Up to 24bit Audio Data Format
† Audio Interface: Master or Slave Mode
† 192-bit Channel Status Buffer
† Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
† Q-subcode Buffer for CD bit stream
2
† Serial µP Interface: 4-wire or I C (max. 400kHz)
† Two Master Clock Outputs: 64fs/128fs/256fs/512fs
† Operating Voltage: 2.7 to 3.6V with 5V Logic Tolerance
† Package: 64pin LQFP
† Ta: -20 to 85°C
MS0573-E-00
2006/12
-1-
ASAHI KASEI
[AK4115]
XTI1
XTO1
AVSS AVDD R VCOM FILT
ACKS
XTI2
XTO2
X'tal
X'tal
Oscillator
Oscillator
PSEL
Clock
Clock
MCKO1
Selector
Generator
MCKO2
Clock
Recovery
RXP0
RXN0
DEM
RX1
8 to 3
DAIF
Input
Decoder
RX2
RX3
RX4
Audio I/F
for RX/TX
LRCK
BICK
SDTO
Selector
RX5
DAUX
RX6
RX7
ELRCK
TX0
Audio I/F
for TX
TXP1
TXN1
EBICK
ELRCK
EMCLK
ASYNC
DIT
Channel
Status
TVDD
TVSS
buffer
Q-subcode
PDN
buffer
DVDD
DVSS
CSN
OVDD
AC-3/MPEG
OVSS
Detect
XTL1
XTL0
VIN
B, C, U
Error &
INT0
VOUT
µP I/F
STATUS
Detect
INT1
CCLK
CDTO
CDTI
P/SN= “L” IIC
Figure 1. AK4115 Block Diagram in serial mode
MS0573-E-00
2006/12
-2-
ASAHI KASEI
[AK4115]
XTI1
XTO1
AVSS AVDD R VCOM FILT
XSEL
ACKS
XTI2
XTO2
X'tal
X'tal
Oscillator
Oscillator
PSEL
Clock
Clock
MCKO1
Selector
Generator
MCKO2
Clock
Recovery
RXP0
RXN0
4 to 2
RX1
Input
RX2
Selector
DEM
DAIF
Audio I/F
Decoder
RX3
for RX/TX
IPS0
LRCK
BICK
SDTO
DAUX
DIF0
DIF1
EBICK
ELRCK
TX0
EMCK
TXP1
TXN1
DIT
TVDD
TVSS
PDN
DVDD
DVSS
OCKS0
OVDD
AC-3/MPEG
OVSS
Detect
XTL1 XTL0
VIN
B,C,U,VOUT
OCKS1
Error &
CM0
STATUS
CM1
Detect
INT0
INT1
P/SN= “H”IPS1
Figure 2. AK4115 Block Diagram in parallel mode
MS0573-E-00
2006/12
-3-
ASAHI KASEI
[AK4115]
„ Ordering Guide
-20 ~ +85 °C
64pin LQFP (0.5mm pitch)
Evaluation board for AK4115
AK4115VQ
AK4115
RX1
AVSS
RXP0
RXN0
ACKS
P/SN
AVDD
VCOM
R
AVSS
56
55
54
53
52
51
50
49
59
57
AVDD
60
58
AVSS
RX2
61
AVDD
RX3
62
IPS0/RX4
63
64
„ Pin Layout
DIF0/RX5
1
48
FILT
TEST
2
47
XTL1
DIF1/RX6
3
46
XTL0
PDN
4
45
PSEL
XSEL/RX7
5
44
IPS1/IIC
DVDD
6
43
BVSS
VIN
7
42
DVSS
DAUX
8
41
DVDD
DVSS
9
40
OCKS0/CSN/CAD0
10
39
OCKS1/CCLK/SCL
MCKO2
11
38
CM1/CDTI/SDA
OVDD
12
37
CM0/CDTO/CAD1
OVSS
13
36
INT1
BICK
14
35
INT0
SDTO
15
34
ELRCK
LRCK
16
33
EMCK
30
31
32
OVDD
OVSS
EBICK
25
TVSS
29
24
TXN1
XTO2
23
TXP1
28
22
TX0
XTI2
21
TVDD
26
20
VOUT
27
19
U
XTI1
18
C
XTO1
17
B
MCKO1
Top View
MS0573-E-00
2006/12
-4-
ASAHI KASEI
[AK4115]
PIN/FUNCTION
No.
1
Pin Name
DIF0
RX5
I/O
I
I
2
TEST
I
3
DIF1
RX6
I
I
4
PDN
I
XSEL
I
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
RX7
DVDD
VIN
DAUX
DVSS
MCKO1
MCKO2
OVDD
OVSS
BICK
SDTO
LRCK
B
C
U
VOUT
TVDD
TX0
TXP1
TXN1
TVSS
XTI1
XTO1
XTI2
XTO2
OVDD
OVSS
EBICK
EMCK
ELRCK
INT0
INT1
I
I
I
O
O
I/O
O
I/O
I/O
I/O
I/O
O
O
O
O
I
O
I
O
I/O
I
I/O
O
O
Function
Audio Data Interface Format #0 Pin in parallel mode
Receiver Channel #5 Pin in serial mode
(Internal biased pin)
TEST Pin
This pin must be connected to AVSS.
Audio Data Interface Format #1 Pin in parallel mode
Receiver Channel #6 Pin in serial mode
(Internal biased pin)
Power-Down Mode Pin
When “L”, the AK4115 is powered-down and reset.
X’tal Oscillator Selection Pin in parallel mode
“L”: X’tal #1 is powered-up.
“H”: X’tal #2 is powered-up.
XSEL pin and XSEL bit are ORed.
Receiver Channel #7 Pin in serial mode
(Internal biased pin)
Digital Power Supply Pin, 3.3V
V-bit Input Pin for Transmitter Output
Auxiliary Audio Data Input Pin
Digital Ground Pin
Master Clock Output #1 Pin
Master Clock Output #2 Pin
Digital Power Supply Pin, 3.3V
Digital Ground Pin
Audio Serial Data Clock Pin
Audio Serial Data Output Pin
Channel Clock Pin
Block-Start Input/Output Pin
C-bit Input/Output Pin
U-bit Input/Output Pin
V-bit Output Pin for Receiver
Input tolerance & TX Output Buffer Power Supply Pin, 3.3V or 5V
Transmit Channel (Through Data) Output #0 Pin
Transmit Channel Positive Output #1 Pin
Transmit Channel Negative Output #1 Pin
Input & TX Output Buffer Ground pin
X’tal #1 Input Pin
X’tal #1 Output Pin
X’tal #2 Input Pin
X’tal #2 Output Pin
Digital Power Supply Pin, 3.3V
Digital Ground Pin
External Serial Data Clock Pin
External Master Clock Input Pin
External Channel Clock Pin
Interrupt #0 Pin
Interrupt #1 Pin
Note 1. Do not allow digital input pins except internal biased pins to float.
MS0573-E-00
2006/12
-5-
ASAHI KASEI
[AK4115]
PIN/FUNCTION (Continued)
No.
37
38
Pin Name
CM0
CDTO
CAD1
CM1
CDTI
I/O
I
O
I
I
I
SDA
I/O
OCKS1
CCLK
I
I
SCL
I
OCKS0
CSN
CAD0
DVDD
DVSS
BVSS
IPS1
I
I
I
I
IIC
I
45
PSEL
I
46
47
48
49
XTL0
XTL1
FILT
AVSS
I
I
O
-
50
R
O
51
VCOM
O
52
AVDD
-
53
P/SN
I
54
ACKS
I
55
RXN0
I
56
RXP0
I
57
58
59
60
61
62
63
AVSS
RX1
AVDD
RX2
AVSS
RX3
AVDD
IPS0
RX4
I
I
I
I
I
39
40
41
42
43
44
64
Function
Master Clock Operation Mode #0 Pin in parallel mode
Control Data Output Pin in serial mode, IIC pin = “L”.
Chip Address #1 Pin in serial mode, IIC pin = “H”.
Master Clock Operation Mode #1 Pin in parallel mode
Control Data Input Pin in serial mode, IIC pin = “L”.
Control Data Pin in serial mode, IIC pin = “H”.
An external pull-up resistor is required.
Output Clock Select #1 Pin in parallel mode
Control Data Clock Pin in serial mode, IIC pin = “L”
Control Data Clock Pin in serial mode, IIC pin = “H”
An external pull-up resistor is required.
Output Clock Select #0 Pin in parallel mode
Chip Select Pin in serial mode, IIC pin = “L”.
Chip Address #0 Pin in serial mode, IIC pin = “H”.
Digital Power Supply Pin, 3.3V
Digital Ground Pin
Substrate Ground Pin
Input Channel Select #1 Pin in parallel mode
IIC Select Pin in serial mode
“L”: 4-wire Serial, “H”: I2C
PLL Source Select Pin
“L”: S/PDIF Input, “H”: ELRCK Input Clock
PSEL pin and PSEL bit are ORed in serial mode.
X’tal Frequency Select #0 Pin
X’tal Frequency Select #1 Pin
PLL Loop Filter Pin
Analog Ground Pin
External Resistor Pin
10kΩ ±1% resistor should be connected to AVSS externally.
Common Voltage Output Pin
4.7µF capacitor should be connected to AVSS externally.
Analog Power Supply Pin, 3.3V
Parallel/Serial Select Pin
“L”: Serial Mode, “H”: Parallel Mode
Master Clock Frequency Auto Setting Mode Pin.
“L”: Disable, “H”: Enable
ACKS pin and ACKS bit are ORed in serial mode.
Receiver Channel #0 Negative Input Pin
(Internal biased pin)
In serial mode, this channel is selected as default channel.
Receiver Channel #0 Positive Input Pin
(Internal biased pin)
In serial mode, this channel is selected as default channel.
Analog Ground Pin
Receiver Channel #1 Pin
(Internal biased pin)
Analog Power Supply Pin, 3.3V
Receiver Channel #2 Pin
(Internal biased pin)
Analog Ground Pin
Receiver Channel #3 Pin
(Internal biased pin)
Analog Power Supply Pin, 3.3V
Input Channel Select #0 Pin in parallel mode
Receiver Channel #4 Pin in serial mode
(Internal biased pin)
Note 1. Do not allow digital input pins except internal biased pins to float.
MS0573-E-00
2006/12
-6-
ASAHI KASEI
[AK4115]
„ Handling of Unused Pin
The unused I/O pin should be processed appropriately as below.
1. Serial Mode (P/SN pin = “L”)
Classification
Analog Input
Analog Output
Digital Input
Digital Output
Digital
Input/Output
Pin Name
RXP0, RXN0, RX7-1
TEST
FILT
VIN, DAUX, XTI1, XTI2, EMCK
MCKO1, MCKO2, VOUT, TX0,
TXP1, TXN1, XTO1, XTO2,
INT0, INT1, CDTO
B, U, C
EBICK, ELRCK
Setting
These pins should be open.
This pin should be connected to AVSS.
This pin should be open.
These pin should be connected to DVSS.
These pins should be open.
These pins should be open when BCU_IC bit is “1”.
These pins should be DVSS when BCU_IO bit is “0”.
These pins should be open in master mode.
These pins should be connected to DVSS in slave
mode.
2. Parallel Mode (P/SN pin = “H”)
Classification
Analog Input
Analog Output
Digital Input
Digital Output
Pin Name
RXP0, RXN0, RX3-1
TEST
FILT
VIN, DAUX, XTI1, XTI2, EMCK,
EBICK, ELRCK
MCKO1, MCKO2, VOUT, TX0,
TXP1, TXN1, XTO1, XTO2,
INT0, INT1, CDTO, B, U, C
Setting
These pins should be open.
This pin should be connected to AVSS.
This pin should be open.
These pin should be connected to DVSS.
These pins should be open.
MS0573-E-00
2006/12
-7-
ASAHI KASEI
[AK4115]
ABSOLUTE MAXIMUM RATINGS
(AVSS, OVSS, DVSS, TVSS, BVSS=0V; Note 2)
Parameter
Symbol
min
max
Power Supplies: Analog
AVDD
-0.3
4.6
Digital
DVDD
-0.3
4.6
Logic Output Buffer
OVDD
-0.3
4.6
Input tolerance and TX Buffer
TVDD
-0.3
6.0
| BVSS – AVSS | (Note 3)
0.3
∆GND1
| BVSS – OVSS | (Note 3)
0.3
∆GND2
| BVSS – DVSS | (Note 3)
0.3
∆GND3
| BVSS – TVSS |
(Note 3)
0.3
∆GND4
Input Current (Any pins except supplies)
IIN
±10
Input Voltage (Note 4)
VIN
-0.3
“TVDD+0.3” or 6.0
Ambient Temperature (Power applied)
Ta
-20
85
Storage Temperature
Tstg
-65
150
Note 2. All voltages with respect to ground.
Note 3. AVSS, OVSS, DVSS, BVSS and TVSS must be connected to the same ground plane.
Note 4. All input pins. The maximum value is low value either “TVDD+0.3V” or “6.0V”.
Pull-up resistor at SDA and SCL pins should be connected to (TVDD+0.3)V or less voltage.
Units
V
V
V
V
V
V
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, OVSS, DVSS, TVSS, BVSS=0V; Note 2)
Parameter
Symbol
min
typ
Power
Analog
AVDD
2.7
3.3
Supplies:
Digital
DVDD
2.7
3.3
(Note 5)
Logic Output Buffer
OVDD
2.7
3.3
Input tolerance and TX Buffer
TVDD
DVDD
5.0
Difference
AVDD – DVDD
-0.3
0
AVDD – OVDD
-0.3
0
OVDD – DVDD
-0.3
0
Note 2. All voltages with respect to ground.
Note 5. The power up sequence among AVDD, DVDD, OVDD and TVDD is not critical.
max
3.6
3.6
3.6
5.5
0.3
0.3
0.3
Units
V
V
V
V
V
V
V
*AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
MS0573-E-00
2006/12
-8-
ASAHI KASEI
[AK4115]
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD, OVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V)
Parameter
Symbol
min
Input Resistance
Zin
Input Voltage
VTH
200
Input Sample Frequency
fs
22
Time deviation Jitter
RX input (PSEL = “0”)
ELRCK input (PSEL = “1”)
Cycle - to - Cycle Jitter
RX input (PSEL = “0”)
ELRCK input (PSEL = “1”)
-
typ
10
-
max
216
Units
kΩ
mVpp
kHz
100
300
-
ps RMS
ps RMS
70
70
-
ps RMS
ps RMS
DC CHARACTERISTICS
(Ta=25°C; AVDD, OVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
Power Supply Current
Normal operation: PDN pin = “H” (Note 6)
AVDD+DVDD+OVDD:
28
42
mA
TVDD:
30
45
mA
Power down:
PDN pin = “L” (Note 7)
AVDD+DVDD+OVDD+TVDD:
10
100
µA
High-Level Input Voltage
VIH
70%DVDD
TVDD
V
Low-Level Input Voltage
VIL
DVSS-0.3
30%DVDD
V
Input Level at AC coupling (Only ELRCK pin)
VAC
0.5
TVDD
Vpp
Except for TX0, TXN1 and TXP1 pins
VOH
OVDD-0.4
V
High-Level Output Voltage
(Iout=-400µA)
Low-Level Output Voltage
VOL
0.4
V
(Except SDA pin: Iout=400µA)
VOL
0.4
V
(
SDA pin: Iout= 3mA)
TX0 Output Level
Output Level (Note 8)
VTXO0
0.4
0.5
0.6
V
TXN1 and TXP1 pins
Professional mode
(TVDD= 4.5 ~ 5.5V)
Output Impedance (Rp + Rn + R1) (Note 9)
RTXPN
88
110
132
Ω
Consumer Mode
(TVDD = 2.7 ~ 5.5V)
Output Level (Note 10)
VTXO1
0.4
0.5
0.6
V
Input Leakage Current
Iin
± 10
µA
Note 6. AVDD, OVDD, DVDD = 3.3V, TVDD=5.0V, CL=20pF, fs=216kHz, X'tal=24.576MHz, Clock Operation Mode 2,
OCKS1=1, OCKS0=1, TX0 output circuit: Figure 23, TX1 output circuit: Figure 25.
AVDD=10mA (typ), OVDD+DVDD=18mA (typ)
Note 7. RX inputs are open and all digital input pins are held TVDD or DVSS.
Note 8. By using Figure 23 or Figure 24.
Note 9. Rp: Output impedance of TXP1, Rn: Output impedance of TXN1, R1 = 75Ω. By using Figure 25.
Note 10. By using Figure 26
MS0573-E-00
2006/12
-9-
ASAHI KASEI
[AK4115]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, OVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Crystal Resonator
Frequency
fXTAL
11.2896
External Clock
Frequency
fECLK
11.2896
Duty
dECLK
40
MCKO1 Output
Frequency
fMCK1
2.816
Duty
dMCK1
40
MCKO2 Output
Frequency
fMCK2
1.408
Duty
dMCK2
40
PLL Clock Recover Frequency (RX7-0)
fpll
22
LRCK Frequency
fs
22
Duty Cycle (at Slave Mode)
dLCK
45
Duty Cycle (at Master Mode)
dLCK
Audio Interface Timing 1
Slave Mode
BICK Period
tBCK
72
BICK Pulse Width Low
tBCKL
27
Pulse Width High
tBCKH
27
tLRB
15
LRCK Edge to BICK “↑” (Note 11)
tBLR
15
BICK “↑” to LRCK Edge (Note 11)
tLRM
LRCK to SDTO (MSB) (3.0V ≤ DVDD,OVDD ≤ 3.6V)
tBSD
BICK “↓” to SDTO
(3.0V ≤ DVDD,OVDD ≤ 3.6V)
tLRM
LRCK to SDTO (MSB) (2.7V ≤ DVDD,OVDD < 3.0V)
tBSD
(2.7
V≤
DVDD,OVDD
<
3.0V)
BICK “↓” to SDTO
tDXH
15
DAUX Hold Time
tDXS
15
DAUX Setup Time
Master Mode
BICK Frequency
fBCK
BICK Duty
dBCK
tMBLR
-15
BICK “↓” to LRCK
tBSD
BICK “↓” to SDTO
tDXH
15
DAUX Hold Time
DAUX Setup Time
tDXS
15
Master Clock Timing 2
EMCK
Frequency
fECLK2
2.816
Duty
dECLK2
40
ELRCK
PLL Lock Range
fEPLL
22
Frequency
fs
22
Duty
dLCK
40
Audio Interface Timing 2
Slave Mode
tEBCK
72
EBICK Period
EBICK Pulse Width Low
tEBCKL
27
Pulse Width High
tEBCKH
27
15
tELRB
ELRCK Edge to BICK “↑”
(Note 12)
tEBLR
15
EBICK “↑” to ELRCK Edge
(Note 12)
15
tEDXH
DAUX Hold Time
tEDXS
15
DAUX Setup Time
Master Mode
EBICK Frequency
fEBCK
EBICK Duty
dEBCK
tEMBLR
-15
EBICK “↓” to ELRCK
tEDXH
15
DAUX Hold Time
DAUX Setup Time
tEDXS
15
typ
max
Units
50
50
50
50
24.576
27.648
60
27.648
60
27.648
60
216
216
55
-
MHz
MHz
%
MHz
%
MHz
%
kHz
kHz
%
%
-
20
20
25
25
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
64fs
50
-
15
15
-
Hz
%
ns
ns
ns
ns
50
50
27.648
60
216
216
60
MHz
%
kHz
kHz
%
-
-
ns
ns
ns
ns
ns
ns
ns
64fs
50
-
15
-
Hz
%
ns
ns
ns
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. EBICK rising edge must not occur at the same time as ELRCK edge.
MS0573-E-00
2006/12
- 10 -
ASAHI KASEI
[AK4115]
SWITCHING CHARACTERISTICS (Continued)
(Ta=25°C; AVDD, OVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF)
Parameter
Symbol
min
Control Interface Timing (4-wire serial mode)
tCCK
200
CCLK Period
80
tCCKL
CCLK Pulse Width Low
tCCKH
80
Pulse Width High
tCDS
50
CDTI Setup Time
tCDH
50
CDTI Hold Time
tCSW
150
CSN “H” Time
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
tDCD
CDTO Delay
tCCZ
CSN “↑” to CDTO Hi-Z
2
Control Interface Timing (I C Bus mode):
fSCL
SCL Clock Frequency
1.3
tBUF
Bus Free Time Between Transmissions
0.6
tHD:STA
Start Condition Hold Time (prior to first clock pulse)
1.3
tLOW
Clock Low Time
0.6
tHIGH
Clock High Time
0.6
tSU:STA
Setup Time for Repeated Start Condition
0
tHD:DAT
SDA Hold Time from SCL Falling
(Note 13)
0.1
tSU:DAT
SDA Setup Time from SCL Rising
tR
Rise Time of Both SDA and SCL Lines
tF
Fall Time of Both SDA and SCL Lines
0.6
tSU:STO
Setup Time for Stop Condition
Cb
Capacitive load on bus
0
tSP
Pulse Width of Spike Noise Suppressed by Input Filter
Reset Timing
PDN Pulse Width
tPW
150
Note 13. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
Note 14. I2C is a registered tradmark of Philips Semiconductors.
MS0573-E-00
typ
max
Units
-
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
400
0.3
0.3
400
50
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
pF
ns
-
-
ns
2006/12
- 11 -
ASAHI KASEI
[AK4115]
„ Timing Diagram
1/fECLK
VIH
XTI
VIL
tECLKH
tECLKL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
1/fMCK1
MCKO1
50%OVDD
tMCKH1
tMCKL1
dMCK1 = tMCKH1 x fMCK1 x 100
= tMCKL1 x fMCK1 x 100
1/fMCK2
MCKO2
50%OVDD
tMCKH2
tMCKL2
dMCK2 = tMCKH2 x fMCK2 x 100
= tMCKL2 x fMCK2 x 100
1/fs
VIH
LRCK
VIL
tLRH
tLRL
dLCK = tLRH x fs x 100
= tLRL x fs x 100
1/fECLK2
VIH
EMCK
VIL
tECLKH2
tECLKL2
dECLK2 = tECLKH2 x fECLK2 x 100
= tECLKL2 x fECLK2 x 100
1/fs
VIH
ELRCK
VIL
tELRH
tELRL
dELCK = tELRH x fs x 100
= tELRL x fs x 100
Figure 3. Clock Timing
MS0573-E-00
2006/12
- 12 -
ASAHI KASEI
[AK4115]
VIH
LRCK
VIL
tBCK
tBLR
tLRB
tBCKL
tBCKH
VIH
BICK
VIL
tLRM
tBSD
50%OVDD
SDTO
tDXS
tDXH
VIH
DAUX
VIL
Figure 4. Serial Interface Timing 1 (Slave Mode)
50%OVDD
LRCK
tMBLR
50%OVDD
BICK
tBSD
50%OVDD
SDTO
tDXS
tDXH
VIH
DAUX
VIL
Figure 5. Serial Interface Timing 1 (Master Mode)
VIH
ELRCK
VIL
tEBCK
tEBLR
tELRB
tEBCKL
tEBCKH
VIH
EBICK
VIL
tEDXS
tEDXH
VIH
DAUX
VIL
Figure 6. Serial Interface Timing 2 (Slave Mode)
MS0573-E-00
2006/12
- 13 -
ASAHI KASEI
[AK4115]
ELRCK
50%OVDD
tEMBLR
50%OVDD
EBICK
tEDXS
tEDXH
VIH
DAUX
VIL
Figure 7. Serial Interface Timing 2 (Master Mode)
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDH
tCDS
CDTI
C1
C0
0
0
VIH
VIL
Hi-Z
CDTO
Figure 8. WRITE/READ Command Input Timing in 4-wire serial mode
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
CDTO
VIL
D3
D2
D1
D0
VIH
VIL
Hi-Z
Figure 9. WRITE Data Input Timing in 4-wire serial mode
MS0573-E-00
2006/12
- 14 -
ASAHI KASEI
[AK4115]
VIH
CSN
VIL
VIH
CCLK
VIL
A1
CDTI
VIH
A0
VIL
tDCD
Hi-Z
CDTO
D7
D6
D5
50%OVDD
Figure 10. READ Data Output Timing 1 in 4-wire serial mode
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D3
D2
D1
D0
50%OVDD
Figure 11. READ Data Input Timing 2 in 4-wire serial mode
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 12. I2C Bus mode Timing
tPW
PDN
VIL
Figure 13. Power Down & Reset Timing
MS0573-E-00
2006/12
- 15 -
ASAHI KASEI
[AK4115]
OPERATION OVERVIEW
„ Non-PCM (Dolby Digital, MPEG, etc) and DTS-CD Bitstream Detection
The AK4115 has a non-PCM bitstream auto-detection function, When the 32-bit mode Non-PCM preamble based on
Dolby “Dolby Digital Data Stream in IEC 60958 Interface” is detected, the NPCM bit sets to “1”. The 96-bit sync code
consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM bit to “1”.
Once the NPCM bit is set to “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync
pattern being detected. When those preambles are detected, the burst preambles Pc (burst information: Figure 51) and Pd
(length code: Figure 52) that follow those sync codes are stored to registers. The AK4115 has also a DTS-CD bitstream
auto-detection function. When the AK4115 detects DTS-CD bitstream, the DTSCD bit sets to “1”. If the next sync code
does not occur within 4096frames, the DTSCD bit sets to “0” until no-PCM bitstream is detected again. The ORed value
of NPCM and DTSCD bits are output to AUTO bit. The AK4115 detects the 14-bit sync word and the 16-bit sync word
of a DTS-CD bitstream, the detection function can be set ON/OFF by DTS14 and DTS16 bits in serial mode. In parallel
mode, the logical OR value of the AUTO and DTS-CD bits are outputted to the INT1 pin. The DTS-CD bit detects both
the 14-bit sync word and the 16-bit sync word.
„ 216kHz Clock Recovery
The integrated low jitter PLL has a wide lock range from 22kHz to 216kHz. The AK4115 has a sampling frequency
detection function (22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz) that
uses either a clock comparison against the X’tal oscillator from the setting of XTL1-0, or the channel status information.
The PLL loses lock when the received sync interval is incorrect.
„ Reference Clock for PLL
The reference clock for the PLL can select the bi-phase signal or the clock supplied from the ELRCK pin. The bi-phase
signals are supplied to RX7-0 pins and the ELRCK pin is supplied to a sampled clock (1fs) from the word clock
(typically used by studio equipment). This is selected by the PSEL bit or the PSEL pin. PSEL bit and PSEL pin are ORed
internally.
PSEL
Reference Clock for PLL
0
RX Input
1
ELRCK Input
Table 1. Setting of PLL Reference Clock
Default
„ PLL Lock Time
The lock time at PSEL = “0” depends on sampling frequency (fs) and FAST bit (See Table 2). FAST bit is useful at lower
sampling frequency and is fixed to “1” in parallel mode. When PSEL is “1”, the lock time is 35ms (max) and is not
related to the setting of the FAST bit. The lock time in Table 2 does not include the power-up time of VCOM voltage.
Therefore, the power-up time of VCOM voltage must be added when PDN pin changes from “L” to “H”. The power-up
time of VCOM voltage is max. 15ms (Capacitor value of VCOM pin = 4.7µF).
PSEL
FAST bit
PLL Lock Time
0
0
≤ (20ms + 384/fs)
0
1
≤ (20ms + 1/fs)
1
≤ 35ms
Table 2. PLL Lock Time (fs: Sampling Frequency)
MS0573-E-00
Default
2006/12
- 16 -
ASAHI KASEI
[AK4115]
„ Word Clock (Studio Sync Clock)
The word clock is used to synchronize clocks among studio equipment and is always synchronized to the sampling
frequency (1fs). The internal PLL generates MCLK, BICK and LRCK from the word clock supplied to the ELRCK pin.
The PLL lock range is 22kHz to 216kHz. The word clock (ELRCK pin) can receive signal levels of 0.5Vpp(min) when
AC coupled. In master mode, the clock phase between ELRCK pin and LRCK pin is within ± 5%. When the AK4115 is
supplied with a bi-phase signal and a word clock (ELRCK), the phase error between the LRCK and ELRCK is within
±1/(128fs). Therefore, use LRCK and not ELRCK for the serial data output stream. When the word clock is not
synchronized to the bi-phase signal, WSYNC bit should be set to “0”.
„ DIT/DIR Mode
The AK4115 operates in either synchronous mode or asynchronous mode. In synchronous mode, transmitter and receiver
are operated by the same clock source. In asynchronous mode, transmitter and receiver are operated by different a
sampling frequencies that are selected by the ASYNC bit. Frequency multiples are not required in asynchronous mode.
1. Synchronous Mode: ASYNC bit = “0”
PSEL and CM1-0 select the clock source and the data source for SDTO. In Mode 2, the clock source is switched from
PLL to X'tal when the PLL goes to the unlock state. In Mode 3, the clock source is fixed to X’tal, but PLL is also
operation and the recovered data such as channel status bit can be monitored. For Mode 2 and Mode 3, it is recommended
that the frequency of X’tal is different from the recovered frequency of the PLL. In Modes 4-6, the PLL source is
ELRCK and MCKO1/2, BICK and LRCK are generated by the PLL. The data source of SDTO is always DAUX.
Mode
PSEL
CM1
CM0
UNLOCK
PLL Status
0
0
0
0
-
ON
1
0
0
1
-
OFF
X'tal Status
ON
(Note 16)
ON
2
0
1
0
0
ON
ON
3
0
1
1
1
-
ON
ON
4
1
0
0
-
ON
5
1
0
1
-
OFF
ON
ON
ON
(Note 16)
ON
6
1
1
0
0
ON
ON
Clock source
PLL
(RX)
X'tal
PLL
(RX)
X'tal
X’tal
PLL
(ELRCK)
X’tal
PLL
(ELRCK)
X'tal
Clock I/O
SDTO
Note 17
RX
Note 17
DAUX
Note 17
RX
Note 17
Note 17
DAUX
DAUX
Note 17
DAUX
Note 17
DAUX
Note 17
DAUX
1
ON
ON
Note 17
DAUX
Note 15. ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note 16: When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is OFF.
Note 17. MCKO1/2, BICK, LRCK
Table 3. Clock operation for DIT/DIR in synchronous mode
MS0573-E-00
2006/12
- 17 -
ASAHI KASEI
[AK4115]
XTI1
XTO1
X'tal
ACKS
XTI2
XTO2
X'tal
XSEL
Oscillator
Oscillator
Clock
Recovery
Clock Selector
Clock
MCKO1
(CM1-0)
Generator
MCKO2
RXP0
RXN0
RX1
DEM
8 to 3
DAIF
Input
Decoder
RX2
RX3
RX4
LRCK
Audio I/F
BICK
for RX/TX
SDTO
Selector
RX5
DAUX
RX6
RX7
TX0
TXP1
TXN1
DIT
Figure 14. Clocks for DIT/DIR in synchronous mode (PSEL bit = “0”)
XTI1
XTO1
ACKS
XSEL
X'tal
Clock
XTO2
X'tal
Oscillator
Oscillator
Recovery
XTI2
Clock Selector
Clock
MCKO1
(CM1-0)
Generator
MCKO2
RXP0
RXN0
RX1
8 to 2
Audio I/F
RX2
RX3
RX4
for RX/TX
Input
LRCK
BICK
SDTO
Selector
RX5
DAUX
RX6
RX7
ELRCK
TX0
TXP1
TXN1
DIT
Figure 15. Clocks for DIT/DIR in synchronous mode (PSEL bit = “1”)
MS0573-E-00
2006/12
- 18 -
ASAHI KASEI
[AK4115]
2. Asynchronous Mode: ASYNC bit = “1”, PSEL = “0”
When ASYNC bit is “1”, DIT and DIR can operate at different sample rates(non-multiples). In Mode1, Mode2 (When
the PLL is the unlock state) and Mode3, SDTO is fixed “L”. The input timing of DAUX should be synchronized with
ELRCK and EBCIK. The master clock of TX can be selected to either X’tal or EMCK by the MSEL bit (See Table 4).
MSEL bit
Master Clock
0
X’tal
Defalut
1
EMCK
Table 4. Master clock setting for TX in asynchronous mode.
RX
Clock
I/O
TX
Mode
CM1
CM0
UNLOCK
PLL
Status
X'tal
Status
0
0
0
-
ON
ON
(Note 19)
PLL
(RX)
Note 20
RX
1
0
1
-
OFF
ON
X'tal
Note 20
“L”
0
ON
ON
PLL
(RX)
Note 20
RX
1
ON
ON
X'tal
Note 20
“L”
-
ON
ON
X'tal
Note 20
“L”
2
1
3
1
Clock
Source
SDTO
0
1
Clock
Source
X’tal
or
EMCK
(Note 22)
X’tal
or
EMCK
X’tal
or
EMCK
X’tal
or
EMCK
X’tal
or
EMCK
Clock
I/O
Note 21
Note 21
Note 21
Note 21
Note 21
Note 18. ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note 19 When the X’tal is not used as clock comparison for sampling frequency detection (i.e. XTL1,0 = “1,1”), the
X’tal is OFF.
Note 20: MCKO1/2, BICK, LRCK
Note 21. EMCK or X’tal, EBICK, ELRCK, DAUX
Note 22. When X’tal is OFF, the clock source supports EMCK only.
Table 5. Clock operation for DIT/DIR in asynchronous mode
XTI1
XTO1
ACKS
XTI2
X'tal
XSEL
X'tal
Oscillator
Oscillator
Clock
Recovery
XTO2
Clock Selector
Clock
MCKO1
(CM1-0)
Generator
MCKO2
RXP0
RXN0
RX1
DEM
8 to 3
DAIF
Input
Decoder
RX2
RX3
RX4
Audio I/F
for RX
“L”
Selector
RX5
LRCK
BICK
SDTO
MSEL
RX6
EMCK
RX7
Audio I/F
TX0
for TX
TXP1
TXN1
ELRCK
EBICK
DAUX
DIT
Figure 16. Clocks for DIT/DIR in asynchronous mode
MS0573-E-00
2006/12
- 19 -
ASAHI KASEI
[AK4115]
„ Block start, Channel status bit, User bit and Validity bit
The AK4115 can control and monitor block start, channel status bits, user bits and validity bit for RX and TX. B, C and
U pins are bi-directional and the direction of input/output can be selected by the BCU_IO bit. B, C, U and VOUT pins
become “L” (BCU_IO bit = “1”) in an unlocked state of Mode 2.
a. Serial mode & Except AES3 mode (P/SN pin = “L”, AES3 bit = “0”)
Block
RX
ASYNC BCU_IO
Start
Channel
Validity
bit
bit
User bit
(B pin)
Status bit
bit
VOUT pin
0
Input
CR191-0 bits
N/A
VRX bit
(Note 24)
0
C pin
VRX bit
1
Output
CR191-0 bits
U pin
VOUT pin
(Note 23)
(Note 24)
0
Input
CR191-0 bits
N/A
1
VRX bit
TX
Channel
Status bit
C pin
CT191-0 bits
(Note 25)
User bit
U pin
CT191-0 bits
All
“0” data
(Note 27)
C pin
CT191-0 bits
(Note 25)
U pin
C pin
VOUT pin
All
CR191-0 bits
U pin
VRX bit CT191-0 bits
“0” data
(Note 23)
(Note 24)
Note 23. Channel status bit for RX can be monitored by both C pin and CR191-0 bits.
Note 24. Validity bit for RX can be monitored by both VOUT pin and VRX bit.
Note 25. C pin and CT191-0 bits are ORed internally.
Note 26. VIN pin and VTX bit are ORed internally.
Note 27. When UDIT bit is “1”, the recovered U bits are used for DIT(DIR-DIT loop mode of U bit).
1
Output
Validity
bit
VIN pin
VTX bit
(Note 26)
VIN pin
VTX bit
(Note 26)
VIN pin
VTX bit
(Note 26)
VTX bit
Table 6. Block start, Channel Status bit, User bit and Validity bit in serial mode except AES3 mode (N/A: Not available)
MS0573-E-00
2006/12
- 20 -
ASAHI KASEI
[AK4115]
b. Serial mode & AES3 mode (P/SN pin = “L”, AES3 bit = “1”, ASYNC bit = “0”)
Block
RX
TX
DIF1 BCU_IO
Start
Channel
Validity
Channel
bit
bit
User bit
User bit
(B pin)
Status bit
bit
Status bit
VOUT pin
CR191-0 bits
C pin
VRX bit
0
Input
SDTO pin
SDTO pin
CT191-0 bits
U pin
SDTO pin
(Note 28)
(Note 32)
(Note 31)
0
C pin
VOUT pin
U pin
All
CR191-0 bits
VRX bit
1
Output
SDTO pin
CT191-0 bits
“0” data
SDTO pin
SDTO pin
(Note 30)
(Note 35)
(Note 29)
(Note 31)
VOUT pin
CR191-0 bits
CT191-0 bits
VRX bit
DAUX
0
Input
SDTO pin
SDTO pin
DAUX pin
SDTO pin
pin
(Note 28)
(Note 33)
(Note 31)
1
C pin
VOUT pin
U pin
CT191-0 bits
CR191-0 bits
VRX bit
DAUX
1
Output
SDTO pin
DAUX pin
SDTO pin
SDTO pin
pin
(Note 30)
(Note 33)
(Note 29)
(Note 31)
Note 28. Channel status bit for RX can be monitored by CR191-0 bits and SDTO pin.
Note 29. Channel status bit for RX can be monitored by C pin, CR191-0 bits and SDTO pin.
Note 30. User bit for RX can be monitored by U pin and SDTO pin.
Note 31. Validity bit for RX can be monitored by VOUT pin, VRX bit and SDTO pin.
Note 32. C pin and CT191-0 bits are ORed internally.
Note 33. Channel status bit can select either CT191-0 bits or DAUX pin by the setting of CTX bit.
Note 34. VIN pin and VTX bit are ORed internally.
Note 35. When UDIT bit is “1”, the recovered U bits are used for DIT(DIR-DIT loop mode of U bit).
Validity
bit
VIN pin
VTX bit
(Note 34)
VIN pin
VTX bit
(Note 34)
DAUX
pin
DAUX
pin
Table 7. Block start, Channel Status bit, User bit and Validity bit in serial mode & AES3 mode
c. Parallel mode (P/SN pin = “H”)
Block
Start
Channel
(B pin)
Status bit
Output
RX
User bit
TX
Validity bit
Channel Status bit
User bit
Validity
bit
Default value of
All
VIN pin
CT191-0 bits
“0” data
Table 8. Block start, Channel Status bit, User bit and Validity bit in parallel mode
C pin
U pin
VOUT pin
MS0573-E-00
2006/12
- 21 -
ASAHI KASEI
[AK4115]
1. Channel Status bit
1-1. RX
The data recovered from the bi-phase input signal is stored in CR191-0 bits. When the BCU_IO bit = “1”, the channel
status bits are available on the C pin according to the block signal timing. The channel status bits are outputted from
SDTO pin with audio data in AES3 mode.
1-2. TX
The channel status bit can controlled by the CT191-0 bits. When BCU_IO bit is “0”, the channel status bits are also
controlled by C pin. CT191-0 bits and the signal on the C pin are ORed internally.
The input to C pin is ignored in AES3 mode. When CTX bit is set to “0”, the channel status bits on DAUX pin are
outputted with audio data from TX. When CTX bit is set to “1”, the values of CT191-0 bits are outputted with audio data
from TX.
When the CCRE bit is “1” and AK4115 is in professional mode (bit0 = “1”), the CRC code can be generated according
to the professional mode definition in the AES3 standard. When the CCRE bit is “0”, the CRC data is not generated and
the data from the CT191-0 bits is passed to the TX directly. In the consumer mode (bit0 = “0”), the CRC code is not
generated.
In the consumer mode (bit0 = “0”), bits20-23(audio channel) must be controlled by the CT20 bit. When the CT20 bit is
“1”, the AK4115 corresponds to “stereo mode”, bits20-23 are set to “1000”(left channel) in sub-frame 1, and is set to
“0100”(right channel) in sub-frame 2. When the CT20 bit is “0”, bits20-23 is set to “0000” in both sub-frame 1 and
sub-frame 2.
All CR191-0 bits are transferred to CT191-0 bits when the CTRAN bit changes from “0” to “1”. The transferred
CT191-0 bits are valid after the next block start signal is detected. CTRAN bit goes to “0” after finishing the transfer.
Don’t write to the CT191-0 bits when the CTRAN bit = “1”.
2. User bit
2-1. RX
When the BCU_IO bit is “1”, the recovered user bit is available on the U pin according to block start timing. The user
bits are outputted from SDTO pin with audio data in AES3 mode.
2-2. TX
When the BCU_IO bit is “0”, the user bit is sent to the U pin according to block start timing. When BCU_IO bit is “1”
and the ASYNC bit is “0”(synchronous mode), the user bit is controlled by the UDIT bit. When the UDIT bit is “0”, user
bit is set to “0”. When the UDIT bit is “1”, the recovered U bits are used for DIT( DIR-DIT loop mode of U bit). This
mode (UDIT bit = “1”) is enabled when the PLL is locked. The input to U pin is ignored in AES3 mode and the user bits
on DAUX pin are outputted with audio data from TX.
MS0573-E-00
2006/12
- 22 -
ASAHI KASEI
[AK4115]
3. Validity bit
3-1. RX
In synchronous mode, the validity bit is available on the VOUT pin according to block start timing. In asynchronous
mode, the validity bit is available on the VOUT pin according to LRCK timing. The VRX bit is available in both modes.
The validity bit is outputted from SDTO pin with audio data in AES3 mode.
3-2. TX
The validity bit is controlled by the VIN pin or the VTX bit. Since the validity bit does not usually update every
sub-frame cycle, it can be controlled by the VIN pin according to LRCK timing in synchronous mode. In asynchronous
mode, it can be controlled by the VIN pin according to ELRCK timing. When the validity bit timing is synchronized with
the block start timing , the BCU_IO bit should be “0”. In asynchronous mode, the validity bit cannot be controlled by the
VIN pin when BCU_IO bit is set to “0”.
The input to VIN pin and VTX bit are ignored in AES3 mode and the validity bit on DAUX is outputted with audio data
from TX.
4. Block Start Signal Timing
In synchronous mode, the block start signal timing depends on LRCK. In asynchronous mode, it depends on ELRCK.
The channel status, user and validity bits are captured with the current audio sample. When the block start signal is an
input (BCU_IO bit = “0”), the block start signal should stay high for more than one sub-frame. When the block start
signal is an output (BCU_IO bit = “1”), the block start signal goes high at the start of frame 0 and remains high until the
end of frame 39.
The input to B pin is ignored in AES3 mode and the B bit on DAUX is used as the block start timing.
B (Input)
Don’t care
Don’t care
B (Output)
C (or U,V)
C(R191) C(L0)
C(R0)
C(L1)
C(L38)
C(R39) C(L40)
R0
L1
L38
R39
LRCK(ELRCK)
(Except I2S)
LRCK(ELRCK)
(I2S)
SDTO (DAUX)
R191
L0
L40
Figure 17. B, C, U, V Input/output timings
MS0573-E-00
2006/12
- 23 -
ASAHI KASEI
[AK4115]
„ Master Clock Output
The AK4115 has two master clock outputs, MCKO1 and MCKO2. MCKO2 has two modes. These modes can be selected
by the XMCK bit.
1) When XMCK bit = “0”
These clocks are derived from either the recovered clock or the X'tal oscillator. The frequencies of the master clock
outputs (MCKO1 and MCKO2) are set by OCKS0 and OCKS1 as shown in Table 9. The 512fs clock is changed into the
256fs clock when sampling frequency is 96kHz or 192kHz. The 512fs or 256fs clock is changed into the 128fs clock
when sampling frequency is 192kHz.
No.
0
1
2
3
OCKS1
0
0
1
1
OCKS0
0
1
0
1
MCKO1 pin MCKO2 pin
X’tal
256fs
256fs
256fs
256fs
128fs
256fs
512fs
256fs
512fs
128fs
64fs
128fs
Table 9. Master Clock Output Frequency
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Default
2) When XMCK bit = “1”
MCKO2 outputs the input clock of the XTI pin. The settings of CM1-0 and OCKS1-0 bits are ignored. The output
frequency can be set by the DIV bit. MCKO1 outputs a clock that is selected by the CM1-0 bits and OCKS1-0 bits.
XMCK bit DIV bit MCKO2 Clock Source
MCKO2 Frequency
1
0
X’tal (Note 36)
x1
1
1
X’tal (Note 36)
x 1/2
Note 36. MCKO2 Clock Source is selected by XSEL bit.
Table 10. Select output frequency of MCKO2
„ Master Clock Auto Setting Mode
The master clock auto setting mode detects the MCLK/LRCK ratio (selects Normal/Double/Quad automatically). When
ACKS is “1”, this mode is enabled. The frequencies of MCKO1 and MCKO2 are shown in Table 11. In this mode, the
settings of OCKS1-0 are ignored. This mode is only supported when the sampling frequency detection circuit is enabled
in PLL mode.(refer to “Sampling Frequency and Pre-emphasis Detection” section.) When ELRCK is selected and
XTL1-0 = “11”, this mode is not supported. In X’tal mode, the frequencies of MCKO1/MCKO2 depend upon OCKS1-0.
The ACKS pin and ACKS bit are ORed internally.
Mode
MCKO1
MCKO2
Sampling Frequency Range
Normal Speed
512fs
256fs
22kHz to 48kHz
Double Speed
256fs
128fs
64kHz to 96kHz
Quad Speed
128fs
64fs
176.4kHz to 216kHz
Table 11. Master Clock Frequency Select (Master Clock Auto Setting Mode)
MS0573-E-00
2006/12
- 24 -
ASAHI KASEI
[AK4115]
„ X’tal Oscillator
The AK4115 has two X’tal oscillators. They can not operate at the same time. The operation of the X’tal oscillator is
selected by the XSEL bit or the XSEL pin.
XSEL
0
1
Status
X’tal #1
X’tal #2
Power-Up
Power-Down
Power-Down
Power-Up
Table 12. Setting of X’tal oscillator
The following circuits are available to feed the clock to the XTI1/2 pins of AK4115.
1) X’tal
XTI1/2
AK4115
XTO1/2
Note: External capacitance depends upon the crystal oscillator (typ. 5-10pF)
Figure 18. X’tal mode
2) External clock
XTI1/2
External Clock
AK4115
XTO1/2
Figure 19. External clock mode
3) Fixed to the Clock Operation Mode 0
XTI1/2
AK4115
XTO1/2
Figure 20. OFF mode
MS0573-E-00
2006/12
- 25 -
ASAHI KASEI
[AK4115]
„ Sampling Frequency and Pre-emphasis Detection
The AK4115 has two methods for detecting the sampling frequency:
1. Clock comparison between the recovered clock and X’tal oscillator
2. Sampling frequency information from channel status
The method is selected by the XTL1,0 pins. When XTL1, 0 = “1,1”, the sampling frequency is detected by the channel
status sampling frequency information. The detected frequency is available on the FS3-0 bits.
XTL1
XTL0
0
0
1
1
0
1
0
1
X’tal Frequency
X’tal #1
X’tal #2
11.2896MHz
12.288MHz
12.288MHz
11.2896MHz
24.576MHz
22.5792MHz
(Use channel status)
(Use channel status)
Table 13. Reference X’tal frequency
Except XTL1, 0 = “1,1”
Register output
fs
FS3
0
0
0
0
0
0
1
1
1
1
1
FS2
FS1
Clock comparison
(Note 37)
FS0
Default
XTL1, 0 = “1, 1”
Consumer
mode
(Note 38)
Byte3
Bit3,2,1,0
0000
0001
0010
0011
0100
0110
Professional mode
(Note 39)
Byte0
Byte4
Bit7,6
Bit6,5,4,3
01
0000
(Others)
10
0000
11
0000
00
1001
00
0001
0
44.1kHz
0
0
44.1kHz ± 3%
0
0
1
Reserved
0
48kHz
1
0
48kHz ± 3%
0
32kHz
1
1
32kHz ± 3%
1
22.05kHz
0
0
22.05kHz ± 3%
1
24kHz
1
0
24kHz ± 3%
0
1
1
64kHz
64kHz ± 3%
0
88.2kHz
1000
00
0
0
1010
88.2kHz ± 3%
0
96kHz
1010
00
1
0
0010
96kHz ± 3%
1
0
0
176.4kHz
1
1
0
0
0
0
1
011
176.4kHz ± 3%
1
192kHz
1110
00
1
0
0011
192kHz ± 3%
Note 37: At least ±3% range is identified as the value in the Table 14. In case of intermediate frequency of those
two, FS3-0 bits indicate no value. When the frequency is ≥ 3% over 192kHz or ≤ 3% under 22kHz,
FS3-0 bits may indicate “0001”, “0101”, “0111” or “1001”.
Note 38: In consumer mode, Byte3 Bit3-0 are copied to FS3-0 bits.
Note 39. In professional mode, FS3-0 bit indicates “0001” except for frequency shown by Table 14.
Table 14. fs Information
MS0573-E-00
2006/12
- 26 -
ASAHI KASEI
[AK4115]
The pre-emphasis information is detected and reported on PEM bit. This informations is extracted from channel 1 by
default. It can be switched to channel 2 by the CS12 bit in control register.
Byte 0
Bits 3-5
0
OFF
≠ 0X100
1
ON
0X100
Table 15. PEM in Consumer Mode
PEM
Pre-emphasis
Byte 0
Bits 2-4
0
OFF
≠110
1
ON
110
Table 16. PEM in Professional Mode
PEM
Pre-emphasis
„ De-emphasis Filter Control
The AK4115 includes a digital de-emphasis filter (tc=50/15µs). This is an IIR filter corresponds to four sampling
frequencies (32kHz, 44.1kHz and 48kHz). When DEAU bit=“1”, the de-emphasis filter is enabled automatically by the
sampling frequency and pre-emphasis information in the channel status. The AK4115 is in this mode by default. In
parallel control mode, the AK4115 is always placed in this mode and the status bits in channel 1 control the de-emphasis
filter. In serial control mode, DEM0/1 bits control the de-emphasis filter when the DEAU bit is “0”. The internal
de-emphasis filter is bypassed and the recovered data is available without any change if either the pre-emphasis or
de-emphasis mode is OFF. When the PEM bit is “0”, the internal de-emphasis filter is always bypassed.
PEM
1
1
1
1
0
FS3
0
0
0
FS2
0
0
0
x
x
FS1
0
1
1
FS0
0
0
1
x
x
(Others)
Mode
44.1kHz
48kHz
32kHz
OFF
OFF
Table 17. De-emphasis Auto Control at DEAU bit = “1” (Default)
PEM
1
1
1
1
0
DEM1
0
0
1
1
x
DEM0
0
1
0
1
x
Mode
44.1kHz
OFF
48kHz
32kHz
OFF
Default
Table 18. De-emphasis Manual Control at DEAU bit = “0”
MS0573-E-00
2006/12
- 27 -
ASAHI KASEI
[AK4115]
„ System Reset and Power-Down
The AK4115 has a power-down mode for all circuits by PDN pin and can be partially powerd-down by PWN bit. The
RSTN bit initializes the register and resets the internal timing. In parallel mode, only the control by PDN pin is enabled.
The AK4115 should be reset once by bringing PDN pin = “L” upon power-up.
PDN Pin:
All analog and digital circuits are placed in power-down and reset mode by bringing PDN pin= “L”. All the
registers are initialized, and clocks are stopped. Reading/Writing to the registers is disabled.
RSTN Bit (Address 00H; D0):
All the registers except PWN and RSTN bits are initialized by bringing RSTN bit = “0”. The internal timing is
also initialized. Writing to registers is not available except the PWN and RSTN bits. Reading from the
registers is disabled.
PWN Bit (Address 00H; D1):
The clock recovery is initialized by bringing PWN bit = “0”. In this case, the clocks are stopped. The registers
are not initialized and the mode settings are maintained. Writing and reading to the registers are enabled.
„ Bi-phase Input
Eight receiver inputs (RX7-0) are available in serial mode and four receiver inputs (RX3-0) are available in parallel mode.
Each input includes an amplifier for unbalanced mode that can accept a signal of 200mVpp or more. IPS2-0 selects the
receiver channel.
IPS2 bit
0
0
0
0
1
1
1
1
IPS1 bit
IPS0 bit
INPUT Data
0
0
RX0
0
1
RX1
1
0
RX2
1
1
RX3
0
0
RX4
0
1
RX5
1
0
RX6
1
1
RX7
Table 19. Recovery Data Select in serial mode
Default
IPS1 pin
IPS0 pin
INPUT Data
0
0
RX0
0
1
RX1
1
0
RX2
1
1
RX3
Table 20. Recovery Data Select in parallel mode
MS0573-E-00
2006/12
- 28 -
ASAHI KASEI
[AK4115]
„ Bi-phase Output
The AK4115 has two transmitter outputs, TX0 and TX1. TX0 is a loop-through output that is selected from the RX input.
TX0 output is selected from RX7-0 by the OPS00, OPS01 and OPS02 bits. In parallel mode, the source of the
loop-through output from TX0 is fixed to RX0.
TX1 accepts output from RX7-0 or the transmitter (DIT; the data from DAUX is transformed to IEC60958 format.). TX1
also has a true RS422 line driver (differential output). The source of the loop-through output from TX1 is selected from
RX7-0 by the OPS10, OPS11 and OPS12 bits. When the DIT bit is set to “1”, TX1 is transmitted to DAUX data. In
parallel mode, TX1 is fixed to DIT.
OPS02
0
0
0
0
1
1
1
1
DIT
0
0
0
0
0
0
0
0
1
OPS01
OPS00
Output Data
0
0
RX0
0
1
RX1
1
0
RX2
1
1
RX3
0
0
RX4
0
1
RX5
1
0
RX6
1
1
RX7
Table 21. Output Data Select for TX0
OPS12
OPS11
OPS10
Output Data
0
0
0
RX0
0
0
1
RX1
0
1
0
RX2
0
1
1
RX3
1
0
0
RX4
1
0
1
RX5
1
1
0
RX6
1
1
1
RX7
x
x
x
DAUX
Table 22. Output Data Select for TX1
MS0573-E-00
Default
Default
2006/12
- 29 -
ASAHI KASEI
[AK4115]
„ Bi-phase signal input circuit
0.1uF
RX
75Ω
Coax
75Ω
AK4115
Figure 21. Consumer Input Circuit (Coaxial Input)
Note: For coaxial input, if a coupling level to this input from the next RX input line
pattern exceeds 50mV, there may be an incorrect operation. In this case, it is
possible to lower the coupling level by adding this decoupling capacitor.
Optical Receiver
Optical
Fiber
470
RX
O/E
AK4115
Figure 22. Consumer Input Circuit (Optical Input)
0.1uF
RXP
110Ω
Twisted
Pair
110Ω
0.1uF
RXN
AK4115
Table 23. Professional Input Circuit (Balanced Input)
Note. When RXN pin is unused, RXN pin must be AC-coupled to ground.
For coaxial input in serial mode, the input level of RX line is small, so care must be taken to avoid crosstalk among the
RX input lines. In this case, a shield is recommended between the input lines. In parallel mode, RX3-0 is available and
RX7-4 change to other pins for audio format control. Those pins must be fixed to “H” or “L”.
MS0573-E-00
2006/12
- 30 -
ASAHI KASEI
[AK4115]
„ Bi-phase signal output circuit
The AK4115 includes two TX output buffers. The output level is proportional to TVDD voltage. The T1 in Figure 23,
Figure 24, Figure 25 and Figure 26 is a transformer of 1:1. The resistor values should use ±1% accuracy.
1. Line Driver of TX0
The output level of TX0 is 0.5V ± 20% using the external resistor network in consumer mode.
R1
TX0
75Ω cable
R2
TVDD R1
R2
3.3V 240Ω 150Ω
3.0V 220Ω 150Ω
5.0V 430Ω 150Ω
TVSS
T1
Figure 23. TX0 External Resistor Network 1
Note: When the AK4115 is in the power-down mode (PDN pin = “L”), power supply current can be reduced by using an
AC coupling capacitor as shown in Figure 24, since TX1 output is undetermined in power-down mode.
0.1uF
R1
TX0
75Ω cable
R2
TVDD R1
R2
3.3V
240Ω 150Ω
3.0V
220Ω 150Ω
5.0V
430Ω 150Ω
TVSS
T1
Figure 24. TX0 External Resistor Network 2
2. Line Driver of TX1
2-1. Professional Mode (TVDD = 4.5V ∼ 5.5V)
The TX1 has an RS422 line driver when TVDD is 5V±10%. The AES3 specification states that the line driver shall have
a balanced output with an internal impedance of 110 ohms ±20% and also requires a balanced output drive capability of 2
to 7 volts peak-to-peak into 110 ohm load. The internal impedance of the RS422 driver along with a series resistors of 75
ohms realizes this requirement.
75Ω
0.1uF
TXP1
110Ω cable
TXN1
T1
Figure 25. Professional Output Driver Circuit
MS0573-E-00
2006/12
- 31 -
ASAHI KASEI
[AK4115]
2-2. Consumer Mode (TVDD = 2.7V ∼ 5.5V)
For consumer use , the specifications require an output impedance of 75 ohms ±20% and a driver level of 0.5 ± 20%
volts peak to peak. A combination of R1 in parallel with R2 meets this requirement. The outputs can be set to ground by
resetting the device or a software mute.
0.1uF
R1
TXP1
75Ω cable
R2
TXN1
TVDD R1
3.3V
270Ω
3.0V
240Ω
5.0V
430Ω
open
T1
R2
150Ω
150Ω
150Ω
Figure 26. Consumer Output Driver Circuit at AC coupling
„ PLL Loop Filter
C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. The value of PLL
Loop Filter includes temperature deviation. Be careful to minimize the noise into the FILT pin. When the Studio Sync
mode is not used, FILT pin can be open.
AK4115
FILT
R
C2
C1
AVSS
Figure 27. PLL Loop Filter
C1 [nF]
C2 [pF]
R [Ω]
24k ± 5%
10 ± 30%
100 ± 30%
Table 24. Value of PLL Loop Filter
MS0573-E-00
2006/12
- 32 -
ASAHI KASEI
[AK4115]
„ Q-subcode buffers
The AK4115 has a Q-subcode buffer for CD applications. The AK4115 takes the Q-subcode into registers by the
following method.
1. The sync word (S0,S1) is constructed of at least 16 “0”s.
2. The start bit is “1”.
3. Those 7bits Q-W follows to the start bit.
4. The distance between two start bits are 8-16 bits.
The QINT bit in the control register goes to “1” when the new Q-subcode differs from old one, and goes to “0” when the
QINT bit is read.
S0
S1
S2
S3
:
S97
S0
S1
S2
S3
:
1
0
0
1
1
:
1
0
0
1
1
:
2
3
4
5
6
7
8
*
0
0
0
0
0
0
0
0…
0
0
0
0
0
0
0
0…
Q2 R2 S2
T2
U2 V2 W2 0…
Q3 R3 S3
T3
U3 V3 W3 0…
:
:
:
:
:
:
:
:
Q97 R97 S97 T97 U97 V97 W97 0…
0
0
0
0
0
0
0
0…
0
0
0
0
0
0
0
0…
Q2 R2 S2
T2
U2 V2 W2 0…
Q3 R3 S3
T3
U3 V3 W3 0…
:
:
:
:
:
:
:
:
↑
Q
Q2
Q3 Q4
CTRL
Q5
Q6
Q7 Q8
ADRS
(*) number of "0" : min=0; max=8.
Figure 28. Configuration of U-bit(CD)
Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
TRACK NUMBER
INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE
SECOND
FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO
ABSOLUTE MINUTE
ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME
CRC
G(x)=x^16+x^12+x^5+1
Figure 29. Q-subcode
Addr
Register Name
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
D6
D4
D3
D2
D1
D0
Q9
Q8
···
···
Q17
Q16
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
Q81
Q80
···
···
Figure 30. Q-subcode register
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
Q3
Q11
···
···
···
···
···
···
···
Q75
Q2
Q10
···
···
···
···
···
···
···
Q74
MS0573-E-00
D5
2006/12
- 33 -
ASAHI KASEI
[AK4115]
„ Error Handing for RX (PSEL = “0”)
The followings nine events the INT0 and INT1 pins to trigger the interrupt condition. When the PLL is OFF (Clock
Operation Mode 1), INT0 and INT1 pins go to “L”.
1. UNLCK
: PLL unlock state detect
“1” when the PLL loses lock. The AK4115 loses lock when the time between two preambles is not
correct or when those preambles are not correct.
2. PAR
: Parity error or bi-phase coding error detection
“1” when parity error or bi-phase coding error is detected, updated every sub-frame cycle.
3. AUTO
: Non-Linear PCM or DTS-CD Bit Stream detection
The OR function of NPCM and DTSCD bits.is available at the AUTO bit.
4. VRX
: Validity flag detection
“1” when validity flag is detected. Updated every sub-frame cycle.
5. AUDION
: Non-audio detection
“1” when the “AUDION” bit in recovered channel status indicates “1”. Updated every block cycle.
6. STC
: Sampling frequency or pre-emphasis information change detection
When either FS3-0 bit or PEM bit is changed, it maintains “1” during 1 sub-frame.
7. QINT
: U-bit Sync flag
“1” when the Q-subcode differs from the old one. Updated every sync code cycle for Q-subcode.
8. CINT
: Channel status sync flag
“1” when received C bit differs from the old one. Updated every block cycle.
9. DAT
: DAT Start ID detect
“1” when the category code indicates “DAT” and “DAT Start ID” is detected. When DCNT bit is
“1”, it does not indicate “1” even if “DAT Start ID” is detected again within “3841 x LRCK”.
When “DAT Start ID” is detected again after “3840 x LRCK” passed, it indicates “1”. When
DCNT bit is “0”, it indicates “1” every “DAT Start ID” detection.
MS0573-E-00
2006/12
- 34 -
ASAHI KASEI
[AK4115]
1. Parallel Mode
In parallel mode, the INT0 pin outputs the ORed signal between UNLCK and PAR. The INT1 pin outputs the ORed
signal between AUTO and AUDION. Once INT0 goes ”H”, it maintains “H” for 1024/fs cycles after all error events are
removed. Table 25 shows the state of each output pins when the INT0/1 pin is “H”.
Event
Pin
UNLCK
PAR
AUTO
AUDION
INT0
INT1
SDTO
VOUT
1
x
x
x
“L”
“L”
“H”
Note 40 Previous Data
0
1
x
x
Output
0
0
x
x
“L”
Output
Output
x
x
1
x
“H”
Note 41
Note 42
Note 43
x
x
x
1
x
x
0
0
“L”
Note 40. INT1 pin outputs “L” or “H” in accordance with the ORed signal between AUTO and
AUDION.
Note 41. INT0 pin outputs “L” or “H” in accordance with the ORed signal between UNLCK and
PAR.
Note 42. SDTO pin outputs “L”, “Previous Data” or “Normal Data” in accordance with the ORed
signal between UNLCK and PAR.
Note 43. VOUT pin outputs “L” or “Normal operation” in accordance with the ORed signal
between PAR and UNCLK.
Table 25. Error Handling in parallel mode (x: Don’t care)
2. Serial Mode
In serial mode, the INT1 and INT0 pins output an ORed signal based on the above nine interrupt events. When masked,
the interrupt event does not affect the operation of the INT1-0 pins (the masks do not affect the registers in 07H and DAT
bit). Once INT0 pin goes to “H”, it remains “H” for 1024/fs (this value can be changed by the EFH1-0 bits) after all
events not masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared.
UNLCK, PAR, AUTO, AUDION and VRX bits in Address=07H indicate the interrupt status events above in real time.
Once QINT, CINT and DAT bits go to “1”, it stays “1” until the register is read.
When the AK4115 loses lock, the channel status bit, user bit, Pc and Pd are initialized. In this initial state, INT0 pin
outputs the ORed signal between UNLCK and PAR bits. INT1 pin outputs the ORed signal between AUTO and
AUDION bits.
UNLCK
1
0
x
Event
Pin
PAR
Others
SDTO
VOUT
x
x
“L”
“L”
1
x
Previous Data
Output
x
x
Output
Output
Table 26. Error Handling in serial mode (x: Don’t care)
MS0573-E-00
TX
Output
Output
Output
2006/12
- 35 -
ASAHI KASEI
Error
(UNLOCK, PAR,..)
[AK4115]
(Error)
INT0 pin
Hold Time (max: 4096/fs)
INT1 pin
Hold Time = 0
Register
(PAR,CINT,QINT)
Hold “1”
Reset
Register
(others)
Command
MCKO,BICK,LRCK
(UNLOCK)
READ 07,08H
Free Run
(fs: around 6kHz)
MCKO,BICK,LRCK
(except UNLOCK)
SDTO
(UNLOCK)
SDTO
(PAR error)
Previous Data
SDTO
(others)
VOUT pin
(UNLOCK)
VOUT pin
(except UNLOCK)
Normal Operation
Figure 31. INT0/1 pin timing
MS0573-E-00
2006/12
- 36 -
ASAHI KASEI
[AK4115]
PDN pin ="L" to "H"
Initialize
Read (07H, 08H)
INT0/1 pin ="H"
No
Yes
Release
Muting
Mute DA C output
Read (07H, 08H)
(Each Error Handling)
Read 07H, 08H
(Res ets registers)
No
INT0/1 pin ="H"
Yes
Figure 32. Error Handling Sequence Example 1
MS0573-E-00
2006/12
- 37 -
ASAHI KASEI
[AK4115]
PDN pin ="L" to "H"
Initialize
Read (07H, 08H)
INT1 pin ="H"
No
Yes
Read (07H, 08H)
and
Detect QSUB= “1”
(Read Q-buffer)
QCRC = “0”
No
New data
is invalid
Yes
INT1 pin ="L"
No
Yes
New data
is valid
Figure 33. Error Handling Sequence Example (for Q/CINT)
MS0573-E-00
2006/12
- 38 -
ASAHI KASEI
[AK4115]
„ Error Handing for ELRCK (PSEL = “1”)
The followings two events cause the INT0 and INT1 pins to show the status of the interrupt conditions. When the PLL is
OFF (Clock Operation Mode 1), the INT0 and INT1 pins go to “L”.
1.
UNLCK : PLL unlock state detect
“1” when the PLL loses lock.
The AK4115 loses lock when the phase difference between the current ELRCK and the previous
ELRCK is more than 5% after “4 x fs”.
The PLL is locked when the phase difference between the current ELRCK and the pervious
ELRCK is less than 2% after “256 x fs”.
When the PLL loses lock, the PLL goes to a free running state. The sampling frequency is
typically 11kHz in this case.
2.
FS3-0
: Sampling frequency detection
FS3-0 bits are updated every “128 x fs”. When FS3-0 bits are changed, the STC bit is not changed
and the INT0 and INT1 pins go to “H” after “1 x fs”
In this mode, INT0 does not have the hold function. Therefore, INT0 and INT1 go to “L” at the same time when those
events are removed. Each INT0/1 pins can mask those two events individually.
1. Parallel Mode
In parallel mode, INT0 triggers UNLCK, and INT1 triggers when FS3-0 bits are changed. INT0 and INT1 go “L” after
each event is removed.
2. Serial Mode
In serial mode, INT1 and INT0 outputs an ORed signal based on the two interrupt events shown above. When masked,
the interrupt event does not affect operation of the INT1-0.
UNLCK
1
0
Event
Pin
Change of FS3-0 bits
SDTO
x
“L”
1
Output
Table 27. Error Handling (x: Don’t care)
MS0573-E-00
TX
Output
Output
2006/12
- 39 -
ASAHI KASEI
[AK4115]
„ Audio Serial Interface Format
1. LRCK, BICK, SDTO and DAUX
In serial mode, the DIF2-0 bits can select eight serial audio data formats as shown in Table 28. In parallel mode, the DIF0
and DIF1 pins can select four serial audio data format as shown in Table 29. In Mode0-7, the serial data is MSB-first, 2's
complement format. The SDTO is clocked out on the falling edge of BICK and DAUX is latched on the rising edge of
BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to 128fs at fs=48kHz.
If the data word length is equal or less than 20bit (Mode0-2), the LSBs in the sub-frame are truncated. In Mode 3-7, the
last 4LSBs are auxiliary data (see Figure 34).
When the Parity Error, Bi-phase Error or Frame Length Error occurs in a sub-frame, the AK4115 continues to output the
last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4115
outputs “0” from SDTO. If DAUX is used, the data is transformed and outputted from SDTO. DAUX is used in Clock
Operation Mode 1, 3 and unlock state of Mode 2.
The input data format to DAUX should be left justified except in Mode5 and 7(Table 28). In Mode5 or 7, both the input
data format of DAUX and output data format of SDTO are I2 S. Mode 6 and 7 are Slave Modes that corresponds to the
Master Mode of Mode4 and 5. In Slave Mode, LRCK and BICK should be synchronized with MCKO1/2.
When AES3 bit is set to “1”, SDTO becomes AES3 mode. The serial data is LSB-first, 2’s complement format. The V,
C, U and B bits behind the audio data are added. The B bit goes to “1” when the B-sync in preamble is detected (Figure
39).
When DAUX is sent to SDTO, the data format depends on DIF0 bit. When DIF0 bit is set to “0”, the received MSB-first,
24bit MSB justified is converted to LSB-first, 24bit MSB justified. Then the only audio data is converted and V, U, C
and B bits set to “0”. When DIF0 bit is set to “1”, the AES3 format received from DAUX pin is maintained and is sent to
SDTO pin. Mode 8-9 support only synchronous mode (ASYNC bit = “0”).
sub-frame of IEC958
0
3 4
preamble
7 8
11 12
27 28 29 30 31
Aux.
V U C P
LSB
MSB
MSB
LSB
23
0
AK4115 Audio Data (MSB First)
Figure 34. Bit configuration
MS0573-E-00
2006/12
- 40 -
ASAHI KASEI
Mode
0
1
2
3
4
5
6
7
8
9
[AK4115]
AES3
bit
0
0
0
0
0
0
0
0
1
1
Mode
4
5
6
7
DIF2
bit
0
0
0
0
1
1
1
1
0
0
DIF1
bit
0
0
1
1
0
0
1
1
0
0
DIF0
bit
0
1
0
1
0
1
0
1
0
1
DIF1
pin
0
0
1
1
DIF0
pin
0
1
0
1
LRCK
I/O
24bit, Left justified
24bit, Left justified
H/L
O
24bit, I2S
24bit, I2S
L/H
O
24bit, Left justified
24bit, Left justified
H/L
I
24bit, I2S
24bit, I2S
L/H
I
Table 29. Audio data format in parallel mode
DAUX
SDTO
24bit, Left justified
16bit, Right justified
24bit, Left justified
18bit, Right justified
24bit, Left justified
20bit, Right justified
24bit, Left justified
24bit, Right justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, I2S
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, I2S
24bit, Left justified
AES3 Mode
AES Mode
AES3 Mode
Table 28. Audio data format in serial mode
DAUX
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
H/L
O
H/L
O
BICK
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
64fs
64fs
I/O
O
O
O
O
O
O
I
I
O
O
BICK
SDTO
64fs
64fs
64-128fs
64-128fs
I/O
O
O
I
I
2. EMCK, ELRCK, EBICK and DAUX
In asynchronous mode, the audio data format of DAUX is selected by EDIF1-0 bits. The clock source of master clock
selects X’tal or EMCK by the MSEL bit. In parallel mode, this function is not supported.
Mode
EDIF1 bit
4
5
6
7
0
0
1
1
ELRCK
EBICK
I/O
I/O
0
24bit, Left justified
H/L
O
64fs
O
1
24bit, I2S
L/H
O
64fs
O
0
24bit, Left justified
H/L
I
64-128fs
I
1
24bit, I2S
L/H
I
64-128fs
I
Table 30. Audio data format in asynchronous mode
EDIF0 bit
DAUX
Default
In asynchronous mode, the frequecny of EMCK/X’tal selects 128fs, 256fs or 512fs. It is controlled by ECKS1-0 bit.
ECKS1
0
0
1
1
ECKS0
EMCK Frequency
0
512fs
1
256fs
0
128fs
1
N/A
Table 31. EMCK Frequency
MS0573-E-00
fs(max)
54kHz
108kHz
216kHz
-
Default
2006/12
- 41 -
Default
ASAHI KASEI
[AK4115]
LRCK(0)
0
1
2
15
16
17
31
0
1
2
15
16
17
31
0
1
BICK
(0:64fs)
15
14
1
0
15
14
1
0
SDTO(0)
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 35. Mode 0 Timing
LRCK(0)
0
1
2
9
10
12
11
31
0
1
2
9
10
11
12
31
0
1
0
1
BICK
(0:64fs)
23
22
21
20
1
0
23
22
21
20
1
0
SDTO(0)
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 36. Mode 3 Timing
LRCK
ELRCK
BICK
EBICK
(64fs)
0
1
23
SDTO(0)
DAUX(I)
2
21
22 21
22
2
24
23
1
31
0
0
1
2
23 22
21
3
22
2
24
23
1
31
0
23 22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 37. Mode 4, 6 Timing
Mode4 : LRCK, BICK, ELRCK, EBICK : Output
Mode6 : LRCK, BICK, ELRCK, EBICK: Input
LRCK
ELRCK
BICK
EBICK
(64fs)
SDTO(0)
DAUX(I)
0
1
2
22
23 22 21
24
23
2
1
25
31
0
1
2
23 22
0
21
22
3
23
2
1
24
25
0
31
0
1
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 38. Mode 5, 7 Timing
MS0573-E-00
Mode5 : LRCK, BICK, ELRCK, EBICK : Output
Mode7 : LRCK, BICK, ELRCK, EBICK : Input
2006/12
- 42 -
ASAHI KASEI
[AK4115]
LRCK(o)
0
1
2
24
25
27
26
28
31
0
1
2
24
25
26
27
31
28
0
1
BICK(o)
(64fs)
SDTO(0)
DAUX(I)
0
1
2
23
V
U
C
0
B
1
2
23
V
U
C
B
0
1
23:MSB, 0:LSB
V: Validity, C: C-bit, U:U-bit, B:B sync
Lch Data
Rch Data
Figure 39. AES3 Mode
„ Serial Control Interface
1. 4-wire serial control mode (IIC pin = “L”)
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2-bits, C1-0 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 8-bits) and Control data (MSB first, 8-bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 24th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the registers to their default values. When the
state of P/SN pin is changed, the AK4115 should be reset by PDN pin = “L”. CSN should be brought “H” after each
word.
CSN
0
1
7
8
9
2
3
4
5
6
0
0
0
0
0 R/W A7 A6
10
11
12
13
14
15 16
A5
A4 A3 A2
A1
A0 D7 D6 D5 D4 D3 D2 D1 D0
A5
A4 A3
A1
A0 D7 D6 D5 D4 D3 D2 D1 D0
17
18
19
20
21
22
23
CCLK
CDTI
WRITE
C1 C0
Hi-Z
CDTO
CDTI
READ
CDTO
C1 C0
0
0
0
0
0 R/W A7 A6
A2
Hi-Z
C1-C0:
R/W:
A7-A0:
D7-D0:
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Chip Address (Fixed to “00”)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 40. 4-wire Serial Control I/F Timing
MS0573-E-00
2006/12
- 43 -
ASAHI KASEI
[AK4115]
2. I2C bus control mode (IIC pin = “H”)
AK4115 supports a fast-mode I2C-bus system (max : 400kHz).
2-1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4115
recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the
SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the
SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the
master device.
2-1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 41. Data transfer
2-1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 42. START and STOP conditions
MS0573-E-00
2006/12
- 44 -
ASAHI KASEI
[AK4115]
2-1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will
release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the
acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4115 will
generates an acknowledge after each byte has been received.
In the read mode, the slave, AK4115 will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP
condition.
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 43. Acknowledge on the I2C-bus
2-1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If the
transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the
SDA line.
The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device
address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0
pin) set them. The eighth bit (LSB) of the first byte (R/W bit) defines whether a write or read condition is requested by
the master. A “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed.
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins.)
Figure 44. The First Byte
MS0573-E-00
2006/12
- 45 -
ASAHI KASEI
[AK4115]
2-2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of AK4115.
After receipt the start condition and the first byte, the AK4115 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4115. The format is MSB first,
8-bits.
A7
A6
A5
A4
A3
A2
A1
A0
Figure 45. The Second Byte
After receipt of the second byte, the AK4115 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8-bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 46. Byte structure after the second byte
The AK4115 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4115 generates an acknowledge, and awaits the next data again. The master can
transmit more than one word instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal 5-bit address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceed 49H prior to generating the stop condition, the address counter will “roll over” to
00H and the previous data will be overwritten.
S
T
A
R
T
SDA
Slave
Address
Register
Address(n)
Data(n)
S
T
Data(n+x) O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 47. WRITE Operation
MS0573-E-00
2006/12
- 46 -
ASAHI KASEI
[AK4115]
2-3. READ Operations
Set R/W bit = “1” for the READ operation of AK4115.
After transmission of a data, the master can read next address’s data by generating the acknowledge instead of
terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal 5-bit address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 49H prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The AK4115 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
2-3-1. CURRENT ADDRESS READ
The AK4115 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1.
After receipt of the slave address with R/W bit set to “1”, the AK4115 generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. If the master does
not generate an acknowledge to the data but generate the stop condition, the AK4115 discontinues transmission.
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Figure 48. CURRENT ADDRESS READ
2-3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues the start condition, slave address(R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4115 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the
master does not generate an acknowledge to the data but generate the stop condition, the AK4115 discontinues
transmission.
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 49. RANDOM READ
MS0573-E-00
2006/12
- 47 -
ASAHI KASEI
[AK4115]
„ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
CLK & Power Down Control
CS12
BCU
CM1
CM0
OCKS1 OCKS0
PWN
RSTN
01H
Format & De-em Control
AES3
DIF2
DIF1
DIF0
DEAU
DEM1
DEM0
ACKS
02H
Input/ Output Control 0
TX1E
OPS12
OPS11
OPS10
TX0E
OPS02
OPS01
OPS00
IPS2
IPS1
IPS0
03H
Input/ Output Control 1
EFH1
EFH0
UDIT
BCU_IO
DIT
04H
INT0 MASK
MQIT0
MAUT0
MCIT0
MULK0
MV0
MSTC0 MAUD0 MPAR0
05H
INT1 MASK
MQIT1
MAUT1
MCIT1
MULK1
MV1
MSTC1 MAUD1 MPAR1
06H
DAT Mask & DTS Detect
DIV
XMCK
FAST
DCNT
DTS16
DTS14
07H
Receiver Status 0
QINT
AUTO
CINT
UNLCK
VRX
STC
AUDION
PAR
08H
Receiver Status 1
FS3
FS2
FS1
FS0
PEM
DAT
DTSCD
NPCM
09H
Receiver Status 2
0
0
0
0
0
0
QCRC
CCRC
0AH Clock Control
TX1NE
0
MCK2E MCK1E ASYNC WSYNC
XSEL
PSEL
0BH
TX Control
MSEL
ECKS1
ECKS0
EDIF1
EDIF0
CTRAN
CCRE
VTX
0CH
RX Channel Status Byte 0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
•
23H
•
RX Channel Status Byte 23
•
•
•
•
•
•
•
•
CR191
CR190
CR189
CR188
CR187
CR186
CR185
CR184
24H
TX Channel Status Byte 0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
•
3BH
•
TX Channel Status Byte 23
•
CT191
•
CT190
•
CT189
•
CT188
•
CT187
•
CT186
•
CT185
•
CT184
3CH
Burst Preamble Pc Byte 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
3DH Burst Preamble Pc Byte 1
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
3EH
Burst Preamble Pd Byte 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
3FH
Burst Preamble Pd Byte 1
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
40H
Q-subcode Address / Control
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
41H
Q-subcode Track
Q17
Q16
Q15
Q14
Q13
Q12
Q11
Q10
42H
Q-subcode Index
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
43H
Q-subcode Minute
Q33
Q32
Q31
Q30
Q29
Q28
Q27
Q26
44H
Q-subcode Second
Q41
Q40
Q39
Q38
Q37
Q36
Q35
Q34
45H
Q-subcode Frame
Q49
Q48
Q47
Q46
Q45
Q44
Q43
Q42
46H
Q-subcode Zero
Q57
Q56
Q55
Q54
Q53
Q52
Q51
Q50
47H
Q-subcode ABS Minute
Q65
Q64
Q63
Q62
Q61
Q60
Q59
Q58
48H
Q-subcode ABS Second
Q73
Q72
Q71
Q70
Q69
Q68
Q67
Q66
49H
Q-subcode ABS Frame
Q81
Q80
Q79
Q78
Q77
Q76
Q75
Q74
0
0
0
0
0
0
CTX
0
4AH Optional Control
MDAT1 MDAT0
Notes:
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values.
All data can be written to the register even if PWN bit is “0”.
Data must not be written to addresses 4BH through FFH.
MS0573-E-00
2006/12
- 48 -
ASAHI KASEI
[AK4115]
„ Register Definitions
Reset & Initialize
Addr
Register Name
00H CLK & Power Down Control
R/W
Default
D7
CS12
R/W
0
D6
BCU
R/W
1
D5
CM1
R/W
0
D4
CM0
R/W
0
D3
D2
OCKS1 OCKS0
R/W
R/W
0
0
D1
PWN
R/W
1
D0
RSTN
R/W
1
RSTN: Timing Reset & Register Initialize
0: Reset & Initialize
1: Normal Operation (Default)
PWN: Power Down
0: Power Down
1: Normal Operation (Default)
OCKS1-0: Master Clock Frequency Select (See Table 9)
CM1-0: Master Clock Operation Mode Select (See Table 3 and Table 5)
BCU: Block start & C/U Output Mode when BCU_IO bit is “1”
0: B, C and U pins output “L”.
1: B, C, and U pins output the data recovered from biphase signal. (Default)
When BCU_IO bit is “0”, BCU bit is ignored.
CS12: Channel Status Select
0: Channel 1 (Default)
1: Channel 2
Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0,
Pc and Pd. The de-emphasis filter is controlled by channel 1 in the Parallel Mode.
Format & De-emphasis Control
Addr
Register Name
01H Format & De-em Control
R/W
Default
D7
AES3
R/W
0
D6
DIF2
R/W
1
D5
DIF1
R/W
1
D4
DIF0
R/W
0
D3
DEAU
R/W
1
D2
DEM1
R/W
0
D1
DEM0
R/W
1
D0
ACKS
R/W
0
ACKS: Master clock Auto Setting Mode
0: Disable (Default)
1: Enable
DEM1-0: 32, 44.1, 48kHz De-emphasis Control (See Table 18)
DEAU: De-emphasis Auto Detect Enable
0: Disable
1: Enable (Default)
DIF2-0, AES3: Audio Data Format Control (See Table 28)
MS0573-E-00
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ASAHI KASEI
[AK4115]
Input/Output Control
Addr
Register Name
02H Input/ Output Control 0
R/W
Default
D7
TX1E
R/W
1
D6
D5
D4
OPS12 OPS11 OPS10
R/W
R/W
R/W
0
0
0
D3
TX0E
R/W
1
D2
D1
D0
OPS02 OPS01 OPS00
R/W
R/W
R/W
0
0
0
OPS02-00: Output Through Data Select for TX0 pin (See Table 21)
TX0E: TX0 Output Enable
0: Disable. TX0 outputs “L”.
1: Enable (Default)
OPS12-10: Output Through Data Select for TX1 pin (See Table 22)
TX1E: TXP1/TXN1 pins Output Enable
0: Disable. TXP1 pin outputs “L”. TXN1 pin outputs “H”.
1: Enable (Default)
Addr
Register Name
03H Input/ Output Control 1
R/W
Default
D7
EFH1
R/W
0
D6
EFH0
R/W
1
D5
D4
UDIT BCU_IO
R/W
R/W
0
1
D3
DIT
R/W
1
D2
IPS2
R/W
0
D1
IPS1
R/W
0
D0
IPS0
R/W
0
IPS2-0: Input Recovery Data Select (See Table 19)
DIT: Through data/Transmit data select for TXP1/N1 pins
0: Through data (RX data).
1: Transmit data (DAUX data). (Default)
BCU_IO: Select I/O of B, C and U pins
0: Input
1: Output (Default)
UDIT: U bit control for DIT
0: U bit is fixed to “0”. (Default)
1: Recovered U bit is used for DIT (loop mode for U bit)
EFH1-0: Interrupt 0 Pin Hold Count Select
00: 512 LRCK
01: 1024 LRCK (Default)
10: 2048 LRCK
11: 4096 LRCK
MS0573-E-00
2006/12
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ASAHI KASEI
[AK4115]
Mask Control for INT0
Addr
Register Name
04H INT0 MASK
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
MQIT0 MAUT0 MCIT0 MULK0 MVRX0 MSTC0 MAUD0 MPAR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
1
1
1
0
MPAR0: Mask enable for PAR bit
0: Mask disable (Default)
1: Mask enable
MAUD0:Mask enable for AUDION bit
0: Mask disable
1: Mask enable (Default)
MSTC0: Mask enable for STC bit
0: Mask disable
1: Mask enable (Default)
MVRX0:Mask enable for VRX bit
0: Mask disable
1: Mask enable (Default)
MULK0:Mask enable for UNLCK bit
0: Mask disable (Default)
1: Mask enable
MCIT0: Mask enable for CINT bit
0: Mask disable
1: Mask enable (Default)
MAUT0:Mask enable for AUTO bit
0: Mask disable
1: Mask enable (Default)
MQIT0: Mask enable for QINT bit
0: Mask disable
1: Mask enable (Default)
When mask is set to “1”, corresponding event does not affect INT0 pin operation.
MS0573-E-00
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ASAHI KASEI
[AK4115]
Mask Control for INT1
Addr
Register Name
05H INT1 MASK
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
MQIT1 MAUT1 MCIT1 MULK1 MVRX1 MSTC1 MAUD MPAR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
1
1
0
1
MPAR1: Mask enable for PAR bit
0: Mask disable
1: Mask enable (Default)
MAUD1:Mask enable for AUDION bit
0: Mask disable (Default)
1: Mask enable
MSTC1: Mask enable for STC bit
0: Mask disable
1: Mask enable (Default)
MVRX1:Mask enable for VRX bit
0: Mask disable
1: Mask enable (Default)
MULK1:Mask enable for UNLCK bit
0: Mask disable
1: Mask enable (Default)
MCIT1: Mask enable for CINT bit
0: Mask disable
1: Mask enable (Default)
MAUT1:Mask enable for AUTO bit
0: Mask disable (Default)
1: Mask enable
MQIT1: Mask enable for QINT bit
0: Mask disable
1: Mask enable (Default)
When mask is set to “1”, corresponding event does not affect INT1 pin operation.
MS0573-E-00
2006/12
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ASAHI KASEI
[AK4115]
DAT Mask & DTS Detect
Addr
Register Name
06H DAT Mask & DTS Detect
R/W
Default
D7
DIV
R/W
0
D6
XMCK
R/W
0
D5
FAST
R/W
0
D4
DCNT
R/W
1
D3
DTS16
R/W
1
D2
D1
D0
DTS14 MDAT1 MDAT0
R/W
R/W
R/W
1
1
1
MDAT0: Mask enable for DAT bit
0: Mask disable
1: Mask enable (Default)
The factor which mask bit is set to “0” affects INT0 pin operation.
MDAT1: Mask enable for DAT bit
0: Mask disable
1: Mask enable (Default)
The factor which mask bit is set to “0” affects INT1 pin operation.
DTS14: DTS-CD 14bit Sync Word Detect
0: Disable
1: Enable (Default)
DTS16: DTS-CD 16bit Sync Word Detect
0: Disable
1: Enable (Default)
DCNT: DAT Start ID Counter
0: Disable
1: Enable (Default)
FAST: Select PLL Lock Time when the biphase signal is recovered.
0: ≤ (20ms + 384/fs) (Default)
1: ≤ (20ms + 1/fs)
XMCK: Select output frequency of MCKO2 (See Table 10)
0: Depends on CM1-0 bits and OCKS1-0 bits (Default)
1: Fixed to X’tal Mode
DIV: MCKO2 Output Frequency Select at X’tal Mode (See Table 10)
0: Same frequency as X’tal (Default)
1: Half frequency of X’tal
MS0573-E-00
2006/12
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ASAHI KASEI
[AK4115]
Receiver Status 0
Addr
Register Name
07H Receiver status 0
R/W
Default
D7
QINT
RD
0
D6
AUTO
RD
0
D5
CINT
RD
0
D4
UNLCK
RD
0
D3
VRX
RD
0
D2
STC
RD
0
D1
AUDION
RD
0
D0
PAR
RD
0
PAR: Parity Error or Bi-phase Error Status
0: No Error
1: Error
This bit goes to “1”, if a Parity Error or Biphase Error is detected in the sub-frame.
AUDION: Audio Bit Output
0: Audio
1: Non Audio
This bit is made by encoding channel status bits.
STC: Sampling Frequency or Pre-emphasis Information Change Detection
0: No detect
1: Detect
This bit goes to “1” when either the FS3-0 or PEM bit changes.
VRX: Validity of channel status for RX
0: Valid
1: Invalid
UNLCK: PLL Lock Status
0: Lock
1: Unlock
CINT: Channel Status Buffer Interrupt
0: No change
1: Changed
This bit goes to “1” when C-bit stored in register addresses 0CH to 24H changes.
AUTO: Non-PCM Auto Detect
0: No detect
1: Detect
QINT: Q-subcode Buffer Interrupt
0: No change
1: Changed
This bit goes to “1” when Q-subcode stored in register addresses 40H to 49H changes.
STC, QINT, CINT and PAR bits are initialized when 07H is read.
MS0573-E-00
2006/12
- 54 -
ASAHI KASEI
[AK4115]
Receiver Status 1
Addr
Register Name
08H Receiver status 1
R/W
Default
D7
FS3
RD
0
D6
FS2
RD
0
D5
FS1
RD
0
D4
FS0
RD
1
D3
PEM
RD
0
D2
DAT
RD
0
D1
DTSCD
RD
0
D0
NPCM
RD
0
D3
0
RD
0
D2
0
RD
0
D1
QCRC
RD
0
D0
CCRC
RD
0
NPCM: Non-PCM Bit Stream Auto Detection
0: No detect
1: Detect
DTSCD: DTS-CD Bit Stream Auto Detection
0: No detect
1: Detect
DAT: DAT Start ID Detect
0: No detect
1: Detect
DAT bit is initialized when 08H is read.
PEM: Pre-emphasis Detect
0: OFF
1: ON
This bit is made by encoding channel status bits.
FS3-0: Sampling Frequency detection (See Table 14)
Receiver Status 1
Addr
Register Name
09H Receiver status 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
CCRC: Cyclic Redundancy Check for Channel Status
0: No error
1: Error
This bit is enabled only in professional mode and only for the channel selected by the CS12 bit.
QCRC: Cyclic Redundancy Check for Q-subcode
0: No error
1: Error
MS0573-E-00
2006/12
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ASAHI KASEI
[AK4115]
Clock Control
Addr
Register Name
0AH Clock Control
R/W
Default
D7
TX1NE
R/W
1
D6
0
RD
0
D5
D4
D3
D2
MCK1E MCK1E ASYNC WSYNC
R/W
R/W
R/W
R/W
1
1
0
0
D1
XSEL
R/W
0
D0
PSEL
R/W
0
D1
CCRE
R/W
1
D0
VTX
R/W
0
PSEL: Setting of PLL reference clock (See Table 1)
XSEL: Setting of X’tal oscillator (See Table 12)
WSYNC: Synchronization between the biphase signal and ELRCK
0: Disable (Default)
1: Enable
ASYNC: Setting of synchronous / asynchronous mode for DIT/DIR
0: Synchronous mode (Default)
1: Asynchronous mode
MCK1E: Setting of MCKO1 output
0: Disable. Output “L”.
1: Enable (Default)
MCK2E: Setting of MCKO2 output
0: Disable. Output “L”.
1: Enable (Default)
TX1NE: Setting of TXN1 pin.
0: Disable. Output “L”. This mode is useful for consumer.
1: Enable (Default)
TX Control
Addr
Register Name
0BH TX Control
R/W
Default
D7
MSEL
RD
0
D6
ECKS1
RD
0
D5
ECKS0
R/W
1
D4
EDIF1
R/W
1
D3
EDIF0
R/W
0
D2
CTRAN
R/W
0
VTX: Setting of Validity bit for TX
0: Valid (Default)
1: Invalid
CCRE: CCRC Enable at professional mode
0: CCRC data is not generated.
1: CCRC data is generated in professional mode. In consumer mode, CCRC data is not generated.
(Default)
CTRAN: Transfer mode of CR191-0 bits
0: Not transfer or finish to transfer (Default)
1: Transfer
All CR191-0 bits is transferred to CT191-0 bits when CTRAN bit changes “0” to “1”. The
transferred CT191-0 bits are valid after next block start signal is detected. CTRAN bit goes to
“0” after finishing the transfer.
EDIF1-0: Setting of audio interface mode in asynchronous mode. (See Table 30)
ECK1-0: Setting of EMCK input frequency (See Table 31)
MSEL: Master clock setting for TX in asynchronous mode (See Table 4)
MS0573-E-00
2006/12
- 56 -
ASAHI KASEI
[AK4115]
Receiver Channel Status
Addr
Register Name
0CH RX Channel Status Byte 0
•
•
23H RX Channel Status Byte 23
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
•
•
•
•
•
•
•
•
CR191 CR190 CR189 CR188 CR187 CR186 CR185 CR184
RD
Not initialized
CR191-0: Receiver Channel Status Byte 23-0
Transmitter Channel Status
Addr
Register Name
24H TX Channel Status Byte 0
R/W
Default
25H TX Channel Status Byte 1
•
•
3BH TX Channel Status Byte 23
R/W
Default
D7
CT7
D6
CT6
D5
CT5
0
CT15
•
CT191
0
CT14
•
CT190
0
CT13
•
CT189
D4
CT4
D3
CT3
R/W
0
0
CT12
CT11
•
•
CT188 CT187
R/W
0
D2
CT2
D1
CT1
D0
CT0
1
CT10
•
CT186
0
CT9
•
CT185
0
CT8
•
CT184
D2
PC2
PC10
PD2
PD10
D1
PC1
PC9
PD1
PD9
D0
PC0
PC8
PD0
PD8
CT7-0: Transmitter Channel Status Byte 0
Default: “00000100”
CT191-8: Transmitter Channel Status Byte 23-1
Default: “00000000”
Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams
Addr
3CH
3DH
3EH
3FH
Register Name
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
R/W
Default
D7
PC7
PC15
PD7
PD15
D6
PC6
PC14
PD6
PD14
D5
PC5
PC13
PD5
PD13
D4
PC4
PC12
PD4
PD12
D3
PC3
PC11
PD3
PD11
RD
Not initialized
PC15-0: Burst Preamble Pc Byte 0 and 1
PD15-0: Burst Preamble Pd Byte 0 and 1
MS0573-E-00
2006/12
- 57 -
ASAHI KASEI
[AK4115]
Q-subcode Buffer
Addr
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
R/W
Default
D7
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
D6
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
D5
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
D3
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
D2
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
RD
Not initialized
Optional Control
Addr
Register Name
4AH Optional Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
0
RD
0
D1
CTX
R/W
0
D0
0
RD
0
CTX: Setting of channel status information for AES3 mode
0: Channel status information on DAUX is sent from TX (Default)
1: Channel status information in control registers (CTX191-0 bits) is sent from TX.
MS0573-E-00
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- 58 -
ASAHI KASEI
[AK4115]
„ Burst Preambles in non-PCM Bitstreams
sub-frame of IEC958
0
3 4
preamble
7 8
Aux.
11 12
27 28 29 30 31
LSB
MSB V U C P
16 bits of bitstream
0
Pa Pb Pc Pd
15
Burst_payload
stuffing
repetition time of the burst
Figure 50. Data structure in IEC60958
Preamble word
Pa
Pb
Pc
Pd
Bits of Pc
Value
0-4
5, 6
7
8-12
13-15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
0
0
1
0
Length of field
Contents
16 bits
sync word 1
16 bits
sync word 2
16 bits
Burst info
16 bits
Length code
Table 32. Burst preamble words
Contents
Value
0xF872
0x4E1F
see Table 33
numbers of bits
Repetition time of burst
in IEC60958 frames
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
reserved, shall be set to “0”
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
data type dependent info
bit stream number, shall be set to “0”
Table 33. Fields of burst info Pc
MS0573-E-00
≤4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
2006/12
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ASAHI KASEI
[AK4115]
„ Non-PCM Bitstream timing
1) When Non-PCM preamble is not coming within 4096 frames,
PDN pin
Bit stream
Pa Pb Pc1 Pd1
Pa Pb Pc2 Pd2
Repetition time
Pa Pb Pc3 Pd3
>4096 frames
AUTO bit
Pc Register
“0”
Pd Register
“0”
Pc1
Pc2
Pd1
Pc3
Pd2
Pd3
Figure 51. Timing example 1
2) When Non-PCM bitstream stops (when MULK0=0),
INT0 hold time
INT0 pin
< PLL Lock time
Bit stream
Pa Pb Pc1 Pd1
Stop
Pa Pb Pcn Pdn
2~3 Syncs (B,M or W)
<Repetition time
AUTO bit
Pc Register
Pd Register
Pc0
Pc1
Pd0
Pcn
Pd1
Pdn
Figure 52. Timing example 2
MS0573-E-00
2006/12
- 60 -
ASAHI KASEI
[AK4115]
SYSTEM DESIGN
Figure 53 shows the example of system connection diagram for 4-wire serial mode.
3.3V
S/PDIF Sources
C1: 0.1µ
C2: 10µ
C2
+
C1
4.7µ
S/PDIF
Sources
60
59
58
57
56
55
54
RX4
RX3
AVSS
RX2
AVDD
RX1
AVSS
RXP0
RXN0
ACKS
53
52
51
10kΩ
50
49
R
61
VCOM
62
P/SN
63
AVDD
64
AVDD
+
AVSS
C1
C1
10n
100p
24kΩ
1 RX5
FILT 48
2 TEST(AVSS)
XTL1 47
3 RX6
XTL0 46
4 PDN
PSEL 45
5 RX7
IIC 44
C2 C1
3.3V
+
6 DVDD
BVSS 43
7 VIN
DVSS 42
8 DAUX
DVDD 41
C1 +
Top View
9 DVSS
C2
3.3V
CSN 40
10 MCKO1
CCLK 39
11 MCKO2
CDTI 38
uP
CDTO 37
13 OVSS
INT1 36
14 BICK
INT0 35
C1
VOUT
TVDD
TX0
TXP1
TXN1
TVSS
XTI1
XTO1
XTI2
XTO2
OVDD
OVSS
EBICK
EMCK 33
U
ELRCK 34
16 LRCK
C
15 SDTO
B
DSP1
12 OVDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DSP2
C1
C1
+
+
uP
C
C2
C
C
C2
C
S/PDIF out
3.3V
5V
Figure 53. Typical Connection Diagram (4-wire serial mode)
Notes:
- For setting of XTL0 and XTL1, refer the Table 13.
- “C” depends on the crystal.
- AVSS, BVSS, TVSS, OVSS and DVSS must be connected the same ground plane.
- Digital signals, especially clocks, should be kept away from the R and FILT pins in order to avoid an effect to
the clock jitter performance.
MS0573-E-00
2006/12
- 61 -
ASAHI KASEI
[AK4115]
PACKAGE
64pin LQFP(Unit:mm)
1.70MAX
12.0 ± 0.3
0.10 ± 0.05
10.0
48
33
+0.05
32
64
17
10.0
49
1
12.0 ± 0.3
1.40 -0.05
16
0.17 ± 0.05
0.5
0.22 ± 0.05
0.10 M
0° ∼ 10°
0.10
0.5 ± 0.2
„ Material & Lead finish
Package molding compound: Epoxy
Lead frame material:
Cu
Lead frame surface treatment: Solder (Pb free) plate
MS0573-E-00
2006/12
- 62 -
ASAHI KASEI
[AK4115]
MARKING
AKM
AK4115VQ
XXXXXXX
1
XXXXXXX: Date code identifier
Revision History
Date (YY/MM/DD)
06/12/13
Revision
00
Reason
First Edition
Page
MS0573-E-00
Contents
2006/12
- 63 -
ASAHI KASEI
[AK4115]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to
customs and tariff s, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notif y that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0573-E-00
2006/12
- 64 -
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