ICST ICS9248YF-146-T Frequency generator & integrated buffers for celeron & pii/iiiâ ¢ Datasheet

Integrated
Circuit
Systems, Inc.
ICS9248-146
Frequency Generator & Integrated Buffers for Celeron & PII/III™
PLL2
48MHz
24_48MHz
/2
XTAL
OSC
PLL1
Spread
Spectrum
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
2
CPU
DIVDER
Stop
SDRAM
DIVDER
Stop
PCI
DIVDER
Stop
3
13
5
REF(1:0)
CPUCLK (2:0)
SDRAM (12:0)
PCICLK (4:0)
PCICLK_F
AGP
DIVDER
Config.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1
These are double strength.
Functionality
Block Diagram
X1
X2
VDDA
*(AGPSEL)REF0
1
*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
ICS9248-146
Pin Configuration
Recommended Application:
Single chip clock solution for SIS630S chipsets.
Output Features:
•
3- CPUs @ 2.5V
•
13 - SDRAM @ 3.3V
•
6- PCI @3.3V,
•
2 - AGP @ 3.3V
•
1- 48MHz, @3.3V fixed.
•
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
•
2- REF @3.3V, 14.318MHz.
Features:
•
Up to 166MHz frequency support
•
Support FS0-FS3 trapping status bit for I2C read back.
•
Support power management: CPU, PCI, SDRAM stops
and Power down Mode form I2C programming.
•
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
•
Uses external 14.318MHz crystal
Skew Specifications:
•
CPU - CPU: < 175ps
•
SDRAM - SDRAM < 250ps (except SDRAM12)
•
PCI - PCI: < 500ps
•
CPU (early) - PCI: 1-4ns (typ. 2ns)
2
AGP (1:0)
Reg.
9248-146 RevA- 4/23/01
Third party brands and names are the property of their respective owners.
FS3 FS2 FS1 FS0
CPU
SDRAM PCICLK
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
100.00
166.67
133.33
66.67
100.00
100.00
133.33
112.00
124.00
138.00
150.00
66.67
100.00
166.67
133.33
100.00
66.67
133.33
100.00
112.00
124.00
138.00
150.00
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.60
31.00
34.50
30.00
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
66.67
100.00
150.00
160.00
133.33
150.00
100.00
120.00
33.33
30.00
30.00
30.00
AGP SEL AGP SEL
=0
=1
66.67
50.00
66.67
50.00
66.66
55.56
66.67
50.00
66.67
50.00
66.67
50.00
66.67
50.00
66.67
50.00
67.20
56.00
62.00
46.50
69.00
51.75
60.00
50.00
66.67
60.00
60.00
60.00
50.00
50.00
50.00
48.00
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-146
Power Groups
General Description
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
The ICS9248-146 is the single chip clock solution for
Desktop/Notebook designs using the SIS 630S style chipset.
It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-146
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
MODE Pin Power Management Control Input
M ODE
Pin 21
Pin 27
Pin 28
Pin 30
Pin 31
0
SDRAM11
SDRAM10
SDRAM9
SDRAM8
1
CPU_STOP#
PCI_STOP#
SDRAM_STOP#
PD#
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Pin Configuration
PIN N U MBER
1, 7, 15, 22, 25,
35, 43
2
3
4, 14, 18, 19, 29,
32, 39, 44
5
6
8
9
13, 12, 11, 10
17, 16,
20
PIN N A ME
TY PE
VDD
P WR
A G P S EL
REF0
F S3
REF1
IN
OUT
IN
OUT
D ES C R IPTION
3.3V P ow er supply for SD RA M output buffers, PCI output buffers,
reference output buffers and 48M H z output
A G P frequency select pin.
14.318 M H z reference clock.
F requency select pin.
14.318 M H z reference clock.
GND
P WR
G round pin for 3V outputs.
X1
X2
F S1
PCICLK _F
F S2
PCICLK 0
PCICLK (4:1)
A G P (1:0)
F S0
48M H z
IN
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
Crystal input,nominally 14.318M H z.
Crystal output, nominally 14.318M H z.
F requency select pin.
P CI clock output, not affected by P CI_STO P #
F requency select pin.
P CI clock output.
P CI clock outputs.
A G P outputs defined as 2X PCI. These may not be stopped.
F requency select pin.
48M H z output clock
P in 27, 28, 30, & 31 function select pins
0=D esktop 1=M obile mode
Clock output for super I/O /U S B default is 24M H z
M ODE
IN
24_48M H z
OUT
23
SD A TA
I/O
D ata pin for I C circuitry 5V tolerant
24
S CLK
IN
Clock pin of I C circuitry 5V tolerant
S tops all PCICLK s besides the PCICLK _F clocks at logic 0 level, w hen input
is low and M O D E pin is in M obile mode
S D RA M clock output
S tops all CPU CLK s clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
S D RA M clock output
S D RA M clock output
S tops all SD RA M clocks at logic 0 level, w hen input is low and M O D E pin
is in M obile mode
A synchronous active low input pin used to pow er dow n the device into a low
pow er state. The internal clocks are disabled and the V CO and the crystal are
stopped. The latency of the pow er dow n w ill not be greater than 3ms.
21
27
28
30
31
CP U _S TO P #
IN
SD RA M 11
OUT
PCI_STO P #
IN
SD RA M 10
S D RA M 9
OUT
OUT
S D RA M _STO P #
IN
PD#
IN
S D RA M 8
26 33, 34, 36, 37,
SD RA M (12, 7:0)
38, 40, 41, 42
45, 46, 47
CP U CLK (2:0)
48
VDDL
2
2
OUT
S D RA M clock output
OUT
S D RA M clock outputs
OUT
CPU clock outputs.
P WR
P ow er pin for the CP U CLK s. 2.5V
Third party brands and names are the property of their respective owners.
2
ICS9248-146
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
Bit 2
Bit 7 Bit 6
Bit 5
Bit 4
FS3
FS1
FS0
FS2
CPU
SDRAM
PCI
0
0
0
0
0
66.67
66.67
33.33
0
0
0
0
1
100.00
100.00
33.33
0
0
0
1
0
166.67
166.67
33.33
0
0
0
1
1
133.33
133.33
33.33
0
0
1
0
0
66.67
100.00
33.33
0
0
1
0
1
100.00
66.67
33.33
0
0
1
1
0
100.00
133.33
33.33
0
0
1
1
1
133.33
100.00
33.33
0
1
0
0
0
112.00
112.00
33.60
0
1
0
0
1
124.00
124.00
31.00
0
1
0
1
0
138.00
138.00
34.50
0
1
0
1
1
150.00
150.00
30.00
0
1
1
0
0
66.67
133.33
33.33
0
1
1
0
1
100.00
150.00
30.00
Bit 2
0
1
1
1
0
150.00
100.00
30.00
Bit 7:4
0
1
1
1
1
160.00
120.00
30.00
1
0
0
0
0
103.00
103.00
34.33
1
0
0
0
1
100.30
100.30
33.43
1
0
0
1
0
200.00
200.00
33.33
1
0
0
1
1
133.73
133.73
33.43
1
0
1
0
0
103.00
137.33
34.33
1
0
1
0
1
137.33
103.00
34.33
1
0
1
1
0
66.87
100.30
33.43
1
0
1
1
1
133.73
100.30
33.43
1
1
0
0
0
110.00
110.00
33.00
1
1
0
0
1
115.00
115.00
34.50
1
1
0
1
0
140.00
140.00
35.00
1
1
0
1
1
101.50
101.50
33.83
1
1
1
0
0
100.30
133.73
33.43
1
1
1
0
1
105.00
140.00
35.00
1
1
1
1
0
105.00
157.50
31.50
1
1
1
1
1
135.33
101.50
33.83
0
F
r
e
q
u
e
n
c
y
i
s
s
e
l
e
c
t
e
d
b
y
h
a
r
d
w
a
r
e
s
e
l
e
c
t
,
L
a
t
c
h
e
d
I
n
p
u
t
s
Bit 3 1 - Frequency is selected by Bit , 2 7:4
al
Bit 1 10 -- SNporrem
ad Spectrum Enabled
Bit 0 10- -TRriusntantienagll outputs
PWD
AGP
SEL = 0
66.67
66.67
66.66
66.67
66.67
66.67
66.67
66.67
67.20
62.00
69.00
60.00
66.67
60.00
60.00
60.00
68.67
66.87
66.67
66.87
68.67
68.67
66.87
66.87
66.00
69.00
70.00
67.67
66.87
70.00
63.00
67.67
AGP
SEL = 1
50.00
50.00
55.56
50.00
50.00
50.00
50.00
50.00
56.00
46.50
51.75
50.00
50.00
50.00
50.00
48.00
50.00
50.00
50.00
50.15
51.50
51.50
50.15
50.15
55.00
57.50
52.50
50.00
50.15
52.50
52.50
50.75
Spread Precentage
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
00000
Note1
0
1
0
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
3
ICS9248-146
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN#
PWD
Bit 7
-
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
47
46
45
-
1
1
1
1
1
1
1
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DESCRIPTION
Sel24_48
(1:24MHz, 0:48MHz)
R e s e r ve d
R e s e r ve d
R e s e r ve d
CPUCLK0
CPUCLK1
CPUCLK2
R e s e r ve d
PIN#
33
34
36
37
38
40
41
42
PWD
1
1
1
1
1
1
1
1
BIT PIN# PWD
Bit 7
1
Bit 6
21
1
Bit 5
20
1
Bit 4
26
1
Bit 3
27
1
Bit 2
28
1
Bit 1
30
1
Bit 0
31
1
DESCRIPTION
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
2
1
Bit 2
3
1
Bit 1
17
1
Bit 0
16
1
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
R e s e r ve d
R e s e r ve d
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
13
12
11
10
9
8
DESCRIPTION
FS3 (Readback)
FS2 (Readback)
FS1 (Readback)
FS0 (Readback)
REF1
REF0
AGPCLK1
AGPCLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
4
DESCRIPTION
R e s e r ve d
24_48MHz
48MHz
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
ICS9248-146
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
PIN#
2,3
Bit6
45
Bit5
Bit4
Bit3
Bit2
Bit1
-
Bit0
-
PWD
DESCRIPTION
0
REF strength 0=1X, 1=2X
CPUCLK2 - Stop - Control
0
0 = C P U _ S TO P # w i l l c o n t r o l C P U C L K 2 ,
1=CPUCLK2 is free running even if CPU_STOP# is low
X
AGPSEL (Readback)
X
MODE (Readback)
X
C P U _ S TO P # ( R e a d b a c k )
X
P C I _ S TO P # ( R e a d b a c k )
X
S D R A M _ S TO P # ( R e a d b a c k )
AGP Speed Toggle
0
0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT PIN# PWD
Bit 7
0
Bit 6
0
Bit 5
1
Bit 4
0
Bit 3
1
Bit 2
0
Bit 1
0
Bit 0
1
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Third party brands and names are the property of their respective owners.
5
ICS9248-146
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .
5.5 V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
115°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Volt age VDD = 3.3 V +/-5%VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
2
VDD+0.3
V
Input High Voltage
VIH
VSS-0.3
0.8
V
Input Low Voltage
VIL
CL=30 pF, CPU @ 66, 100 MHz
390
400
mA
Supply Current
IDD
Power Down
PD
300
600
µA
Input frequency
Fi
VDD = 3.3 V;
12
14.318
16
MHz
Logic Inputs
5
pF
Input Capacitance1
CIN
X1 & X2 pins
27
45
pF
CINX
To 1st crossing of target Freq.
3
Transition Time
Ttrans
From 1st crossing to 1% target Freq.
Settling Time
TS
Clk Stabilization1
Skew
Skew
1
TSTAB
TCPU-PCI
TCPU-SDRAM
From VDD= 3.3 V to 1% target Freq.
CPUVT= 1.5 V PCI VT=1.25V
CPUVT= 1.5 V SDRAM VT=1.25
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
1
-500
1.9
-300
3
4
0
ms
ns
ps
ICS9248-146
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
RDSP2B
VO = VDD*(0.5)
10
Output Impedance1
RDSN2B
VO = VDD*(0.5)
10
Output Impedance1
VOH2B
IOH = -12.0 mA
Output High Voltage
2
VOL2B
IOL = 12 mA
Output Low Voltage
VOH = 1.7 V
IOH2B
Output High Current
VOL = 0.7 V
IOL2B
19
Output Low Current
1
t
V
=
0.4
V,
V
=
2.0
V
0.4
1.2
Rise Time
r2B
OL
OH
1
tf2B
VOH = 2.0 V, VOL = 0.4 V
0.4
1.1
Fall Time
1
Duty Cycle
0:1
Skew window
0:2
Skew window
1
Jitter, Cycle-to-cycle
MAX UNITS
20
Ω
20
Ω
V
0.4
V
-19
mA
mA
1.6
ns
1.6
ns
46.9
55
%
dt2B
VT = 1.25 V
tsk2B
VT = 1.25 V
43
175
ps
tsk2B
VT = 1.25 V
142
375
ps
VT = 1.25 V, CPU=66 MHz
177
250
ps
tjcyc-cyc
45
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24-48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
1
Output Impedance
RDSP5B
VO = VDD*(0.5)
20
1
VO = VDD*(0.5)
20
Output Impedance
RDSN5B
IOH = -14 mA
2.4
Output High Voltage
VOH15
IOL = 6.0 mA
Output Low Voltage
VOL5
IOH5
VOH = 2.0 V
Output High Current
IOL5
VOL = 0.8 V
10
Output Low Current
Rise Time1
tr5
VOL = 0.4 V, VOH = 2.4 V
0.4
1.45
4
ns
1
tf5
dt5
VOH = 2.4 V, VOL = 0.4 V
0.4
1.5
4
ns
VT = 1.5 V
VT = 1.5 V
45
52.5
210
55
500
%
ps
Fall Time
1
Duty Cycle
Jitter
1
MAX UNITS
Ω
60
Ω
60
V
0.4
V
-20
mA
mA
tcycle to cycle
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-146
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
1
Output Impedance
RDSP1B
VO = VDD*(0.5)
12
1
VO = VDD*(0.5)
12
Output Impedance
RDSN1B
IOH = -1 mA
2.4
Output High Voltage
VOH1
IOL = 1 mA
Output Low Voltage
VOL1
IOH1
VOH @ MIN = 1.0 V
Output High Current
IOL1
VOL @ MIN = 1.95 V
29
Output Low Current
1
Rise Time
1
Fall Time
1
Duty Cycle
1
Skew window
1
Jitter, Cycle-to-cycle
1
MAX UNITS
Ω
55
Ω
55
V
0.55
V
-29
mA
mA
tr1
VOL = 0.4 V, VOH = 2.4 V
0.5
2.3
2.5
ns
tf1
dt1
VOH = 2.4 V, VOL = 0.4 V
0.5
2.3
2.5
ns
VT = 1.5 V
45
51.2
55
%
tsk1
VT = 1.5 V
108
500
ps
tjcyc-cyc1
VT = 1.5 V
353
500
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
1
Rise Time
1
Fall Time
1
Duty Cycle
Skew window1(0:11)
1( 0:12)
Skew window
1
Jitter, Cycle-to-cycle
1
1
RDSP3B
1
RDSN3B
VOH3
VOL3
IOH3
IOL3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8V
10
10
2.4
MAX UNITS
Ω
24
Ω
24
V
0.4
V
-46
mA
mA
tr3
VOL = 0.4 V, VOH = 2.4 V
0.8
1.6
ns
tf3
dt3
VOH = 2.4 V, VOL = 0.4 V
0.8
1.6
ns
48.5
55
%
tsk3
VT = 1.5 V
192
250
ps
tsk3
VT = 1.5 V
290
500
ps
VT = 1.5 V, CPU=66,100,133 MHz
173
250
ps
tjcyc-cyc3
VT = 1.5 V
45
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-146
Electrical Characteristics - AGP
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
MAX UNITS
VO=VDD*(0.5)
12
55
Ω
VO=VDD*(0.5)
IOH = -18 mA
IOL = 18 mA
VOH = 2.0 V
VOL = 0.8 V
12
2
55
19
Ω
V
V
mA
mA
RDSN4B
VOH4B
VOL4B
IOH4B
IOL4B
Rise Time1
tr4B
VOL = 0.4 V, VOH = 2.4 V
0.5
Fall Time1
tf4B
dt4B
VOH = 2.4 V, VOL = 0.4 V
0.5
VT = 1.5 V
45
Jitter Cyc-Cyc
TYP
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Duty Cycle1
Skew window1
1
RDSP4B
MIN
1
1
tsk
tjcyc-cyc
1
0.4
-19
VT = 1.5 V
VT = 1.5 V
1.5
2
ns
1.6
2
ns
52.3
55
%
55.5
175
ps
239
500
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Output High Voltage
VOH5
IOH = -12 mA
2.4
IOL = 9 mA
0.4
Output Low Voltage
VOL5
VOH = 2.0 V
-22
Output High Current
IOH5
VOL = 0.8 V
16
Output Low Current
IOL5
Rise Time1
tr5
VOL = 0.4 V, VOH = 2.4 V
1.8
4
1
Fall Time
tf5
VOH = 2.4 V, VOL = 0.4 V
1.9
4
1
Duty Cycle
dt5
VT = 50%
45
54.5
55
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
UNITS
V
V
mA
mA
ns
ns
%
ICS9248-146
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 7
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Read:
How to Write:
Controlle r (Host)
Start Bit
Address
D2(H )
Controlle r (Host)
Start Bit
Address
D3(H )
ICS (Sla ve/Re ceiver)
ICS (Slave/Rece ive r)
A CK
Byte Count
A CK
Dummy Command Code
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
ACK
A CK
Stop Bit
Byte 0
Dummy Byte Count
Byte 1
Byte 0
Byte 2
Byte 1
Byte 3
Byte 2
Byte 4
Byte 3
Byte 5
Byte 4
Byte 6
Byte 5
Byte 7
Byte 6
Byte 7
A CK
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
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10
ICS9248-146
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248146 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
ICS9248-146
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-146. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-146.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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12
ICS9248-146
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-146. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-146 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-146 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-146.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
13
ICS9248-146
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation.
SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-146. All other clocks will continue to run while
the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that
guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to
the SDRAM clocks inside the ICS9248-146.
3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
14
ICS9248-146
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-146 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
15
ICS9248-146
c
N
L
E1
INDEX
AREA
E
1 2
h x 45°
D
A
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
N
α
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
A1
-Ce
SEATING
PLANE
N
.10 (.004) C
48
b
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
D (inch)
MIN
.620
MAX
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS9248yF-146-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
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16
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.