Micron MT48H16M32LGCJ-75L 512mb: 32 meg x 16, 16 meg x 32 mobile sdram Datasheet

512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Features
Mobile SDRAM
MT48H32M16LF – 8 Meg x 16 x 4 banks
MT48H16M32LF/LG – 4 Meg x 32 x 4 banks
Features
Options
• Endur-IC™ technology
• Fully synchronous; all signals registered on positive
edge of system clock
• VDD = 1.7–1.95V; VDDQ = 1.7–1.95V
• Internal, pipelined operation; column address can
be changed every clock cycle
• Four internal banks for concurrent operation
• Programmable burst lengths: 1, 2, 4, 8, and
continuous1
• Auto precharge, includes concurrent auto precharge
• Auto refresh and self refresh modes
• LVTTL-compatible inputs and outputs
• On-chip temperature sensor to control refresh rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive (DS)
Table 1:
DQ Bus
Width
x16
x32
Table 2:
• VDD/VDDQ
– 1.8V/1.8V
• Row size option
– Standard addressing option
– Reduced page-size option
• Configuration
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
– 16 Meg x 32 (4 Meg x 32 x 4 banks)
• Plastic “green” packages
– 54-Ball VFBGA (10mm x 11.5mm)
– 90-Ball VFBGA (10mm x 13mm)
• Timing – cycle time
– 7.5ns at CL = 3
– 8ns at CL = 3
• Power
– Standard IDD2P/IDD7
– Low IDD2P/IDD7
• Operating temperature range
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
• Design revision
Configuration Addressing
Architecture
JEDECStandard
Option
Reduced
Page-Size
Option2
Number of banks
Bank address balls
Row address balls
Column address balls
Row address balls
Column address balls
4
BA0, BA1
A0–A12
A0–A9
A0–A12
A0–A8
4
BA0, BA1
–
–
A0–A13
A0–A7
Key Timing Parameters
-75
-8
Clock Rate (MHz)
LF
LG3, 4
32M16
16M32
CJ5
CM3
-75
-8
None
L
None
IT
:A
Access Time
CL = 2
CL = 3
CL = 2
CL = 3
104
100
133
125
9ns
9ns
6ns
7ns
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
H
Notes: 1. For continuous page burst, contact factory
for availability.
2. For reduced page-size option, contact factory for availability.
3. LG is a reduced page-size option. Contact
factory for availability.
4. Only available for x32 configuration.
5. Only available for x16 configuration.
CL = CAS (READ) latency
Speed
Grade
Marking
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
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Figure 5:
Figure 6:
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Figure 9:
Figure 10:
Figure 11:
Figure 12:
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Figure 25:
Figure 26:
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Figure 30:
Figure 31:
Figure 32:
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Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
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Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure 50:
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
Figure 56:
512Mb Mobile SDRAM Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
32 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
16 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
54-Ball FBGA (Top View) – 10mm x 11.5mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
90-Ball VFBGA (Top View) – 10mm x 13mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
EMR Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Activating a Specific Row in a Specific Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Deep Power-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Typical Self Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Single READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
READ – Continuous-Page Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
READ – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Single WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Single WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
WRITE – Continuous-Page Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
54-Ball VFBGA (10mm x 11.5mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
90-Ball VFBGA (10mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Burst Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Truth Table – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Truth Table – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Truth Table – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .47
AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
IDD Specifications and Conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IDD Specifications and Conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IDD7 Specifications and Conditions (x16 and x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Capacitance (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Capacitance (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
General Description
Figure 1:
512Mb Mobile SDRAM Part Numbering
Power
Example Part Number: MT48H16M32LFCM-75IT:A
MT48
Mobile
Configuration
VDD/
VDDQ
Package
Temp. Revision
Speed
VDD/VDDQ
:A Design revision
H
1.8V/1.8V
Configuration Row Size Option
Operating Temp.
32 Meg x 16
Standard
32M16LF
16 Meg x 32
Standard
16M32LF
Commercial
IT
Industrial
16 Meg x 32 Reduced page-size 16M32LG
Power
Standard IDD2/IDD7
Package
54-Ball (10 x 11.5 VFBGA) Pb–free
CJ
90-Ball (10 x 13 VFBGA) Pb–free
CM
L
Low IDD2/IDD7
Speed Grade
-75
tCK
= 7.5ns
-8
tCK
= 8.0ns
General Description
The Micron® 512Mb Mobile SDRAM is a high-speed CMOS, dynamic random-access
memory containing 536,870,912-bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1K
columns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8,192 rows by
512 columns by 32 bits. In a reduced page-size option, each of the x32’s 134,217,728-bit
banks is organized as 16,384 rows by 256 columns x32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A12 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations with a read burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three
banks will hide the PRECHARGE cycles and provide seamless high-speed, randomaccess operation.
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Functional Block Diagrams
The 512Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto
refresh mode is provided, along with a power-saving deep power-down mode. All inputs
and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle
during a burst access.
Functional Block Diagrams
Figure 2:
32 Meg x 16 SDRAM
BA1
0
0
1
1
CKE
BA0
0
1
0
1
Bank
0
1
2
3
CLK
CONTROL
LOGIC
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
BANK3
BANK2
BANK1
EXT MODE
REGISTER
MODE REGISTER
REFRESH 13
COUNTER
13
ROWADDRESS
MUX
13
13
BANK0
ROWADDRESS
8,192
LATCH
AND
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 1,024 x 16)
2
DQML,
DQMH
SENSE AMPLIFIERS
16
16,384
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
1,024
(x16)
2
DATA
OUTPUT
REGISTER
16
16
DQ0–
DQ15
DATA
INPUT
REGISTER
COLUMN
DECODER
10
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
COLUMNADDRESS
COUNTER/
LATCH
10
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Functional Block Diagrams
Figure 3:
16 Meg x 32 SDRAM
BA1
0
0
1
1
CKE
BA0
0
1
0
1
Bank
0
1
2
3
CLK
CONTROL
LOGIC
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
BANK3
BANK2
BANK1
EXT MODE
REGISTER
MODE REGISTER
REFRESH 13
COUNTER
13
ROWADDRESS
MUX
13
13
BANK0
ROWADDRESS
8,192
LATCH
AND
DECODER
BANK0
MEMORY
ARRAY
(8,192 x 512 x 32)
4
DQM0–3
SENSE AMPLIFIERS
32
16,384
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
32
32
512
(x32)
4
DQ0–
DQ31
DATA
INPUT
REGISTER
COLUMN
DECODER
9
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
COLUMNADDRESS
COUNTER/
LATCH
9
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Ball Assignments
Ball Assignments
Figure 4:
54-Ball FBGA (Top View) – 10mm x 11.5mm
1
2
3
VSS
DQ15
DQ14
4
5
6
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
DQ8
VSSQ1
Vss
VDD
LDQM
DQ7
UDQM
CLK
CKE
CAS#
RAS#
WE#
A12
A11
A9
BA0
BA1
CS#
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
A
B
C
D
E
F
G
H
J
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. The E2 pin is a test pin and must be tied to VSSQ in normal operation.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Ball Assignments
Figure 5:
90-Ball VFBGA (Top View) – 10mm x 13mm
1
2
3
4
5
6
7
8
9
DQ26
DQ24
VSS
VDD
DQ23
DQ21
DQ28
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
VDDQ
DQ31
NC
NC
DQ16
VSSQ
VSS
DQM3
A3
A2
DQM2
VDD
A4
A5
A6
A10
A0
A1
A7
A8
A12
A13/NC
BA1
A11
CLK
CKE
A9
BA0
CS#
RAS#
DQM1
DNU1
NC
CAS#
WE#
DQM0
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
DQ13
DQ15
VSS
VDD
DQ0
DQ2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. The K2 “DNU” ball should not be used in the application. However, it may be connected to
VSS (ground).
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Ball Descriptions
Ball Descriptions
Table 3:
VFBGA Ball Descriptions
54-Ball VFBGA
90-Ball VFBGA
Symbol
Type
Description
F2
J1
CLK
Input
F3
J2
CKE
Input
G9
J8
CS#
Input
F7, F8, F9
J9, K7, K8
Input
E8, F1
K9, K1, F8, F2
CAS#,
RAS#, WE#
DQM0–3,
LDQM,
UDQM
G7, G8
J7, H8
BA0, BA1
Input
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9, G2,
G1
G8, G9, F7, F3,
G1, G2, G3, H1,
H2, J3, G7, H9,
H3
A0–A12
Input
–
H7
A13/NC
Input
Clock: CLK is driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CLK. CLK also increments
the internal burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides precharge powerdown and SELF REFRESH operation (all banks idle), active powerdown (row active in any bank), deep power-down (all banks
idle), or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK,
are disabled during power-down and self refresh modes,
providing low standby power.
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for external
bank selection on systems with multiple banks. CS# is considered
part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input/Output mask: DQM is sampled HIGH and is an input mask
signal for write accesses and an output enable signal for read
accesses. Input data is masked during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) during a
READ cycle. For the x16, LDQM corresponds to DQ0–DQ7 and
HDQM corresponds to DQ8–DQ16. For the x32, DQM0
corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15,
DQM2 corresponds to DQ16–DQ23, and DQM3 corresponds to
DQ24–DQ31. DQM0–3 (or LDQM and HDQM if x16) are
considered same state when referenced as DQM.
Bank address input(s): BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0 and BA1 become “don’t care” when registering an
ALL BANK PRECHARGE (A10 HIGH).
Address inputs: A0–A12 are sampled during the ACTIVE
command (row-address A0–A12) and READ/WRITE command
[column-address A0–A8 (x32); column-address A0–A9 (x16); with
A10 defining auto precharge] to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be
precharged (A10 HIGH) or bank selected by BA0, BA1. The
address inputs also provide the op-code during a LOAD MODE
REGISTER command.
H7 is used for the LG, reduced page-size, option (see Table 1 on
page 1); otherwise, leave as NC.
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Input
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Ball Descriptions
Table 3:
VFBGA Ball Descriptions (Continued)
54-Ball VFBGA
90-Ball VFBGA
Symbol
Type
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
R8, N7, R9, N8,
P9, M8, M7, L8,
L2, M3, M2, P1,
N2, R1, N3, R2,
E8, D7, D8, B9,
C8, A9, C7, A8,
A2, C3, A1, C2,
B1, D2, D3, E2
B2, B7, C9, D9,
E1, L1, M9, N9,
P2, P7
B8, B3, C1, D1,
E9, L9, M1, N1,
P3, P8
A7, F9, L7, R7
A3, F1, L3, R3
E3, E7, K3
DQ0–DQ31
I/O
–
K2
VSSQ
DNU
A7, B3, C7, D3
A3, B7, C3, D7
A9, E7, J9
A1, E3, J1
–
E2
–
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
Description
Data input/output: Data bus.
VDDQ
Supply DQ power: Provide isolated power to DQ for improved noise
immunity.
VssQ
Supply DQ ground: Provide isolated ground to DQ for improved noise
immunity.
VDD
VSS
NC
Supply Core power supply.
Supply Ground.
–
Internally not connected: These balls could be left unconnected,
but it is recommended they be connected to Vss.
–
This TEST pin must be tied to VSS or VSSQ in normal operation.
–
Should not be used in the application. However, it may be
connected to Vss (ground).
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Functional Description
Functional Description
In general, the 512Mb SDRAMs (4 Meg x 32 x 4 banks) are quad-bank DRAMs that
operate at 1.8V and include a synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK).
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A12 select the row). The address bits (A0–A9 for x16 and A0–A8 for
x32) registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Once the
power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock
is defined as a signal cycling within timing constraints specified for the clock ball), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command must be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for programming the mode registers.
Because the mode registers will power up in an unknown state, they should be loaded
prior to applying any operational command.
Register Definition
Mode Register
There are two mode registers in the component: mode register and extended mode
register (EMR). The mode register is illustrated in Figure 6 on page 14. The mode register
is used to define the specific mode of operation of the SDRAM. This definition includes
the selection of a burst length (BL), a burst type, a CAS latency (CL), an operating mode
and a write burst mode, as shown in Figure 6 on page 14. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored
information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the BL, M3 specifies the type of burst, M4–M6 specify
the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and
M10 and M11 should be set to zero. M12 and M13 should be set to zero to prevent the
extended mode register from being programmed.
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Register Definition
The mode registers must be loaded when all banks are idle, and the controller must wait
t
MRD before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with the BL being programmable, as shown in Figure 6 on page 14. The BL determines the maximum number of
column locations that can be accessed for a given READ or WRITE command. BL = 1, 2,
4, 8, or continuous locations are available for both the sequential and the interleaved
burst types, and a continuous-page burst is available for the sequential type. The continuous-page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary BLs.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the BL is effectively selected. All accesses for that burst take place within this block, meaning that the
burst will wrap within the block if a boundary is reached. The block is uniquely selected
by A1–A8 when BL = 2, A2–A8 when BL = 4, and A3–A8 when BL = 8. The remaining (least
significant) address bit(s) is (are) used to select the starting location within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the BL, the burst type, and the
starting column address, as shown in Table 4 on page 15.
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Register Definition
Figure 6:
Mode Register Definition
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
Address Bus
M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
14 13
0 0
0
12 11 10
9
8
7
6 5
4
3
2
1
Reserved1 WB Op Mode CAS Latency BT Burst Length
Mode
Register (Mx)
Burst Length
M14 M13 Mode Register Definition
0
0
Base mode register
M2 M1 M0
M3 = 0
M3 = 1
0
1
Reserved
0
0
0
1
1
1
0
Extended mode register
0
0
1
2
2
1
1
Reserved
0
1
0
4
4
0
1
1
8
8
M9
Write Burst Mode
1
0
0
Reserved
Reserved
0
Programmed burst length
1
0
1
Reserved
Reserved
1
Single location access
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
M8
M7
Operating Mode
0
0
Normal operation
–
–
All other states reserved
M6 M5 M4
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
M3
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Burst Type
0
Sequential
1
Interleaved
1. Should be programmed to “0” to ensure compatibility with future devices.
14
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Register Definition
Table 4:
Burst Definition Table
Burst
Length
Order of Accesses Within a Burst
Starting Column Address
2
4
8
A2
0
0
0
0
1
1
1
1
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
CAS Latency (CL)
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 7 on page 16.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use.
Reserved states should not be used because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed BL applies to READ bursts, but write accesses are singlelocation accesses.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Register Definition
Extended Mode Register (EMR)
The EMR controls the functions beyond those controlled by the mode register. These
additional functions are special features of the mobile device that helps reduce overall
system power consumption. They include temperature-compensated self refresh
(TCSR) control, partial-array self refresh (PASR), and output drive strength.
The EMR is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and
retains the stored information until it is programmed again or the device loses power.
Figure 7:
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 3
DON’T CARE
UNDEFINED
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. Each READ command may be to any bank. DQM is LOW.
2. For CL = 2, DQM should be taken LOW at READ command. For CL = 3, DQM should be taken
LOW one cycle after the READ command.
16
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Register Definition
Figure 8:
EMR Definition
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E14 E13 E12 E11 E10 E9
E8
E7
E6
14
1
8
7
6 5
DS
E6
E5
Driver Strength
0
0
0
1
Full-strength driver
Half-strength driver
1
1
0
1
Quarter-strength driver
One eighth-strength driver
13 12
0
11 10
9
set to “0”
E14 E13 Mode Register Definintion
0 Standard mode register
0
1 Reserved
0
0 Extended mode register
1
1 Reserved
1
E12 E11 E10 E9
0
0
0
0
–
–
–
–
Notes:
E8
0
–
E7
0 Normal operation
– All other states reserved
E5
E4
E3
4
3
TCSR1
E2
2
E1
Address Bus
E0
0
1
PASR
Extended Mode
Register
E2
0
0
E1
0
0
E0 Partial-Array Self Refresh Coverage
0 Full array
1 Half array
0
1
0
Quarter array
0
1
1
1
0
0
1
0
1
Reserved
Reserved
One-eighth array
1
1
0
One-sixteenth array
1
1
1
Reserved
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
The extended mode register must be programmed with E7 through E12 set to “0.” It
must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either
of these requirements results in unspecified operation. Once the values are entered, the
extended mode register settings will be retained even after exiting deep power-down
mode.
Temperature-Compensated Self Refresh (TCSR)
On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for
automatic control of the self refresh oscillator. Programming of the TCSR bits will have
no effect on the device. The self refresh oscillator will continue refresh at the factory
programmed optimal rate for the device temperature.
Partial-Array Self Refresh (PASR)
For further power savings during self refresh, the partial-array self refresh (PASR) feature
allows the controller to select the amount of memory that will be refreshed during self
refresh. The following refresh options are available.
1. All banks (banks 0, 1, 2, and 3).
2. Two banks (banks 0 and 1; BA1=0).
3. One bank (bank 0; BA1 = BA0 = 0).
4. Half bank (bank 0; BA1 = BA0 = row address MSB = 0).
5. Quarter bank (bank 0; BA1 = BA0; row address MSB = row address MSB - 1 = 0).
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Register Definition
WRITE and READ commands occur to any bank selected during standard operation, but
only the selected banks or segments of a bank in PASR will be refreshed during self
refresh. It is important to note that data in unused banks or portions of banks will be lost
when PASR is used.
Driver Strength
Bits E5 and E6 of the extended mode register can be used to select the driver strength of
the DQ outputs. This value should be set according to the application’s requirements.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Commands
Commands
Table 5 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear on pages 41–44;
these tables provide current state/next state information.
Table 5:
Truth Table – Commands and DQM Operation
Notes 4 and 5 apply to all commands
Name (Function)
CS#
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Notes:
RAS# CAS#
WE#
DQM
ADDR
DQs
Notes
H
L
L
L
L
L
X
H
L
H
H
H
X
H
H
L
L
H
X
H
H
H
L
L
X
X
X
L/H
L/H
X
X
X
Bank/Row
Bank/Col
Bank/Col
X
X
X
X
X
Valid
X
1
1
2
3
3
6, 7, 8
L
L
L
L
H
L
L
H
X
X
Code
X
X
X
9
10, 11
L
X
X
L
X
X
L
X
X
L
X
X
X
L
H
Op-Code
X
X
X
Active
High-Z
12
1. COMMAND INHIBIT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A0–A12 provide row address.
3. BA0–BA1 provide bank address; A0–A9 provide column address; A10 HIGH enables the auto
precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
5. All states and sequences not shown are reserved and/or illegal.
6. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command
could coincide with data on the bus. However, the DQs column reads a don’t care state to
illustrate that the BURST TERMINATE command can occur when there is no data present.
7. Applies only to read and write bursts with auto precharge disabled; this command is undefined and should not be used for READ bursts with auto precharge enabled.
8. This command is a BURST TERMINATE if CKE is HIGH, deep power-down if CKE is LOW.
9. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
10. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
11. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
12. BA0–BA1 select either the standard mode register or the extended mode register (BA0 = 0,
BA1 = 0 select the standard mode register; BA0 = 0, BA1 = 1 select extended mode register;
other combinations of BA0–BA1 are reserved.) A0–A12 provide the op-code to be written to
the selected mode register.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Commands
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
Load Mode Register
The mode register is loaded via inputs A0–A12, BA0, and BA1. (See "Mode Register" on
page 12.) The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER
commands can only be issued when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided selects the row. This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided selects the starting
column location. The value on input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end
of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM
inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding
DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will
provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided selects the starting
column location. The value on input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end
of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject
to the DQM input logic level appearing coincident with the data. If a given DQM signal is
registered LOW, the corresponding data will be written to memory; if the DQM signal is
registered HIGH, the corresponding data inputs will be ignored, and a write will not be
executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the precharge command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Commands
Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is non persistent in that it is either enabled or disabled for each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in "Burst Type" on
page 13.
BURST TERMINATE
The BURST TERMINATE command is used to truncate fixed-length bursts. The most
recently registered READ or WRITE command prior to the BURST TERMINATE
command will be truncated, as shown in "Operations" on page 22.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is non
persistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum tRP has been met after the
PRECHARGE command, as shown in "Operations" on page 22.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 512Mb SDRAM requires
8,192 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed AUTO
REFRESH command every 7.8125µs will meet the refresh requirement and ensure that
each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a
burst at the minimum cycle rate (tRFC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command, except CKE is disabled (LOW). Once the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock ball) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for tXSR because time is
required for the completion of any internal refresh in progress.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
7.8125µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Deep Power-Down
Deep power-down is an operating mode used to achieve maximum power reduction by
eliminating the power of the whole memory array of the devices. Array data will not be
retained once the device enters deep power-down mode.
This mode is entered by having all banks idle then CS# and WE# held LOW with RAS#
and CAS# held HIGH at the rising edge of the clock, while CKE is LOW. This mode is
exited by asserting CKE HIGH.
Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 9 on page 23).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 10 on page 23, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE commands to different banks is
defined by tRRD.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 9:
Activating a Specific Row in a Specific Bank
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A12
BANK
ADDRESS
BA0, BA1
DON´T CARE
Figure 10:
Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3
T0
T1
T2
T3
CLK
tCK
tCK
COMMAND
ACTIVE
NOP
tCK
NOP
READ or
WRITE
tRCD (MIN)
DON’T CARE
READs
READ bursts are initiated with a READ command, as shown in Figure 11.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 12 on page 25 shows general
timing for each possible CL setting.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 11:
READ Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A8
COLUMN
ADDRESS
A9, A11, A12
EN AP
A101
DIS AP
BA0, BA1
BANK
ADDRESS
DON’T CARE
Notes:
1. EN AP = enable auto precharge
DIS AP = disable auto precharge
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z.
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL -1.
Figure 7 on page 16 shows CLs of two and three; data element n + 3 is either the last of a
burst of four or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous
READ command. Full-speed random read accesses can be performed to the same bank,
as shown in Figure 12 on page 25, or each subsequent READ may be performed to a
different bank.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 12:
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
X = 1 cycle
BANK,
COL b
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
DOUT
b
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CL = 3
DON’T CARE
Notes:
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1. Each READ command may be to any bank. DQM is LOW.
25
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 13:
Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CL = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
a
NOP
DOUT
x
NOP
DOUT
m
CL = 3
DON’T CARE
Notes:
1. Each READ command may be to any bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 14 on page 27 and
Figure 15 on page 28. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress dataout from the READ. Once the WRITE command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 (in Figure 15 on page 28) then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13 on
page 26 shows the case where the clock frequency allows for bus contention to be
avoided without adding a NOP cycle, and Figure 15 on page 28 shows the case where the
additional NOP is needed.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated). The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 16 on page 28 for
each possible CL; data element n + 3 is either the last of a burst of four or the last desired
of a longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Figure 14:
READ-to-WRITE
T0
T1
T2
T3
T4
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
WRITE
BANK,
COL b
tCK
tHZ
DOUT n
DQ
DIN b
tDS
DON’T CARE
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. CL = 3. The READ command may be to any bank, and the WRITE command may be to any
bank. If a burst of one is used, then DQM is not required.
27
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 15:
READ-to-WRITE with Extra Clock Cycle
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
WRITE
BANK,
COL b
tHZ
DIN b
DOUT n
DQ
tDS
DON’T CARE
Notes:
Figure 16:
1. CL = 3. The READ command may be to any bank, and the WRITE command may be to any
bank.
READ-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
BANK a,
ROW
DOUT
n+2
DOUT
n+1
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CL = 3
DON’T CARE
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. DQM is LOW.
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 17 on page 29 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
Figure 17:
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 3
DON’T CARE
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. DQM is LOW.
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 18.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z and any additional input
data will be ignored (see Figure 19 on page 31).
Figure 18:
WRITE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A8
COLUMN
ADDRESS
A9, A11, A12
EN AP
A101
DIS AP
BA0, BA1
BANK
ADDRESS
VALID ADDRESS
Notes:
DON’T CARE
1. EN AP = enable auto precharge
DIS AP = disable auto precharge
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 20 on page 31. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 21 on page 32, or each subsequent WRITE may be
performed to a different bank.
Figure 19:
WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
DQ
DIN
n
DIN
n+1
DON’T CARE
Notes:
Figure 20:
1. BL = 2. DQM is LOW.
WRITE-to-WRITE
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
DIN
b
DON’T CARE
Notes:
1. DQM is LOW. Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 22 on page 32. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not activated). The PRECHARGE command should be issued tWR after the clock edge at which
the last desired input data element is registered. The auto precharge mode requires a
t
WR of at least one clock plus time, regardless of frequency.
In addition, when truncating a WRITE burst at high clock frequencies (tCK < 15ns), the
DQM signal must be used to mask input data for the clock edge prior to, and the clock
edge coincident with, the PRECHARGE command. An example is shown in Figure 23 on
page 33. Data n + 1 is either the last of a burst of two or the last desired of a longer burst.
Following the PRECHARGE command, a subsequent command to the same bank
cannot be issued until tRP is met.
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
31
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Figure 21:
Random WRITE Cycles
T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DIN
n
DIN
a
DIN
x
DIN
m
CLK
DQ
DON’T CARE
Notes:
Figure 22:
1. Each WRITE command may be to any bank. DQM is LOW.
WRITE-to-READ
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DOUT
b
DOUT
b+1
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
DON’T CARE
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. The WRITE command may be to any bank, and the READ command may be to any bank.
DQM is LOW. CL = 2 for illustration.
32
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 23:
WRITE-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
NOP
ACTIVE
NOP
CLK
tWR@ tCK ≥ 15ns
DQM
t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
tWR@ tCK < 15ns
DQM
t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
BANK
(a or all)
BANK a,
COL n
NOP
NOP
ACTIVE
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
DON’T CARE
Notes:
Figure 24:
1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Terminating a WRITE Burst
T0
T1
T2
COMMAND
WRITE
BURST
TERMINATE
ADDRESS
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
CLK
DQ
NEXT
COMMAND
DON’T CARE
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command will be ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock previous to the BURST
TERMINATE command. This is shown in Figure 24 on page 33, where data n is the last
desired data element of a longer burst.
PRECHARGE
The PRECHARGE command (see Figure 25 on page 34) is used to deactivate the open
row in a particular bank or the open row in all banks. The bank(s) will be available for a
subsequent row access some specified time (tRP) after the precharge command is
issued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank
has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank.
Figure 25:
PRECHARGE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9, A11, A12
All Banks
A10
Bank Selected
BA0,1
BANK
ADDRESS
VALID ADDRESS
DON’T CARE
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (64ms) since no REFRESH operations are performed in
this mode.
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 28 on page 36.
Figure 26:
Power-Down
((
))
((
))
CLK
tCKS
CKE
> tCKS
((
))
COMMAND
((
))
((
))
NOP
NOP
All banks idle
Input buffers gated off
Enter power-down mode.
Exit power-down mode.
ACTIVE
tRCD
tRAS
tRC
DON’T CARE
Deep Power-Down
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data on the memory array will not
be retained once deep power-down mode is executed. Deep power-down mode is
entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH
at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep
power-down.
Figure 27:
Deep Power-Down Command
CK#
CK
CKE
CS#
RAS#
CAS#
WE#
A0–A12
BA0, BA1
DON’T CARE
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
35
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 28:
Deep Power-Down
T0
T1
Ta1
Ta2
Ta3
))
((
))
CK
tIS
tCKE
CKE
COMMAND
Ta01
T2 ( (
((
))
DPD2
NOP
All Banks idle with no
activity on the data bus
T = 100µs
((
))
((
))
NOP
Enter deep power-down mode
Vaild3
NOP
Exit deep power-down mode
DON’T CARE
Notes:
1. Clock must be stable prior to CKE going HIGH.
2. DPD = Deep power-down mode command; PRE ALL = Precharge all banks.
3. Exit of deep power-down mode must be followed by the sequence described in the Deep
Power-Down” section on page 35.
In order to exit deep power-down mode, CKE must be asserted HIGH. After exiting, the
following sequence is needed in order to enter a new command:
1. Maintain NOP input conditions for a minimum of 100µs.
2. Issue PRECHARGE commands for all banks.
3. Issue two or more AUTO REFRESH commands.
The values of the mode register and extended mode register will be retained upon
exiting deep power-down.
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended (see
examples in Figure 29 on page 37 and Figure 30 on page 37).
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
36
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 29:
Clock Suspend During WRITE Burst
T0
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN
n+1
DIN
n+2
CLK
CKE
INTERNAL
CLOCK
COMMAND
BANK,
COL n
ADDRESS
DIN
n
DIN
DON’T CARE
Notes:
Figure 30:
1. For this example, BL = 4 or greater, and DQM is LOW.
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
ADDRESS
BANK,
COL n
DQ
NOP
NOP
DOUT
n
NOP
DOUT
n+1
NOP
NOP
DOUT
n+2
DOUT
n+3
DON’T CARE
Notes:
1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed BL.
READ commands access columns according to the programmed BL and sequence, just
as in the normal mode of operation.
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Concurrent Auto Precharge
An access command (READ or WRITE) to a second bank while an access command with
auto precharge enabled on a first bank is executing is not allowed by SDRAMs, unless
the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent
auto precharge. Four cases where concurrent auto precharge occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 31).
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 32 on page 39).
Figure 31:
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
Page Active
READ - AP
BANK n
NOP
READ - AP
BANK m
READ with Burst of 4
NOP
NOP
NOP
Idle
Interrupt Burst, Precharge
tRP - BANK m
t RP - BANK n
BANK m
ADDRESS
Page Active
Precharge
READ with Burst of 4
BANK n,
COL a
NOP
BANK m,
COL d
DOUT
a
DQ
DOUT
a+1
DOUT
d
DOUT
d+1
CL = 3 (bank n)
CL = 3 (bank m)
DON’T CARE
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. DQM is LOW.
38
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
Figure 32:
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
READ with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
Write-Back
WRITE with Burst of 4
BANK n,
COL a
t WR - BANK m
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CL = 3 (bank n)
DON’T CARE
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN d at T4.
39
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Operations
WRITE with Auto Precharge
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 33).
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 34).
Figure 33:
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
NOP
READ - AP
BANK m
WRITE with Burst of 4
DIN
a
DQ
NOP
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
Interrupt Burst, Write-Back
Page Active
BANK m
NOP
BANK m,
COL d
DOUT
d+1
DOUT
d
DIN
a+1
CL = 3 (bank m)
DON’T CARE
Notes:
Figure 34:
1. DQM is LOW.
WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE with Burst of 4
WRITE - AP
BANK m
NOP
Interrupt Burst, Write-Back
tWR - BANK n
BANK m
ADDRESS
DQ
Page Active
NOP
Precharge
tRP - BANK n
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK n,
COL a
DIN
a
NOP
BANK m,
COL d
DIN
a+1
DIN
a+2
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. DQM is LOW.
40
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Truth Tables
Truth Tables
Table 6:
Truth Table – CKE
Notes: 1–4
CKEn-1
CKEn
Current State
Commandn
Actionn
L
L
L
H
H
L
Power-Down
Self refresh
Clock suspend
Deep power-down
Power-Down
Deep power-down
Self refresh
Clock suspend
All banks idle
All banks idle
All banks idle
Reading or writing
X
X
X
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
BURST TERMINATE
AUTO REFRESH
VALID
Table 8 on page 44
Maintain power-down
Maintain self refresh
Maintain clock suspend
Maintain deep power-down
Exit power-down
Exit deep power-down
Exit self refresh
Exit clock suspend
Power-Down entry
Deep power-down entry
Self refresh entry
Clock suspend entry
H
H
Notes:
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
Notes
5
6
5
7
8
5
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result
of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Deep power-down is power savings feature of this Mobile SDRAM device. This command is
BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW.
6. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
7. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during the
tXSR period.
8. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
41
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Truth Tables
Table 7:
Truth Table – Current State Bank n, Command to Bank n
Notes: 1–6; notes appear below table
Current State
CS#
RAS#
CAS#
WE#
Any
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
Idle
Row active
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
Notes:
Command (Action)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
Notes
7
7
8
9
9
10
9
9
10
11
9
9
10
11
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 6 on page 41) and
after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
3. Current state definitions:
The bank has been precharged, and tRP has been met.
A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 7, and according to Table 8 on page 44.
Idle:
Row active:
Precharging:
Starts with registration of a PRECHARGE command and ends when
RP is met. Once tRP is met, the bank will be in the idle state.
Starts with registration of an ACTIVE command and ends when tRCD
is met. Once tRCD is met, the bank will be in the row active state.
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends whentRP has been met. Once tRP is met, the bank
will be in the idle state.
t
Row activating:
Read w/autoprecharge enabled:
Write w/autoprecharge enabled:
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Truth Tables
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing:
6.
7.
8.
9.
10.
11.
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
Starts with registration of an AUTO REFRESH command and ends
when tRFC is met. Once tRFC is met, the SDRAM will be in the all
banks idle state.
Accessing mode
Starts with registration of a LOAD MODE REGISTER command and
register:
ends when tMRD has been met. Once tMRD is met, the Mobile
SDRAM will be in the all banks idle state.
Precharging all:
Starts with registration of a PRECHARGE ALL command and ends
when tRP is met. Once tRP is met, all banks will be in the idle state.
All states and sequences not shown are illegal or reserved.
Not bank-specific; requires that all banks are idle.
Does not affect the state of the bank and acts as a NOP to that bank.
READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
This command is BURST TERMINATE when CKE is HIGH.
43
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Truth Tables
Table 8:
Truth Table – Current State Bank n, Command to Bank m
Notes: 1–6; notes appear below and on next page
Current State
CS#
RAS#
CAS#
WE#
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Idle
Row
activating,
active, or
precharging
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
Read
(with auto
precharge)
Write
(with auto
precharge)
Notes:
Command (Action)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7, 8
7, 9
10
7, 11
7, 12
10
7, 13, 14
7, 13, 15
10
7, 13, 16
7, 13, 17
10
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (Table 6 on page 41) and after
tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
Idle:
Row active:
Read:
Write:
Read w/autoprecharge enabled:
Write w/autoprecharge enabled:
The bank has been precharged, and tRP has been met.
A row in the bank has been activated, and tRCD has been met. No
data bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends whentRP has been met. Once tRP is met, the bank
will be in the idle state.
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued
when all banks are idle.
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Truth Tables
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 11 on
page 24).
9. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used one clock prior to the WRITE command to prevent bus contention.
10. Burst in bank n continues as initiated.
11. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the
data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
12. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank will interrupt the WRITE on bank n when registered. The last
valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m burst.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n
will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE
to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in
registered one clock prior to the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m interrupt the WRITE on bank n when registered. The PRECHARGE to
bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE to
bank m.
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
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Electrical Specifications
Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed in Table 9 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 9:
Absolute Maximum Ratings
Voltage/Temperature
Voltage on VDD/VDDQ supply relative to VSS
Voltage on inputs, NC or I/O balls relative to VSS
Storage temperature plastic
Table 10:
Min
Max
Units
–0.3
–0.3
–55
+2.7
+2.7
+150
V
°C
DC Electrical Characteristics and Operating Conditions
Notes: 1, 5, 6; notes appear on pages 51–52
Parameter/Condition
Symbol
Supply voltage
I/O supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output high voltage:
Output low voltage:
Input leakage current:
Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V)
Operating temperature
Commercial
Industrial
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
46
VDD
VDDQ
VIH
VIL
VOH
VOL
II
TA
TA
Min
Max
1.7
1.95
1.7
1.95
0.8 × VDDQ VDDQ + 0.3
–0.3
+0.3
0.9 × VDDQ
–
–
0.2
–1.0
1.0
0
–40
+70
+85
Units
V
V
V
V
V
V
µA
Notes
22
22
28
28
°C
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Electrical Specifications
Table 11:
Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11; notes appear on pages 51–52
AC Characteristics
-75
Parameter
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out High-Z time
Data-out Low-Z time
Data-out hold time (load)
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE command period
ACTIVE-to-READ or WRITE delay
Refresh period (8,192 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time
Exit SELF REFRESH-to-ACTIVE command
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
Symbol
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
Min
t
AC (3)
AC (2)
t
AH
t
AS
t
CH
t
CL
tCK (3)
tCK (2)
t
CKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ (3)
tHZ (2)
tLZ
tOH
tRAS
tRC
tRCD
tREF
tRFC
tRP
tRRD
tT
tWR
tXSR
Max
Min
6
9
t
47
-8
1
1.5
3
3
7.5
9.6
1
2.5
1
1.5
1
1.5
7
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
tCK
ns
ns
ns
120,000
7
9
1
2.5
48
72
20
64
80
19
2
0.3
15
80
Units
1
2.5
3
3
8
10
1
2.5
1
2.5
1
2.5
6
9
1
2.5
44
67.5
19
Max
1.2
120,000
64
80
19
2
0.5
15
80
1.2
Notes
23
23
10
10
7
31
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Electrical Specifications
Table 12:
AC Functional Characteristics
Notes: 5, 6, 8, 9,11; notes appear on pages 51–52
Parameter
Symbol
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
CL = 3
Data-out High-Z from PRECHARGE command
CL = 2
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48
t
CCD
CKED
t
PED
t
DQD
tDQM
t
DQZ
t
DWD
t
DAL
t
DPL
t
BDL
t
CDL
tRDL
tMRD
tROH(3)
tROH(2)
t
-75
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
-8
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
Units
t
CK
CK
t
CK
t
CK
tCK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
tCK
tCK
tCK
tCK
t
Notes
17
14
14
17
17
17
17
15, 21
16, 21
17
17
16, 21
25
17
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Electrical Specifications
Table 13:
IDD Specifications and Conditions (x16)
Notes: 1, 5, 6, 11, 13; notes appear on pages 51–52; VDD = 1.7V to 1.95V, VDDQ = 1.7V to 1.95V
Max
Parameter/Condition
Operating current:
Active mode; Burst = 1; READ or WRITE; tRC = tRC (MIN)
Standby current:
Power-down mode; All banks idle; CKE = LOW
Standby current:
Non-power-down mode; All banks idle; CKE = HIGH
Standby current:
Active mode; CKE = LOW; CS# = HIGH; All banks active; No
accesses in progress
Standby current:
Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD
met; No accesses in progress
Operating current:
Burst mode; READ or WRITE; All banks active, half DQs toggling
every cycle
tRFC = tRFC (MIN)
Auto refresh current
tRFC = 7.8125µs
CKE = HIGH; CS# = HIGH
Deep power-down
Table 14:
Symbol
-75
-8
Units
Notes
IDD1
95
90
mA
18, 19
IDD2P
Standard
IDD2P
Low Power
IDD2N
500
500
µA
29
300
300
20
20
mA
IDD3P
20
20
mA
12, 19
IDD3N
30
30
mA
12, 19
IDD4
90
85
mA
18, 19
IDD5
IDD6
IZZ
85
5
10
80
5
10
mA
mA
µA
12, 18, 19,
26
29, 30
IDD Specifications and Conditions (x32)
Notes: 1, 5, 6, 11, 13; notes appear on pages 51–52; VDD = 1.7V to 1.95V, VDDQ = 1.7V to 1.95V
Max
Parameter/Condition
Operating current:
Active mode; Burst = 1; READ or WRITE; tRC = tRC (MIN)
Standby current:
Power-down mode; All banks idle; CKE = LOW
Standby current:
Non-power-down mode; All banks idle; CKE = HIGH
Standby current:
Active mode; CKE = LOW; CS# = HIGH; All banks active; No
accesses in progress
Standby current:
Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD
met; No accesses in progress
Operating current:
Burst mode; READ or WRITE; All banks active, half DQs toggling
every cycle
tRFC = tRFC (MIN)
Auto refresh current
tRFC = 7.8125µs
CKE = HIGH; CS# = HIGH
Deep power-down
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MT48H32M16LF_1.fm - Rev. H 6/07 EN
49
Symbol
-75
-8
Units
Notes
IDD1
115
110
mA
18, 19
IDD2P
Standard
IDD2P
Low Power
IDD2N
500
500
µA
29
300
300
20
20
mA
IDD3P
20
20
mA
12, 19
IDD3N
30
30
mA
12, 19
IDD4
120
115
mA
18, 19
IDD5
IDD6
IZZ
85
5
10
80
5
10
mA
mA
µA
12, 18, 19,
26
29, 30
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Electrical Specifications
Table 15:
IDD7 Specifications and Conditions (x16 and x32)
Notes:1–6, 8, 11, 13, 15, 27; notes appear on pages 51–52; VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Self refresh
CKE = LOW; tCK = tCK (MIN);
Address and control inputs are stable;
Data bus inputs are stable.
Figure 35:
Symbol
Low IDD7
Option “L”
Standard IDD7
Option
Units
Notes
IDD7a
IDD7b
IDD7c
IDD7d
IDD7a
IDD7b
IDD7c
IDD7d
IDD7a
IDD7b
IDD7c
IDD7d
IDD7a
IDD7b
IDD7c
IDD7d
IDD7a
IDD7b
IDD7c
IDD7d
300
230
180
160
250
200
170
150
210
175
155
140
180
155
145
135
170
145
135
130
500
430
380
360
440
380
350
330
410
365
335
305
390
350
315
300
380
340
320
290
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
17, 29
Full array, 85°C
Full array, 70°C
Full array, 45°C
Full array, 15°C
Half array, 85°C
Half array, 70°C
Half array, 45°C
Half array, 15°C
1/4 array, 85°C
1/4 array, 70°C
1/4 array, 45°C
1/4 array, 15°C
1/8 array, 85°C
1/8 array, 70°C
1/8 array, 45°C
1/8 array, 15°C
1/16 array, 85°C
1/16 array, 70°C
1/16 array, 45°C
1/16 array, 15°C
Typical Self Refresh Current vs. Temperature
250
Full array
Half array
1/4 array
1/8 array
1/16 array
Current (µA)
200
150
100
50
0
-40
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-30
-20
-10
0
50
10
20
30
40
Temperature (°C)
50
60
70
80
90
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Notes
Table 16:
Capacitance (x16)
Note: 2; notes appear on pages 51–52
Parameter
Input capacitance: CLK
Input capacitance: All other input-only balls
Input/Output capacitance: DQs
Table 17:
Symbol
Min
Max
Units
CI1
CI2
CIO
2.0
2.0
2.5
5.0
5.0
6.0
pF
pF
pF
Symbol
Min
Max
Units
CI1
CI2
CIO
2.0
2.0
2.5
5.0
5.0
6.0
pF
pF
pF
Capacitance (x32)
Note: 2; notes appear on pages 51–52
Parameter
Input capacitance: CLK
Input capacitance: All other input-only balls
Input/Output capacitance: DQs
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +1.8V; TA = 25°C; ball under test biased at
0.9V, 1.25V, and 1.4V, respectively; f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (–40°C ≤ TA ≤ +85°C for TA on IT parts) is
ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
20pF
Test loads with full DQ driver strength. Performance will vary with actual system DQ
bus capacitive loading, termination, and programmed drive strength.
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover
point. If the input transition time is longer than tT (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
51
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Notes
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -75, and tCK = 8ns for -8, CL = 3.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤ 3ns.
23. The only time that the clock frequency is allowed to change is during clock stop,
power down, or self-refresh modes.
24. Auto precharge mode only. The precharge timing budget (tRP) begins at 7ns for -8
after the first clock delay, after the last WRITE is executed. May not exceed limit set for
precharge mode.
25. Parameter guaranteed by design.
26. CKE is HIGH during refresh command period tRFC (MIN), else CKE is LOW. The IDD7
limit is actually a nominal value and does not result in a fail value.
27. Values for IDD7 for 85°C are 100 percent tested. Values for 70°C, 45°C, and 15°C are
sampled only.
28. IOUT = 4mA for full-drive strength. Other drive strengths require appropriate scale.
29. Current is taken 500ms after entering into this operating mode to allow tester measuring unit settling time.
30. Deep power-down current is a nominal value at 25°C. This parameter is not tested.
31. There must be one tCK during the tWR time for WRITE auto precharge.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
52
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Timing Diagrams
Figure 36:
Initialize and Load Mode Register
T0
CLK
((
))
((
))
Tn + 1
T1
tCK
To + 1
Tp + 1
Tq + 1
Tr + 1
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tCKS tCKH
CKE
((
))
((
))
COMMAND1
((
))
((
))
DQM
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
CODE
((
))
((
))
VALID
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
CODE
((
))
((
))
VALID
((
))
((
))
BA0, BA1
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0
BA0 == L,
L,
BA1
BA1==HL
((
))
((
))
VALID
((
))
((
))
DQ
((
))
((
))
((
))
((
))
tRP
tRFC2
tCMS tCMH
NOP
((
))
((
))
PRE
AR
((
))
((
))
AR
((
))
((
))
LMR
((
))
((
))
LMR
((
))
((
))
((
))
((
))
VALID
((
))
((
))
((
))
((
))
((
))
((
))
tAS tAH
ALL BANKS
t AS tAH
tAS tAH
High-Z
BA0 = L,
BA1 = L
((
))
((
))
((
))
T = 100µs
Power-up:
VDD and
CLK stable
tRFC2
tMRD3
Load Mode
Register
Precharge
all banks
tMRD3
Load Extended
Mode Register
DON’T CARE
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. PRE = PRECHARGE command, AR = AUTO REFRESH command, LMR = LOAD MODE REGISTER
command.
2. Only NOPs or COMMAND INHIBITs may be issued during tRFC time.
3. At least one NOP or COMMAND INHIBIT is required during tMRD time.
53
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 37:
Power-Down Mode
T0
T1
tCK
CLK
T2
((
))
((
))
tCL
tCKS
tCH
CKE
tCKS
PRECHARGE
Tn + 2
tCKS
((
))
tCKH
tCMS tCMH
COMMAND
Tn + 1
NOP
((
))
((
))
NOP
NOP
ACTIVE
DQM
((
))
((
))
A0–A9, A11, A12
((
))
((
))
ROW
((
))
((
))
ROW
((
))
((
))
BANK
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
tAH
BANK(S)
High-Z
((
))
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. Violating refresh requirements during power-down may result in a loss of data.
See Table 11 on page 47.
54
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 38:
Clock Suspend Mode
T0
T1
T2
tCK
CLK
T3
T4
T5
T6
T7
T8
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM
tAS
A0–A9,
A11, A12
tAH
2
COLUMN e
COLUMN m2
tAS
tAH
A10
tAS
BA0, BA1
tAH
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
DOUT m
tHZ
DOUT m + 1
tDS
tDH
DOUT e
DOUT e + 1
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. A9 and A11 = “Don’t Care.” See Table 11 on page 47.
55
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 39:
Auto Refresh Mode
T0
T1
CLK
tCK
T2
((
))
((
))
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
NOP
AUTO
REFRESH
NOP
A0–A9,
A11, A12
ALL BANKS
A10
SINGLE BANK
tAS
DQ
((
))
( ( NOP
))
To + 1
((
))
AUTO
REFRESH
NOP
((
))
((
))
DQM
BA0, BA1
((
))
((
))
((
))
CKE
COMMAND
Tn + 1
tCL
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
BANK
((
))
((
))
tAH
BANK(S)
High-Z
tRP
tRFC
tRFC
Precharge all
active banks
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
DON’T CARE
UNDEFINED
1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not
required. See Table 11 on page 47.
56
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 40:
Self Refresh Mode
T0
T1
CLK
tCK
tCL
tCH
T2
tCKS
> tRAS
CKE
COMMAND
tCKS
tCKH
tCMS
tCMH
PRECHARGE
Tn + 1
((
))
((
))
AUTO
REFRESH
((
))
((
))
((
))
NOP ( (
((
))
((
))
((
))
((
))
A0–A9,
A11, A12
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ALL BANKS
SINGLE BANK
tAS
BA0, BA1
DQ
To + 2
AUTO
REFRESH
))
DQM
A10
To + 1
((
))
((
))
((
))
NOP
((
))
((
))
tAH
BANK(S)
High-Z
tRP
Precharge all
active banks
tXSR
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not
required. See Table 11 on page 47.
57
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 41:
READ – Without Auto Precharge
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
PRECHARGE
tCMH
DQM
tAS
ROW
ADDR
tAS
ROW
COLUMN m
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK(S)
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
tOH
DOUT m + 1
BANK
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tRP
CL
tHZ
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.
58
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 42:
READ – With Auto Precharge
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM
tAS
ROW
ADDR
tAS
ROW
COLUMN m
tAH
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
tRCD
DOUT m
tAC
tOH
DOUT m + 1
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tRP
CL
tHZ
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 4, CL = 2.
59
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 43:
Single READ – Without Auto Precharge
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP3
NOP3
T6
T7
T8
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
PRECHARGE
NOP
ACTIVE
NOP
tCMH
DQM
tAS
ROW
ADDR
tAS
ROW
COLUMN m
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK(S)
tOH
tAC
DQ
tLZ
tRCD
BANK
DOUT m
tHZ
CL
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRECHARGE.
60
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 44:
Single READ – With Auto Precharge
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP3
READ
T6
T7
T8
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
NOP3
tCMS
NOP
NOP
ACTIVE
NOP
tCMH
DQM
tAS
ROW
ADDR
tAS
ROW
COLUMN m
tAH
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
ROW
tAH
BANK
BANK
BANK
tOH
tAC
DQ
DOUT m
tRCD
tHZ
CL
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 1, CL = 2, and the READ burst is followed by an auto precharge.
61
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 45:
Alternating Bank Read Accesses
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM
tAS
ADDR
ROW
tAS
A10
ROW
COLUMN m
tAH
ROW
COLUMN b
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK 0
BANK 0
BANK 3
BANK 3
tAC
tOH
tAC
DQ
tLZ
tRCD - bank 0
DOUT m
tAC
BANK 0
tAC
tAC
tOH
tOH
tOH
DOUT m + 1
DOUT m + 2
DOUT m + 3
tRP - bank 0
CL - bank 0
tAC
tOH
DOUT b
tRCD - bank 0
tRAS - bank 0
tRC - bank 0
tRCD - bank 4
tRRD
CL - bank 4
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 4, CL = 2.
62
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 46:
READ – Continuous-Page Burst
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
((
))
((
))
tCK
tCH
tCKS
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAH
ROW
tAS
((
))
((
))
NOP
BURST TERM
NOP
NOP
((
))
((
))
COLUMN m
tAH
((
))
((
))
ROW
tAS
BA0, BA1
Tn + 4
((
))
((
))
DQM
A10
Tn + 3
((
))
((
))
tCMS
ADDR
Tn + 2
tCKH
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tAC
tAC
tOH
Dout m
DQ
DOUT m+1
tLZ
tRCD
CAS Latency
tAC
tOH
tAC ( (
))
tOH
((
))
DOUT m+2
((
))
tAC
tOH
DOUT m-1
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
DOUT m
tOH
DOUT m+1
tHZ
All locations within same row
Full page completed
Notes:
tAC
tOH
DON’T CARE
UNDEFINED
1. For this example, CL = 2.
63
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 47:
READ – DQM Operation
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP
T6
T7
NOP
NOP
T8
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
tCMH
DQM
tAS
ROW
ADDR
tAS
COLUMN m
tAH
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
tOH
tAC
tAC
tOH
tOH
DQ
DOUT m
tLZ
tRCD
tHZ
CL
tLZ
DOUT m + 2
DOUT m + 3
tHZ
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, CL = 2.
64
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 48:
WRITE – Without Auto Precharge
T0
tCK
CLK
T1
tCL
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
T7
T8
T9
PRECHARGE
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
ADDR
ROW
tAS
A10
ROW
COLUMN m
tAH
ALL BANKs
ROW
ROW
tAS
BA0, BA1
tAH
tAH
BANK
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tRAS
tDS
BANK
tDH
DIN m + 3
tWR2
tRP
tRC
DON’T CARE
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 1, and the WRITE burst is followed by an auto precharge.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency.
65
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 49:
WRITE – With Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
ADDR
ROW
tAS
A10
ROW
COLUMN m
tAH
ENABLE AUTO PRECHARGE
ROW
ROW
tAS
BA0, BA1
tAH
tAH
BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tRAS
tDS
tDH
DIN m + 3
tWR2
tRP
tRC
DON’T CARE
UNDEFINED
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 4.
2. There must be one tCK during the tWR time for WRITE auto precharge.
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 50:
Single WRITE – Without Auto Precharge
T0
T1
T2
tCK
CLK
T3
T4
NOP3
NOP3
T5
T6
T7
T8
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
PRECHARGE
NOP
ACTIVE
NOP
tCMH
DQM
tAS
ROW
ADDR
tAS
COLUMN m
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
tAH
BANK
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRP
tWR2
tRAS
tRC
DON’T CARE
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. PRECHARGE command not allowed or tRAS would be violated.
67
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 51:
Single WRITE – With Auto Precharge
T0
T1
tCK
CLK
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
ACTIVE
T9
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
NOP
NOP
WRITE
tCMS
NOP
NOP
tCMH
DQM
tAS
ADDR
tAS
ROW
COLUMN m
tAH
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
tDS
DQ
BANK
tDH
DIN m
tRCD
tRAS
tWR
tRP
tRC
DON’T CARE
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.
2. There must be one tCK during the tWR time for WRITE auto precharge.
68
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 52:
Alternating Bank Write Accesses
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
T9
WRITE
NOP
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
tCMH
DQM
tAS
ADDR
tAS
A10
ROW
COLUMN m
tAH
ROW
COLUMN b
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
tDS
tDH
DIN m
DQ
BANK 1
tDS
tDH
DIN m + 1
tDS
BANK 1
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tRCD - bank 0
tDS
DIN b
tWR - bank 0
tRAS - bank 0
tRC - bank 0
tDH
BANK 0
tDS
tDH
DIN b + 1
tDS
tDH
DIN b + 2
tRP - bank 0
tDS
tDH
DIN m + 3
tRCD - bank 0
tWR - bank 1
tRCD - bank 1
tRRD
DON’T CARE
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 4.
69
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 53:
WRITE – Continuous-Page Burst
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
COMMAND
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
NOP
tCMS tCMH
ADDR
tAS
A10
((
))
((
))
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m
tAH
((
))
((
))
ROW
tAS
BA0, BA1
tAH
ROW
Tn + 3
((
))
((
))
DQM
tAS
Tn + 2
((
))
((
))
CKE
tCMS
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
tDS
DIN m + 1
tDH
DIN m + 2
tRCD
tDS
tDH
DIN m + 3
((
))
((
))
tDS
tDH
DIN m - 1
All locations within same row
Full-page burst does
not self-terminate. Can
use BURST TERMINATE
command to stop.1, 2
Full page completed
DON’T CARE
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. tWR must be satisfied prior to PRECHARGE command.
2. Page left open; no tRP.
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 54:
WRITE – DQM Operation
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
ADDR
ROW
tAS
A10
COLUMN m
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DON’T CARE
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1. For this example, BL = 4.
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Package Dimensions
Package Dimensions
Figure 55:
54-Ball VFBGA (10mm x 11.5mm)
0.65 ±0.05
Seating
plane
0.1 A
A
Solder ball material:
SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or
SAC105 (98.5% Sn, 1% Ag, 0.5% Cu)
Substrate material: plastic laminate
54X Ø0.45
Dimensions
apply to solder
balls post reflow.
Pre-reflow balls
are Ø0.42 on
Ø0.40 SMD ball
pads.
Mold compound: epoxy novolac
10 ±0.10
5 ±0.05
Ball A1 ID
9
8
7
3
2
Ball A1 ID
1
A
5.75 ±0.05
B
3.2
C
D
6.4
11.5 ±0.1
E
F
G
H
0.8 TYP
J
0.8 TYP
3.2
6.4
Notes:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
1.0 MAX
1. All dimensions are in millimeters.
2. Green packaging composition is available upon request.
72
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©2005 Micron Technology, Inc. All rights reserved.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Package Dimensions
Figure 56:
90-Ball VFBGA (10mm x 13mm)
0.65 ±0.05
Seating
plane
A
Solder ball material:
SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or
SAC105 (98.5% Sn, 1% Ag, 0.5% Cu)
0.1 A
90X Ø0.45
Dimensions apply
to solder balls post
reflow. The prereflow balls are
Ø0.42 on Ø0.40
SMD ball pads.
Substrate material: plastic laminate
10 ±0.1
Mold compound: epoxy novolac
Ball A1 ID
5 ±0.05
9 8
7
3 2
Ball A1 ID
1
A
B
C
D
5.6
6.5 ±0.05
E
F
G
11.2
13 ±0.1
H
J
K
L
M
N
P
0.8 TYP
R
0.8 TYP
3.2
6.4
Notes:
1.0 MAX
1. All dimensions are in millimeters.
2. Green packaging composition is available upon request.
®
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[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, the Micron logo, and Endur-IC are trademarks of Micron Technology, Inc. All other trademarks are the
property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
73
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.