CY7C107D CY7C1007D 1-Mbit (1M x 1) Static RAM Features Functional Description [1] ■ Pin- and function-compatible with CY7C107B/CY7C1007B ■ High speed The CY7C107D and CY7C1007D are high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and tri-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected. The output pin (DOUT) is placed in a high-impedance state when: — tAA = 10 ns ■ Low active power — ICC = 80 mA @ 10 ns ■ Low complementary metal oxide semiconductor (CMOS) standby power — ISB2 = 3 mA ■ Deselected (CE HIGH) ■ When the write operation is active (CE and WE LOW) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A19). ■ 2.0 V data retention ■ Automatic power-down when deselected ■ CMOS for optimum speed/power ■ Transistor transistor logic (TTL) compatible inputs and outputs ■ CY7C107D available in Pb-free 28-pin 400-Mil wide Molded SOJ package. CY7C1007D available in Pb-free 28-pin 300-Mil wide Molded SOJ package Read from the device by taking Chip Enable (CE) LOW while while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the data output (DOUT) pin. Logic Block Diagram DIN CE SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 INPUT BUFFER 1M x 1 ARRAY POWER DOWN COLUMN DECODER A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 WE DOUT Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05469 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 7, 2011 [+] Feedback CY7C107D CY7C1007D Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics.................................................. 4 Capacitance ....................................................................... 5 Thermal Resistance........................................................... 5 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics................................................. 6 Data Retention Characteristics ........................................ 7 Data Retention Waveform ................................................ 7 Switching Waveforms ...................................................... 7 Document #: 38-05469 Rev. *H Truth Table ........................................................................ 8 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Page 2 of 14 [+] Feedback CY7C107D CY7C1007D Pin Configuration [2] SOJ Top View A10 A11 A12 A13 A14 A15 NC A16 A17 A18 A19 DOUT WE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A9 A8 A7 A6 A5 A4 NC A3 A2 A1 A0 DIN CE Selection Guide CY7C107D-10 CY7C1007D-10 Unit Maximum access time 10 ns Maximum operating current 80 mA Maximum CMOS standby current, ISB2 3 mA Note 2. NC pins are not connected on the die. Document #: 38-05469 Rev. *H Page 3 of 14 [+] Feedback CY7C107D CY7C1007D DC input voltage [3] 0.5 V to VCC + 0.5 V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature 65 °C to +150 °C Current into outputs (LOW) ......................................... 20 mA Static discharge voltage........................................... > 2001 V (per MIL-STD-883, Method 3015) Latch-up current ..................................................... > 200 mA Ambient temperature with power applied55 °C to +125 °C Operating Range Supply voltage on VCC relative to GND [3] 0.5 V to +6.0 V DC voltage applied to outputs in High-Z state [3] 0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Speed Industrial –40 °C to +85 °C 5 V 0.5 V 10 ns Electrical Characteristics (Over the Operating Range) Parameter Description 7C107D-10 7C1007D-10 Test Conditions Unit Min Max 2.4 V 0.4 V VOH Output HIGH voltage IOH = 4.0 mA VOL Output LOW voltage IOL = 8.0 mA VIH Input HIGH voltage 2.2 VCC + 0.5 V VIL Input LOW voltage [3] 0.5 0.8 V IIX Input leakage current GND < VI < VCC 1 +1 A IOZ Output leakage current GND < VI < VCC, output disabled –1 +1 A ICC VCC operating supply current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 80 mA 83 MHz 72 mA 66 MHz 58 mA 40 MHz 37 mA ISB1 Automatic CE Power-down current— TTL Inputs Max VCC, CE > VIH, VIN >VIH or VIN < VIL, f = f max 10 mA ISB2 Automatic CE Power-down current— CMOS Inputs Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = 0 3 mA Note 3. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. Document #: 38-05469 Rev. *H Page 4 of 14 [+] Feedback CY7C107D CY7C1007D Capacitance [4] Parameter CIN: Addresses Description Test Conditions Input capacitance Max TA = 25 °C, f = 1 MHz, VCC = 5.0 V CIN: Controls COUT Output capacitance Unit 7 pF 10 pF 10 pF Thermal Resistance [4] Parameter Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 300-Mil Wide SOJ 400-Mil Wide SOJ Unit 59.16 58.76 C/W 40.84 40.54 C/W AC Test Loads and Waveforms [5] ALL INPUT PULSES 3.0V Z = 50 90% OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* 90% 10% 10% GND 1.5V Rise Time: 3 ns (a) (b) Fall Time: 3 ns High-Z characteristics: R1 480 5V OUTPUT INCLUDING JIG AND SCOPE R2 255 5 pF (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05469 Rev. *H Page 5 of 14 [+] Feedback CY7C107D CY7C1007D Switching Characteristics (Over the Operating Range) [6] Parameter 7C107D-10 7C1007D-10 Description Unit Min Max Read Cycle tpower [7] VCC(typical) to the first access 100 s tRC Read cycle time 10 ns tAA Address to data valid 10 ns tOHA Data hold from address change 3 tACE CE LOW to data valid 10 ns 3 ns CE LOW to Low Z tLZCE [8] [8, 9] ns tHZCE CE HIGH to High Z 5 ns tPU [10] CE LOW to power-up 0 ns CE HIGH to power-down 10 ns tWC Write cycle time 10 ns tSCE CE LOW to write end 7 ns tAW Address set-up to write end 7 ns tHA Address hold from write end 0 ns tSA Address set-up to write start 0 ns tPWE WE pulse width 7 ns tSD Data set-up to write end 6 ns tHD Data hold from write end tPD [10] Write Cycle tLZWE tHZWE [11] 0 ns WE HIGH to Low Z [8] 3 ns WE LOW to High Z [8, 9] 6 ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 9. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 5. Transition is measured when the outputs enter a high impedance state. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 38-05469 Rev. *H Page 6 of 14 [+] Feedback CY7C107D CY7C1007D Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for data retention ICCDR Data retention current tCDR [12] Chip deselect to data retention time tR [13] Operation recovery time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Min Max Unit 2.0 V 3 mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC VDR > 2V 4.5V tR tCDR CE Switching Waveforms Figure 1. Read Cycle No. 1 (Address Transition Controlled) [14, 15] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 2. Read Cycle No. 2 [15, 16] ADDRESS tRC CE tACE tHZCE tLZCE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 12. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c) 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. 14. Device is continuously selected, CE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 38-05469 Rev. *H Page 7 of 14 [+] Feedback CY7C107D CY7C1007D Switching Waveforms(continued) Figure 3. Write Cycle No. 1 (CE Controlled) [17] tWC ADDRESS tSA tSCE CE tHA tAW tPWE WE tHD tSD DATA IN DATA VALID HIGH IMPEDANCE DATA OUT Figure 4. Write Cycle No. 2 (WE Controlled) [17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD tHD DATA VALID DATA IN tHZWE DATA UNDEFINED DATA OUT tLZWE HIGH IMPEDANCE Truth Table CE WE DOUT Mode Power H X High Z Power-down Standby (ISB) L H Data out Read Active (ICC) L L High Z Write Active (ICC) Note 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05469 Rev. *H Page 8 of 14 [+] Feedback CY7C107D CY7C1007D Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C107D-10VXI 51-85032 28-pin (400-Mil) Molded SOJ (Pb-free) CY7C1007D-10VXI 51-85031 28-pin (300-Mil) Molded SOJ (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 xx7 D - 10 VX I Temperature Range: I = Industrial Package Type: VX = 28-pin Molded SOJ (Pb-free) Speed: 10 ns D = C9, 90 nm Technology xx7 = 07 or 007 = (400-Mil / 300-Mil) 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05469 Rev. *H Page 9 of 14 [+] Feedback CY7C107D CY7C1007D Package Diagrams Figure 5. 28-pin (400-Mil) Molded SOJ, 51-85032 51-85032 *E Document #: 38-05469 Rev. *H Page 10 of 14 [+] Feedback CY7C107D CY7C1007D Package Diagrams(continued) Figure 6. 28-pin (300-Mil) Molded SOJ, 51-85031 51-85031 *D All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05469 Rev. *H Page 11 of 14 [+] Feedback CY7C107D CY7C1007D Acronyms Acronym Description BGA ball grid array CMOS complementary metal oxide semiconductor FBGA very fine ball gird array I/O input/output JTAG joint test action group SRAM static random access memory TTL Transistor transistor logic Document Conventions Units of Measure Symbol Unit of Measure °C degrees Celsius A microamperes mA milliampere MHz megahertz ns nanoseconds pF picofarads V volts ohms W watts Document #: 38-05469 Rev. *H Page 12 of 14 [+] Feedback CY7C107D CY7C1007D Document History Page Document Title: CY7C107D/CY7C1007D, 1-Mbit (1M x 1) Static RAM Document Number: 38-05469 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233722 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165) Pb-free offering in Ordering Information *B 263769 See ECN RKF Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics Table Shaded Ordering Information *C 307601 See ECN RKF Reduced Speed bins to –10 and –12 ns *D 560995 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 *E 802877 See ECN VKN Changed ICC specs from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz *F 2898399 03/24/2010 AJU Updated Package Diagrams *G 3104943 12/08/2010 AJU Added Ordering Code Definitions. *H 3218989 04/07/2011 PRAS Document #: 38-05469 Rev. *H Added TOC Added Acrnyms and Units of Measure table. Updated Package diagrams from *C to *D (51-85032) Page 13 of 14 [+] Feedback CY7C107D CY7C1007D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. 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Document #: 38-05469 Rev. *H Revised April 7, 2011 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback