FEDL610Q482-02 Issue Date: May.9, 2014 ML610Q482/ML610482 8-bit Microcontroller GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), buzzer driver, battery level detect circuit, and RC oscillation type A/D converter, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications. The on-chip debug function that is installed enables program debugging and programming. The ML610Q482P/ ML610482P supporting industrial temperature -40°C to +85°C, are also available. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system: 16-bit instructions − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function (ML610Q482) − Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 0.244µs (@4.096 MHz system clock) • Internal memory − ML610Q482 Internal 64KByte Flash ROM (32K×16 bits) (including unusable 1KByte TEST area) Internal 4KByte Data RAM (4096×8 bits) − ML610482 Internal 64KByte Mask ROM (32K×16 bits) (including unusable 1KByte TEST area) Internal 4KByte Data RAM (4096×8 bits) • Interrupt controller − 2 non-maskable interrupt sources (Internal source: 1, External source: 1) − 18 maskable interrupt sources (Internal sources: 14, External sources: 4) • Time base counter − Low-speed time base counter ×1 channel Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) − High-speed time base counter ×1 channel • Watchdog timer − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s @32.768 kHz) • Timers − 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3) − Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3) 1/32 FEDL610Q482-02 ML610Q482/ML610482 • PWM − Resolution 16 bits × 1 channel • Synchronous serial port − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable • UART − TXD/RXD × 1 channel − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • I2C bus interface − Master function only − Fast mode (400 kbps@4MHｚ), standard mode (100 kbps@1MHｚ, 50kbps@500kHz) • Buzzer driver − 4 output modes, 8 frequencies, 16 duty levels • RC oscillation type A/D converter − 24-bit counter − Time division × 2 channels • Analog Comparator − Operating voltage: VDD=1.8V～3.6V − Common mode input voltage: 0.2V～VDD－1.0V − Input offset voltage: 50mV(max) − Interrupt allow edge selection and sampling selection • General-purpose ports − Non-maskable interrupt input port × 1 channel − Input-only port × 6 channels (including secondary functions) − Output-only port × 4 channels (including secondary functions) − Input/output port × 22 channels (including secondary functions) • Reset − Reset through the RESET_N pin − Power-on reset generation when powered on − Reset when oscillation stop of the low-speed clock is detected − Reset by the watchdog timer (WDT) overflow • Power supply voltage detect function − Judgment voltages: One of 16 levels − Judgment accuracy: ±2% (Typ.) • Clock − Low-speed clock: (This LSI can not guarantee the operation withouｔ low-speed clock) Crystal oscillation (32.768 kHz/38.4KHz) − High-speed clock: Built-in RC oscillation (500 kHz) Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock − Selection of high-speed clock mode by software: Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock 2/32 FEDL610Q482-02 ML610Q482/ML610482 • Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). − STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) − Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. • Guaranteed operating range − Operating temperature: −20°C to +70°C (P version: −40°C to +85°C) − Operating voltage: VDD = 1.1V to 3.6V • Product name – Supported Function ROM type Operating temperature Product availability ML610Q482-ｘｘｘWA Flash ROM -20°C to +70°C Yes ML610Q482P-ｘｘｘWA Flash ROM -40°C to +85°C Yes ML610482-ｘｘｘWA Mask ROM -20°C to +70°C Yes ML610482P-ｘｘｘWA Mask ROM -40°C to +85°C Yes ROM type Operating temperature Product availability ML610Q482-ｘｘｘTB Flash ROM -20°C to +70°C Yes ML610Q482P-ｘｘｘTB Flash ROM -40°C to +85°C Yes ML610482-ｘｘｘTB Mask ROM -20°C to +70°C - ML610482P-ｘｘｘTB Mask ROM -40°C to +85°C - - Chip (Die) - -48-pin plastic TQFP - xxx: ROM code number Q:Flash ROM version P: Wide range temperature version WA: Chip TB: TQFP 3/32 FEDL610Q482-02 ML610Q482/ML610482 BLOCK DIAGRAM ML610Q482 Block Diagram Figure 1 show the block diagram of the ML610Q482. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE ALU TEST Instruction Decoder IN0* CS0* RS0* RT0* CRT0* RCM* IN1* CS1* RS1* RT1* CMPP CMPM DSR/CSR EA PC Instruction Register RESET & TEST Interrupt Controller INT 1 OSC INT 4 Power INT 1 INT 1 INT 4 WDT TBC VPP SSIO SCK0* SIN0* SOUT0* UART RXD0* TXD0* I2C SDA* SCL* INT 1 INT 1 INT 1 PWM PWM0* Buzzer BZ0* 8bit Timer ×4 BLD RC-ADC ×2 Analog Comparator Program Memory (Flash) 64Kbyte BUS Controller RAM 4096byte LSCLK* OUTCLK* VDDL VDDX LR Data-bus XT0 XT1 OSC0* OSC1* ECSR1～3 SP VDD VSS RESET_N ELR1～3 INT 9 INT 1 NMI P00 to P03 P10, P11 GPIO P20, P21, P22, P24 P30 to P35 P40 to P47 PA0 to PA7 Figure 1 ML610Q482 Block Diagram 4/32 FEDL610Q482-02 ML610Q482/ML610482 ML610482 Block Diagram Figure 2 show the block diagram of the ML610482. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE ALU TEST Instruction Decoder IN0* CS0* RS0* RT0* RCT0* RCM* IN1* CS1* RS1* RT1* CMPP CMPM * Secondary DSR/CSR EA PC Instruction Register RESET & TEST Interrupt Controller INT 1 OSC INT 4 Power INT 4 INT 1 INT 1 WDT SSIO SCK0* SIN0* UART RXD0* TXD0* INT 1 INT 1 I2C TBC SDA* SCL* INT 1 PWM PWM0* Buzzer BZ0* 8bit Timer ×4 BLD RC-ADC ×2 Analog Comparator Program Memory (Mask ROM) 64Kbyte BUS Controller RAM 4096byte LSCLK* OUTCLK* VDDL VDDX LR Data-bus XT0 XT1 OSC0* OSC1* ECSR1～3 SP VDD VSS RESET_N ELR1～3 INT 5 INT 1 NMI P00 to P03 P10, P11 GPIO P20, P21, P22, P24 P30 to P35 P40 to P47 PA0 to PA7 function or Tertiary function Figure 2 ML610482 Block Diagram 5/32 FEDL610Q482-02 ML610Q482/ML610482 PIN CONFIGURATION 36 35 34 33 32 31 30 29 28 27 26 25 P22 P21 P20 VSS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 ML610Q482 TQFP48 Pin Layout (Flash ROM version only) 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 VDD P11/OSC1 P10/OSC0 VSS VPP NMI RESET_N TEST P47 P46 P45 P44 CMPP CMPM P00 P01 P02 P03 VSS P24 P40 P41 P42 P43 1 2 3 4 5 6 7 8 9 10 11 12 P30 P31 P34 P32 P33 P35 VDD VDDL VSS VDDX XT0 XT1 Note: The assignment of the pads P30 to P35 are not in order. Figure 3 ML610Q482 TQFP48 Pin Configuration 6/32 FEDL610Q482-02 ML610Q482/ML610482 34 P20 33 VSS 32 PA7 31 PA6 30 PA5 29 PA4 28 PA3 27 PA2 26 PA1 25 PA0 □ □ □ □ □ □ □ □ □ □ □ □ （NC） 35 P21 ■ 36 P22 （NC） ML610Q482 Chip Pin Layout & Dimension ■ P33 41 □ □ 20 VPP P35 42 □ □ 19 NMI VDD 43 □ □ 18 RESET_N VDDL 44 □ □ 17 TEST VSS 45 □ □ 16 P47 VDDX 46 □ □ 15 P46 XT0 47 □ □ 14 P45 XT1 48 □ □ 13 P44 （NC) （NC) （NC) ■ ■ ■ ■ ■ ■ （NC) ■ □ □ □ □ □ □ □ □ □ □ □ □ ■ （NC） 21 VSS 12 □ P43 □ 11 40 P42 P32 10 22 P10/OSC0 P41 □ 9 □ P40 39 8 P34 P24 23 P11/OSC1 7 □ VSS □ 6 38 P03 P31 5 24 VDD P02 □ 4 □ P01 37 3 P30 P00 ■ 2 ■ CMPM ■ ■ 1 ■ ■ CMPP （NC) （NC) （NC) （NC) （NC) （NC) 3.00mm （NC) （NC) （NC) 2.76mm (NC): No Connection Note: The assignment of the pads P30 to P35 are not in order. Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 2.76 mm × 3.00 mm 48 pins 100 µm 80 µm × 80 µm 350 µm VSS level Figure 4 ML610Q482 Chip Layout & Dimension 7/32 FEDL610Q482-02 ML610Q482/ML610482 ML610Q482 Pad Coordinates Table 1 ML610Q482 Pad Coordinates Chip Center: X=0,Y=0 PAD No. Pad Name X (µm) Y (µm) PAD No. Pad Name X (µm) Y (µm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CMPP CMPM P00 P01 P02 P03 VSS P24 P40 P41 P42 P43 P44 P45 P46 P47 TEST RESET_N NMI VPP VSS P10 P11 VDD -1036.0 -830.0 -730.0 -482.0 -382.0 -134.0 -34.0 219.0 327.0 655.0 775.0 1023.0 1260.0 1260.0 1260.0 1260.0 1260.0 1260.0 1260.0 1260.0 1260.0 1261.3 1261.3 1260.0 -1380.0 -1380.0 -1380.0 -1380.0 -1380.0 -1380.0 -1380.0 -1380.0 -1380.0 -1380.0 -1380.0 -1380.0 -912.0 -778.0 -530.0 -426.0 -167.0 -67.0 181.0 281.0 411.0 610.0 858.0 1010.0 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS P20 P21 P22 P30 P31 P34 P32 P33 P35 VDD VDDL VSS VDDX XT0 XT1 1023.0 775.0 651.0 403.0 279.0 31.0 -93.0 -341.0 -458.0 -666.0 -766.0 -1032.0 -1260.0 -1260.0 -1260.0 -1260.0 -1260.0 -1260.0 -1260.0 -1260.0 -1260.0 -1260.0 -1260.0 -1260.0 1380.0 1380.0 1380.0 1380.0 1380.0 1380.0 1380.0 1380.0 1380.0 1380.0 1380.0 1380.0 922.0 769.0 521.0 417.0 169.0 67.0 -122.0 -333.0 -503.0 -673.0 -773.0 -1021.0 8/32 FEDL610Q482-02 ML610Q482/ML610482 25 PA0 26 PA1 27 PA2 29 PA4 28 PA3 30 PA5 31 PA6 33 VSS 32 PA7 35 P21 34 P20 36 P22 ML610482 Chip Pin Layout & Dimension 24 VDD 23 P11/OSC1 P30 37 P31 38 22 P10/OSC0 P34 39 P32 40 21 VSS 19 NMI P33 41 P35 42 18 RESET_N 17 TEST VDD 43 VDDL 44 VSS 45 2.46 mm 16 P47 15 P46 VDDX 46 XT0 47 14 P45 13 P44 P43 12 P41 10 P42 11 P24 8 P40 9 P03 6 VSS 7 P01 4 P02 5 CMPM 2 P00 3 CMPP 1 XT1 48 2.44 mm Y X Note: The assignment of the pads P30 to P35 are not in order. Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 2.44 mm × 2.46mm 48 pins 100 µm 80 µm × 80 µm 350 µm VSS level Figure 5 ML610482 Chip Layout & Dimension 9/32 FEDL610Q482-02 ML610Q482/ML610482 ML610482 Pad Coordinates Table 2 ML610482 Pad Coordinates Chip Center: X=0,Y=0 PAD No. Pad Name X (µm) Y (µm) PAD No. Pad Name X (µm) Y (µm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CMPP CMPM P00 P01 P02 P03 VSS P24 P40 P41 P42 P43 P44 P45 P46 P47 TEST RESET_N NMI -1010 -804 -704 -456 -356 -108 -8 205 313 641 761 1009 1100 1100 1100 1100 1100 1100 1100 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -842 -708 -460 -356 -97 3 251 VSS P10 P11 VDD 1100 1100 1100 1100 351 524 772 885 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS P20 P21 P22 P30 P31 P34 P32 P33 P35 VDD VDDL VSS VDDX XT0 XT1 1025 777 653 405 281 33 -91 -339 -451 -659 -759 -1025 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 844 691 443 339 91 -11 -212 -312 -434 -574 -694 -942 Note: PADNo.20 does not exist. 10/32 FEDL610Q482-02 ML610Q482/ML610482 PIN LIST PAD No. Primary function Secondary function Pin name I/O Function Pin name Negative power supply ⎯ ⎯ pin Positive power supply ⎯ ⎯ pin Power supply pin for ⎯ internal logic ⎯ (internally generated) Power supply pin for ⎯ low-speed oscillation ⎯ (internally generated) Power supply pin for ⎯ ⎯ Flash ROM Input/output pin for I/O ⎯ testing 7,21, 33,45 Vss 24,43 VDD 44 VDDL 46 VDDX 20 VPP 17 TEST 18 RESET_ N I Reset input pin 47 XT0 I 48 XT1 19 I/O Tertiary function Function ⎯ Pin name I/O ⎯ ⎯ ⎯ Function ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Low-speed clock oscillation pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ O Low-speed clock oscillation pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ NMI I Non-maskable interrupt pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3 P00/EXI 0 I ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4 P01/EXI 1 I ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 5 P02/EXI 2/RXD0 I ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6 P03/EXI 3 I ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 CMPP I ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2 CMPM I ⎯ ⎯ ⎯ ⎯ 22 P10 23 Input port, External interrupt 0, Capture 0 input Input port, External interrupt 1, Capture 1 input Input port, External interrupt 2, UART0 receive Input port, External interrupt 3 ⎯ ⎯ I Analog comparator non-inverted input Analog comparator inverted input Input port OSC0 I High-speed oscillation ⎯ ⎯ ⎯ P11 I Input port OSC1 O High-speed oscillation ⎯ ⎯ ⎯ 34 P20/LE D0 O Output port LSCLK O Low-speed clock output ⎯ ⎯ ⎯ 35 P21LED 1 O Output port OUTCLK O High-speed clock output ⎯ ⎯ ⎯ 36 P22/LE D2 O Output port BZ0 O BZ0 output ⎯ ⎯ ⎯ 8 P24/LE D4 O Output port PWM0 O PWM0 output ⎯ ⎯ ⎯ 37 P30 I/O Input/output port IN0 I RC type ADC0 oscillation input pin ⎯ ⎯ ⎯ 38 P31 I/O Input/output port CS0 O RC type ADC0 reference capacitor connection pin ⎯ ⎯ ⎯ 40 P32 I/O Input/output port RS0 O ⎯ ⎯ ⎯ 41 P33 I/O Input/output port RT0 O ⎯ ⎯ ⎯ 39 P34 I/O Input/output port RCT0 O PWM0 O PWM0 output RC type ADC0 reference resistor connection pin RC type ADC0 resistor sensor connection pin RC type ADC0 resistor/capacitor sensor connection pin 11/32 FEDL610Q482-02 ML610Q482/ML610482 PAD No. 42 Primary function Pin name I/O Function Secondary function Pin name I/O RCM O Tertiary function P35 I/O Input/output port I/O Input/output port I/O Input/output port SDA I/O Function RC type ADC oscillation monitor I2C data input/output SCL I/O I2C clock input/output I/O Input/output port I/O Input/output port Input/output port, Timer 0/Timer I/O 2/PWM0 external clock input Input/output port, I/O Timer 1/Timer 3 external clock input RXD0 I UART data input SOUT0 I I/O SSIO synchronous clock SSIO data output I TXD0 O UART data output PWM0 O PWM output IN1 I RC type ADC1 oscillation input pin SIN0 I SSIO0 data input CS1 O SCK0 I/O SSIO0 synchronous clock SOUT0 O SSIO0 data output ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 9 P40 10 P41 11 P42 12 P43 13 P44/T02 P0CK 14 P45/T13 P1CK 15 P46 I/O Input/output port RS1 O 16 P47 I/O Input/output port RT1 O 25 PA0 I/O ⎯ ⎯ 26 PA1 I/O ⎯ ⎯ 27 PA2 I/O ⎯ ⎯ 28 PA3 I/O ⎯ ⎯ 29 PA4 I/O ⎯ ⎯ 30 PA5 I/O ⎯ ⎯ 31 PA6 I/O ⎯ ⎯ 32 PA7 I/O ⎯ ⎯ Input/output port Input/output port Input/output port Input/output port Input/output port Input/output port Input/output port Input/output port RC type ADC1 reference capacitor connection pin RC type ADC1 reference resistor connection pin RC type ADC1 resistor sensor connection pin ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Pin name I/O ⎯ SIN0 SCK0 ⎯ Function ⎯ SSIO data input Note: *1：A VPP terminal exists only ML610Q482. 12/32 FEDL610Q482-02 ML610Q482/ML610482 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary/ Tertiary Logic — Negative — — — — Secondary Secondary — — Secondary — Secondary — Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive System Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. XT0 I Crystal connection pin for low-speed clock. XT1 O A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL are connected across this pin and VSS as required. OSC0 I Crystal/ceramic connection pin for high-speed clock. OSC1 O A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors CDH and CGH (see measuring circuit 1) are connected across this pin and VSS. This pin is used as the secondary function of the P10 pin(OSC0) and P11 pin(OSC1). LSCLK O Low-speed clock output pin. This pin is used as the secondary function of the P20 pin. OUTCLK O High-speed clock output pin. This pin is used as the secondary function of the P21 pin. General-purpose input port RESET_N I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P10,P11 I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose output port P20,P21, O General-purpose output port. Since these pins have secondary functions, the pins cannot be used as a P22,P24 port when the secondary functions are used. General-purpose input/output port P30-P35 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P40-P47 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. PA0-PA7 I/O General-purpose input/output port. P00-P03 I 13/32 FEDL610Q482-02 ML610Q482/ML610482 Pin name Primary/ Secondary/ Tertiary Logic Secondary Positive Primary/Se condary Positive Secondary Positive Secondary Positive I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P41 or P45 pin. I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. Tertiary — Tertiary Positive Tertiary Positive PWM0 output pin. This pin is used as the tertiary function of the P24 or P43 or P34 pin. PWM0 external clock input pin. This pin is used as the primary function of the P44 pin. Tertiary Positive Primary — Primary Positive/ negative Positive/ negative I/O UART TXD0 O RXD0 I Description UART data output pin. This pin is used as the secondary function of the P43 pin. UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. 2 I C bus interface 2 SDA I/O I C data input/output pin. This pin is used as the secondary function of the P40 pin. This pin has an NMOS open drain output. When using this pin as 2 a function of the I C, externally connect a pull-up resistor. 2 SCL O I C clock output pin. This pin is used as the secondary function of the P41 pin. This pin has an NMOS open drain output. When using this pin as a 2 function of the I C, externally connect a pull-up resistor. Synchronous serial (SSIO) SCK0 SIN0 SOUT0 PWM PWM0 T02P0CK O O External interrupt NMI I EXI0-3 Timer T02P0CK T13P1CK I I I External non-maskable interrupt input pin. An interrupt is generated on both edges. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00-P03 pins. External clock input pin used for both Timer 0 and Timer 2. The clocks for these timers are selected by software. This pin is used as the primary function of the P44 pin. External clock input pin used for both Timer 1 and Timer 3. The clocks for these timers are selected by software. This pin is used as the primary function of the P45 pin. Primary Primary — Primary — Buzzer BZ0 O Buzzer signal output pin. This pin is used as the secondary function of the P22 pin. LED drive LED0,1,2,4 O NMOS open drain output pins to drive LED. These pins are used as the primary function of the P20,P21,P22,P24 pins. Secondary Positive/ negative Primary Positive/ negative 14/32 FEDL610Q482-02 ML610Q482/ML610482 Pin name I/O Description RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function of the P30 pin. CS0 O Channel 0 reference capacitor connection pin. This pin is used as the secondary function of the P31 pin. RS0 O This pin is used as the secondary function of the P32 pin which is the reference resistor connection pin of Channel 0. RT0 O Resistor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P34 pin. CRT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P33 pin. RCM O RC oscillation monitor pin. This pin is used as the secondary function of the P35 pin. IN1 I Oscillation input pin of Channel 1. This pin is used as the secondary function of the P44 pin. CS1 O Reference capacitor connection pin of Channel 1. This pin is used as the secondary function of the P45 pin. RS1 O Reference resistor connection pin of Channel 1. This pin is used as the secondary function of the P46 pin. RT1 O Resistor sensor connection pin for measurement of Channel 1. This pin is used as the secondary function of the P47 pin. Analog comparator CMPP I Non-inverted input pin. CMPM I Inverted input pin. For testing TEST Power supply VSS VDD VDDL I/O Input/output pin for testing. A pull-down resistor is internally connected. — — — VDDX — VPP — Negative power supply pin. Positive power supply pin. Positive power supply pin (internally generated) for internal logic. Capacitors CL0 and CL1 (see measuring circuit 1) are connected between this pin and VSS. Plus-side power supply pin (internally generated) for low-speed oscillation. Capacitor Cx (see measuring circuit 1) is connected between this pin and VSS. Power supply pin for programming Flash ROM. A pull-up resistor is internally connected. Primary/ Secondary/ Tertiary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Logic — — — — — — — — — — — — — — — — — — — — — — — — — — Note: *1：A VPP terminal exists only ML610Q482. 15/32 FEDL610Q482-02 ML610Q482/ML610482 TERMINATION OF UNUSED PINS Table 2 shows methods of terminating the unused pins. Table 2 Pin *1 VPP RESET_N TEST NMI P00 to P03 P10, P11 P20, P21, P22, P24 P30 to P35 P40 to P47 PA0 to PA7 CMPP,CMPM Termination of Unused Pins Recommended pin termination Open Open Open Open VDD or VSS VDD Open Open Open Open VDD *1：A VPP terminal exists only ML610Q482. Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 16/32 FEDL610Q482-02 ML610Q482/ML610482 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 2 VPP *1 Ta = 25°C −0.3 to +9.5 V Power supply voltage 3 VDDL Ta = 25°C −0.3 to +3.6 V Power supply voltage 4 VDDX Ta = 25°C −0.3 to +3.6 V VIN Ta = 25°C −0.3 to VDD+0.3 V Input voltage Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V Output current 1 IOUT1 Port3–A, Ta = 25°C −12 to +11 mA Output current 2 IOUT2 Port2, Ta = 25°C −12 to +20 mA Power dissipation PD Ta = 25°C 1.16 W Storage temperature TSTG ⎯ −55 to +150 °C *1 : ML610Q482 only RECOMMENDED OPERATING CONDITIONS (VSS = 0V) Parameter Symbol Condition Range ML610Q482, ML610482 −20 to +70 ML610Q482P, ML610482P −40 to +85 ⎯ 1.1 to 3.6 30k to 36k 30k to 650k 30k to 4.2M 1.0±30% 0.1±30% 0.1±30% Operating temperature TOP Operating voltage VDD Operating frequency (CPU) fOP Capacitor externally connected to VDDL pin Capacitor externally connected to VDDX pin CL0 CL1 VDD = 1.1 to 3.6V VDD = 1.3 to 3.6V VDD = 1.8 to 3.6V ⎯ ⎯ CX ⎯ Unit °C V Hz µF µF 17/32 FEDL610Q482-02 ML610Q482/ML610482 CLOCK GENERATION CIRCUIT OPERATING CONDITIONS (VSS = 0V) Parameter Low-speed crystal oscillation frequency Recommended equivalent series resistance value of low-speed crystal oscillation Low-speed crystal oscillation *1 external capacitor High-speed crystal/ceramic oscillation frequency High-speed crystal oscillation external capacitor Symbol Condition fXTL Rating Unit Min. Typ. Max. ⎯ ⎯ 32.768k/38.4k ⎯ Hz RL ⎯ ⎯ ⎯ 40k Ω ⎯ 0 ⎯ CDL/CGL CL=6pF of crystal *2 oscillation CL=9pF of crystal oscillation CL=12pF of crystal oscillation ⎯ 6 ⎯ ⎯ 12 ⎯ ⎯ ⎯ 4.0M / 4.096M ⎯ fXTH pF Hz CDH ⎯ ⎯ 24 ⎯ pF ⎯ ⎯ 24 ⎯ CGH *1 : The external CDL and CGL need to be adjusted in consideration of variation of internal loading capacitance CD and CG, and other additional capacitance such as PCB layout. *2 : When using a crystal oscillator CL = 6pF, there is a possibility that can not be adjusted by external CDL and CGL. OPERATING CONDITIONS OF FLASH ROM (ML610Q482 only) Parameter Operating temperature Symbol TOP VDD VDDL VPP CEP YDR Operating voltage Write cycles Data retention *1 Condition At write/erase *1 At write/erase *1 At write/erase *1 At write/erase ⎯ ⎯ (VSS = 0V) Unit °C Range 0 to +40 2.75 to 3.6 2.5 to 2.75 7.7 to 8.3 10 10 V cycles years : Those voltages must be supplied to VDDL pin and VPP pin when programming and eraseing Flash ROM. VPP pin has an internal pulldown resister. CONDITIONS OF ANALOG COMPARATOR (VDD = 1.1 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Common mode Input voltage Input offset voltage Response time Wake-up time Circuit current (during operation) CMVIN VCMPOF TCMP TCMPw VDD = 1.8 to 3.6V VDD = 1.8 to 3.6V, Ta = 25°C VDD = 1.8 to 3.6V, Ta = 25°C Over drive = 100mV 0.2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VDD－1 50 100 3 V mV µｓ ｍｓ ICMP VDD = 1.8 to 3.6V,Ta = 25°C ⎯ 2 4 µA 1 18/32 FEDL610Q482-02 ML610Q482/ML610482 DC CHARACTERISTICS (1/6) (VDD = 1.1 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. 500kHz RC oscillation frequency fRC 4 PLL oscillation frequency* fPLL VDD = 1.3 to 3.6V Ta = 25°C Ta = −40 to +85°C LSCLK = 32.768kHz VDD = 1.8 to 3.6V Typ. −10% Typ. −35% -2.5% 500 500 8.192 Typ. +10% Typ. +35% +2.5% kHz kHz MHz Low-speed crystal oscillation ⎯ ⎯ 0.3 2 s TXTL 2 start time* 500kHz RC oscillation start TRC ⎯ ⎯ 50 500 µs time 1 High-speed crystal oscillation VDD = 1.8 to 3.6V ― 2 20 TXTH 3 start time* ms PLL oscillation start time TPLL VDD = 1.8 to 3.6V ― 1 10 Low-speed oscillation stop ⎯ 0.2 3 20 TSTOP *1 detect time Reset pulse width PRST ⎯ 200 ⎯ ⎯ µs Reset noise elimination ⎯ ⎯ ⎯ 0.3 PNRST pulse width Power-on reset activation ⎯ ⎯ ⎯ 10 ms TPOR power rise time 1 * : When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. 2 * : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF. 3 * : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera). 4 * : 1024 clock average. VIL1 RESET_N VIL1 PRST Reset pulse width (PRST) 0.9xVDD VDD 0.1xVDD TPOR Power-on reset activation power rise time (TPOR ) 19/32 FEDL610Q482-02 ML610Q482/ML610482 DC CHARACTERISTICS (2/6) (VDD = 1.1 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. BLD threshold voltage BLD threshold voltage temperature deviation VBLD ∆VBLD VDD = 1.35 to 3.6V LD2–0 = 0H LD2–0 = 1H LD2–0 = 2H LD2–0 = 3H LD2–0 = 4H LD2–0 = 5H LD2–0 = 6H LD2–0 = 7H LD2–0 = 8H LD2–0 = 9H LD2–0 = 0AH LD2–0 = 0BH LD2–0 = 0CH LD2–0 = 0DH LD2–0 = 0EH LD2–0 = 0FH VDD = 1.35 to 3.6V Typ. −2% ⎯ 1.35 1.4 1.45 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.7 2.9 Typ. +2% 0.1 ⎯ V 1 %/°C DC CHARACTERISTICS (ML610Q482) (3/6) (VDD = 1.1 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. CPU: In STOP state. 0.5 Ta = 25°C ⎯ 0.2 Supply current 1 IDD1 µA Low-speed/high-speed ⎯ ⎯ ⎯ 5 oscillation: stopped. CPU: In HALT state (LTBC, 1.3 Ta = 25°C ⎯ 0.5 2 4 Supply current 2 IDD2 µA WDT: Operating* * ). 6 ⎯ ⎯ ⎯ High-speed oscillation: Stopped. CPU: In 32.768kHz operating 7 Ta = 25°C ⎯ 5 1 2 Supply current 3 IDD3 µA state.* * 12 ⎯ ⎯ ⎯ High-speed oscillation: Stopped. 1 85 Ta = 25°C ⎯ 70 CPU: In 500kHz CR operating Supply current 4 IDD4 µA state. ⎯ ⎯ ⎯ 100 CPU: In 4.096MHz operating 1 Ta = 25°C ⎯ 0.83 2 mA Supply current 5 IDD5 state* .PLL: In oscillating state. ⎯ ⎯ ⎯ 1.2 VDD = 1.8 to 3.6V CPU: In 4.096MHz operating 1.4 Ta = 25°C ⎯ 1.3 state.Crystal/ceramic: In mA Supply current 6 IDD6 2 3 oscillating state. * * ⎯ ⎯ 2.0 ⎯ VDD = 3.0V 1 * : When the CPU operating rate is 100% (No HALT state). 2 * : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF. 3 * : Use 4.096MHz Crystal Oscillator HC49SFWB (Kyocera). 4 * : Significant bits of BLKCON0~BLKCON4 registers are all “1”. 20/32 FEDL610Q482-02 ML610Q482/ML610482 DC CHARACTERISTICS (ML610482) (4/6) (VDD = 1.1 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. CPU: In STOP state. 0.5 Ta = 25°C ⎯ 0.2 Supply current 1 IDD1 µA Low-speed/high-speed ⎯ ⎯ ⎯ 2.5 oscillation: stopped. CPU: In HALT state (LTBC, 1.3 Ta = 25°C ⎯ 0.5 2 4 Supply current 2 IDD2 µA WDT: Operating* * ). 3.5 ⎯ ⎯ ⎯ High-speed oscillation: Stopped. CPU: In 32.768kHz operating 5 Ta = 25°C ⎯ 3 1 2 Supply current 3 IDD3 µA state.* * 8 ⎯ ⎯ ⎯ High-speed oscillation: Stopped. 1 65 Ta = 25°C ⎯ 40 CPU: In 500kHz CR operating Supply current 4 IDD4 µA state. ⎯ ⎯ ⎯ 75 CPU: In 4.096MHz operating 0.65 Ta = 25°C ⎯ 0.5 2 Supply current 5 IDD5 mA state* .PLL: In oscillating state. ⎯ ⎯ ⎯ 0.75 VDD = 1.8 to 3.6V CPU: In 4.096MHz operating 1.1 Ta = 25°C ⎯ 0.9 state.Crystal/ceramic: In mA Supply current 6 IDD6 2 3 oscillating state. * * ⎯ ⎯ ⎯ 1.3 VDD = 3.0V 1 * : When the CPU operating rate is 100% (No HALT state). 2 * : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF. 3 * : Use 4.096MHz Crystal Oscillator HC49SFWB (Kyocera). 4 * : Significant bits of BLKCON0~BLKCON4 registers are all “1”. 21/32 FEDL610Q482-02 ML610Q482/ML610482 DC CHARACTERISTICS (5/6) Parameter (VDD = 1.1 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. IOL1 = +0.5mA, VDD = 1.8 to 3.6V IOL1 = +0.1mA, VDD = 1.3 to 3.6V VDD −0.5 VDD −0.3 VDD −0.3 ⎯ ⎯ IOL1 = +0.03mA, VDD = 1.1 to 3.6V VOL2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.5 0.5 ⎯ ⎯ 0.3 IOL2 = +5mA, VDD = 1.8 to 3.6V ⎯ ⎯ 0.5 VOL3 IOL3 = +3mA, VDD = 2.0 to 3.6V 2 (when I C mode is selected) ⎯ ⎯ 0.4 IOOH VOH = VDD (in high-impedance state) ⎯ ⎯ 1 IOH1 = −0.5mA, VDD = 1.8 to 3.6V Output voltage 1 (P20, P21, P22, nd P24/2 function is selected) (P30–P35) (P40–P47) (PA0–PA7) Output voltage 2 (P20, P21, P22, nd P24/2 function is Not selected) Output voltage 3 (P40, P41) Output leakage (P20, P21, P22, P24) (P30–P35) (P40–P47) *1 (PA0–PA7) VOH1 IOH1 = -0.03mA, VDD = 1.1 to 3.6V VOL1 IOOL IIH1 Input current 1 (RESET_N) Input current 1 (TEST) IIL1 IIH1 IIL1 Input current 2 (NMI) (P00–P03) (P10, P11) (P30–P35) (P40–P47) (PA0–PA7) IOH1 = -0.1mA, VDD = 1.3 to 3.6V −1 ⎯ ⎯ 0 −600 −600 −600 20 10 2 -1 ⎯ −300 −300 −300 300 300 300 ⎯ 1 −20 -10 -2 600 600 600 ⎯ VDD = 1.8 to 3.6V 2 30 200 VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V 0.2 0.01 −200 −200 −200 30 30 −30 −30 −30 200 200 −2 -0.2 -0.01 VOL = VSS (in high-impedance state) VIH1 = VDD VDD = 1.8 to 3.6V VIL1 = VSS VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VIH1 = VDD VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VIL1 = Vss IIH2 VIH2 = VDD (when pulled-down) IIL2 VIL2 = VSS (when pulled-up) IIH2Z VIH2 = VDD (in high-impedance state) ⎯ ⎯ 1 IIL2Z VIL2 = VSS (in high-impedance state) −1 ⎯ ⎯ V 2 µA 3 µA 4 22/32 FEDL610Q482-02 ML610Q482/ML610482 DC CHARACTERISTICS (6/6) Parameter Input voltage 1 (RESET_N) (TEST) (NMI) (P00–P03) (P10, P11) (P31–P35) (P40–P43) (P45–P47) *1 (PA0–PA7) Input voltage 2 (P30, P44) Input pin capacitance (NMI) (P00–P03) (P10, P11) (P30–P35) (P40–P47) (PA0–PA7) (VDD = 1.1 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. VDD = 1.3 to 3.6V 0.7 ×VDD ⎯ VDD VDD = 1.1 to 3.6V 0.7 ×VDD ⎯ VDD VDD = 1.3 to 3.6V 0 ⎯ 0.3 ×VDD VIH1 VIL1 VDD = 1.1 to 3.6V 0 ⎯ 0.2 ×VDD VIH2 ⎯ 0.7 ×VDD ⎯ VDD VIL2 ⎯ 0 ⎯ 0.3 ×VDD CIN f = 10kHz Vrms = 50mV Ta = 25°C ⎯ ⎯ 5 V 5 pF ⎯ 23/32 FEDL610Q482-02 ML610Q482/ML610482 MEASURING CIRCUITS MEASURING CIRCUIT 1 XT0 32.768kHz crystal XT1 CGH P10/OSC0 CDH P11/OSC1 4.096MHz crystal VDD VDDL VDDX CV: 1µF 1µF CL0: 0.1µF CL1: CX: 0.1µF 24pF CGH: 24pF CDH: 32.768kHz crystal: C-001R (Epson Toyocom) 4.096MHz crystal: HC49SFWB (Kyocera) VSS A CV CL1 CL0 CX MEASURING CIRCUIT 2 (*2) VIL Input pins (*1) Output pins VIH VDD VDDL VDDX V VSS (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. 24/32 FEDL610Q482-02 ML610Q482/ML610482 MEASURING CIRCUIT 3 (*2) VIL Input pins RS1 Output pins VIH VDD VDDL VDDX A VSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. MEASURING CIRCUIT 4 Input pins Output pins (*3) A VDD VDDL VDDX VSS *3: Measured at the specified output pins. VIL Input pins (*1) Output pins VIH VDD VDDL VDDX Waveform monitoring MEASURING CIRCUIT 5 VSS *1: Input logic circuit to determine the specified measuring conditions. 25/32 FEDL610Q482-02 ML610Q482/ML610482 AC CHARACTERISTICS (External Interrupt) (VDD = 1.1 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. External interrupt disable period TNUL Interrupt: Enabled (MIE = 1), CPU: NOP operation System clock: 32.768kHz ⎯ 76.8 106.8 µs P00–P03 (Rising-edge interrupt) tNUL P00–P03 (Falling-edge interrupt) tNUL NMI, P00–P03 (Both-edge interrupt) tNUL AC CHARACTERISTICS (UART) (VDD = 1.3 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Transmit baud rate ⎯ tTBRT 1 ⎯ BRT* 1 ⎯ s 1 BRT* BRT* 1 BRT* s −3% +3% 1 * : Baud rate period (including the error of the clock frequency selected) set with the UART0 baud rate register (UA0BRTL,H) and the UART0 mode register 0 (UA0MOD0). Receive baud rate ⎯ tRBRT tTBRT TXD0* tRBRT RXD0* *: Indicates the secondary function of the port. 26/32 FEDL610Q482-02 ML610Q482/ML610482 AC CHARACTERISTICS (Synchronous Serial Port) (VDD = 1.3 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. 2 When RC oscillation is active * 10 ⎯ ⎯ µs SCLK input cycle (VDD = 1.3 to 3.6V) tSCYC (slave mode) When high-speed oscillation is 1 ⎯ ⎯ µs 3 active * (VDD = 1.8 to 3.6V) SCLK output cycle 1 tSCYC ⎯ ⎯ SCLK* ⎯ s (master mode) 2 When RC oscillation is active * 4 ⎯ ⎯ µs (VDD = 1.3 to 3.6V) SCLK input pulse width tSW (slave mode) When high-speed oscillation is 0.4 ⎯ ⎯ µs 3 active * (VDD = 1.8 to 3.6V) 1 1 1 SCLK* SCLK* SCLK* SCLK output pulse width s tSW ⎯ (master mode) ×0.4 ×0.5 ×0.6 2 When RC oscillation is active * ⎯ ⎯ 500 (VDD = 1.3 to 3.6V) SOUT output delay time ns tSD (slave mode) When high-speed oscillation is 240 3 active * (VDD = 1.8 to 3.6V) 2 When RC oscillation is active * ⎯ ⎯ 500 (VDD = 1.3 to 3.6V) SOUT output delay time ns tSD (master mode) When high-speed oscillation is 240 3 active * (VDD = 1.8 to 3.6V) SIN input setup time tSS ⎯ 80 ⎯ ⎯ ns (slave mode) 2 When RC oscillation is active * 500 ⎯ ⎯ (VDD = 1.3 to 3.6V) SIN input setup time tSS ns (master mode) When high-speed oscillation is 240 ⎯ ⎯ 3 active * (VDD = 1.8 to 3.6V) 2 When RC oscillation is active * 300 ⎯ ⎯ (VDD = 1.3 to 3.6V) SIN input hold time ns tSH When high-speed oscillation is 80 ⎯ ⎯ 3 active * (VDD = 1.8 to 3.6V) 1 * : Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1) 2 * : When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0) 3 * : When Crystal/ceramic oscillation , built-in PLL oscillation , or external clock input is selected with OSCM1–0 of the frequency control register (FCON0) tSCYC tSW tSW SCLK0* tSD tSD SOUT0* tSS tSH SIN0* *: Indicates the secondary function of the port. 27/32 FEDL610Q482-02 ML610Q482/ML610482 AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kbit/s) (VDD = 1.8 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency ⎯ 0 ⎯ 100 kHz fSCL SCL hold time tHD:STA ⎯ 4.0 ⎯ ⎯ µs (start/restart condition) SCL ”L” level time tLOW ⎯ 4.7 ⎯ ⎯ µs SCL ”H” level time tHIGH ⎯ 4.0 ⎯ ⎯ µs SCL setup time tSU:STA ⎯ 4.7 ⎯ ⎯ µs (restart condition) SDA hold time tHD:DAT ⎯ 0 ⎯ ⎯ µs SDA setup time tSU:DAT ⎯ 0.25 ⎯ ⎯ µs SDA setup time ⎯ 4.0 ⎯ ⎯ µs tSU:STO (stop condition) Bus-free time ⎯ 4.7 ⎯ ⎯ µs tBUF AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kbit/s) (VDD = 1.8 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency ⎯ 0 ⎯ 400 kHz fSCL SCL hold time tHD:STA ⎯ 0.6 ⎯ ⎯ µs (start/restart condition) SCL ”L” level time ⎯ 1.3 ⎯ ⎯ µs tLOW SCL ”H” level time ⎯ 0.6 ⎯ ⎯ µs tHIGH SCL setup time tSU:STA ⎯ 0.6 ⎯ ⎯ µs (restart condition) SDA hold time tHD:DAT ⎯ 0 ⎯ ⎯ µs SDA setup time tSU:DAT ⎯ 0.1 ⎯ ⎯ µs SDA setup time tSU:STO ⎯ 0.6 ⎯ ⎯ µs (stop condition) Bus-free time ⎯ 1.3 ⎯ ⎯ µs tBUF Start condition Restart condition Stop condition P40/SDA P41/SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 28/32 FEDL610Q482-02 ML610Q482/ML610482 AC CHARACTERISTICS (RC Oscillation A/D Converter) (VDD = 1.3 to 3.6V, VSS = 0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified) Parameter Symbol RS0, RS1, RT0, RT0-1,RT1 fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 Resistors for oscillation Oscillation frequency VDD = 1.5V RS to RT oscillation frequency *1 ratio VDD = 1.5V Oscillation frequency VDD = 3.0V RS to RT oscillation frequency *1 ratio VDD = 3.0V Rating Condition Unit Min. Typ. Max. CS0, CT0, CS1 ≥ 740pF 1 ⎯ ⎯ kΩ Resistor for oscillation = 1kΩ Resistor for oscillation = 10kΩ Resistor for oscillation = 100kΩ RT0, RT0-1, RT1 = 1kHz RT0, RT0-1, RT1 = 10kHz RT0, RT0-1, RT1 = 100kHz Resistor for oscillation = 1kΩ Resistor for oscillation = 10kΩ Resistor for oscillation = 100kΩ RT0, RT0-1, RT1 = 1kHz RT0, RT0-1, RT1 = 10kHz RT0, RT0-1, RT1 = 100kHz 209.4 41.29 4.71 5.567 0.99 0.104 407.3 49.76 5.04 8.006 0.99 0.100 330.6 55.27 5.97 5.982 1 0.108 486.7 59.28 5.993 8.210 1 0.108 435.1 64.16 7.06 6.225 1.01 0.118 594.6 72.76 7.04 8.416 1.01 0.115 kHz kHz kHz ⎯ ⎯ ⎯ kHz kHz kHz ⎯ ⎯ ⎯ 1 * : Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1−CS0 oscillation) fOSCX(RS0−CS0 oscillation) , IN0 CS0 RCT0 (*1) VIL *1: Input logic circuit to determine the specified measuring conditions. VDDL fOSCX(RT1−CS1 oscillation) fOSCX(RS1−CS1 oscillation) VDDX RT0, RT0-1, RT1: 1kΩ /10kΩ/100kΩ RS0, RS1: 10kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 RCM VDD CV RT1 RI1 RT0 RS0 RS0 RT0 Input pins VIH , CVR1 RI0-1 CT0 CS0 RI0 CVR0 RS1 fOSCX(RT0−CS0 oscillation) fOSCX(RS0−CS0 oscillation) (x = 1, 2, 3) CS1 Kfx = Frequency measurement (fOSCX) VSS CL1 CL0 CX Note: - Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. - When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. - Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. 29/32 FEDL610Q482-02 ML610Q482/ML610482 PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 30/32 FEDL610Q482-02 ML610Q482/ML610482 REVISION HISTORY Document No. FEDL610Q482P-01 FEDL610Q482-02 Date Dec.9, 2009 May.9,2014 Page Previous Current Edition Edition – All 1,3,4,5,6, 7,9,12,14 ,1516,17, 18,21,22, 23,24 – All 1,3,4,5,6, 7,,8,9,10, 11,13,16, 1718,19, 20,21,22, 23,26,27, 28,29 3 4 - 18 18 19 29 30 Description Formally edition 1 Change header and footer Add ML610Q482, ML610482 and ML610482P Change from "Shipment" to " Product name – Supported Function " Change "RESET" to "Reset pulse width (PRST)" and " Power-on reset activation power rise time (TPOR )". Update Package Dimensions 31/32 FEDL610Q482-02 ML610Q482/ML610482 NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. 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