Freescale MCF51AC128A Mcf51ac256 coldfire microcontroller Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MCF51AC256
Rev.1 , 06/2008
MCF51AC256
80 LQFP
14 mm × 14 mm
MCF51AC256 ColdFire
Microcontroller
The MCF51AC256 is a member of the ColdFire® family of
32-bit variable-length reduced instruction set (RISC)
microcontroller. This document provides an overview of the
MCF51AC256 series, focusing on its highly integrated and
diverse feature set.
The MCF51AC256 series is based on the V1 ColdFire core
and operates at processor core speeds up to 50.33 MHz. As
part of Freescale’s Controller Continuum®, it is an ideal
upgrade for designs based on the MC9S08AC128 series of
8-bit microcontrollers.
The MCF51AC256 features the following functional units:
• V1 ColdFire core with background debug module
• Up to 256 KBytes of flash memory
• Up to 32 Kbytes of static RAM (SRAM)
• Up to two analog comparators (ACMP)
• Analog-to-digital converter (ADC) with up to 24
channels
• Controller-area network (CAN)
• Cyclic redundancy check (CRC)
• Inter-integrated circuit (IIC)
• Keyboard interrupt (KBI)
• Multipurpose clock generator (MCG)
• Rapid general-purpose input/output (RGPIO)
• Two serial communications interfaces (SCI)
• Up to two serial parallel interfaces (SPI)
• Two flexible timer modules (FTM)
• Timer pulse-width modulator (TPM)
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Preliminary—Subject to Change Without Notice
64 LQFP
10 mm × 10 mm
64 QFP
14 mm × 14 mm
Table of Contents
1
2
3
4
MCF51AC256 Family Configurations . . . . . . . . . . . . . . . . . . . .3
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.4 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.5 Pinouts and Packaging . . . . . . . . . . . . . . . . . . . . . . . . .10
Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .14
2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .14
2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .14
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15
2.4 Electrostatic Discharge (ESD)
Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . .16
2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .22
2.7 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .23
2.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.9 External Oscillator (XOSC) Characteristics . . . . . . . . .26
2.10 MCG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.11.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . .30
2.11.3 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.12 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .35
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .36
3.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .36
3.2 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .39
3.3 64-pin QFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . .42
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
List of Figures
Figure 1. MCF51AC256 Block Diagram . . . . . . . . . . . . . . . . . . . . 4
Figure 2. 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. 64-Pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Typical IOH vs. VDD–VOH at VDD = 3V
(Low Drive, PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. Typical IOH vs. VDD–VOH at VDD = 3V
(High Drive, PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Typical IOH vs. VDD–VOH at VDD = 5V
(Low Drive, PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . .
Figure 7. Typical IOH vs. VDD–VOH at VDD = 5 V
(High Drive, PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . .
Figure 8. ADC Input Impedance Equivalency Diagram . . . . . . .
Figure 9. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . .
Figure 13.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . .
Figure 14.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . .
Figure 15.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . .
Figure 16.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . .
21
21
24
29
30
30
31
33
33
34
34
List of Tables
Table 1. MCF51AC256 Series Device Comparison . . . . . . . . . . 3
Table 2. MCF51AC256 Series Functional Units . . . . . . . . . . . . . 5
Table 3. Orderable Part Number Summary. . . . . . . . . . . . . . . . . 9
Table 4. Pin Availability by Package Pin-Count . . . . . . . . . . . . . 11
Table 5. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 15
Table 7. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 16
Table 10.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. ESD and Latch-Up Protection Characteristics. . . . . . . 17
Table 11. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 22
Table 12.Analog Comparator Electrical Specifications. . . . . . . . 23
Table 13.5 Volt 12-bit ADC Operating Conditions . . . . . . . . . . . 23
Table 14.5 Volt 12-bit ADC Characteristics
(VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . 24
Table 15.Oscillator Electrical Specifications
(Temperature Range = –40 to 105×C Ambient) . . . . . 26
Table 16.MCG Frequency Specifications
(Temperature Range = –40 to 125×C Ambient) . . . . . 27
Table 17.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18.TPM/FTM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19.MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . 31
Table 20.SPI Electrical Characteristic . . . . . . . . . . . . . . . . . . . . 32
Table 21.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 22.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51AC256 Family Configurations
1
MCF51AC256 Family Configurations
1.1
Device Comparison
The MCF51AC256 series is summarized in Table 1.
Table 1. MCF51AC256 Series Device Comparison
MCF51AC256A MCF51AC256B MCF51AC128A
MCF51AC128C
80-pin 64-pin
80-pin
Feature
80-pin 64-pin 80-pin
64-pin
Flash memory size (Kbytes)
256
128
RAM size (Kbytes)
32
32 or 161
V1 ColdFire core with BDM (background debug
module)
Yes
ACMP1 (analog comparator)
Yes
ACMP2 (analog comparator)
Yes
ADC (analog-to-digital converter) channels (12-bit)
24
CAN (controller area network)
Yes
No
Yes
COP (computer operating properly)
Yes
CRC (cyclic redundancy check)
Yes
RTI
Yes
DBG (debug)
Yes
IIC1 (inter-integrated circuit)
Yes
IRQ (interrupt request input)
Yes
INTC (interrupt controller)
Yes
KBI (keyboard interrupts)
Yes
LVD (low-voltage detector)
Yes
MCG (multipurpose clock generator)
Yes
OSC (crystal oscillator)
Yes
Port
I/O2
69
54
69
54
RGPIO (rapid general-purpose I/O)
16
SCI1, SCI2 (serial communications interfaces)
Yes
SPI1 (serial peripheral interface)
Yes
SPI2 (serial peripheral interface)
Yes
No
Yes
No
FTM1 (flexible timer module) channels
FTM2 channels
No
69
54
69
54
Yes
No
Yes
No
6
2
6
2
Yes
No
Yes
No
6
6
2
6
2
TPM3 (timer pulse-width modulator) channels
VBUS (debug visibility bus)
64-pin
2
Yes
No
Yes
No
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
MCF51AC256 Family Configurations
1
2
The members of MCF51AC128 with CAN support have 32 K-byte RAM. The other members have 16 K-byte RAM.
Up to 16 pins on Ports E and F are shared with the ColdFire Rapid GPIO module.
1.2
Block Diagram
BDM
ADC
BKPT
TPMCLK
ColdFire V1 core
RESET
FTM1
SIM
IRQ/
TPMCLK
TPMCLK
COP
LVD
IRQ
FTM2
FLASH
MCF51AC256 = 256 KB
MCF51AC128 = 128 KB
Port A:
ACMP2O
ACMP2 ACMP2–
ACMP2+
IIC1
Port F:
FTM1CH5
FTM1CH4
FTM1CH3
FTM1CH2
Port E:
FTM1CH1
FTM1CH0
Port H:
FTM2CH5
FTM2CH4
FTM2CH3
FTM2CH2
Port F:
FTM2CH1
FTM2CH0
KBI
MCG
OSC
CAN
TPMCLK
TPM3
Port B:
TPM3CH1
TPM3CH0
Port C:
SDA1
SCL1
Port G:
KBIP4
KBIP3
KBIP2
KBIP1
KBIP0
Port D:
KBIP7
KBIP6
KBIP5
Port G:
EXTAL
XTAL
Port A:
RXCAN
TXCAN
Port B
BKGD/MS
Port J:
DDATA3DDATA0
PST3VBUS PST0
Port H:
PSTCLK
Port D:
ACMP1O
ACMP1 ACMP1–
ACMP1+
Port C
DBG
Port B:
ADP7ADP0
Port D:
ADP15ADP8
Port A:
ADP17ADP16
Port G:
ADP19ADP18
Port H:
ADP23ADP20
Port D
VREFH
VREFL
VDDAD
VSSAD
Port E
VREFH
VREFL
VDDAD
VSSAD
Port A
Figure 1 shows the connections between the MCF51AC256 series pins and modules.
RAM
SCI1
Port E:
RXD1
TXD1
SCI2
Port C:
RXD2
TXD2
SPI1
Port E:
SS1
SPSCK1
MOSI1
MISO1
RTC
VREG
Port H:
SS2
SPI2 SPSCK2
MOSI2
MISO2
Port G
VDD
VSS
VSS
Port E:
RGPIO7
RGPIO6
RGPIO5
RGPIO4
RGPIO3
RGPIO2
RGPIO1
RGPIO0
CRC
PTG6/EXTAL
PTG5/XTAL
PTG4/KBI1P4/AD1P19
PTG3/KBI1P3/AD1P18
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBI1P0
Port H
RGPIO
PTD7/KBI1P7/AD1P15
PTD6/FTM1CLK/AD1P14
PTD5/AD1P13
PTD4/FTM2CLK/AD1P12
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10/ACMP1O
PTD1/AD1P9/ACMP1–
PTD0/AD1P8/ACMP1+
PTE7/RGPIO7/SPSCK1
PTE6/RGPIO6/MOSI1
PTE5/RGPIO5/MISO1
PTE4/RGPIO4/SS1
PTE3/RGPIO3/FTM1CH1
PTE2/RGPIO2/FTM1CH0
PTE1/RGPIO1/RxD1
PTE0/RGPIO0/TxD1
PTF7/RGPIO15
PTF6/FTM1FLT/RGPIO14
PTF5/RGPIO13/FTM2CH1
PTF4/RGPIO12/FTM2CH0
PTF3/RGPIO11/FTM1CH5
PTF2/RGPIO10/FTM1CH4
PTF1/RGPIO9/FTM1CH3
PTF0/RGPIO8/FTM1CH2
PTH6/MISO2
PTH5/MOSI2
PTH4/SPSCK2
PTH3/FTM2CH5/BKPT/AD1P23
PTH2/FTM2CH4/PSTCLK1/AD1P22
PTH1/FTM2CH3/PSTCLK0/AD1P21
PTH0/FTM2CH2/AD1P20
Port J
Port F:
RGPIO15
RGPIO14
RGPIO13
RGPIO12
RGPIO11
RGPIO10
RGPIO9
RGPIO8
Port F
MCF51AC256 = 32 KB
MCF51AC128 = 16 KB
PTA7/AD1P17
PTA6/AD1P16
PTA5/ACMP2+
PTA4/ACMP2–
PTA3/ACMP2O
PTA2
PTA1/RXCAN
PTA0/TXCAN
PTB7/AD1P7
PTB6/AD1P6
PTB5/AD1P5
PTB4/AD1P4
PTB3/AD1P3
PTB2/AD1P2
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
PTC6/FTM2FLT
PTC5/RxD2
PTC4/SS2
PTC3/TxD2
PTC2/MCLK
PTC1/SDA1
PTC0/SCL1
PTJ7/DDATA3
PTJ6/DDATA2
PTJ5/DDATA1
PTJ4/DDATA0
PTJ3/PST3
PTJ2/PST2
PTJ1/PST1
PTJ0/PST0
Figure 1. MCF51AC256 Block Diagram
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51AC256 Family Configurations
1.3
Features
Table 2 describes the functional units of the MCF51AC256 series.
Table 2. MCF51AC256 Series Functional Units
Functional Unit
Function
CF1CORE (V1 ColdFire core)
Executes programs and interrupt handlers
BDM (background debug module)
Provides single pin debugging interface (part of the V1 ColdFire core)
DBG (debug)
Provides debugging and emulation capabilities (part of the V1 ColdFire
core)
VBUS (debug visibility bus)
Allows for real-time program traces (part of the V1 ColdFire core)
SIM (system integration module)
Controls resets and chip level interfaces between modules
FLASH (flash memory)
Provides storage for program code, constants and variables
RAM (random-access memory)
Provides storage for program variables
RGPIO (rapid general-purpose input/output)
Allows for I/O port access at CPU clock speeds
VREG (voltage regulator)
Controls power management across the device
COP (computer operating properly)
Monitors a countdown timer and generates a reset if the timer is not
regularly reset by the software
LVD (low-voltage detect)
Monitors internal and external supply voltage levels, and generates a reset
or interrupt when the voltages are too low
CF1_INTC (interrupt controller)
Controls and prioritizes all device interrupts
ADC (analog-to-digital converter)
Measures analog voltages at up to 12 bits of resolution
FTM1, FTM2 (flexible timer/pulse-width
modulators)
Provide a variety of timing-based features
TPM3 (timer/pulse-width modulator)
Provides a variety of timing-based features
CRC (cyclic redundancy check)
Accelerates computation of CRC values for ranges of memory
ACMP1, ACMP2 (analog comparators)
Compare two analog inputs
IIC1 (inter-integrated circuit)
Supports standard IIC communications protocol
KBI (keyboard interrupt)
Provides pin interrupt capabilities
MCG (multipurpose clock generator)
Provides clocking options for the device, including a phase-locked loop
(PLL) and frequency-locked loop (FLL) for multiplying slower reference
clock sources
OSC (crystal oscillator)
Allows a crystal or ceramic resonator to be used as the system clock source
or reference clock for the PLL or FLL
CAN (controller area network)
Supports standard CAN communications protocol
SCI1, SCI2 (serial communications interfaces)
Serial communications UARTs capable of supporting RS-232 and LIN
protocols
SPI1 (8-bit serial peripheral interfaces)
Provide 8-bit 4-pin synchronous serial interface
SPI2 (16-bit serial peripheral interfaces)
Provide 16-bit 4-pin synchronous serial interface
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
MCF51AC256 Family Configurations
1.3.1
•
•
•
•
•
•
•
•
Feature List
32-bit Version 1 ColdFire® central processor unit (CPU)
— Up to 50.33 MHz at 2.7 V – 5.5 V
— Provide 0.94 Dhrystone 2.1 DMIPS per MHz performance when running from internal RAM (0.76 DMIPS per
MHz when running from flash)
— Implements instruction set revision C (ISA_C)
On-chip memory
— Up to 256 KBytes flash memory read/program/erase over full operating voltage and temperature
— Up to 32 KBytes static random access memory (SRAM)
— Security circuitry to prevent unauthorized access to SRAM and flash contents
Power-Saving Modes
— Three low-power stop plus wait modes
— Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain
enabled to specific peripherals in stop3 mode
System protection features
— Watchdog computer operating properly (COP) reset
— Low-voltage detection with reset or interrupt
— Illegal opcode and illegal address detection with programmable reset or exception response
— Flash block protection
Debug support
— Single-wire background debug interface
— Real-time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that can be configured
into a 1- or 2-level trigger
— On-chip trace buffer provides programmable start/stop recording conditions plus support for continuous or
PC-profiling modes
— Support for real-time program (and optional partial data) trace using the debug visibility bus
V1 ColdFire interrupt controller (CF1_INTC)
— Support of 40 peripheral I/O interrupt requests plus seven software (one per level) interrupt requests
— Fixed association between interrupt request source and level plus priority, up to two requests can be remapped to
the highest maskable level + priority
— Unique vector number for each interrupt source
— Support for service routine interrupt acknowledge (software IACK) read cycles for improved system performance
Multipurpose clock generator (MCG)
— Oscillator (XOSC); loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or
1 MHz to 16 MHz
— FLL/PLL controlled by internal or external reference
— Trimmable internal reference allows 0.2% resolution and 2% deviation
Analog-to-digital converter (ADC)
— 24 analog inputs with 12 bits resolution
— Output formatted in 12-, 10- or 8-bit right-justified format
— Single or continuous conversion (automatic return to idle after single conversion)
— Operation in low-power modes for lower noise operation
— Asynchronous clock source for lower noise operation
— Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value
— On-chip temperature sensor
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51AC256 Family Configurations
•
•
•
•
•
•
Flexible timer/pulse-width modulators (FTM)
— 16-bit Free-running counter or a counter with initial and final value. The counting can be up and unsigned, up and
signed, or up-down and unsigned
— Up to 6 channels, and each channel can be configured for input capture, output compare or edge-aligned PWM
mode, all channels can be configured for center-aligned PWM mode
– Channels can operate as pairs with equal outputs, pairs with complimentary outputs or independent channels
(with independent outputs)
– Each pair of channels can be combined to generate a PWM signal (with independent control of both edges of
PWM signal)
– Deadtime insertion is available for each complementary pair
— The load of the FTM registers which have write buffer can be synchronized; write protection for critical registers
— Generation of the triggers to ADC (hardware trigger)
— A fault input for global fault control
— Backwards compatible with TPM
Timer/pulse width modulator (TPM)
— 16-bit free-running or modulo up/down count operation
— Two channels, each channel may be input capture, output compare, or edge-aligned PWM
— One interrupt per channel plus terminal count interrupt
Cyclic redundancy check (CRC) generator
— High speed hardware CRC generator circuit using 16-bit shift register
— CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial
— Error detection for all single, double, odd, and most multi-bit errors
— Programmable initial seed value
Analog comparators (ACMP)
— Full rail to rail supply operation
— Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output
— Option to compare to fixed internal bandgap reference voltage
— Option to allow comparator output to be visible on a pin, ACMPxO
Inter-integrated circuit (IIC)
— Compatible with IIC bus standard
— Multi-master operation
— Software programmable for one of 64 different serial clock frequencies
— Interrupt driven byte-by-byte data transfer
— Arbitration lost interrupt with automatic mode switching from master to slave
— Calling address identification interrupt
— Bus busy detection
— 10-bit address extension
Controller area network (CAN)
— Implementation of the CAN protocol — Version 2.0A/B
– Standard and extended data frames
– Zero to eight bytes data length
– Programmable bit rate up to 1 Mbps
– Support for remote frames
— Five receive buffers with FIFO storage scheme
— Three transmit buffers with internal prioritization using a “local priority” concept
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
MCF51AC256 Family Configurations
•
•
•
1.4
— Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, four 16-bit filters, or
eight 8-bit filters
— Programmable wakeup functionality with integrated low-pass filter
— Programmable loopback mode supports self-test operation
— Programmable listen-only mode for monitoring of CAN bus
— Programmable bus-off recovery functionality
— Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error
passive, bus-off)
— Internal timer for time-stamping of received and transmitted messages
Serial communications interfaces (SCI)
— Full-duplex, standard non-return-to-zero (NRZ) format
— Double-buffered transmitter and receiver with separate enables
— Programmable baud rates (13-bit modulo divider)
— Interrupt-driven or polled operation
— Hardware parity generation and checking
— Programmable 8-bit or 9-bit character length
— Receiver wakeup by idle-line or address-mark
— Optional 13-bit break character generation / 11-bit break character detection
— Selectable transmitter output polarity
Serial peripheral interfaces (SPI)
— Master or slave mode operation
— Full-duplex or single-wire bidirectional option
— Programmable transmit bit rate
— Double-buffered transmit and receive
— Serial clock phase and polarity options
— Slave select output
— Selectable MSB-first or LSB-first shifting
— 16-bit and FIFO operations in SPI2
Input/Output
— 69 GPIOs
— 8 keyboard interrupt pins with selectable polarity
— Hysteresis and configurable pull-up device on all input pins; Configurable slew rate and drive strength on all
output pins
— 16-bits Rapid GPIO pins connected to the processor’s local 32-bit platform bus with set, clear, and faster toggle
functionality
Part Numbers
MCF 51 AC 256 X V XX E
Status
(MCF = Fully Qualified ColdFire)
(PCF = Product Engineering)
Core
Family
Pb free indicator
Package designator
Temperature range
(V = –40°C to 105°C, C= –40°C to 85°C )
CAN Feature (A: With CAN, B/C: Without CAN)
Memory size designator
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51AC256 Family Configurations
Table 3. Orderable Part Number Summary
Freescale Part Number
Description
Flash / SRAM
(Kbytes)
Package
Temperature
MCF51AC256AVFUE
MCF51AC256 ColdFire Microcontroller with CAN
256 / 32
64 QFP
–40°C to 105°C
MCF51AC256BVFUE
MCF51AC256 ColdFire Microcontroller without CAN
256 / 32
64 QFP
–40°C to 105°C
MCF51AC256AVLKE
MCF51AC256 ColdFire Microcontroller with CAN
256 / 32
80 LQFP
–40°C to 105°C
MCF51AC256BVLKE
MCF51AC256 ColdFire Microcontroller without CAN
256 / 32
80 LQFP
–40°C to 105°C
MCF51AC256AVPUE
MCF51AC256 ColdFire Microcontroller with CAN
256 / 32
64 LQFP
–40°C to 105°C
MCF51AC256BVPUE MCF51AC256 ColdFire Microcontroller without CAN
256 / 32
64 LQFP
–40°C to 105°C
MCF51AC128AVFUE
128 / 32
64 QFP
–40°C to 105°C
MCF51AC128CVFUE MCF51AC128 ColdFire Microcontroller without CAN
128 / 16
64 QFP
–40°C to 105°C
MCF51AC128AVLKE
MCF51AC128 ColdFire Microcontroller with CAN
128 / 32
80 LQFP
–40°C to 105°C
MCF51AC128CVLKE
MCF51AC128 ColdFire Microcontroller without CAN
128 / 16
80 LQFP
–40°C to 105°C
MCF51AC128AVPUE
MCF51AC128 ColdFire Microcontroller with CAN
128 / 32
64 LQFP
–40°C to 105°C
128 / 16
64 LQFP
–40°C to 105°C
MCF51AC128 ColdFire Microcontroller with CAN
MCF51AC128CVPUE MCF51AC128 ColdFire Microcontroller without CAN
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
MCF51AC256 Family Configurations
1.5
Pinouts and Packaging
80-Pin
LQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTG3 / KBI1P3 / AD1P18
PTD3 / KBI1P6 / AD1P11
PTD2 / KBI1P5 / AD1P10 / ACMP1O
VSSAD
VDDAD
PTD1 / AD1P9 / ACMP1–
PTD0 / AD1P8 / ACMP1+
PTB7 / AD1P7
PTB6 / AD1P6
PTB5 / AD1P5
PTB4 / AD1P4
PTB3 / AD1P3
PTB2 / AD1P2
PTB1 / TPM3CH1 / AD1P1
PTB0 / TPM3CH0 / AD1P0
PTH3 / FTM2CH5 / BKPT / AD1P23
PTH2 / FTM2CH4 / PSTCLK1 / AD1P22
PTH1 / FTM2CH3 / PSTCLK0 / AD1P21
PTH0 / FTM2CH2 / AD1P20
PTA7 / AD1P17
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PTE4 / RGPIO4 / SS1
PTE5 / RGPIO5 / MISO1
PTE6 / RGPIO6 / MOSI1
PTE7 / RGPIO7 / SPSCK1
VSS
VDD
PTJ4 / DDATA0
PTJ5 / DDATA1
PTJ6 / DDATA2
PTJ7 / DDATA3
PTG0 / KBI1P0
PTG1 / KBI1P1
PTG2 / KBI1P2
•PTA0 / TxCAN
•PTA1 / RxCAN
PTA2
PTA3 / ACMP2O
PTA4 / ACMP2–
PTA5 / ACMP2+
PTA6 / AD1P16
PTC4 / SS2
IRQ / TPMCLK
RESET
PTF0 / RGPIO8 / FTM1CH2
PTF1 / RGPIO9 / FTM1CH3
PTF2 / RGPIO10 / FTM1CH4
PTF3 / RGPIO11 / FTM1CH5
PTF4 / RGPIO12 / FTM2CH0
PTC6 / FTM2FLT
PTF7 / RGPIO15
PTF5 / RGPIO13 / FTM2CH1
PTF6 / RGPIO14 / FTM1FLT
PTJ0 / PST0
PTJ1 / PST1
PTJ2 / PST2
PTJ3 / PST3
PTE0 / RGPIO0 / TxD1
PTE1 / RGPIO1 / RxD1
PTE2 / RGPIO2 / FTM1CH0
PTE3 / RGPIO3 / FTM1CH1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTC5 / RxD2
PTC3 / TxD2
PTC2 / MCLK
PTH6 / MISO2
PTH5 / MOSI2
PTH4 / SPCK2
PTC1 / SDA1
PTC0 / SCL1
VDD
VSS
PTG6 / EXTAL
PTG5 / XTAL
BKGD / MS
VREFL
VREFH
PTD7 / KBI1P7 / AD1P15
PTD6 / FTM1CLK / AD1P14
PTD5 / AD1P13
PTD4/FTM2CLK/AD1P12
PTG4 / KBI1P4 / AD1P19
Figure 2 shows the pinout of the 80-pin LQFP.
• TxCAN and RxCAN are not available in the
members that do not support CAN
Figure 2. 80-Pin LQFP
Figure 3 shows the pinout of the 64-pin LQFP and QFP.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PTC5 / RxD2
PTC3 / TxD2
PTC2 / MCLK
PTC1 / SDA1
PTC0 / SCL1
VSS
PTG6 / EXTAL
PTG5 / XTAL
BKGD / MS
VREFL
VREFH
PTD7 / KBI1P7 / AD1P15
PTD6 / FTM1CLK / AD1P14
PTD5 / AD1P13
PTD4 / FTM2CLK / AD1P12
PTG4 / KBI1P4 / AD1P19
MCF51AC256 Family Configurations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64-Pin QFP
64-Pin LQFP
PTG3 / KBI1P3 / AD1P18
PTD3 / KBI1P6 / AD1P11
PTD2 / KBI1P5 / AD1P10 /ACMP1O
VSSAD
VDDAD
PTD1 / AD1P9 / ACMP1PTD0 / AD1P8 / ACMP1+
PTB7 / AD1P7
PTB6 / AD1P6
PTB5 / AD1P5
PTB4 / AD1P4
PTB3 / AD1P3
PTB2 / AD1P2
PTB1 / TPM3CH1 / AD1P1
PTB0 / TPM3CH0 / AD1P0
PTA7 / AD1P17
PTE4 / RGPIO4 / SS1
PTE5 / RGPIO5 / MISO1
PTE6 / RGPIO6 / MOSI1
PTE7 / RGPIO7 / SPSCK1
VSS
VDD
PTG0 / KBI1P0
PTG1 / KBI1P1
PTG2 / KBI1P2
•PTA0 / TxCAN
•PTA1 / RxCAN
PTA2
PTA3 / ACMP2O
PTA4 / ACMP2PTA5 / ACMP2+
PTA6 / AD1P16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PTC4
IRQ / TPMCLK
RESET
PTF0 / RGPIO8 / FTM1CH2
PTF1 / RGPIO9 / FTM1CH3
PTF2 / RGPIO10 / FTM1CH4
PTF3 / RGPIO11 / FTM1CH5
PTF4 / RGPIO12 / FTM2CH0
PTC6 / FTM2FLT
PTF7 / RGPIO15
PTF5 / RGPIO13 / FTM2CH1
PTF6 / RGPIO14 / FTM1FLT
PTE0 / RGPIO0 / TxD1
PTE1 / RGPIO1 / RxD1
PTE2 / RGPIO2 / FTM1CH0
PTE3 / RGPIO3 / FTM1CH1
• TxCAN and RxCAN are not available in the
members that do not support CAN
Figure 3. 64-Pin QFP and LQFP
Table 4 shows the package pin assignments.
Table 4. Pin Availability by Package Pin-Count
Pin
Number
Lowest <--
Priority
--> Highest
80
64
Port Pin
Alt 1
Alt 2
1
1
PTC4
SS2
2
2
IRQ
TPMCLK1
3
3
RESET
4
4
PTF0
RGPIO8
FTM1CH2
5
5
PTF1
RGPIO9
FTM1CH3
6
6
PTF2
RGPIO10
FTM1CH4
7
7
PTF3
RGPIO11
FTM1CH5
8
8
PTF4
RGPIO12
FTM2CH0
Alt 3
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
11
MCF51AC256 Family Configurations
Table 4. Pin Availability by Package Pin-Count (continued)
Pin
Number
Lowest <--
Priority
80
64
Port Pin
Alt 1
9
9
PTC6
FTM2FLT
--> Highest
Alt 2
10
10
PTF7
RGPIO15
11
11
PTF5
RGPIO13
FTM2CH1
12
12
PTF6
RGPIO14
FTM1FLT
13
—
PTJ0
PST0
14
—
PTJ1
PST1
15
—
PTJ2
PST2
16
—
PTJ3
PST3
17
13
PTE0
RGPIO0
18
14
PTE1
RGPIO1
RxD1
19
15
PTE2
RGPIO2
FTM1CH0
20
16
PTE3
RGPIO3
FTM1CH1
21
17
PTE4
RGPIO4
SS1
22
18
PTE5
RGPIO5
MISO1
23
19
PTE6
RGPIO6
MOSI1
24
20
PTE7
RGPIO7
SPSCK1
25
21
VSS
26
22
VDD
27
—
PTJ4
DDATA0
28
—
PTJ5
DDATA1
29
—
PTJ6
DDATA2
30
—
PTJ7
DDATA3
31
23
PTG0
KBI1P0
32
24
PTG1
KBI1P1
33
25
PTG2
KBI1P2
34
26
PTA0
TxCAN2
35
27
PTA1
RxCAN3
36
28
PTA2
37
29
PTA3
38
30
PTA4
ACMP2-
39
31
PTA5
ACMP2+
40
32
PTA6
AD1P16
41
33
PTA7
AD1P17
Alt 3
TxD1
ACMP2O
42
—
PTH0
FTM2CH2
AD1P20
43
—
PTH1
FTM2CH3
PSTCLK0
44
—
PTH2
FTM2CH4
PSTCLK1
AD1P22
45
—
PTH3
FTM2CH5
BKPT
AD1P23
46
34
PTB0
TPM3CH0
AD1P0
47
35
PTB1
TPM3CH1
AD1P1
48
36
PTB2
AD1P2
AD1P21
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51AC256 Family Configurations
Table 4. Pin Availability by Package Pin-Count (continued)
Pin
Number
Lowest <--
Priority
--> Highest
80
64
Port Pin
Alt 1
Alt 2
49
37
PTB3
AD1P3
50
38
PTB4
AD1P4
51
39
PTB5
AD1P5
52
40
PTB6
AD1P6
53
41
PTB7
AD1P7
54
42
PTD0
AD1P8
ACMP1+
55
43
PTD1
AD1P9
ACMP1–
56
44
VDDAD
57
45
VSSAD
58
46
PTD2
KBI1P5
AD1P10
59
47
PTD3
KBI1P6
AD1P11
60
48
PTG3
KBI1P3
AD1P18
61
49
PTG4
KBI1P4
AD1P19
62
50
PTD4
FTM2CLK
AD1P12
63
51
PTD5
AD1P13
64
52
PTD6
FTM1CLK
AD1P14
65
53
PTD7
KBI1P7
AD1P15
66
54
VREFH
67
55
VREFL
68
56
BKGD
MS
69
57
PTG5
XTAL
70
58
PTG6
EXTAL
71
59
VSS
72
—
VDD
73
60
PTC0
74
61
PTC1
SDA1
75
—
PTH4
SPCK2
76
—
PTH5
MOSI2
77
—
PTH6
MISO2
78
62
PTC2
MCLK
79
63
PTC3
TxD2
80
64
PTC5
RxD2
Alt 3
ACMP1O
SCL1
1
TPMCLK, FTM1CLK, and FTM2CLK options are configured
via software; out of reset, FTM1CLK, FTM2CLK, and
TPMCLK are available to FTM1, FTM2, and TPM3
respectively.
2
TxCAN is available in the member that supports CAN.
3 RxCAN is available in the member that supports CAN.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Preliminary Electrical Characteristics
2
Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the MCF51AC256 microcontroller,
including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for
production silicon. Finalized specifications will be published after complete characterization and device qualifications have
been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
2.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 5. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
2.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 6 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD).
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
14
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 6. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to 5.8
V
Input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
±25
mA
IDD
120
mA
Tstg
–55 to 150
°C
Maximum current into VDD
Storage temperature
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
2.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than
being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between
actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 7. Thermal Characteristics
Rating
Operating temperature range (packaged)
Maximum junction temperature
Symbol
Value
TA
–40 to 105
TJ
150
Unit
°C
°C
Thermal resistance 1,2,3,4
80-pin LQFP
1s
2s2p
TBD
TBD
θJA
64-pin LQFP
°C/W
1s
2s2p
TBD
TBD
1s
2s2p
TBD
TBD
64-pin QFP
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Preliminary Electrical Characteristics
2
Junction to Ambient Natural Convection
1s — Single layer board, one signal layer
4
2s2p — Four layer board, 2 signal and 2 power layers
3
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
2.4
Electrostatic Discharge (ESD) Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling
precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices
can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits.
(http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification
requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification.
Table 8. ESD and Latch-up Test Conditions
Model
Human Body
Machine
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ω
Storage Capacitance
C
100
pF
Number of Pulse per pin
—
3
Series Resistance
R1
0
Ω
Storage Capacitance
C
200
pF
Number of Pulse per pin
—
3
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 8. ESD and Latch-up Test Conditions (continued)
Model
Latch-up
Description
Symbol
Value
Unit
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
Table 9. ESD and Latch-Up Protection Characteristics
Num
2.5
Rating
Symbol
Min
Max
Unit
1
Human Body Model (HBM)
VHBM
±2000
—
V
2
Machine Model (MM)
VMM
±200
—
V
3
Charge Device Model (CDM)
VCDM
±500
—
V
4
Latch-up Current at TA = 85°C
ILAT
±100
—
mA
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
Table 10. DC Characteristics
Num C
1
Parameter
— Operating voltage
Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = –4 mA
3 V, ILoad = –2 mA
5 V, ILoad = –2 mA
3 V, ILoad = –1 mA
2
Symbol
Output high voltage — High Drive (PTxDSn = 1)
5 V, ILoad = –15 mA
P
3 V, ILoad = –8 mA
5 V, ILoad = –8 mA
3 V, ILoad = –4 mA
Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 4 mA
3 V, ILoad = 2 mA
5 V, ILoad = 2 mA
3 V, ILoad = 1 mA
3
Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 15 mA
P
3 V, ILoad = 8 mA
5 V, ILoad = 8 mA
3 V, ILoad = 4 mA
4
P
Output high current — Max total IOH for all ports
5V
3V
VOH
Min
Typical1
Max
Unit
2.7
—
5.5
V
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8
—
—
—
—
1.5
1.5
0.8
0.8
—
—
100
60
VOL
IOHT
—
—
V
V
mA
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Preliminary Electrical Characteristics
Table 10. DC Characteristics (continued)
Parameter
Symbol
Min
Typical1
Max
Unit
Output low current — Max total IOL for all ports
5V
3V
IOLT
—
—
—
—
100
60
mA
Num C
5
P
6
P Input high voltage; all digital inputs
VIH
0.65 x VDD
—
—
7
P Input low voltage; all digital inputs
VIL
—
—
0.35 x VDD
8
P Input hysteresis; all digital inputs
Vhys
0.06 x VDD
2
9
P Input leakage current; input only pins
10
P High Impedance (off-state) leakage current2
11
3
P Internal pullup resistors
4
V
mV
|IIn|
—
0.1
1
μA
|IOZ|
—
0.1
1
μA
RPU
20
45
65
kΩ
RPD
20
45
65
kΩ
12
P Internal pulldown resistors
13
C Input Capacitance; all non-supply pins
CIn
—
—
8
pF
14
P POR rearm voltage
VPOR
0.9
1.4
2.0
V
15
D POR rearm time
tPOR
10
—
—
μs
3.9
4.0
4.0
4.1
4.1
4.2
2.48
2.54
2.56
2.62
2.64
2.70
4.5
4.6
4.6
4.7
4.7
4.8
4.2
4.3
4.3
4.4
4.4
4.5
2.84
2.90
2.92
2.98
3.00
3.06
2.66
2.72
2.74
2.80
2.82
2.88
Vhys
—
—
100
60
—
—
mV
VRAM
—
0.6
1.0
V
16
17
18
19
20
P
P
P
P
P
Low-voltage detection threshold —
high range
VDD falling
VDD rising
Low-voltage detection threshold —
low range
VDD falling
VDD rising
Low-voltage warning threshold —
high range 1
VDD falling
VDD rising
Low-voltage warning threshold —
high range 0
VDD falling
VDD rising
Low-voltage warning threshold
low range 1
VDD falling
VDD rising
Low-voltage warning threshold —
low range 0
21
P
22
T
23
D RAM retention voltage
VDD falling
VDD rising
VLVD1
VLVD0
VLVW3
VLVW2
VLVW1
VLVW0
V
V
V
V
V
V
Low-voltage inhibit reset/recover hysteresis
5V
3V
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 10. DC Characteristics (continued)
Num C
Parameter
DC injection
24
1
2
3
4
5
6
7
8
current5 6 7 8
Symbol
(single pin limit)
VIN >VDD
VIN <VSS
D DC injection current (Total MCU limit, includes
sum of all stressed pins)
VIN >VDD
VIN <VSS
Min
Typical1
Max
Unit
0
0
—
—
2
–0.2
mA
0
0
—
—
25
–5
IIC
mA
Typical values are based on characterization data at 25°C unless otherwise stated.
Measured with VIn = VDD or VSS.
Measured with VIn = VSS.
Measured with VIn = VDD.
Power supply must maintain regulation within operating VDD range during instantaneous and operating
maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may
flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will
shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not
consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce
overall power consumption).
All functional non-supply pins are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting
resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two
values.
The RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19
Preliminary Electrical Characteristics
–6.0E-3
VDD–VOH (V)
Average of IOH
-40°C
25°C
–4.0E-3
105°C
IOH (A)
–5.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
0
0.3
0.5
0.8
VSupply–VOH
0.9
1.2
1.5
Figure 4. Typical IOH vs. VDD–VOH at VDD = 3V (Low Drive, PTxDSn = 0)
–20.0E-3
VDD–VOH (V)
Average of IOH
–18.0E-3
–16.0E-3
–14.0E-3
–12.0E-3
–10.0E-3
–8.0E-3
–6.0E-3
–4.0E-3
–2.0E-3
000E+0
-40°C
25°C
IOH (A)
105°C
0
0.3
0.5
0.8
VSupply–VOH
0.9
1.2
1.5
Figure 5. Typical IOH vs. VDD–VOH at VDD = 3V (High Drive, PTxDSn = 1)
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
VDD–VOH (V)
Average of IOH
–7.0E-3
–6.0E-3
-40°C
25°C
–5.0E-3
105°C
IOH (A)
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
0.00
0.30
0.50
0.80
1.00
1.30
2.00
VSupply–VOH
Figure 6. Typical IOH vs. VDD–VOH at VDD = 5V (Low Drive, PTxDSn = 0)
–30.0E-3
VDD–VOH (V)
Average of IOH
-40°C
25°C
–20.0E-3
105°C
IOH (A)
–25.0E-3
–15.0E-3
–10.0E-3
–5.0E-3
000E+0
0.00
0.30
0.50
0.80
1.00
1.30
2.00
VSupply–VOH
Figure 7. Typical IOH vs. VDD–VOH at VDD = 5 V (High Drive, PTxDSn = 1)
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
21
Preliminary Electrical Characteristics
2.6
Supply Current Characteristics
Table 11. Supply Current Characteristics
Num
C
Parameter
Symbol
1
C
Run supply current3 measured at
clock = 2 MHz, fBus = 1MHz)
(CPU
2
C
Run supply current3 measured at
clock = 16 MHz, fBus = 8 MHz)
(CPU
3
C
Run supply current3 measured at
clock = 50 MHz, fBus = 25 MHz)
(CPU
RIDD
RIDD
RIDD
VDD (V)
Typical1
Max2
5
2.67
TBD
3
2.64
TBD
5
14.8
TBD
3
14.7
TBD
5
42
TBD
3
41.8
TBD
Unit
mA
mA
mA
Stop2 mode supply current
–40 °C
25 °C
105 °C
4
C
TBD
TBD
TBD
μA
5
0.80
3
0.80
TBD
TBD
TBD
0.90
TBD
TBD
TBD
3
0.90
TBD
TBD
TBD
5
300
nA
3
300
nA
5
110
μA
3
90
μA
5, 3
5
μA
S2IDD
–40 °C
25 °C
105 °C
μA
Stop3 mode supply current
–40 °C
25 °C
105 °C
5
C
5
S3IDD
–40 °C
25 °C
105 °C
6
C
RTI adder to stop2 or stop34, 25°C
S23IDDRTI
7
C
LVD adder to stop3 (LVDE = LVDSE = 1)
S3IDDLVD
8
C
μA
enabled5
Adder to stop3 for oscillator
(ERCLKEN =1 and EREFSTEN = 1)
S3IDDOSC
μA
1
Typicals are measured at 25°C.
Values given here are preliminary estimates prior to completing characterization.
3 All modules clocks switch on, code run from flash, FEI mode, and does not include any dc loads on port pins.
4 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode.
5 Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0).
2
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
2.7
Analog Comparator (ACMP) Electricals
Table 12. Analog Comparator Electrical Specifications
Num
C
Symbol
Min
Typical
Max
Unit
1
—
Supply voltage
VDD
2.7
—
5.5
V
2
T
Supply current (active)
IDDAC
—
20
35
μA
3
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
4
D
Analog input offset voltage
VAIO
20
40
mV
5
D
Analog Comparator hysteresis
6
D
7
8
2.8
Rating
VH
3.0
6.0
20.0
mV
Analog input leakage current
IALKG
—
—
1.0
μA
D
Analog Comparator initialization delay
tAINIT
—
—
1.0
μs
D
Bandgap Voltage Reference
Factory trimmed at VDD = 3.0 V, Temp = 25°C
VBG
1.19
1.20
1.21
V
ADC Characteristics
Table 13. 5 Volt 12-bit ADC Operating Conditions
Symb
Min
Typical1
Max
Unit
VDDAD
2.7
—
5.5
V
Delta to VDD (VDD-VDDAD)2
ΔVDDAD
–100
0
100
mV
)2
ΔVSSAD
–100
0
100
mV
Ref Voltage
High
VREFH
2.7
VDDAD
VDDAD
V
Ref Voltage
Low
VREFL
VSSAD
VSSAD
VSSAD
V
Input Voltage
VADIN
VREFL
—
VREFH
V
Input
Capacitance
CADIN
—
4.5
5.5
pF
Input
Resistance
RADIN
—
3
5
kΩ
—
—
—
—
2
5
Characteristic
Conditions
Absolute
Supply voltage
Ground voltage
Delta to VSS (VSS-VSSAD
12 bit mode
fADCK > 4MHz
fADCK < 4MHz
Analog Source
Resistance
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
8 bit mode (all valid fADCK)
ADC
Conversion
Clock Freq.
High Speed (ADLPC=0)
Low Power (ADLPC=1)
kΩ
RAS
fADCK
—
—
—
—
5
10
—
—
10
0.4
—
8.0
0.4
—
4.0
Comment
External to
MCU
MHz
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Preliminary Electrical Characteristics
1
Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
DC potential difference.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
+
VADIN
VAS
+
–
CAS
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 8. ADC Input Impedance Equivalency Diagram
Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C
Symb
Min
Typical1
Max
Unit
Supply
CurrentADLPC
=1ADLSMP=1
ADCO=1
T
IDDAD
—
133
—
μA
Supply
CurrentADLPC
=1ADLSMP=0
ADCO=1
T
IDDAD
—
218
—
μA
Supply
CurrentADLPC
=0ADLSMP=1
ADCO=1
T
IDDAD
—
327
—
μA
Supply
CurrentADLPC
=0ADLSMP=0
ADCO=1
P
IDDAD
—
0.582
1
mA
IDDAD
—
0.011
1
μA
Characteristic
Supply Current
Conditions
Stop, Reset, Module Off
Comment
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic
Conditions
ADC
Asynchronous
Clock Source
High Speed (ADLPC=0)
Conversion
Time (Including
sample time)
Short Sample (ADLSMP=0)
C
Symb
T
fADACK
Low Power (ADLPC=1)
T
Long Sample (ADLSMP=1)
tADC
Short Sample (ADLSMP=0)
Sample Time
T
Long Sample (ADLSMP=1)
Total
Unadjusted
Error
Differential
Non-Linearity
Integral
Non-Linearity
Zero-Scale
Error
Full-Scale
Error
tADS
Input Leakage
Error
Temp Sensor
Slope
Max
2
3.3
5
1.25
2
3.3
—
20
—
—
40
—
—
3.5
—
—
23.5
—
—
±3.0
—
—
±1
±2.5
T
10 bit mode
P
8 bit mode
T
—
±0.5
±1.0
12 bit mode
T
—
±1.75
—
10 bit mode3
P
—
±0.5
±1.0
8 bit mode4
T
—
±0.3
±0.5
12 bit mode
T
—
±1.5
—
10 bit mode
T
—
±0.5
±1.0
8 bit mode
T
—
±0.3
±0.5
12 bit mode
T
—
±1.5
—
10 bit mode
P
—
±0.5
±1.5
8 bit mode
T
—
±0.5
±0.5
12 bit mode
T
—
±1
—
10 bit mode
T
—
±0.5
±1
8 bit mode
T
—
±0.5
±0.5
—
–1 to 0
—
—
—
±0.5
8 bit mode
—
—
±0.5
12 bit mode
—
±1
—
—
±0.2
±2.5
—
±0.1
±1
—
1.396
—
—
3.266
—
—
3.638
—
ETUE
DNL
INL
EZS
EFS
D
10 bit mode
D
10 bit mode
EQ
EIL
8 bit mode
Temp Sensor
Voltage
Typical1
12 bit mode
12 bit mode
Quantization
Error
Min
25°C
D
VTEMP25
D
m
–40 °C — 25 °C
25 °C — 85 °C
Unit
Comment
MHz
tADACK =
1/fADACK
ADCK
cycles
ADCK
cycles
LSB2
See Table 8
for conversion
time variances
Includes
quantization
LSB2
LSB2
LSB2
VADIN = VSSAD
LSB2
VADIN = VDDAD
LSB2
LSB2
Pad leakage4 *
RAS
V
mV/°C
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
Preliminary Electrical Characteristics
1
Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
1 LSB = (VREFH - VREFL)/2N
3
Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
4
Based on input pad leakage current. Refer to pad electricals.
2.9
External Oscillator (XOSC) Characteristics
Table 15. Oscillator Electrical Specifications (Temperature Range = –40 to 105°C Ambient)
C
Rating
Symbol
Min
Typical1
Max
Unit
1
C
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1) FEE or FBE mode 2
High range (RANGE = 1) PEE or PBE mode 3
High range (RANGE = 1, HGO = 1) BLPE mode
High range (RANGE = 1, HGO = 0) BLPE mode
flo
fhi-fll
fhi-pll
fhi-hgo
fhi-lp
32
1
1
1
1
—
—
—
—
—
38.4
5
16
16
8
kHz
MHz
MHz
MHz
MHz
2
— Load capacitors
3
—
Num
See crystal or resonator
manufacturer’s recommendation.
C1
C2
Feedback resistor
Low range (32 kHz to 38.4 kHz)
High range (1 MHz to 16 MHz)
RF
10
1
MW
Series resistor
4
5
6
—
T
T
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
Crystal start-up time 4
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)5
High range, high gain (RANGE = 1, HGO = 1)5
Square wave input clock frequency (EREFS = 0, ERCLKEN =
1)
FEE or FBE mode 2
PEE or PBE mode 3
BLPE mode
RS
t
t
t
CSTL-LP
CSTL-HGO
t
CSTH-LP
CSTH-HGO
fextal
—
—
—
0
100
0
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
200
400
5
15
—
—
—
—
0.03125
1
0
—
—
—
5
16
40
kΩ
ms
MHz
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25
kHz to 39.0625 kHz.
3 When MCG is configured for PEE or PBE mode, input clock source must be divisible using RDIV to within the range of 1 MHz
to 2MHz.
4
This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to
achieve specifications.
5 4 MHz crystal
2
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
26
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
MCU
EXTAL
XTAL
RS
RF
C1
2.10
Crystal or Resonator
C2
MCG Specifications
Table 16. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient)
Num C
Rating
Symbol
Min
Typical
Max
Unit
1
Internal reference frequency - factory
P trimmed at VDD = 5 V and temperature
= 25 °C
fint_ft
—
31.25
—
kHz
2
P
Average internal reference frequency –
untrimmed 1
fint_ut
25
32.7
41.66
kHz
3
P
Average internal reference frequency –
user trimmed
fint_t
31.25
—
39.0625
kHz
4
D Internal reference startup time
tirefst
—
60
100
μs
5
DCO output frequency range untrimmed 1
—
value provided for reference: fdco_ut =
1024 X fint_ut
fdco_ut
25.6
33.48
42.66
MHz
6
D DCO output frequency range - trimmed
fdco_t
32
—
40
MHz
7
Resolution of trimmed DCO output
D frequency at fixed voltage and
temperature (using FTRIM)
Δfdco_res_t
—
±0.1
±0.2
%fdco
8
Resolution of trimmed DCO output
D frequency at fixed voltage and
temperature (not using FTRIM)
Δfdco_res_t
—
±0.2
±0.4
%fdco
9
Total deviation of trimmed DCO output
D frequency over voltage and
temperature
Δfdco_t
—
0.5
–1.0
±2
%fdco
10
Total deviation of trimmed DCO output
D frequency over fixed voltage and
temperature range of 0 – 70 °C
Δfdco_t
—
±0.5
±1
%fdco
11
D FLL acquisition time 2
tfll_acquire
—
—
1
ms
12
D PLL acquisition time
3
tpll_acquire
—
—
1
ms
13
Long term Jitter of DCO output clock
D
(averaged over 2ms interval) 4
CJitter
—
0.02
0.2
%fdco
14
D VCO operating frequency
fvco
7.0
—
55.0
MHz
17
D
fpll_jitter_625ns
—
0.5665
—
%fpll
18
D Lock entry frequency tolerance 6
Dlock
±1.49
—
±2.98
%
Jitter of PLL output clock measured
over 625 ns5
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Table 16. MCG Frequency Specifications (continued)(Temperature Range = –40 to 125°C Ambient)
Num C
19
1
2
3
4
5
6
7
Rating
D Lock exit frequency tolerance
7
Symbol
Min
Typical
Max
Unit
Dunl
±4.47
—
±5.97
%
tfll_acquire+
1075(1/fint_t)
s
20
D Lock time — FLL
tfll_lock
—
—
21
D Lock time — PLL
tpll_lock
—
—
22
Loss of external clock minimum
D frequency – RANGE = 0
floc_low
(3/5) x fint
—
tpll_acquire+
1075(1/fpll_ref)
—
s
kHz
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it
is already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus
speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and
the sample point of a bit using 8 time quanta per bit.
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG
is already in lock, then the MCG may stay in lock.
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
o
2.11
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
Preliminary Electrical Characteristics
2.11.1
Control Timing
Table 17. Control Timing
Num
C
1
D
2
D
Symbol
Min
Typical1
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
dc
—
24
MHz
Internal low-power oscillator period
tLPO
800
1500
μs
Parameter
2
3
D
External reset pulse width
(tcyc = 1/fSelf_reset)
textrst
100
—
ns
4
D
Reset low drive
trstdrv
66 x tcyc
—
ns
5
D
Active background debug mode latch setup time
tMSSU
500
—
ns
6
D
Active background debug mode latch hold time
tMSH
100
—
ns
7
D
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
8
D
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
D
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
Slew rate control disabled (PTxSE = 0), Low Drive
Slew rate control enabled (PTxSE = 1), Low Drive
tRise, tFall
—
—
11
35
40
75
IRQ pulse width
KBIPx pulse width
9
ns
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 105 °C.
1
2
textrst
RESET PIN
Figure 9. Reset Timing
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
29
Preliminary Electrical Characteristics
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 10. IRQ/KBIPx Timing
2.11.2
Timer (TPM/FTM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 18. TPM/FTM Input Timing
NUM
C
1
—
2
Function
Symbol
Min
Max
Unit
External clock frequency
fTPMext
DC
fBus/4
MHz
—
External clock period
tTPMext
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTPMext
tclkh
TPMxCLK
tclkl
Figure 11. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 12. Timer Input Capture Pulse
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
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Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
2.11.3
MSCAN
Table 19. MSCAN Wake-up Pulse Characteristics
1
Num
C
Parameter
Symbol
1
D
MSCAN Wake-up dominant pulse filtered
tWUP
2
D
MSCAN Wake-up dominant pulse pass
tWUP
Min
Typical1
5
Max
Unit
2
μs
5
μs
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
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Preliminary—Subject to Change Without Notice
31
Preliminary Electrical Characteristics
2.12
SPI Characteristics
Table 20 and Figure 13 through Figure 16 describe the timing requirements for the SPI system.
Table 20. SPI Electrical Characteristic
Num1
C
1
D
2
D
Characteristic2
Symbol
Min
Max
Unit
Master
Slave
fop
fop
fBus/2048
dc
fBus/2
fBus/4
Hz
Master
Slave
tSCK
tSCK
2
4
2048
Master
Slave
tLead
tLead
—
1/2
1/2
—
tSCK
Master
Slave
tLag
tLag
—
1/2
1/2
—
tSCK
Operating frequency
Cycle time
—
tcyc
Enable lead time
3
D
4
D
5
D
Clock (SPSCK) high time Master and
Slave
tSCKH
1/2 tSCK – 25
—
ns
6
D
Clock (SPSCK) low time Master and
Slave
tSCKL
1/2 tSCK – 25
—
ns
7
D
Master
Slave
tSI(M)
tSI(S)
30
30
—
—
ns
8
D
Master
Slave
tHI(M)
tHI(S)
30
30
—
—
ns
9
D
Access time, slave3
tA
0
40
ns
10
D
slave4
tdis
—
40
ns
11
D
Master
Slave
tSO
tSO
25
25
—
—
ns
12
D
Master
Slave
tHO
tHO
–10
–10
—
—
ns
Enable lag time
Data setup time (inputs)
Data hold time (inputs)
Disable time,
Data setup time (outputs)
Data hold time (outputs)
1
Refer to Figure 13 through Figure 16.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
3 Time to data active from high-impedance state.
4 Hold time to high-impedance state.
2
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
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Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
SS1
(OUTPUT)
3
2
2
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
11
MOSI
(OUTPUT)
LSB IN
12
11
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
2
3
2
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN(2)
LSB IN
12
11
MOSI
(OUTPUT)
BIT 6 . . . 1
MSB OUT(2)
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI Master Timing (CPHA = 1)
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33
Preliminary Electrical Characteristics
SS
(INPUT)
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
2
SCK
(CPOL = 1)
(INPUT)
5
4
8
MISO
(OUTPUT)
12
11
BIT 6 . . . 1
MSB OUT
SLAVE
SEE
NOTE
SLAVE LSB OUT
7
6
MOSI
(INPUT)
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 15. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
3
2
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
(INPUT)
5
4
11
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
SLAVE
12
MSB OUT
6
BIT 6 . . . 1
9
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 16. SPI Slave Timing (CPHA = 1)
2.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see Chapter 4, “Memory.”
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
34
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 21. Flash Characteristics
Num
C
1
—
2
Characteristic
Symbol
Min
Supply voltage for program/erase
Vprog/erase
—
Supply voltage for read operation
3
—
4
5
Typical1
Max
Unit
2.7
5.5
V
VRead
2.7
5.5
V
Internal FCLK frequency2
fFCLK
150
200
kHz
—
Internal FCLK period (1/FCLK)
tFcyc
5
6.67
μs
—
Byte program time (random location)2
2
tprog
9
tFcyc
tBurst
4
tFcyc
6
—
Byte program time (burst mode)
7
—
Page erase time3
tPage
4000
tFcyc
8
—
Mass erase time2
tMass
20,000
tFcyc
9
C
Program/erase endurance4
TL to TH = –40°C to 105°C
T = 25°C
10
C
Data retention5
tD_ret
10,000
—
—
100,000
—
—
cycles
15
100
—
years
1
Typical values are based on characterization data at VDD = 5.0 V, 25°C unless otherwise stated.
The frequency of this clock is controlled by a software setting.
3 These values are hardware state machine controlled. User code does not need to count cycles. This information
supplied for calculating approximate time to program and erase.
4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on
how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical
Endurance for Nonvolatile Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines
typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2
2.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
2.14.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
35
Mechanical Outline Drawings
3
Mechanical Outline Drawings
3.1
80-pin LQFP Package
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
36
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
37
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
38
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanical Outline Drawings
3.2
64-pin LQFP Package
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
39
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
40
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
41
Mechanical Outline Drawings
3.3
64-pin QFP Package
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
42
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
43
Mechanical Outline Drawings
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
44
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Revision History
4
Revision History
Table 22. Revision History
Revision
1
Description
Initial published
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
45
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Document Number: MCF51AC256
Rev.1
06/2008
Preliminary—Subject to Change Without Notice
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