DS91M125 www.ti.com SNLS290C – AUGUST 2008 – REVISED APRIL 2013 DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input Check for Samples: DS91M125 FEATURES DESCRIPTION • The DS91M125 is a 1:4 M-LVDS repeater designed for driving and distributing clock or data signals to up to four multipoint networks. 1 2 • • • • • • • • DC - 125 MHz / 250 Mbps Low Jitter, Low Skew, Low Power Operation Independent Driver Enable Pins Outputs Conform to TIA/EIA-899 M-LVDS Standard Controlled Transition Times Minimize Reflections Inputs Conform to TIA/EIA-644-A LVDS Standard 8 kV ESD on M-LVDS Output Pins Protects Adjoining Components Flow-Through Pinout Simplifies PCB Layout Industrial Operating Temperature Range (−40°C to +85°C) Available in a Space Saving SOIC-16 Package APPLICATIONS • • • Multidrop / Multipoint Clock and Data Distribution High-Speed, Low Power, Short-Reach Alternative to TIA/EIA-485/422 Clock Distribution in AdvancedTCA (ATCA) and MicroTCA (μTCA, uTCA) Backplanes M-LVDS (Multipoint LVDS) is a new family of bus interface devices based on LVDS technology specifically designed for multipoint and multidrop cable and backplane applications. It differs from standard LVDS in providing increased drive current to handle double terminations that are required in multipoint applications. Controlled transition times minimize reflections that are common in multipoint configurations due to unterminated stubs. A single DS91M125 channel is a 1:4 repeater that accepts M-LVDS/LVDS/CML/LVPECL signals and converts them to M-LVDS signal levels. Each output has an associated independent driver enable pin. The DS91M125 input conforms to the LVDS standard. The DS91M125 has a flow-through pinout for easy PCB layout. It provides a new alternative for high speed multipoint interface applications. It is packaged in a space saving SOIC-16 package. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated DS91M125 SNLS290C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com Typical Application Line Card in SLOT 1 Line Card in SLOT N-1 Line Card in SLOT N M-LVDS Receivers M-LVDS Receivers DS91M125 RT Z0 RT RT Z0 RT RT Z0 RT RT Z0 RT RT = ZLOADED BACKPLANE Connection Diagram DE0 1 16 B0 DE1 2 15 A0 DE2 3 14 A1 VDD 4 13 B1 GND 5 12 B2 DI+ 6 11 A2 DI- 7 10 A3 DE3 8 9 B3 Figure 1. 16-Lead (0.150″ Wide) Molded Small Outline Package, JEDEC See Package Number D 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 DS91M125 www.ti.com SNLS290C – AUGUST 2008 – REVISED APRIL 2013 Logic Diagram DE0 B0 A0 DE1 B1 A1 DI+ DI- B2 A2 DE2 B3 A3 DE3 PIN DESCRIPTIONS Number Name I/O, Type 1, 2, 3, 8 DE I, LVCMOS Description 6 DI+ I, LVDS Non-inverting receiver input pin. 7 DI- I, LVDS Inverting receiver input pin. 5 GND Power 10, 11, 14, 15 A O, M-LVDS Non-inverting driver output pin. 9, 12, 13, 16 B O, M-LVDS Inverting driver output pin. 4 VDD Power Driver enable pins: When DE is low, the driver is disabled. When DE is high, the driver is enabled. There is a 300 kΩ pulldown resistor on each pin. Ground pin. Power supply pin, +3.3V ± 0.3V Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 3 DS91M125 SNLS290C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) −0.3V to +4V Supply Voltage −0.3V to (VDD + 0.3V) LVCMOS Input Voltages −1.9V to +5.5V M-LVDS Output Voltages −0.3V to (VDD + 0.3V) LVDS Input Voltages Maximum Package Power Dissipation at +25°C SOIC Package 2.21W Derate SOIC Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC) 19.2 mW/°C above +25°C θJA 52°C/W θJC 19°C/W Maximum Junction Temperature 140°C −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering, 4 seconds) ESD Susceptibility 260°C HBM (3) ≥ 8 kV MM (4) ≥ 250V CDM (1) (2) (3) (4) (5) (5) ≥ 1250V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. JESD22-A114C Machine Model, applicable std. JESD22-A115-A Field Induced Charge Device Model, applicable std. JESD22-C101-C RECOMMENDED OPERATING CONDITIONS Min Typ Max Units Supply Voltage, VDD 3.0 3.3 3.6 V Voltage at M-LVDS Outputs −1.4 +3.8 V Voltage at LVDS Inputs 0 VDD V LVCMOS Input Voltage High VIH 2.0 VDD V LVCMOS Input Voltage Low VIL 0 0.8 V +85 °C Operating Free Air Temperature TA 4 −40 Submit Documentation Feedback +25 Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 DS91M125 www.ti.com SNLS290C – AUGUST 2008 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) (4) Symbol Parameter Conditions Min Typ Max Units V LVCMOS DC Specifications VIH High-Level Input Voltage 2.0 VDD VIL Low-Level Input Voltage GND 0.8 V IIH High-Level Input Current VIH = 3.6V IIL Low-Level Input Current VCL Input Clamp Voltage -15 ±1 15 μA VIL = 0V -15 ±1 15 μA IIN = -18 mA -1.5 480 V M-LVDS Driver DC Specifications |VAB| Differential output voltage magnitude RL = 50Ω, CL = 5pF ΔVAB Change in differential output voltage magnitude between logic states See Figure 2and Figure 4 VOS(SS) Steady-state common-mode output voltage RL = 50Ω, CL = 5pF |ΔVOS(SS)| Change in steady-state common-mode output voltage between logic states See Figure 2 and Figure 3 VA(OC) Maximum steady-state open-circuit output voltage See Figure 5 VB(OC) Maximum steady-state open-circuit output voltage VP(H) Voltage overshoot, low-to-high level output mV −50 0 +50 mV 0.3 1.6 2.1 V 0 +50 mV 0 2.4 V 0 2.4 V 1.2VSS V RL = 50Ω, CL = 5pF,CD = 0.5pF See Figure 7 and Figure 8 (5) VP(L) 650 −0.2V Voltage overshoot, high-to-low level output V SS (6) IOS Differential short-circuit output current See Figure 6 IA Driver output current VA = 3.8V, VB = 1.2V IB Driver output current -43 43 mA 32 µA VA = 0V or 2.4V, VB = 1.2V −20 +20 µA VA = −1.4V, VB = 1.2V −32 VB = 3.8V, VA = 1.2V VB = 0V or 2.4V, VA = 1.2V −20 VB = −1.4V, VA = 1.2V −32 −4 IAB Driver output differential current (IA − IB) VA = VB, −1.4V ≤ V ≤ 3.8V IA(OFF) Driver output power-off current VA = 3.8V, VB = 1.2V, DE = 0V 0V ≤ VDD ≤ 1.5V (1) (2) (3) (4) (5) (6) VA = 0V or 2.4V, VB = 1.2V, DE = 0V 0V ≤ VDD ≤ 1.5V −20 VA = −1.4V, VB = 1.2V, DE = 0V 0V ≤ VDD ≤ 1.5V −32 µA 32 µA +20 µA µA +4 µA 32 µA +20 µA µA The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. CL includes fixture capacitance and CD includes probe capacitance. Specification is ensured by characterization and is not tested in production. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 5 DS91M125 SNLS290C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)(4) Symbol IB(OFF) Parameter Conditions Driver output power-off current Min VB = 3.8V, VA = 1.2V, DE = 0V 0V ≤ VDD ≤ 1.5V VB = 0V or 2.4V, VA = 1.2V, DE = 0V 0V ≤ VDD ≤ 1.5V −20 VB = −1.4V, VA = 1.2V, DE = 0V 0V ≤ VDD ≤ 1.5V −32 Driver output power-off differential current (IA(OFF) − IB(OFF)) VA = VB, −1.4V ≤ V ≤ 3.8V, DE = 0V 0V ≤ VDD ≤ 1.5V −4 CA Driver output capacitance VDD = OPEN CB Driver output capacitance CAB CA/B IAB(OFF) Typ Max Units 32 µA +20 µA µA +4 µA 7.8 pF 7.8 pF Driver output differential capacitance 3 pF Driver output capacitance balance (CA/CB) 1 LVDS Receiver DC Specifications VIT+ Positive-going differential input voltage threshold -5 VIT− Negative-going differential input voltage threshold VCMR Common mode voltage range VID = 100 mV IIN Input current VIN = 3.6V, VDD = 3.6V CIN Input capacitance −100 100 -5 0.05 mV mV VDD0.05 V ±1 ±10 µA VIN = 0V, VDD = 3.6V ±1 ±10 µA VDD = OPEN 5 pF POWER SUPPLY CURRENT ICCD Driver Supply Current RL = 50Ω, DE = VDD 67 78 mA ICCZ TRI-STATE Supply Current DE = GND 21 26 mA 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 DS91M125 www.ti.com SNLS290C – AUGUST 2008 – REVISED APRIL 2013 SWITCHING CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter (1) (2) (3) Conditions Min Typ Max Units DRIVER AC SPECIFICATION tPLH Differential Propagation Delay Low to High RL = 50Ω, CL = 5 pF, 3.0 5.5 8.5 ns tPHL Differential Propagation Delay High to Low CD = 0.5 pF 3.0 5.5 8.5 ns tSKD1 (tsk(p)) Pulse Skew |tPLHD − tPHLD| (4) (5) See Figure 7 and Figure 8 65 350 ps 65 400 ps 2.2 2.5 ns 5.5 ns tSKD2 Channel-to-Channel Skew tSKD3 Part-to-Part Skew (7) (5) tSKD4 Part-to-Part Skew (8) (6) (5) (5) tTLH (tr) Rise Time tTHL (tf) Fall Time (5) tPZH Enable Time (Z to Active High) tPZL tPLZ tPHZ Disable Time (Active High to Z) fMAX Maximum Operating Frequency (5) (1) (2) (3) (4) (5) (6) (7) (8) 1.1 2.0 3.0 ns 1.1 2.0 3.0 ns RL = 50Ω, CL = 5 pF, 6 11 ns Enable Time (Z to Active Low ) CD = 0.5 pF 6 11 ns Disable Time (Active Low to Z) See Figure 9 and Figure 10 6 11 ns 6 11 125 ns MHz The ELECTRICAL CHARACTERISTICS tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. CL includes fixture capacitance and CD includes probe capacitance. tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Specification is ensured by characterization and is not tested in production. tSKD2, Channel-to-Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels. tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating temperature range. tSKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. TEST CIRCUITS AND WAVEFORMS CL A RL/2 DI+ Power Supply D Power Supply DI- VOS RL/2 Driver ENABLED VAB CL CL B Figure 2. Differential Driver Test Circuit Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 7 DS91M125 SNLS290C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com A ~ 1.9V B ~ 1.3V 'VOS(SS) VOS VOS(PP) Figure 3. Differential Driver Waveforms A 3.32 k: DI+ Power Supply D Power Supply VTEST RL DI- VAB 3.32 k: B Vary VTEST ± 1.0V to 3.4V Figure 4. Differential Driver Full Load Test Circuit DI+ A Power Supply D Power Supply DI- V = VA or VB B 1.62 k: V Figure 5. Differential Driver DC Open Test Circuit DI+ A Power Supply D Power Supply DI- IOS B Vary VTEST ± 1.0V to 3.4V VTEST Figure 6. Differential Driver Short-Circuit Test Circuit 8 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 DS91M125 www.ti.com SNLS290C – AUGUST 2008 – REVISED APRIL 2013 CL A DI+ Signal Generator CD D DI- RL B 50: Driver ENABLED 50: CL Figure 7. Driver Propagation Delay and Transition Time Test Circuit 1.3V DI+ 1.2V 1.2V DI- 1.1V tPLH tPHL B VOH 0V (Differential) 0V VOL A VDIFF VP(H) VSS 90% 90% 0V 0V VDIFF = A - B VP(L) 10% 10% 0 VSS tTLH tTHL Figure 8. Driver Propagation Delays and Transition Time Waveforms CL A Power Supply RL/2 DI+ D Power Supply CD VOS(SS) TYP DI- RL/2 B DE Generator CL 50: Figure 9. Driver TRI-STATE Delay Test Circuit Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 9 DS91M125 SNLS290C – AUGUST 2008 – REVISED APRIL 2013 DE www.ti.com VDD VDD / 2 VDD /2 0V tPHZ tPZH ~ 0.6V A-B WHEN DIN = L 50% 50% 0V 0V A-B WHEN DIN = H 50% 50% ~ 0.6V tPLZ tPZL Figure 10. Driver TRI-STATE Delay Waveforms 10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 DS91M125 www.ti.com SNLS290C – AUGUST 2008 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS 3.4 3.4 f = 125 MHz DRIVER FALL TIME (10-90%) (ns) DRIVER RISE TIME (10-90%) (ns) f = 125 MHz 3.0 VCC = 3.0 V 2.6 2.2 1.8 VCC = 3.6 V VCC = 3.3 V 1.4 1.0 -50 -10 30 70 110 3.0 VCC = 3.0 V 2.6 2.2 1.8 1.4 1.0 -50 150 -10 TEMPERATURE (°C) 750 600 450 300 f = 1 MHz VCC = 3.3V 150 TA = 25°C 0 50 75 100 125 f = 125 MHz VCC = 3.0 V 7.0 6.0 5.0 VCC = 3.6 V VCC = 3.3 V 4.0 3.0 2.0 -50 -10 30 70 110 150 Figure 14. Driver Propagation Delay (tPLHD) as a Function of Temperature 8.0 180 VCC = 3.3V f = 125 MHz VCC = 3.0 V 7.0 POWER SUPPLY CURRENT (mA) DRIVER PROPAGATION DELAY (tPHLD) (ns) 150 TEMPERATURE (°C) Figure 13. Driver Output Signal Amplitude as a Function of Resistive Load 6.0 5.0 VCC = 3.6 V VCC = 3.3 V 3.0 2.0 -50 110 8.0 RESISTIVE LOAD (:) 4.0 70 Figure 12. Driver Fall Time as a Function of Temperature DRIVER PROPAGATION DELAY (tPLHD) (ns) VOD - DRIVER OUTPUT AMPLITUDE (mV) 900 25 30 TEMPERATURE (°C) Figure 11. Driver Rise Time as a Function of Temperature 0 VCC = 3.6 V VCC = 3.3 V TA = 25°C 150 RL = 50: On all CH) 4 Outputs ON 120 3 Outputs ON 90 2 Outputs ON 60 1 Output ON 30 0 -10 30 70 110 150 0 TEMPERATURE (°C) 25 50 75 100 125 FREQUENCY (MHz) Figure 15. Driver Propagation Delay (tPHLD) as a Function of Temperature Figure 16. Driver Power Supply Current as a Function of Frequency Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 11 DS91M125 SNLS290C – AUGUST 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS91M125 PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) DS91M125TMA/NOPB ACTIVE SOIC D 16 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS91M125 TMA DS91M125TMAX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS91M125 TMA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS91M125TMAX/NOPB Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.3 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS91M125TMAX/NOPB SOIC D 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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