DATASHEET High Performance 1A LDO ISL80510 Features The ISL80510 is a single output Low Dropout voltage regulator (LDO) capable of sourcing up to 1A output current. This LDO operates from input voltages of 2.2V to 6V. The output voltage of ISL80510 can be programmed from 0.8V to 5.5V. • ±1.8% VOUT accuracy guaranteed over line, load and TJ = -40°C to +125°C A submicron BiCMOS process is utilized for this product family to deliver the best in class analog performance and overall value. This CMOS LDO consumes significantly lower quiescent current as a function of load compared to bipolar LDOs, which translates into higher efficiency and packages with smaller footprints. State-of-the-art internal compensation achieves a very fast load transient response and excellent PSRR. The ISL80510 provides an output accuracy of ±1.8% VOUT accuracy over all load, line and temperature variation (TJ = -40°C to +125°C). An external capacitor on the soft-start pin provides an adjustable soft starting of the output voltage ramp to control the inrush current. The ENABLE feature allows the part to be placed into a low quiescent current shutdown mode. Table 1 shows the differences between the ISL80510 and others in its family. • Very low 130mV dropout voltage at VOUT = 2.5V • Stable with a 4.7µF output ceramic capacitor • Very fast transient response • Programmable output soft-start time • Excellent PSRR over wide frequency range • Current limit protection • Thermal shutdown function • Available in an 8 Ld DFN package • Pb-free (RoHS compliant) Applications • Noise-sensitive instrumentation systems • Post regulation of switched mode power supplies • Industrial systems • Medical equipment • Telecommunications and networking equipment TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS • Servers PART NUMBER MAX OUTPUT CURRENT ISL80510 1.0A ISL80505 0.5A • Hard disk drives (HD/HDD) ISL80510 VIN 1 8 VIN CIN 2 7 SS CSS ENABLE 80 EPAD 6 FB 4 70 VOUT 3 5 VOUT VOUT GND R1 COUT CPB (optional) R2 IOUT = 0.6A 60 PSRR (dB) VIN 50 40 30 20 10 VIN = 2.3V VOUT = 1.8V COUT = 10µF CPB= 10nF R1 = 2.61kΩ R2 = 1kΩ 0 100 FIGURE 1. TYPICAL APPLICATION CIRCUIT July 28, 2015 FN8767.0 1 1k IOUT = 1A 10k FREQUENCY (Hz) IOUT = 0.2A 100k 1M FIGURE 2. PSRR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL80510 Block Diagram VIN REFERENCE + SOFT-START ENABLE CONTROL LOGIC THE RMAL SENSO R + EA FET DRIV ER WITH CURRE NT LIMIT VOUT SS FB GND FIGURE 3. BLOCK DIAGRAM Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL80510IRAJZ 0510 ISL80510EVAL1Z Evaluation Board TEMP RANGE (°C) -40 to +125 PACKAGE (RoHS Compliant) 8 Ld 3x3 DFN PKG DWG. # L8.3X3J NOTES: 1. Add “-T*” for Tape and Reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL80510. For more information on MSL please see Technical Brief TB363. Submit Document Feedback 2 FN8767.0 July 28, 2015 ISL80510 Pin Configuration ISL80510 (8 LD 3x3 DFN) TOP VIEW VOUT 1 8 VIN VOUT 2 EPAD FB 3 GND 4 7 VIN 6 SS 5 ENABLE Pin Descriptions PIN NUMBER PIN NAME 1, 2 VOUT 3 FB 4 GND 5 ENABLE 6 SS External capacitor on this pin adjusts start-up ramp and controls inrush current. 7, 8 VIN Input supply; A minimum of 4.7µF X5R/X7R input capacitor is required for proper operation. See “External Capacitor Requirements” on page 10 for more details. - EPAD Submit Document Feedback DESCRIPTION Regulated output voltage. A minimum 4.7µF X5R/X7R output capacitor is required for stability. See “External Capacitor Requirements” on page 10 for more details. This pin is the input to the control loop error amplifier and is used to set the output voltage of the LDO. Ground VIN independent chip enable. TTL and CMOS compatible. EPAD at ground potential; It is recommended to solder the EPAD to the ground plane. 3 FN8767.0 July 28, 2015 ISL80510 Absolute Maximum Ratings Thermal Information VIN Relative to GND (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VOUT Relative to GND (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V ENABLE, FB, SS Relative to GND (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .2.5kV Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 250V Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV Latch-up (Tested per JESD78C, Class 2, Level A) . . . . . ±100mA at +85°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 8 Ld DFN Package (Notes 5, 6). . . . . . . . . . 48 7 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions (Notes 7, 8) Junction Temperature Range (TJ) (Note 7) . . . . . . . . . . . .-40°C to +125°C VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5.5V ENABLE, FB, SS relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 6V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 7. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions define limits where specifications are guaranteed. 8. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current. Electrical Specifications Unless otherwise noted, 2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 10 and Tech Brief TB379. Boldface limits apply across the operating temperature range, -40°C to +125°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNIT 491 500 509 mV DC CHARACTERISTICS Feedback Pin Voltage VFB 2.2V < VIN < 6V; 0A < ILOAD < 1A 1 µA Line Regulation (VOUT(LOW LINE) VOUT(HIGH LINE))/VOUT(LOW LINE) VFB = 0.5V VIN = 2.2V to 6V; ILOAD = 100mA -0.9 0.9 % Load Regulation (VOUT(NO LOAD) VOUT(FULL LOAD))/VOUT(NO LOAD) VIN = 2.2V; ILOAD = 0A to 1A -0.9 0.9 % Feedback Input Current Ground Pin Current IQ Ground Pin Current in Shutdown ISHDN 0.01 ILOAD = 0A, VIN = 2.2V 2.2 4.6 mA ILOAD = 1A, VIN = 2.2V 2.8 5.7 mA ENABLE Pin = 0V, VIN = 6V 0.2 12 µA 130 212 mV 1.75 2.15 A Dropout Voltage (Note 10) VDO ILOAD = 1A, VOUT = 2.5V Output Short-circuit Current OCP VOUT = 0V 1.35 Thermal Shutdown Temperature TSD 160 °C Thermal Shutdown Hysteresis TSDn 30 °C f = 1kHz, ILOAD = 1A; VIN = 2.2V; VOUT = 1.8V 48 dB f = 120Hz, ILOAD = 1A; VIN = 2.2V; VOUT = 1.8V 58 dB VIN = 2.2V; VOUT = 1.8V; ILOAD = 1A, BW = 100Hz < f < 100kHz 75 µVRMS AC CHARACTERISTICS Input Supply Ripple Rejection PSRR Output Noise Voltage Submit Document Feedback 4 FN8767.0 July 28, 2015 ISL80510 Electrical Specifications Unless otherwise noted, 2.2V < VIN < 6V, VOUT = 0.5V, TJ = +25°C. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 10 and Tech Brief TB379. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) MIN (Note 9) TYP MAX (Note 9) UNIT Turn-on Threshold 0.5 0.8 1 V Hysteresis 10 80 200 mV PARAMETER SYMBOL TEST CONDITIONS ENABLE PIN CHARACTERISTICS ENABLE Pin Turn-on Delay COUT = 4.7µF, ILOAD = 1A ENABLE Pin Leakage Current VIN = 6V, ENABLE = 3V 100 µs 1 µA SOFT-START CHARACTERISTICS IPD SS Pin Currents (Note 11) VIN = 3.5V, ENABLE = 0V, SS = 1V ICHG 0.5 1 1.3 mA -3.3 -2 -0.8 µA NOTES: 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. Dropout is defined as the difference in supply VIN and VOUT when the output is below its nominal regulation. 11. IPD is the internal pull-down current that discharges the external SS capacitor on disable. ICHG is the current from the SS pin that charges the external SS capacitor during start-up. Typical Operating Performance IL = 0A. Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, 100 180 140 +85°C 120 100 +25°C 80 60 0°C 40 20 0 0 0.2 0.3 0.4 0.5 0.6 +125°C 80 70 +85°C 60 50 40 30 0°C -40°C 0.7 0.8 0.9 0 2.2 1.0 2.5 2.8 3.1 OUTPUT CURRENT (A) 3.4 3.7 4.0 4.3 4.6 OUTPUT VOLTAGE (V) 4.9 5.2 5.5 FIGURE 5. DROPOUT vs OUTPUT VOLTAGE FIGURE 4. DROPOUT vs OUTPUT CURRENT 180 180 160 IOUT = 1A +125°C 160 +85°C 140 DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) +25°C 20 10 -40°C 0.1 IOUT = 500mA 90 +125°C DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 160 VOUT = 2.5V 120 100 80 -40°C 60 0°C +25°C 40 VOUT = 2.5V 140 120 IOUT = 1A 100 80 60 40 IOUT = 500mA 20 20 0 2.2 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 OUTPUT VOLTAGE (V) 4.9 FIGURE 6. DROPOUT vs OUTPUT VOLTAGE Submit Document Feedback 5 5.2 5.5 0 -40 -25 -10 5.0 20 35 50 65 80 95 110 125 TEMPERATURE (°C) FIGURE 7. DROPOUT vs TEMPERATURE FN8767.0 July 28, 2015 ISL80510 Typical Operating Performance IL = 0A. (Continued) Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, 3.0 3.0 2.5 2.5 +125°C +85°C GROUND CURRENT (mA) GROUND CURRENT (mA) IOUT = 0A 2.0 1.5 +25°C -40°C 1.0 2.0 1.5 +25°C 1.0 -40°C 0.5 0.5 0 +125°C +85°C 0 0.2 0.4 0.6 0.8 0 2.2 1.0 2.7 3.3 3.8 4.4 4.9 5.4 6.0 INPUT VOLTAGE (V) OUTPUT CURRENT (A) FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE FIGURE 8. GROUND CURRENT vs OUTPUT CURRENT 3.0 7 IOUT = 0A 6 SHUTDOWN CURRENT (µA) GROUND CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 5 VIN = 6V 4 VIN = 5V 3 VIN = 2.2V 2 VIN = 3V 0 -40 -25 -10 5.0 20 35 50 65 80 95 0 110 125 VIN = 4V -40 -25 -10 5.0 1.0 0.7 0.6 EN FALLING THRESHOLD 0.4 0.3 0.2 0.1 0 -40 0.9 EN THRESHOLD VOLTAGE (V) EN RISING THRESHOLD 0.5 50 65 80 95 110 125 1.0 VIN = 2.2V 0.8 35 FIGURE 11. SHUTDOWN CURRENT vs TEMPERATURE FIGURE 10. GROUND CURRENT vs TEMPERATURE 0.9 20 TEMPERATURE (°C) TEMPERATURE (°C) EN THRESHOLD VOLTAGE (V) VIN = 2.5V 1 SOLID LINE = RISING THRESHOLD DOTTED LINE = FALLING THRESHOLD 0.8 0.7 0.6 0.5 0.4 0.3 +85°C +25°C +125°C -40°C 0.2 0.1 -25 -10 5.0 20 35 50 65 80 95 TEMPERATURE (°C) FIGURE 12. EN THRESHOLDS vs TEMPERATURE Submit Document Feedback 6 110 125 0 2.2 2.7 3.3 3.8 4.4 4.9 5.4 6.0 INPUT VOLTAGE (V) FIGURE 13. EN THRESHOLDS vs INPUT VOLTAGE FN8767.0 July 28, 2015 ISL80510 Typical Operating Performance IL = 0A. (Continued) Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, 2.0 1.854 1.8 1.836 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.6 +125°C 1.4 1.2 1.0 +85°C 0.8 0.6 +25°C 0.4 1.818 1.800 1.782 -40°C 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.746 6.0 0 0.2 INPUT VOLTAGE (V) 0.4 0.6 0.8 1.0 OUTPUT CURRENT (A) FIGURE 14. OUTPUT VOLTAGE vs INPUT VOLTAGE FIGURE 15. OUTPUT VOLTAGE vs OUTPUT CURRENT 1.854 1.854 IOUT = 10mA IOUT = 0A 1.836 OUTPUT VOLTAGE (V) 1.836 OUTPUT VOLTAGE (V) +125°C -40°C 1.764 0.2 0 +85°C +25°C 1.818 1.800 IOUT = 1A 1.782 1.764 +25°C +85°C 1.818 1.800 +125°C -40°C 1.782 1.764 1.746 -40 -25 -10 5.0 20 35 50 65 80 95 110 125 1.746 2.2 2.7 TEMPERATURE (°C) FIGURE 16. OUTPUT VOLTAGE vs TEMPERATURE 3.3 3.8 4.4 4.9 INPUT VOLTAGE (V) 5.4 6.0 FIGURE 17. OUTPUT VOLTAGE vs INPUT VOLTAGE 2.2 OUTPUT VOLTAGE (V) RLOAD = 3.6Ω VIN = 2.2V 2.0 EN (2V/DIV) 1.8 1.6 SS (500mV/DIV) VIN = 6V 1.4 VOUT (500mV/DIV) 1.2 1.0 -40 -25 -10 5.0 20 35 50 65 80 95 110 125 TEMPERATURE (°C) FIGURE 18. CURRENT LIMIT vs TEMPERATURE Submit Document Feedback 7 ILOAD (500mA/DIV) 2ms/DIV FIGURE 19. ENABLE START-UP (CSS = 10nF) FN8767.0 July 28, 2015 ISL80510 Typical Operating Performance IL = 0A. (Continued) Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, COUT = 10µF, CPB = 10nF COUT = 4.7µF VOUT (AC- COUPLED, 50mV/DIV) VOUT (AC- COUPLED, 20mV/DIV) 10mA <-> 1A AT 2A/µs 10mA <-> 1A AT 2A/µs ILOAD (1A/DIV) ILOAD (1A/DIV) 200µs/DIV 200µs/DIV FIGURE 20. LOAD TRANSIENT RESPONSE FIGURE 21. LOAD TRANSIENT RESPONSE COUT = 4.7µF, ILOAD = 10mA COUT = 10µF, CPB = 10nF, ILOAD = 10mA VOUT (AC- COUPLED, 10mV/DIV) VOUT (AC- COUPLED, 10mV/DIV) 2.2V <-> 6V AT 1V/µs VIN (2V/DIV) VIN (2V/DIV) 2.2V <-> 6V AT 1V/µs 200µs/DIV 200µs/DIV FIGURE 22. LINE TRANSIENT RESPONSE FIGURE 23. LINE TRANSIENT RESPONSE 80 80 70 IOUT = 0.6A 70 IOUT = 0.2A 50 40 30 IOUT = 0.8A IOUT = 1A 20 IOUT = 0.2A IOUT = 0.6A IOUT = 0.4A 60 PSRR (dB) PSRR (dB) 60 IOUT = 0.4A 50 40 30 IOUT = 1A IOUT = 0.8A 20 10 10 CPB = 10nF 0 100 1k 10k 100k FREQUENCY (Hz) FIGURE 24. PSRR vs FREQUENCY Submit Document Feedback 8 1M 0 100 VIN = 2.3V CPB = 10nF 10k 10k 100k 1M FREQUENCY (Hz) FIGURE 25. PSRR vs FREQUENCY FN8767.0 July 28, 2015 ISL80510 Typical Operating Performance Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued) 80 80 70 70 IOUT = 0.4A 50 IOUT = 0.2A 40 30 IOUT = 1A 20 10 IOUT = 0.2A 50 40 30 IOUT = 1A IOUT = 0.8A 10 COUT = 4.7µF 1k IOUT = 0.4A 20 IOUT = 0.8A 0 100 IOUT = 0.6A 60 IOUT = 0.6A PSRR (dB) PSRR (dB) 60 10k FREQUENCY (Hz) 100k COUT = 100µF 0 100 1k 1M OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz) FIGURE 26. PSRR vs FREQUENCY (COUT = 4.7µF) 10k FREQUENCY (Hz) 100k 1M FIGURE 27. PSRR vs FREQUENCY (COUT = 100µF) 10.00 IOUT = 1A 1.00 0.10 0.01 100 1k 10k 100k FREQUENCY (Hz) FIGURE 28. OUTPUT NOISE SPECTRAL DENSITY Submit Document Feedback 9 FN8767.0 July 28, 2015 ISL80510 Applications Information OUTPUT CAPACITOR Input Voltage Requirements The ISL80510 is a linear voltage regulator operating from 2.2V to 6V input voltage and regulates output voltage between 0.8V to 5.5V, a maximum 1A output current. Due to the nature of an LDO, VIN must be some margin higher than VOUT plus dropout at the maximum rated current of the application if active filtering (PSRR) is expected from VIN to VOUT. The generous dropout specification of this family of LDOs allows applications to design a level of efficiency. Enable Operation The ENABLE turn-on threshold is typically 800mV with 80mV of hysteresis. An internal pull-up or pull-down resistor to change these values is available upon request. As a result, this pin must not be left floating, and should be tied to VIN if not used. A 1kΩ to 10kΩ pull-up resistor is required for applications that use open collector or open-drain outputs to control the ENABLE pin. The ENABLE pin may be connected directly to VIN for applications with outputs that are always on. The ISL80510 applies state-of-the-art internal compensation to keep the selection of the output capacitor simple for the customer. Stable operation over full temperature, VIN range, VOUT range and load extremes are guaranteed for all capacitor types and values assuming a minimum of 4.7µF X5R/X7R is used for local bypass on VOUT. This output capacitor must be connected to the VOUT and GND pins of the LDO with PCB traces no longer than 0.5cm. There is a growing trend to use very low ESR Multilayer Ceramic Capacitors (MLCC) because they can support fast load transients and also bypass very high frequency noise from other sources. However, the effective capacitance of MLCCs drops with applied voltage, age and temperature. X7R and X5R dielectric ceramic capacitors are strongly recommended as they typically maintain a capacitance range within ±20% of nominal voltage over full operating ratings of temperature and voltage. Additional capacitors of any value in ceramic, POSCAP, alum/tantalum electrolytic types may be placed in parallel to improve PSRR at higher frequencies and/or load transient AC output voltage tolerances. Output Voltage INPUT CAPACITOR The output voltage can be set to be an external resistor divider network. The values of resistors R1 and R2 can be calculated by using Equation 1. For proper operation, a minimum capacitance of 4.7µF X5R/X7R is required at the input. This ceramic input capacitor must be connected to the VIN and GND pins of the LDO with PCB traces no longer than 0.5cm. V OUT R 1 = R 2 ---------------- – 1 0.5 (EQ. 1) Soft-start Operation The soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or LDO enable. This start-up ramp time can be set by adding an external capacitor from the SS pin to ground. An internal 2µA current source charges up the CSS and the feedback reference voltage is clamped to the voltage across it. The start-up time is set by Equation 2. C SS x0.5 t start = -----------------------2A (EQ. 2) Equation 3 determines the CSS required for a specific start-up inrush current, where VOUT is the output voltage, COUT is the total capacitance on the output and IINRUSH is the desired inrush current. V OUT xC OUT x2A C SS = ---------------------------------------------------I INRUSH x0.5V (EQ. 3) The external capacitor is always discharged to ground at the beginning of start-up or enabling. External Capacitor Requirements External capacitors are required for proper operation. Careful attention must be paid to the layout guidelines and selection of capacitor type and value to ensure optimal performance. Submit Document Feedback 10 PHASE BOOST CAPACITOR (CPB) A small phase boost capacitor, CPB, can be placed across the top resistor, R1, in the feedback resistor divider network in order to improve the AC performances of the LDO for the applications where the output capacitor is 10µF or larger. For 10µF output capacitor, the recommended CPB value can be calculated by using Equation 4. 1 C PB = ----------------------------------2x6000xR 1 (EQ. 4) This zero increases the crossover frequency of the LDO and provides additional phase resulting in faster load transient response Power Dissipation and Thermals The junction temperature must not exceed the range specified in the “Recommended Operating Conditions (Notes 7, 8)” on page 4. The power dissipation can be calculated by using Equation 5: P D = V IN – V OUT I OUT + V IN I GND (EQ. 5) The maximum allowable junction temperature, TJ(MAX) and the maximum expected ambient temperature, TA(MAX) determine the maximum allowable power dissipation, as shown in Equation 6: P D MAX = T J MAX – T A JA (EQ. 6) JA is the junction-to-ambient thermal resistance. FN8767.0 July 28, 2015 ISL80510 For safe operation, ensure that the power dissipation PD, calculated from Equation 5, is less than the maximum allowable power dissipation PD(MAX). . IN OUT The DFN package uses the copper area on the PCB as a heatsink. The EPAD of this package must be soldered to the copper plane (GND plane) for effective heat dissipation. Figure 29 shows a curve for the JA of the DFN package for different copper area sizes. COUT R1 49 ISL80510 CIN EN 47 CPB JA °C/W 45 R2 CSS GND 43 FIGURE 30. EXAMPLE FOR PCB LAYOUT 41 39 37 2 4 6 8 10 12 14 16 18 20 22 24 EPAD-MOUNT COPPER LAND AREA ON PCB, mm2 FIGURE 29. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND AREA ON PCB General PowerPAD Design Considerations The following is an example of how to use via’s to remove heat from the IC. Thermal Fault Protection The power level and the thermal impedance of the package (+48°C/W for DFN) determine when the junction temperature exceeds the thermal shutdown temperature. In the event that the die temperature exceeds around +160°C, the output of the LDO will shut down until the die temperature cools down to about +130°C. Current Limit Protection The ISL80510 LDO incorporates protection against overcurrent due to any short or overload condition applied to the output pin. The LDO performs as a constant current source when the output current exceeds the current limit threshold noted in the “Electrical Specifications” table on page 4. If the short or overload condition is removed from VOUT, then the output returns to normal voltage regulation mode. In the event of an overload condition, the LDO may begin to cycle on and off due to the die temperature exceeding thermal fault condition and subsequently cooling down after the power device is turned off. FIGURE 31. PCB VIA PATTERN A minimum of 4 vias evenly distributed to fill the thermal pad footprint is recommended. Keep the vias small but not so small that their inside diameter prevents solder wicking through the holes during reflow. Connect all vias to the ground plane. It is important the vias have a low thermal resistance for efficient heat transfer. Do not use “thermal relief” patterns to connect the vias. It is important to have a complete connection of the plated through-hole to each plane. PC Board Layout The performances of this LDO depend greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum performance. • A minimum capacitance of 4.7µF X5R/X7R ceramic input capacitor must be placed to the VIN and GND pins of the LDO with PCB traces no longer than 0.5cm. • A minimum capacitance of 4.7µF X5R/X7R ceramic output capacitor must be placed to the VOUT and GND pins of the LDO with PCB traces no longer than 0.5cm. • Connect the EPAD to the ground plane with low-thermal resistance vias. Figure 30 shows an example for 2-layer PCB layout. The bottom layer is the ground plane Submit Document Feedback 11 FN8767.0 July 28, 2015 ISL80510 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION July 28, 2015 FN8767.0 CHANGE Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 12 FN8767.0 July 28, 2015 ISL80510 Package Outline Drawing L8.3x3J 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1 3/15 2X 1.950 3.00 B 0.15 8 5 3.00 (4X) 6X 0.65 A 1.64 +0.10/ - 0.15 6 PIN 1 INDEX AREA 4 8X 0.30 8X 0.400 ± 0.10 TOP VIEW 6 PIN #1 INDEX AREA 1 4 0.10 M C A B 2.38 +0.10/ - 0.15 BOTTOM VIEW SEE DETAIL "X" ( 2.38 ) ( 1.95) 0.10 C Max 1.00 C 0.08 C SIDE VIEW ( 8X 0.60) (1.64) ( 2.80 ) PIN 1 C 0 . 2 REF 5 (6x 0.65) 0 . 00 MIN. 0 . 05 MAX. ( 8 X 0.30) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Submit Document Feedback 13 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN8767.0 July 28, 2015