Intersil ISL8025A Compact synchronous buck regulator Datasheet

Compact Synchronous Buck Regulators
ISL8025, ISL8025A
Features
The ISL8025, ISL8025A are highly efficient, monolithic,
synchronous step-down DC/DC converters that can deliver 5A of
continuous output current from a 2.7V to 5.5V input supply. The
devices use current mode control architecture to deliver a very low
duty cycle operation at high frequency with fast transient
response and excellent loop stability.
• 2.7V to 5.5V input voltage range
• Very low ON-resistance FET’s - P-channel 45mΩ and
N-channel 19mΩ typical values
• High efficiency synchronous buck regulator with up to 95%
efficiency
• Pin-to-pin compatible with ISL8023 and ISL8024
• 0.8% reference accuracy over-temperature/load/line
• Complete BOM with as few as 3 external parts
• Internal soft-start: 1ms or adjustable
• Soft-stop output discharge during disable
• Adjustable frequency from 500kHz to 4MHz - default at
1MHz (ISL8025), 2MHz (ISL8025A)
• External synchronization up to 4MHz
• Over-temperature, overcurrent, overvoltage and negative
overcurrent protection
The ISL8025, ISL8025A integrates a very low ON-resistance
P-Channel (45mΩ) high-side FET and N-Channel (19mΩ)
low-side FET to maximize efficiency and minimize external
component count. The 100% duty-cycle operation allows less
than 225mV dropout voltage at 5A output current. The
operation frequency of the pulse-width modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency, which is set by connecting the FS pin high, is 1MHz
for the ISL8025 and 2MHz for the ISL8025A.
The ISL8025, ISL8025A can be configured for discontinuous or
forced continuous operation at light load. Forced continuous
operation reduces noise and RF interference, while
discontinuous mode provides higher efficiency by reducing
switching losses at light loads.
Fault protection is provided by internal hiccup mode current
limiting during short circuit and overcurrent conditions. Other
protection, such as overvoltage and over-temperature, are also
integrated into the device. A power-good output voltage
monitor indicates when the output is in regulation.
The ISL8025, ISL8025A offers a 1ms Power-good (PG) timer
at power-up. When in shutdown, the ISL8025, ISL8025A
discharges the output capacitor through an internal soft-stop
switch. Other features include internal fixed or adjustable
soft-start and internal/external compensation.
Applications
•
•
•
•
•
•
DC/DC POL modules
μC/µP, FPGA and DSP power
Plug-in DC/DC modules for routers and switchers
Portable instruments
Test and measurement systems
Li-ion battery powered devices
Related Literature
• See AN1806, “5A Low Quiescent Current High Efficiency
Synchronous Buck Regulator”
The ISL8025, ISL8025A are offered in a space saving 16 Ld
3x3 Pb-free QFN package with an exposed pad for improved
thermal performance and 1mm maximum height. The
complete converter occupies less than 0.22 in2 area.
SGND 10
FB 9
100kΩ
+0.6V
*C3 IS OPTIONAL. IT IS
RECOMMENDED TO PUT A
PLACEHOLDER FOR IT AND CHECK
LOOP ANALYSIS BEFORE USE.
EN
5 EN
R3
(EQ. 1)
1
90
C3*
22pF
EFFICIENCY (%)
PHASE 13
3 PG
R2
200kΩ
FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION
(INTERNAL COMPENSATION OPTION)
February 20, 2013
FN8357.0
100
VOUT
GND
PGND 11
SYNC
+1.8V/5A
PGND 12
2 VDD
4
VO
R 2 = R 3 ⎛ ------------ – 1⎞
⎝ VFB
⎠
PHASE 14
ISL8025, ISL8025A
8 COMP
PAD
PG
VIN
17
R1
100kΩ
1
7 SS
GND
+2.7V …+5.5V
C1
2 x 22µF
6 FS
VIN
PHASE 15
VIN 16
L1
1.0µH C2
2 x 22µF
80
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
60
50
40
0.0
0.5
1.0
1.5 2.0 2.5 3.0
OUTPUT LOAD (A)
3.5
4.0
4.5
5.0
FIGURE 2. EFFICIENCY vs LOAD
FSW = 1MHz, VIN = 5V, MODE = PFM, TA = +25°C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL8025, ISL8025A
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Operating Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SKIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
17
17
17
17
17
17
18
18
18
18
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Pin Configuration
VIN
PHASE
PHASE
PHASE
ISL8025, ISL8025A
(16 LD TQFN)
TOP VIEW
16
15
14
13
12
PGND
11
PGND
PG 3
10
SGND
SYNC 4
9
FB
VIN 1
VDD 2
5
6
7
8
EN
FS
SS
COMP
PAD
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1, 16
VIN
Input supply voltage. Place a minimum of two 22µF ceramic capacitors from VIN to PGND as close as
possible to the IC for decoupling.
2
VDD
3
PG
Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation.
4
SYNC
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case
of SYNC pin float.
5
EN
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output
capacitor when driven to low.
6
FS
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
if FS is connected to VIN.
7
SS
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from
SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
8, 9
COMP, FB
The feedback network of the regulator, FB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if COMP is not tied to VDD. Otherwise, COMP is
disconnected thru a MOSFET for internal compensation. Must connect COMP to VDD in internal
compensation mode. The output voltage is set by an external resistor divider connected to FB. With a
properly selected divider, the output voltage can be set to any voltage between the power rail (reduced
by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical
application. Additional external networks across COMP and SGND might be required to improve the
loop compensation of the amplifier operation.
In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the
regulator output voltage.
10
SGND
Signal ground.
Input supply voltage for the logic. Connect VIN pin.
11, 12
PGND
Power ground.
13, 14, 15
PHASE
Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω
resistor when the device is disabled. See“FUNCTIONAL BLOCK DIAGRAM” on page 5 for more detail.
Exposed Pad
-
3
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as
many vias as possible under the pad connecting to SGND plane for optimal thermal performance.
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
OPERATION FREQUENCY
(MHz)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8025IRTAJZ
025A
1
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
ISL8025AIRTAJZ
25AA
2
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8025, ISL8025A. For more information on MSL please see techbrief
TB363.
TABLE 1. SUMMARY OF KEY DIFFERENCES
IOUT
(MAX)
(A)
PART
NUMBER
ISL8025
5
ISL8025A
VIN
RANGE
(V)
VOUT
RANGE
(V)
PART SIZE
(mm)
2.7 to 5.5
0.6 to 5.5
3x3
FSW RANGE
(MHz)
Programmable
0.5MHz to 4MHz
Programmable 1MHz to 4MHz
NOTES:
4. The Evaluation Kit default configuration is VOUT = 1.8V, FSW = 1MHz.
5. VREF is 0.6V.
TABLE 2. ISL8025 COMPONENT SELECTION
VOUT
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
3.6V
C1
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
C2
4 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
C3
22pF
22pF
22pF
22pF
22pF
22pF
22pF
L1
0.47~1µH
0.47~1µH
0.47~1µH
0.68~1.5µH
0.68~1.5µH
1~2.2µH
1~2.2µH
R2
33kΩ
100kΩ
150kΩ
200kΩ
316kΩ
450kΩ
500kΩ
R3
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
TABLE 3. ISL8025A COMPONENT SELECTION
VOUT
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
3.6V
C1
22µF
22µF
22µF
22µF
22µF
22µF
22µF
C2
3 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
C3
22pF
22pF
22pF
22pF
22pF
22pF
22pF
L1
0.22~0.47µH
0.22~0.47µH
0.22~0.47µH
0.33~0.68µH
0.33~0.68µH
0.47~1µH
0.47~1µH
R2
33kΩ
100kΩ
150kΩ
200kΩ
316kΩ
450kΩ
500kΩ
R3
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
4
FN8357.0
February 20, 2013
ISL8025, ISL8025A
COMP
SS
SHUTDOWN
FS
SYNC
55pF
Soft
SOFTSTART
SHUTDOWN
VDD
100kΩ
+
BANDGAP VREF
+
EN
+
COMP
-
EAMP
-
VIN
OSCILLATOR
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
3pF
+
P
PHASE
LS
DRIVER
N
PGND
FB
SLOPE
Slope
COMP
0.8V
6kΩ
+
CSA
-
+
OV
0.85*VREF
PG
+
UV
+
OCP
-
+
SKIP
-
ISET
THRESHOLD
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
0.5V
SCP
+
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
5
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Absolute Maximum Ratings
Thermal Information
(Reference to GND)
Thermal Resistance
θJA (°C/W) θJC (°C/W)
16 LD TQFN Package (Notes 6, 7) . . . . . . .
47
6.5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . .100mA @ +85°C
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 5A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are
at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
2.5
2.7
V
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
IVIN
Shutdown Supply Current
ISD
2.2
2.4
V
SYNC = GND, no load at the output
50
µA
SYNC = GND, no load at the output and no
switches switching
50
60
µA
SYNC = VIN, FSW = 1MHz, no load at the output
8
15
mA
SYNC = VIN, FSW = 2MHz, no load at the output
16
23
mA
SYNC = GND, VIN = 5.5V, EN = low
5
7
µA
0.600
0.605
V
OUTPUT REGULATION
Reference Voltage
VREF
VFB Bias Current
IVFB
0.595
VFB = 0.75V
0.1
µA
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
0.2
%/V
Soft-Start Ramp Time Cycle
SS = SGND
1
ms
Soft-Start Charging Current
ISS
VSS = 0.1V
1.45
1.85
2.25
µA
OVERCURRENT PROTECTION
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
Positive Peak Current Limit
IPLIMIT
Peak Skip Limit
ISKIP
Zero Cross Threshold
5A application
5A application (See “Application Information”
on page 18 for more detail)
6
7.5
9
A
0.8
1
1.2
A
200
mA
-200
6
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are
at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
Negative Current Limit
TEST CONDITIONS
INLIMIT
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
-4.5
-3
-1.5
A
COMPENSATION
Error Amplifier Trans-Conductance
Trans-Resistance
RT
FSW = VIN
60
µA/V
FSW with resistor
120
µA/V
5A application (test at 3.6V)
0.155
0.175
0.195
Ω
VIN = 5V, IO = 200mA
45
55
mΩ
VIN = 2.7V, IO = 200mA
70
90
mΩ
VIN = 5V, IO = 200mA
19
25
mΩ
VIN = 2.7V, IO = 200mA
28
37
mΩ
PHASE
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
PHASE Maximum Duty Cycle
%
100
PHASE Minimum On-Time
SYNC = High
140
ns
OSCILLATOR
Nominal Switching Frequency
FSW
FSW = VIN, ISL8025
800
1000
1200
kHz
FSW = VIN, ISL8025A
1600
2000
2400
kHz
FSW with RS = 402kΩ
490
kHz
FSW with RS = 42.2kΩ
4200
kHz
SYNC Logic Low-to-High Transition Range
0.70
SYNC Hysteresis
0.75
0.80
0.15
SYNC Logic Input Leakage Current
VIN = 3.6V
3.6
V
V
5
µA
0.3
V
1
2
ms
0.01
0.1
µA
PG
Output Low Voltage
Delay Time (Rising Edge)
Time from VOUT reached regulation
PG Pin Leakage Current
PG = VIN
0.5
OVP PG Rising Threshold
0.80
UVP PG Rising Threshold
0.48
0.51
V
0.54
V
UVP PG Hysteresis
30
mV
PGOOD Delay Time (Falling Edge)
7.5
µs
EN
Logic Input Low
0.4
Logic Input High
0.9
V
V
EN Logic Input Leakage Current
Pulled up to 5.5V
0.1
1
µA
Thermal Shutdown
Temperature Rising
150
°C
Thermal Shutdown Hysteresis
Temperature Falling
25
°C
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Typical Operating Performance
100
100
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V,
EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A.
80
70
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
60
50
40
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
80
70
60
50
40
0.0
5.0
90
90
EFFICIENCY (%)
EFFICIENCY (%)
100
80
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
60
50
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
EFFICIENCY (%)
EFFICIENCY (%)
4.0
4.5
5.0
70
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
60
50
4.0
4.5
FIGURE 8. EFFICIENCY vs LOAD (2MHz 3.3VIN PWM)
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
80
8
3.5
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
40
0.0
5.0
90
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
3.0
50
90
1.5
2.5
60
100
1.0
2.0
70
100
0.5
1.5
80
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
40
0.0
1.0
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM)
100
0.5
0.5
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM)
40
0.0
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.8VOUT
0.9VOUT
80
70
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
60
50
5.0
40
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 9. EFFICIENCY vs LOAD (2MHz 3.3VIN PFM)
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Typical Operating Performance
100
100
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V,
EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A. (Continued)
80
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
60
50
40
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 11. EFFICIENCY vs LOAD (2MHz 5VIN PFM)
0.906
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
0.807
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
0.903
OUTPUT VOLTAGE (V)
0.810
OUTPUT VOLTAGE (V)
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
60
40
0.0
5.0
0.813
0.804
0.801
0.798
0.795
0.900
0.897
0.894
0.891
0.888
0.885
0.792
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
0.882
0.0
5.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 0.8V)
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 0.9V)
1.219
1.515
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
1.209
1.204
1.199
1.194
1.189
1.184
1.179
0.0
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
1.510
OUTPUT VOLTAGE (V)
1.214
OUTPUT VOLTAGE (V)
70
50
FIGURE 10. EFFICIENCY vs LOAD (2MHz 5VIN PWM)
0.789
0.0
80
1.505
1.500
1.495
1.490
1.485
1.480
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
9
1.475
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 15. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V,
EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A. (Continued)
1.815
2.505
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
1.800
1.795
1.790
1.785
1.780
1.775
0.0
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
2.500
OUTPUT VOLTAGE (V)
1.805
2.495
2.490
2.485
2.480
2.475
2.470
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
2.465
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT LOAD (A)
FIGURE 16. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
FIGURE 17. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
3.309
5VIN PFM
5VIN PWM
3.301
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.810
3.293
3.285
3.277
3.269
3.261
3.253
3.245
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 18. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
10
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Typical Operating Performance
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A).
PHASE 5V/DIV
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 19. START-UP AT NO LOAD (PFM)
FIGURE 20. START-UP AT NO LOAD (PWM)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 21. SHUTDOWN AT NO LOAD (PFM)
500µs/DIV
FIGURE 22. SHUTDOWN AT NO LOAD (PWM)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 23. START-UP AT 5A LOAD (PWM)
11
500µs/DIV
FIGURE 24. SHUTDOWN AT 5A LOAD (PWM)
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A). (Continued)
IOUT 2A/DIV
VOUT 1V/DIV
VEN 5V/DIV
PG 5V/DIV
IOUT 2A/DIV
VOUT 1V/DIV
VEN 5V/DIV
PG 5V/DIV
1ms/DIV
200µs/DIV
FIGURE 25. START-UP AT 5A LOAD (PFM)
FIGURE 26. SHUTDOWN AT 5A LOAD (PFM)
IOUT 2A/DIV
IOUT 2A/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 27. START-UP VIN AT 5A LOAD (PFM)
FIGURE 28. START-UP VIN AT 5A LOAD (PWM)
IOUT 2A/DIV
IOUT 2A/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 29. SHUTDOWN VIN AT 5A LOAD (PFM)
FIGURE 30. SHUTDOWN VIN AT 5A LOAD (PWM)
12
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A). (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 31. START-UP VIN AT NO LOAD (PFM)
FIGURE 32. START-UP VIN AT NO LOAD (PWM)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
2ms/DIV
2ms/DIV
FIGURE 33. SHUTDOWN VIN AT NO LOAD (PFM)
FIGURE 34. SHUTDOWN VIN AT NO LOAD (PWM)
PHASE 1V/DIV
PHASE 1V/DIV
10ns/DIV
10ns/DIV
FIGURE 35. JITTER AT NO LOAD PWM
FIGURE 36. JITTER AT FULL LOAD PWM
13
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A). (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
IL 1A/DIV
500ns/DIV
20ms/DIV
FIGURE 37. STEADY STATE AT NO LOAD PWM
FIGURE 38. STEADY STATE AT NO LOAD PFM
PHASE 5V/DIV
VOUT RIPPLE 100mV/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
IL 2A/DIV
500ns/DIV
200µs/DIV
FIGURE 39. STEADY STATE AT 5A PWM
FIGURE 40. LOAD TRANSIENT (PWM)
PHASE 5V/DIV
VOUT RIPPLE 100mV/DIV
IL 2A/DIV
VOUT 1V/DIV
IL 2A/DIV
PG 5V/DIV
200µs/DIV
10µs/DIV
FIGURE 41. LOAD TRANSIENT (PFM)
FIGURE 42. OUTPUT SHORT CIRCUIT
14
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A). (Continued)
PHASE 5V/DIV
VOUT 1V/DIV
500mA MODE TRANSITION,
COMPLETELY ENTER TO PWM AT 590mA
VOUT1 RIPPLE 20mV/DIV
IL 5A/DIV
PG 5V/DIV
IL 1A/DIV
50µs/DIV
2µs/DIV
FIGURE 43. OVERCURRENT PROTECTION
FIGURE 44. PFM TO PWM TRANSITION
PHASE 5V/DIV
PHASE 5V/DIV
Back to PFM at 420mA
VOUT 1V/DIV
VOUT1 RIPPLE 20mV/DIV
IL 2A/DIV
PG 5V/DIV
IL 1A/DIV
2µs/DIV
20µs/DIV
FIGURE 45. PWM TO PFM TRANSITION
FIGURE 46. OVERVOLTAGE PROTECTION
VOUT 1V/DIV
PG 2V/DIV
2ms/DIV
FIGURE 47. OVER-TEMPERATURE PROTECTION
15
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Theory of Operation
The ISL8025, ISL8025A are step-down switching regulators
optimized for battery-powered applications. The regulators
operate at 1MHz or 2MHz fixed default switching frequency for
high efficiency and allow smaller form factor, when FS is
connected to VIN. By connecting a resistor from FS to SGND, the
operational frequency adjustable range is 500kHz to 4MHz. At
light load, the regulator reduces the switching frequency, unless
forced to the fixed frequency, to minimize the switching loss and
to maximize the battery life. The quiescent current when the
output is not loaded is typically only 50µA. The supply current is
typically only 5µA when the regulator is shut down.
PWM Control Scheme
Pulling the SYNC pin HI (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL8025, ISL8025A
employs the current-mode pulse-width modulation (PWM) control
scheme for fast transient response and pulse-by-pulse current
limiting. Figure 3 on page 5 shows the Functional Block Diagram.
The current loop consists of the oscillator, the PWM comparator,
current sensing circuit and the slope compensation for the
current loop stability. The slope compensation is 440mV/Ts,
which changes with frequency. The gain for the current sensing
circuit is typically 200mV/A. The control reference for the current
loops comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-Channel MOSFET. The N-FET stays on
until the end of the PWM cycle. Figure 48 shows the typical
operating waveforms during the PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and the
current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 55pF and 100kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 1.6V.
16
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 48. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNC pin LO (<0.4V) forces the converter into PFM
mode. The ISL8025, ISL8025A enters a pulse-skipping mode at
light load to minimize the switching loss by reducing the
switching frequency. Figure 49 illustrates the skip-mode
operation. A zero-cross sensing circuit shown in Figure 3 on
page 5 monitors the N-FET current for zero crossing. When 16
consecutive cycles are detected, the regulator enters the skip
mode. During the sixteen detecting cycles, the current in the
inductor is allowed to become negative. The counter is reset to
zero when the current in any cycle does not cross zero.
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator shown in Figure 3 on page 5.
Each pulse cycle is still synchronized by the PWM clock. The
P-FET is turned on at the clock's rising edge and turned off when
the output is higher than 1.2% of the nominal regulation or when
its current reaches the peak Skip current limit value. Then, the
inductor current is discharging to 0A and stays at zero (the
internal clock is disabled), and the output voltage reduces
gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the P-FET will be turned on again at the rising edge of the internal
clock as it repeats the previous operations.
The regulator resumes normal PWM mode operation when the
output voltage drops 2.5% (1.2% for 2MHz) below the nominal
voltage.
FN8357.0
February 20, 2013
ISL8025, ISL8025A
PWM
PFM
PWM
CLOCK
16 CYCLES
IL
PFM CURRENT LIMIT
LOAD CURRENT
0
NOMINAL +1%
VOUT
NOMINAL -1.5%
NOMINAL
FIGURE 49. SKIP MODE OPERATION WAVEFORMS
Frequency Adjust
PG
The frequency of operation is fixed at 1MHz when FS is tied to VIN.
Adjustable frequency ranges from 500kHz to 4MHz via a simple
resistor connecting FS to SGND, according to Equation 2:
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After 1ms delay of the soft-start period, PG
becomes high impedance as long as the output voltage is within
nominal regulation voltage set by VFB. When VFB drops 15% below
or raises 0.8V above the nominal regulation voltage, the ISL8025,
ISL8025A pulls PG low. Any fault condition forces PG low until the
fault condition is cleared by attempts to soft-start. For logic level
output voltages, connect an external pull-up resistor, R1, between
PG and VIN. A 100kΩ resistor works well in most applications.
220 ⋅ 10 3
R FS [ kΩ ] = ------------------------------ – 14
f OSC [ kHz ]
(EQ. 2)
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3. The current
sensing circuit has a gain of 200mV/A, from the P-FET current to
the CSA output. When the CSA output reaches the threshold, the
OCP comparator is trippled to turn off the P-FET immediately. The
overcurrent function protects the switching converter from a
shorted output by monitoring the current flowing through the
upper MOSFET.
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to 1. If,
on the subsequent cycle, another overcurrent condition is
detected, the OC fault counter will be incremented. If there are
17 sequential OC fault detections, the regulator will be shut down
under an overcurrent fault condition. An overcurrent fault
condition will result in the regulator attempting to restart in a
hiccup mode within the delay of eight soft-start periods. At the
end of the 8th soft-start wait period, the fault counters are reset
and soft-start is attempted again. If the overcurrent condition
goes away during the delay of 8 soft-start periods, the output will
resume back into regulation point after hiccup mode expires.
Negative Current Protection
Similar to overcurrent, the negative current protection is realized
by monitoring the current across the low-side N-FET, as shown in
Figure 3 on page 5. When the valley point of the inductor current
reaches -3A for 4 consecutive cycles, both P-FET and N-FET are off.
The 100Ω in parallel to the N-FET will activate discharging the
output into regulation. The control will begin to switch when output
is within regulation. The regulator will be in PFM for 20µs before
switching to PWM if necessary.
17
UVLO
When the input voltage is below the undervoltage lock-out (UVLO)
threshold, the regulator is disabled.
Soft Start-Up
The soft-start-up reduces the in-rush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed, so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
200kHz, so that the output can start-up smoothly at light load
condition. During soft-start, the IC operates in the SKIP mode to
support pre-biased output condition.
Tie SS to SGND for internal soft-start is approximately 1ms.
Connect a capacitor from SS to SGND to adjust the soft-start
time. This capacitor, along with an internal 1.85µA current
source sets the soft-start interval of the converter, tSS, as shown
by Equation 3.
C SS [ μF ] = 3.1 ⋅ t SS [ s ]
(EQ. 3)
CSS must be less than 33nF to insure proper soft-start reset after
fault condition.
Enable
The enable (EN) input allows the user to control the turning on or
off of the regulator for purposes, such as power-up sequencing.
When the regulator is enabled, there is typically a 600µs delay
FN8357.0
February 20, 2013
ISL8025, ISL8025A
for waking up the bandgap reference and then the soft-start-up
begins.
or low output ripple is required. It is recommended to check the
system level performance along with the simulation model.
Discharge Mode (Soft-Stop)
Output Voltage Selection
When a transition to shutdown mode occurs or the VIN UVLO is
set, the outputs discharge to GND through an internal 100Ω
switch.
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage,
relative to the internal reference voltage, and feed it back to the
inverting input of the error amplifier (refer to Figure 1).
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-FET is typically 45mΩ and the
ON-resistance for the N-FET is typically 19mΩ.
The output voltage programming resistor, R2, will depend on the
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor, R3,
is typically between 10kΩ and 100kΩ, as shown in Equation 5.
100% Duty Cycle
VO
R 2 = R 3 ⎛ ------------ – 1⎞
⎝ VFB
⎠
The ISL8025, ISL8025A features a 100% duty cycle operation to
maximize the battery life. When the battery voltage drops to a
level that the ISL8025, ISL8025A can no longer maintain the
regulation at the output, the regulator completely turns on the
P-FET. The maximum dropout voltage under the 100% duty-cycle
operation is the product of the load current and the
ON-resistance of the P-FET.
Thermal Shut-Down
The ISL8025, ISL8025A has built-in thermal protection. When the
internal temperature reaches +150°C, the regulator is completely
shut down. As the temperature drops to +125°C, the ISL8025,
ISL8025A resumes operation by stepping through the soft-start.
If the output voltage desired is 0.6V, then R3 is left unpopulated
and R2 is shorted. There is a leakage current from VIN to PHASE.
It is recommended to preload the output with 10µA minimum.
For better performance, add 15pF in parallel with R2 (200kΩ).
Check loop analysis before use in application.
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide a filtering
function to prevent the switching current flowing back to the
battery rail. At least two 22µF X5R or X7R ceramic capacitors are
a good starting point for the input capacitor selection.
Loop Compensation Design
Application Information
Output Inductor and Capacitor Selection
To consider steady state and transient operations, the ISL8025
typically uses a 1.0µH output inductor and the ISL8025A uses a
0.47µF. The higher or lower inductor value can be used to
optimize the total converter system performance. For example,
for higher output voltage 3.3V application, in order to decrease
the inductor current ripple and output voltage ripple, the output
inductor value can be increased. It is recommended to set the
ripple inductor current approximately 30% of the maximum
output current for optimized performance. The inductor ripple
current can be expressed, as shown in Equation 4:
When COMP is not connected to VDD, the COMP pin is active for
external loop compensation. The ISL8025, ISL8025A uses
constant frequency peak current mode control architecture to
achieve a fast loop transient response. An accurate current
sensing pilot device in parallel with the upper MOSFET is used for
peak current control signal and overcurrent protection. The
inductor is not considered as a state variable since its peak
current is constant, and the system becomes a single order
system. It is much easier to design a type II compensator to
stabilize the loop than to implement voltage mode control. Peak
current mode control has an inherent input voltage feed-forward
function to achieve good line regulation. Figure 50 shows the
small signal model of the synchronous buck regulator.
^
iin
(EQ. 4)
The ISL8025, ISL8025A uses an internal compensation network
and the output capacitor value is dependent on the output
voltage. The ceramic capacitor is recommended to be X5R or
X7R. The recommended X5R or X7R minimum output capacitor
values are shown in Table 2.
In Table 2, the minimum output capacitor value is given for the
different output voltage to make sure that the whole converter
system is stable. Additional output capacitance should be added
for better performances in applications where high load transient
18
ILd^ 1:D
^
iL
LP
vo^
RLP
Vind^
+
GAIN (VLOOP (S(fi))
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL8025, ISL8025A protects
the typical peak current 6A. The saturation current needs to be
over 7A for maximum output current application.
^
Vin
+
VO ⎞
⎛
V O • ⎜ 1 – ---------⎟
V IN⎠
⎝
ΔI = --------------------------------------L • fS
(EQ. 5)
RT
Rc
Ro
Co
Ti(S)
d^
K
Fm
+
Tv(S)
He(S)
v^comp
-Av(S)
FIGURE 50. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Example: VIN = 5V, VO = 1.8V, IO = 4A, fs = 1MHz, R2 = 200kΩ,
R3 = 100kΩ, Co = 2x22µF/3mΩ, L = 1µH, fc = 100kHz, then
compensator resistance R6:
Vo
R2
C3
V FB
R3
V REF
3
-
(EQ. 10)
R 6 = 17.45 ×10 ⋅ 100kHz ⋅ 1.8V ⋅ 44μF = 138kΩ
V COMP
GM
It is acceptable to use 137kΩ as the closest standard value for
R6.
+
R6
C7
C6
FIGURE 51. TYPE II COMPENSATOR
Figure 51 shows the type II compensator and its transfer function
is expressed, as shown in Equation 6:
S ⎞⎛
S
⎛ 1 + ------------ 1 + -------------⎞
⎝
GM ⋅ R 3
ω cz1⎠ ⎝
ω cz2⎠
v̂ comp
A v ( S ) = ----------------- = -------------------------------------------------------- --------------------------------------------------------------- (EQ. 6
( C6 + C7 ) ⋅ ( R2 + R3 ) ⎛
S
S
v̂ FB
S 1 + -------------⎞ ⎛ 1 + -------------⎞
⎝
⎠⎝
⎠
ω
ω
cp1
cp2
where,
R2 + R3
C6 + C7
1
1
ω cz1 = --------------- , ω cz2 = ---------------, ω cp1 = -----------------------, ω cp2 = ----------------------R6 C6 C7
C3 R2 R3
R6 C6
R2 C3
1.8V ⋅ 44 μF
C 6 = -------------------------------- = 144pF
4A ⋅ 137kΩ
(EQ. 11)
3mΩ ⋅ 44μF-,----------------------------------------------1
C 7 = max (--------------------------------) = (1pF,2.3pF)
137kΩ
π ⋅ 1MHz ( 137kΩ )
(EQ. 12)
It is also acceptable to use the closest standard values for C6 and
C7. There is approximately 3pF parasitic capacitance from VCOMP to
GND; Therefore, C7 is optional. Use C6 = 150pF and C7 = OPEN.
1
C 3 = ------------------------------------------------ = 16pF
π100kHz ⋅ 200kΩ
(EQ. 13)
Use C3 = 15pF. Note that C3 may increase the loop bandwidth
from previous estimated value. Figure 52 shows the simulated
voltage loop gain. It is shown that it has a 150kHz loop
bandwidth with a 42° phase margin and 10dB gain margin. It
may be more desirable to achieve an increased phase margin.
This can be accomplished by lowering R6 by 20% to 30%.
60
Compensator design goal:
High DC gain
45
Choose Loop bandwidth fc less than 100kHz
30
GAIN (dB)
Gain margin: >10dB
Phase margin: >40°
The compensator design procedure is as follows:
The loop gain at crossover frequency of fc has a unity gain.
Therefore, the compensator resistance R6 is determined by
Equation 7.
2πf c V o C o R t
3
R 6 = ---------------------------------- = 17.45 ×10 ⋅ f c V o C o
GM ⋅ V FB
15
0
-15
-30
100
(EQ. 7)
180
Ro Co Vo Co
Rc Co 1
C 6 = --------------- = --------------- ,C 7 = max (--------------,----------------)
R6
Io R6
R 6 πf s R 6
120
Put compensator zero 2 to 5 times fc
1
C 3 = ---------------πf c R 2
(EQ. 9)
19
100k
1M
150
PHASE (°)
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 8. An optional zero can boost the phase margin. ωCZ2 is
a zero due to R2 and C3.
10k
FREQUENCY (Hz)
Where GM is the sum of the trans-conductance, gm, of the
voltage error amplifier in each phase. Compensator capacitor C6
is then given by Equation 8.
(EQ. 8)
1k
90
60
30
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 52. SIMULATED LOOP GAIN
FN8357.0
February 20, 2013
ISL8025, ISL8025A
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For ISL8025, ISL8025A,
the power loop is composed of the output inductor L’s, the output
capacitor (COUT), the PHASE pins, and the PGND pin. It is
necessary to make the power loop as small as possible and the
connecting traces among them should be direct, short and wide.
The switching node of the converter, the PHASE pins, and the
traces connected to the node are very noisy, so keep the voltage
feedback trace away from these noisy traces. The input capacitor
should be placed as close as possible to the VIN pin. The ground
of input and output capacitors should be connected as close as
possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to add at
least 5 vias ground connection within the pad for the best
thermal relief.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
February 20, 2013
FN8357.0
CHANGE
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
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our winning team, visit our website and career page at www.intersil.com.
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Also, please check the product information page to ensure that you have the most updated datasheet: ISL8025, ISL8025A
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20
FN8357.0
February 20, 2013
ISL8025, ISL8025A
Package Outline Drawing
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 1.50
3.00
A
12X 0.50
B
13
6
PIN 1
INDEX AREA
16
6
PIN #1
INDEX AREA
12
3.00
1
1.60 SQ
4
9
(4X)
0.15
0.10 M C A B
5
8
16X 0.40±0.10
TOP VIEW
4 16X 0.23 ±0.05
BOTTOM VIEW
SEE DETAIL “X”
0.10 C
C
0.75 ±0.05
0.08 C
SIDE VIEW
(12X 0.50)
(2.80 TYP) (
1.60)
(16X 0.23)
C
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
(16X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220 WEED.
either a mold or mark feature.
21
FN8357.0
February 20, 2013