TI OPA2314 3-mhz, low-power, low-noise, rrio, 1.8-v cmos operational amplifier Datasheet

OPA314
OPA2314
OPA4314
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SBOS563F – MAY 2011 – REVISED AUGUST 2013
3-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS
Operational Amplifier
Check for Samples: OPA314, OPA2314, OPA4314
FEATURES
DESCRIPTION
•
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The OPA314 family of single-, dual-, and quadchannel operational amplifiers represents a new
generation of low-power, general-purpose CMOS
amplifiers. Rail-to-rail input and output swings, low
quiescent current (150 μA typ at 5.0 VS) combined
with a wide bandwidth of 3 MHz, and very low noise
(14 nV/√Hz at 1 kHz) make this family very attractive
for a variety of battery-powered applications that
require a good balance between cost and
performance. The low input bias current supports
applications with mega-ohm source impedances.
1
2
Low IQ: 150 µA/ch
Wide Supply Range: 1.8 V to 5.5 V
Low Noise: 14 nV/√Hz at 1 kHz
Gain Bandwidth: 3 MHz
Low Input Bias Current: 0.2 pA
Low Offset Voltage: 0.5 mV
Unity-Gain Stable
Internal RF/EMI Filter
Extended Temperature Range:
–40°C to +125°C
APPLICATIONS
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Battery-Powered Instruments:
– Consumer, Industrial, Medical
– Notebooks, Portable Media Players
Photodiode Amplifiers
Active Filters
Remote Sensing
Wireless Metering
Handheld Test Equipment
The robust design of the OPA314 devices provides
ease-of-use to the circuit designer: unity-gain stability
with capacitive loads of up to 300 pF, an integrated
RF/EMI rejection filter, no phase reversal in overdrive
conditions, and high electrostatic discharge (ESD)
protection (4-kV HBM).
These devices are optimized for low-voltage
operation as low as +1.8 V (±0.9 V) and up to +5.5 V
(±2.75 V), and are specified over the full extended
temperature range of –40°C to +125°C.
The OPA314 (single) is available in both SC70-5 and
SOT23-5 packages. The OPA2314 (dual) is offered in
SO-8, MSOP-8, and DFN-8 packages. The quadchannel OPA4314 is offered in a TSSOP-14 package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
OPA314
OPA2314
OPA4314
SBOS563F – MAY 2011 – REVISED AUGUST 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
SC70-5
DCK
SAA
SOT23-5
DBV
RAZ
OPA314
OPA2314
OPA4314
(1)
SO-8
D
O2314
MSOP-8
DGK
OCPQ
DFN-8
DRB
QXY
TSSOP-14
PW
OPA4314
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage
Signal input terminals
Voltage (2)
UNIT
7
V
(V–) – 0.5 to (V+) + 0.5
V
±10
mA
Output short-circuit (3)
Continuous
mA
Operating temperature, TA
–40 to +150
°C
Storage temperature, Tstg
–65 to +150
°C
Junction temperature, TJ
+150
°C
Human body model (HBM)
4000
V
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
ESD rating
(1)
(2)
(3)
2
Current
(2)
OPA314, OPA2314, OPA4314
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
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OPA4314
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SBOS563F – MAY 2011 – REVISED AUGUST 2013
ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V (1)
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
At TA = +25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
OPA314, OPA2314, OPA4314
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
2.5
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
vs Temperature
PSRR
vs power supply
VCM = (VS+) – 1.3 V
VCM = (VS+) – 1.3 V
Over temperature
Channel separation, dc
mV
μV/°C
1
78
92
dB
74
At dc
dB
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
Over temperature
(V–) – 0.2
(V+) + 0.2
V
VS = 1.8 V to 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V
75
96
dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V (2)
66
80
dB
VS = 1.8 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V
70
86
dB
VS = 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V
73
90
dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V (2)
60
dB
INPUT BIAS CURRENT
IB
Input bias current
±0.2
Over temperature
IOS
Input offset current
±0.2
Over temperature
±10
pA
±600
pA
±10
pA
±600
pA
NOISE
Input voltage noise (peak-topeak)
5
μVPP
f = 10 kHz
13
nV/√Hz
f = 1 kHz
14
nV/√Hz
f = 1 kHz
5
fA/√Hz
Differential
VS = 5.0 V
1
pF
Common-mode
VS = 5.0 V
5
pF
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
INPUT CAPACITANCE
CIN
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
Over temperature
Phase margin
(1)
(2)
VS = 1.8 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ
90
115
dB
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ
100
128
dB
VS = 1.8 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ (2)
90
100
dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ (2)
94
110
dB
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ
90
110
dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.2 V, RL = 2 kΩ
VS = 5.0 V, G = +1, RL = 10 kΩ
100
dB
65
deg
Parameters with minimum or maximum specification limits are 100% production tested at +25ºC, unless otherwise noted. Over
temperature limits are based on characterization and statistical analysis.
Specified by design and characterization; not production tested.
Copyright © 2011–2013, Texas Instruments Incorporated
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OPA2314
OPA4314
SBOS563F – MAY 2011 – REVISED AUGUST 2013
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ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V(1) (continued)
Boldface limits apply over the specified temperature range: TA = –40°C to +125°C.
At TA = +25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
OPA314, OPA2314, OPA4314
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
VS = 1.8 V, RL = 10 kΩ, CL = 10 pF
2.7
MHz
VS = 5.0 V, RL = 10 kΩ, CL = 10 pF
3
MHz
VS = 5.0 V, G = +1
1.5
V/μs
To 0.1%, VS = 5.0 V, 2-V step , G = +1
2.3
μs
To 0.01%, VS = 5.0V, 2-V step , G = +1
3.1
μs
Overload recovery time
VS = 5.0 V, VIN × Gain > VS
5.2
μs
Total harmonic distortion +
noise (4)
VS = 5.0 V, VO = 1 VRMS, G = +1, f = 1 kHz, RL = 10 kΩ
0.001
%
GBW
Gain-bandwidth product
SR
Slew rate (3)
tS
Settling time
THD+N
OUTPUT
VO
Voltage output swing from supply
rails
Over temperature
VS = 1.8 V, RL = 10 kΩ
5
15
mV
VS = 5.5 V, RL = 10 kΩ
5
20
mV
VS = 1.8 V, RL = 2 kΩ
15
30
mV
VS = 5.5 V, RL = 2 kΩ
22
40
mV
30
mV
VS = 5.5 V, RL = 10 kΩ
60
mV
ISC
Short-circuit current
VS = 5.5 V, RL = 2 kΩ
VS = 5.0 V
±20
mA
RO
Open-loop output impedance
VS = 5.5 V, f = 100 Hz
570
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
Over temperature
Power-on time
5.5
V
OPA314, OPA2314, OPA4314, VS = 1.8 V, IO = 0 mA
1.8
130
180
µA
OPA2314, OPA4314, VS = 5.0 V, IO = 0 mA
150
190
µA
OPA314, VS = 5.0 V, IO = 0 mA
150
210
µA
220
µA
VS = 5.0 V, IO = 0 mA
VS = 0 V to 5 V, to 90% IQ level
44
µs
TEMPERATURE
(3)
(4)
4
Specified range
–40
+125
°C
Operating range
–40
+150
°C
Storage range
–65
+150
°C
Signifies the slower value of the positive or negative slew rate.
Third-order filter; bandwidth = 80 kHz at –3 dB.
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SBOS563F – MAY 2011 – REVISED AUGUST 2013
THERMAL INFORMATION: OPA314
OPA314
THERMAL METRIC (1)
DBV (SOT23)
DCK (SC70)
5 PINS
5 PINS
θJA
Junction-to-ambient thermal resistance
228.5
281.4
θJC(top)
Junction-to-case(top) thermal resistance
99.1
91.6
θJB
Junction-to-board thermal resistance
54.6
59.6
ψJT
Junction-to-top characterization parameter
7.7
1.5
ψJB
Junction-to-board characterization parameter
53.8
58.8
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
N/A
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION: OPA2314
OPA2314
THERMAL METRIC (1)
D (SO)
DGK (MSOP)
DRB (DFN)
8 PINS
8 PINS
8 PINS
θJA
Junction-to-ambient thermal resistance
138.4
191.2
53.8
θJC(top)
Junction-to-case(top) thermal resistance
89.5
61.9
69.2
θJB
Junction-to-board thermal resistance
78.6
111.9
20.1
ψJT
Junction-to-top characterization parameter
29.9
5.1
3.8
ψJB
Junction-to-board characterization parameter
78.1
110.2
20.0
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
N/A
11.6
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION: OPA4314
OPA4314
THERMAL METRIC (1)
PW (TSSOP)
UNITS
14 PINS
θJA
Junction-to-ambient thermal resistance
121.0
θJC(top)
Junction-to-case(top) thermal resistance
49.4
θJB
Junction-to-board thermal resistance
62.8
ψJT
Junction-to-top characterization parameter
5.9
ψJB
Junction-to-board characterization parameter
62.2
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: OPA314 OPA2314 OPA4314
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OPA314
OPA2314
OPA4314
SBOS563F – MAY 2011 – REVISED AUGUST 2013
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PIN CONFIGURATIONS
DCK PACKAGE
SC70-5
(TOP VIEW)
+IN
1
V-
2
-IN
3
5
4
DBV PACKAGE
SOT23-5
(TOP VIEW)
V+
OUT
1
V-
2
+IN
3
1
-IN A
2
+IN A
3
V-
4
Exposed
Thermal
Die Pad
on
Underside(2)
V+
4
-IN
OUT
DRB PACKAGE(1)
DFN-8
(TOP VIEW)
OUT A
5
D, DGK PACKAGES
SO-8, MSOP-8
(TOP VIEW)
8
V+
7
OUT B
6
-IN B
5
+IN B
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
PW PACKAGE
TSSOP-14
(TOP VIEW)
14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
OUT A
1
-IN A
2
+IN A
A
B
D
C
(1) Pitch: 0,65 mm.
(2) Connect thermal pad to V–. Pad size: 1,8 mm × 1,5 mm.
6
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SBOS563F – MAY 2011 – REVISED AUGUST 2013
TYPICAL CHARACTERISTICS
Table 1. Characteristic Performance Measurements
TITLE
FIGURE
Open-Loop Gain and Phase vs Frequency
Figure 1
Open-Loop Gain vs Temperature
Figure 2
Quiescent Current vs Supply Voltage
Figure 3
Quiescent Current vs Temperature
Figure 4
Offset Voltage Production Distribution
Figure 5
Offset Voltage Drift Distribution
Figure 6
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
Figure 7
Offset Voltage vs Temperature
Figure 8
CMRR and PSRR vs Frequency (RTI)
Figure 9
CMRR and PSRR vs Temperature
Figure 10
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V)
Figure 11
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V)
Figure 12
Input Voltage Noise vs Common-Mode Voltage (5.5 V)
Figure 13
Input Bias and Offset Current vs Temperature
Figure 14
Open-Loop Output Impedance vs Frequency
Figure 15
Maximum Output Voltage vs Frequency and Supply Voltage
Figure 16
Output Voltage Swing vs Output Current (over Temperature)
Figure 17
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V)
Figure 18
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (5.5 V)
Figure 19
Small-Signal Overshoot vs Load Capacitance
Figure 20
Small-Signal Step Response, Noninverting (1.8 V)
Figure 21
Small-Signal Step Response, Noninverting ( 5.5 V)
Figure 22
Large-Signal Step Response, Noninverting (1.8 V)
Figure 23
Large-Signal Step Response, Noninverting ( 5.5 V)
Figure 24
Positive Overload Recovery
Figure 25
Negative Overload Recovery
Figure 26
No Phase Reversal
Figure 27
Channel Separation vs Frequency (Dual)
Figure 28
THD+N vs Amplitude (G = +1, 2 kΩ, 10 kΩ)
Figure 29
THD+N vs Amplitude (G = –1, 2 kΩ, 10 kΩ)
Figure 30
THD+N vs Frequency (0.5 VRMS, G = +1, 2 kΩ, 10 kΩ)
Figure 31
EMIRR
Figure 32
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OPA2314
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TYPICAL CHARACTERISTICS
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
RL = 10 kW/10 pF
VS = ±2.5 V
140
-20
10 kW, 5.5 V
100
-40
80
-60
60
-80
40
-100
20
-120
0
-140
-20
1
10
100
1k
10k
100k
1M
Phase (°)
Gain (dB)
120
0
Open-Loop Gain (dB)
140
OPEN-LOOP GAIN
vs TEMPERATURE
-160
10M
130
2 kW, 5.5 V
120
10 kW, 1.8 V
110
100
-50
0
-25
Frequency (Hz)
25
Figure 1.
160
170
155
Quiescent Current (mA/Ch)
Quiescent Current (mA/Ch)
125
QUIESCENT CURRENT
vs TEMPERATURE
180
160
150
140
130
120
110
100
VS = 5.5 V
150
145
140
135
130
VS = 1.8 V
125
90
80
120
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-50
0
-25
Supply Voltage (V)
25
100
125
Figure 4.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT DISTRIBUTION
30
10
25
Percent of Amplifiers (%)
12
8
6
4
20
15
10
5
0
0
-1.4
-1.3
-1.2
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
2
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 5.
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75
50
Temperature (°C)
Figure 3.
Percent of Amplifiers (%)
100
Figure 2.
QUIESCENT CURRENT
vs SUPPLY
8
75
50
Temperature (°C)
Figure 6.
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SBOS563F – MAY 2011 – REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
OFFSET VOLTAGE vs TEMPERATURE
1000
1500
800
1000
Offset Voltage (mV)
Offset Voltage (mV)
600
400
200
0
-200
-400
-600
-800
-2
0
-500
-1000
Typical Units
VS = ±2.75 V
-1000
-2.75
500
Typical Units
VS = ±2.75 V
-1500
-1.25
-0.5
0
0.5
1.25
2
2.75
-40 -25 -10
5
20
Common-Mode Voltage (V)
CMRR AND PSRR
vs FREQUENCY (Referred-to-Input)
CMRR AND PSRR
vs TEMPERATURE
80
95
110 125
104
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
65
Figure 8.
+PSRR
100
-PSRR
60
CMRR
40
20
0
50
Figure 7.
120
80
35
Temperature (°C)
VS = ±2.75 V
102
100
98
CMRR
96
94
92
PSRR
90
88
86
84
10
100
1k
10k
100k
1M
-50
0
-25
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
Figure 9.
Figure 10.
0.1-Hz to 10-Hz INPUT VOLTAGE NOISE
INPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
Voltage (0.5 mV/div)
Voltage Noise (nv/ÖHz)
100
VS = ±0.9 V
VS = ±2.75 V
10
Time (1 s/div)
10
100
1k
10k
100k
Frequency (Hz)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
VOLTAGE NOISE
vs COMMON-MODE VOLTAGE
INPUT BIAS AND OFFSET CURRENT
vs TEMPERATURE
20
1000
900
18
800
Input Bias Current (pA)
Voltage Noise (nV/ÖHz)
VS = ±2.75 V
f = 1 kHz
16
14
12
700
IB
600
500
400
300
200
IOS
100
10
0
0
0.5
1
2
1.5
2.5
3
3.5
4
5
4.5
5.5
-50
-25
0
25
Common-Mode Input Voltage (V)
50
75
Figure 14.
OPEN-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE
vs FREQUENCY AND SUPPLY VOLTAGE
150
6
VIN = 5.5 V
VIN = 3.3 V
VIN = 1.8 V
5
10k
Voltage (VPP)
Output Impedance (W)
125
Figure 13.
100k
VS = ±0.9 V
1k
4
3
2
1
RL = 10 kW
CL = 10 pF
VS = ±2.75 V
0
1
1
10
100
1k
10k
100k
1M
10M
10k
100k
Frequency (Hz)
1M
10M
Frequency (Hz)
Figure 15.
Figure 16.
OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT (Over Temperature)
CLOSED-LOOP GAIN vs FREQUENCY
40
3
VS = 1.8 V
G = -1 V/V
G = +1 V/V
G = +10 V/V
2
20
1
Gain (dB)
Output Voltage Swing (V)
100
Temperature (°C)
+25°C
0
+125°C
-40°C
0
-1
-2
VS = ±2.75 V
-3
0
5
10
15
20
25
30
35
40
-20
10k
100k
Figure 17.
10
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1M
10M
Frequency (Hz)
Output Current (mA)
Figure 18.
Copyright © 2011–2013, Texas Instruments Incorporated
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OPA314
OPA2314
OPA4314
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SBOS563F – MAY 2011 – REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
CLOSED-LOOP GAIN vs FREQUENCY
40
SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE
70
VS = 5.5 V
G = -1 V/V
G = +1 V/V
G = +10 V/V
60
50
Gain (dB)
Overshoot (%)
20
0
40
30
20
VS = ±2.75 V
Gain = +1 V/V
RL = 10 kW
10
-20
0
10k
100k
1M
10M
0
400
600
800
1000
1200
Capacitive Load (pF)
Figure 19.
Figure 20.
SMALL-SIGNAL PULSE RESPONSE (Noninverting)
SMALL-SIGNAL PULSE RESPONSE (Inverting)
Voltage (25 mV/div)
VIN
ZL = 10 pF + 10 kW
ZL = 100 pF + 10 kW
ZL = 10 pF + 10 kW
ZL = 100 pF + 10 kW
Time (1 ms/div)
Time (1 ms/div)
Figure 21.
Figure 22.
LARGE-SIGNAL PULSE RESPONSE (Inverting)
1
0.75
2
Gain = +1
VS = ±0.9 V
RL = 10 kW
VIN
0.5
0
VOUT
1
VIN
0.5
0
-0.5
-0.5
-1
-0.75
-1.5
-1
Gain = +1
VS = ±2.75 V
RL = 10 kW
1.5
Voltage (V)
0.25
-0.25
Gain = +1
VS = ±2.75 V
RF = 10 kW
VIN
Voltage (25 mV/div)
Gain = +1
VS = ±0.9 V
RF = 10 kW
LARGE-SIGNAL PULSE RESPONSE (Noninverting)
Voltage (V)
200
Frequency (Hz)
VOUT
-2
Time (1 ms/div)
Figure 23.
Time (1 ms/div)
Figure 24.
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OPA2314
OPA4314
SBOS563F – MAY 2011 – REVISED AUGUST 2013
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
POSITIVE OVERLOAD RECOVERY
NEGATIVE OVERLOAD RECOVERY
3
1
0.5
Output
2
Voltage (0.5 V/div)
Voltage (0.5 V/div)
2.5
1.5
1
0.5
0
Input
0
-0.5
-1
-1.5
-2
Output
Input
-0.5
-2.5
-1
-3
0
4
2
6
8
10
12
14
0
6
8
10
Figure 25.
Figure 26.
NO PHASE REVERSAL
CHANNEL SEPARATION vs FREQUENCY
OPA2314
-60
Channel Separation (dB)
VIN
VOUT
3
12
Time (2 ms/div)
4
2
Voltage (1 V/div)
4
2
Time (2 ms/div)
1
0
-1
-2
14
VS = ±2.75 V
-80
-100
-120
-3
-4
-140
0
250
500
750
1000
100
1k
Figure 27.
THD+N vs OUTPUT AMPLITUDE
(G = +1 V/V)
10M
THD+N vs OUTPUT AMPLITUDE
(G = –1 V/V)
VS = ±2.5 V
f = 1 kHz
BW = 80 kHz
G = +1 V/V
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
1M
0.1
0.01
Load = 2 kW
0.001
Load = 10 kW
0.1
1
10
0.01
Load = 2 kW
0.001
VS = ±2.5 V
f = 1 kHz
BW = 80 kHz
G = -1 V/V
0.0001
0.01
1
10
Output Amplitude (VRMS)
Figure 29.
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Load = 10 kW
0.1
Output Amplitude (VRMS)
12
100k
Figure 28.
0.1
0.0001
0.01
10k
Frequency (Hz)
Time (125 ms/div)
Figure 30.
Copyright © 2011–2013, Texas Instruments Incorporated
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OPA2314
OPA4314
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SBOS563F – MAY 2011 – REVISED AUGUST 2013
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
ELECTROMAGNETIC INTERFERENCE REJECTION RATIO
REFERRED TO NONINVERTING INPUT (EMIRR IN+) vs
FREQUENCY
Total Harmonic Distortion + Noise (%)
VS = ±2.5 V
VOUT = 0.5 VRMS
BW = 80 kHz
G = +1 V/V
0.01
Load = 2 kW
0.001
Load = 10 kW
0.0001
10
100
1k
10k
100k
EMIRR IN+ (dB)
THD+N vs FREQUENCY
0.1
120
110
100
90
80
70
60
50
40
30
20
10
0
10M
PRF = −10 dBm
VS = ±2.5 V
VCM = 0 V
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 31.
10G
G001
Figure 32.
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OPA314
OPA2314
OPA4314
SBOS563F – MAY 2011 – REVISED AUGUST 2013
www.ti.com
APPLICATION INFORMATION
The OPA314 is a family of low-power, rail-to-rail input and output operational amplifiers specifically designed for
portable applications. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and suitable for a wide
range of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected
to any point between V+ and ground. The input common-mode voltage range includes both rails, and allows the
OPA314 series to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes them ideal for driving
sampling analog-to-digital converters (ADCs).
The OPA314 features 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per channel,
providing good ac performance at very low power consumption. DC applications are also well served with a very
low input noise voltage of 14 nV/√Hz at 1 kHz, low input bias current (0.2 pA), and an input offset voltage of
0.5 mV (typical).
OPERATING VOLTAGE
The OPA314 series op amps are fully specified and ensured for operation from +1.8 V to +5.5 V. In addition,
many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating voltages or
temperature are shown in the Typical Characteristics graphs. Power-supply pins should be bypassed with 0.01μF ceramic capacitors.
RAIL-TO-RAIL INPUT
The input common-mode voltage range of the OPA314 series extends 200 mV beyond the supply rails. This
performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a
P-channel differential pair, as shown in Figure 33. The N-channel pair is active for input voltages close to the
positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the P-channel pair is on for inputs
from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small transition region, typically
(V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region can vary up to 300 mV
with process variation. Thus, the transition region (both stages on) can range from (V+) – 1.7 V to (V+) – 1.5 V
on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this transition region, PSRR, CMRR,
offset voltage, offset drift, and THD may be degraded compared to device operation outside this region.
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
Figure 33. Simplified Schematic
14
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SBOS563F – MAY 2011 – REVISED AUGUST 2013
INPUT AND ESD PROTECTION
The OPA314 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case
of input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long
as the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Figure 34 shows how a series
input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal
noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 34. Input Current Protection
COMMON-MODE REJECTION RATIO (CMRR)
CMRR for the OPA314 is specified in several ways so the best match for a given application may be used; see
the Electrical Characteristics. First, the CMRR of the device in the common-mode range below the transition
region [VCM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the device when
the application requires use of one of the differential input pairs. Second, the CMRR over the entire commonmode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through the
transition region (see Figure 7).
EMI SUSCEPTIBILITY AND INPUT FILTERING
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the op amp, the dc offset observed at the amplifier output may shift from its nominal value
while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor
junctions. While all op amp pin functions can be affected by EMI, the signal input pins are likely to be the most
susceptible. The OPA314 operational amplifier family incorporate an internal input low-pass filter that reduces the
amplifiers response to EMI. Both common-mode and differential mode filtering are provided by this filter. The
filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a roll-off of 20 dB per decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. Figure 32 illustrates the results of this
testing on the OPAx314. Detailed information can also be found in the application report, EMI Rejection Ratio of
Operational Amplifiers (SBOA128), available for download from www.ti.com.
RAIL-TO-RAIL OUTPUT
Designed as a micro-power, low-noise operational amplifier, the OPA314 delivers a robust output drive capability.
A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing capability.
For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply rail regardless of the
power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to the
rails; refer to the typical characteristic graph, Output Voltage Swing vs Output Current.
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OPA314
OPA2314
OPA4314
SBOS563F – MAY 2011 – REVISED AUGUST 2013
www.ti.com
CAPACITIVE LOAD AND STABILITY
The OPA314 is designed to be used in applications where driving a capacitive load is required. As with all op
amps, there may be specific instances where the OPA314 can become unstable. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether or
not an amplifier is stable in operation. An op amp in the unity-gain (+1-V/V) buffer configuration that drives a
capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise gain. The
capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that
degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the OPA314 remains stable with a pure capacitive load up to
approximately 1 nF. The equivalent series resistance (ESR) of some very large capacitors (CL greater than 1 μF)
is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable.
Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This
increased capability is evident when observing the overshoot response of the amplifier at higher voltage gains.
See the typical characteristic graph, Small-Signal Overshoot vs. Capacitive Load.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 35.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
Figure 35. Improving Capacitive Load Drive
DFN PACKAGE
The OPA2314 (dual version) uses the DFN style package (also known as SON); this package is a QFN with
contacts on only two sides of the package bottom. This leadless package maximizes printed circuit board (PCB)
space and offers enhanced thermal and electrical characteristics through an exposed pad. One of the primary
advantages of the DFN package is its low, 0.9-mm height. DFN packages are physically small, have a smaller
routing area, improved thermal performance, reduced electrical parasitics, and use a pinout scheme that is
consistent with other commonly-used packages, such as SO and MSOP. Additionally, the absence of external
leads eliminates bent-lead issues.
The DFN package can easily be mounted using standard PCB assembly techniques. See Application Note,
QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages
(SCBA017), both available for download from www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the DFN package should be connected
to the most negative potential (V–).
16
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OPA4314
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SBOS563F – MAY 2011 – REVISED AUGUST 2013
APPLICATION EXAMPLES
GENERAL CONFIGURATIONS
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as Figure 36 shows.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 36. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task, as Figure 37 shows. For best results, the amplifier should have a bandwidth that is eight to 10 times the
filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 37. Two-Pole Low-Pass Sallen-Key Filter
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OPA314
OPA2314
OPA4314
SBOS563F – MAY 2011 – REVISED AUGUST 2013
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2012) to Revision F
•
Page
Changed document title (removed "Value Line Series") ...................................................................................................... 1
Changes from Revision D (March 2012) to Revision E
•
Page
Added "Value Line Series" to title ......................................................................................................................................... 1
Changes from Revision C (February 2012) to Revision D
Page
•
Changed product status from mixed status to production data ............................................................................................ 1
•
Deleted shading and footnote 2 from Package Information table ........................................................................................ 2
Changes from Revision B (December 2011) to Revision C
Page
•
Changed first Features bullet ................................................................................................................................................ 1
•
Deleted shading from OPA314 SOT23-5 row (DBV package) in Package Information table .............................................. 2
•
Added OPA2314, OPA4314 to first two Power Supply, Quiescent current per amplifier parameter rows in Electrical
Characteristics table ............................................................................................................................................................. 4
•
Added OPA314 Power Supply, Quiescent current per amplifier parameter row to Electrical Characteristics table ............ 4
Changes from Revision A (August 2011) to Revision B
•
18
Page
Deleted shading from OPA2314 MSOP-8 row in Package Information table ...................................................................... 2
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
(4)
OPA2314AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
-40 to 125
O2314
OPA2314AIDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
OCPQ
OPA2314AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 125
OCPQ
OPA2314AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2314
OPA2314AIDRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QXY
OPA2314AIDRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QXY
OPA314AIDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAZ
OPA314AIDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAZ
OPA314AIDCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SAA
OPA314AIDCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
SAA
OPA4314AIPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4314
OPA4314AIPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4314
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2314 :
• Enhanced Product: OPA2314-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA2314AIDGKR
VSSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2314AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA2314AIDRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA2314AIDRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA314AIDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
OPA314AIDBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
OPA314AIDCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
OPA4314AIPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Dec-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2314AIDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA2314AIDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA2314AIDRBR
SON
DRB
8
3000
367.0
367.0
35.0
OPA2314AIDRBT
SON
DRB
8
250
210.0
185.0
35.0
OPA314AIDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
OPA314AIDBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
OPA314AIDCKR
SC70
DCK
5
3000
180.0
180.0
18.0
OPA4314AIPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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