Renesas M306H3FCFP Single-chip 16-bit cmos microcomputer with data acquisition controller Datasheet

M306H3MC-XXXFP/FCFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
REJ03B0086-0100Z
Rev.1.00
2004.03.23
1. DESCRIPTION
The M306H3MC-XXXFP/FCFP is single-chip microcomputer using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and is packaged in a 116-pin plastic molded QFP. This
single-chip microcomputer operates using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, this is capable of executing instructions at high speed. This
also features a built-in data acquisition circuit, making this correspondence to Teletext broadcasting service.
1.1 Features
• Memory capacity .................................. <ROM>128K bytes
<RAM>5K bytes
• Shortest instruction execution time ...... 100 ns (f(XIN)=10 MHz)
• Supply voltage ..................................... 4.75 V to 5.25V(at f(XIN)=10 MHz)
2.60V to 5.25V(at f(XCIN)=32kHZ, only in low power dissipation mode)
• Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software
interrupt sources; 7 levels (Including key input interrupt)
• Multifunction 16-bit timer ...................... 5 output timers + 6 input timers
• Serial I/O .............................................. 5 channels
UART/clock synchronous: 3
Clock synchronous: 2
• DMAC .................................................. 2 channels (trigger: 24 sources)
• A-D converter ....................................... 8 bits X 8 channels (Expandable up to 10 channels)
• CRC calculation circuit ......................... 1 circuit
• Watchdog timer .................................... 1 line
• Programmable I/O ............................... 87 lines
_______
• Input port .............................................. 1 port (P85 shared with NMI pin)
• Output port ........................................... 1 port (P11 shared with SLICEON pin)
• Chip select output ................................ 4 lines
• Clock generating circuit ....................... 2 built-in circuits
(built-in feedback resistor and external ceramic or crystal oscillator)
• Data acquisition circuit ......................... For PDC, VPS, EPG-J, XDS and WSS
1.2 Applications
DVD recorder, HDD recorder
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M306H3MC-XXXFP/FCFP
Table of contents
1. DESCRIPTION ...................................................... 1
1.1 Features ........................................................... 1
1.2 Applications ..................................................... 1
1.3 Pin Configuration ............................................. 3
1.4 Performance Outline ........................................ 4
1.5 Block Diagram ................................................. 6
2. OPERATION OF FUNCTIONAL BLOCKS ............ 10
2.1 Memory ............................................................ 10
2.2 Central Processing Unit (CPU) ........................ 11
2.3 Reset ............................................................... 13
2.4 Processor Mode ............................................... 23
2.5 Clock Generating Circuit .................................. 39
2.6 Protection ......................................................... 56
2.7 Interrupt ........................................................... 57
2.8 Watchdog Timer .............................................. 75
2.9 DMAC .............................................................. 77
2.10 Timer .............................................................. 87
2.11 Serial I/O ........................................................ 108
2.12 A-D Converter ................................................ 158
2.13 CRC Calculation Circuit ................................. 175
2.14 Expansion Function ....................................... 177
2.15 Programmable I/O Ports ................................ 237
3. ELECTRICAL CHARACTERISTICS ...................... 249
4. FLASH MEMORY VERSION ................................. 270
4.1 Flash Memory Performance ............................ 270
4.2 Memory Map .................................................... 272
4.3 Software Commands ....................................... 284
5. PACKAGE OUTLINE ............................................. 299
6. USAGE NOTES ..................................................... 300
7. DIFFELENCES BETWEEN M306H3MC-XXXFP/FCFP
AND M306H2MC-XXXFP/FCFP ............................ 317
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M306H3MC-XXXFP/FCFP
1.3 Pin Configuration
P42/A18
P37/A15
P40/A16
P41/A17
P35/A13
P36/A14
P34/A12
VCC
P31/A9
P32/A10
P33/A11
VSS
P30/A8(/-/D7)
P26/A6(/D6/D5)
P27/A7(/D7/D6)
P24/A4(/D4/D3)
P25/A5(/D5/D4)
P21/A1(/D1/D0)
P22/A2(/D2/D1)
P23/A3(/D3/D2)
P17/D15/INT5
P20/A0(/D0/-)
P14/D12
P15/D13/INT3
P16/D14/INT4
P12/D10
P13/D11
P11/D9
P10/D8
Figures 1.3.1 shows the pin configuration (top view).
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
P07/D7
P06/D6
88
58
P43/A19
89
57
P44/CS0
P05/D5
P04/D4
90
56
P45/CS1
91
55
P03/D3
P02/D2
92
54
P46/CS2
P47/CS3
93
53
P50/WRL/WR
P01/D1
94
52
P00/D0
P107/AN7/KI3
P106/AN6/KI2
95
51
P51/WRH/BHE
P52/RD
96
50
P53/BCLK
97
49
P105/AN5/KI1
P104/AN4/KI0
98
48
P54/HLDA
P55/HOLD
99
47
P103/AN3
P102/AN2
P101/AN1
100
46
AV SS
103
P100/AN0
VREF
104
105
AV CC
P97/ADTRG/SIN4
44
P56/ALE
P57/RDY/CLKOUT
P60/CTS0/RTS0
P61/CLK0
43
P62/RXD0/SCL0
42
41
P63/TXD0/SDA0
P64/CTS1/RTS1/CLKS1
106
40
P65/CLK1
107
39
START
SYNCIN
108
38
109
37
SVREF
TEST2
VDD3
110
36
P66/RXD1/SCL1
P67/TXD1/SDA1
P11/SLICEON
M1
111
35
TEST1
112
34
CVIN1
VSS3
113
33
VDD2
LP4
114
32
LP3
115
31
116
30
LP2
VSS2
Note 1. P70 and P71 are N channel open-drain output pins.
Figure 1.3.1 Pin configuration (top view)
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P71/RXD2/SCL2/TA0 IN/TB5IN(Note 1)
P70/TXD2/SDA2/TA0 OUT(Note 1)
P72/CLK2/TA1 OUT
P73/CTS2/RTS2/TA1 IN
P75/TA2 IN
P74/TA2 OUT
P80/TA4 OUT
P77/TA3 IN
P76/TA3 OUT
P81/TA4 IN
P84/INT2
P83/INT1
P82/INT0
Vcc
P85/NMI
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Vss
XIN
8
RESET
XOUT
6
P86/XCOUT
7
CNVss
5
P87/XCIN
4
P90/TB0IN/CLK3
BYTE
3
P92/TB2IN/SOUT3
P91/TB1IN/SIN3
2
P93/TB3IN/JSTIN
1
Rev.1.00
45
M306H3MC-XXXFP/FCFP
102
P95/ANEX0/CLK4
P94/TB4IN/RMTIN
FSCIN
P96/ANEX1/SOUT4
101
116P6A-A
M306H3MC-XXXFP/FCFP
1.4 Performance Outline
Table 1.4.1 is a performance outline.
Table 1.4.1 Performance outline
Item
Number of basic instructions
Shortest instruction execution time
Memory
ROM
capacity
RAM
I/O port
P0 to P10 (except P85)
Input port
P85
Output
P11
Multifunction timer
Output
Input
Serial I/O
A-D converter
DMAC
CRC calculation circuit
Watchdog timer
Interrupt
Clock generation circuit
Power supply voltage
Flash memory
Performance
91 instructions
100 ns (f(BCLK)= 10MHZ, VCC= 4.75V to 5.25V)
128K bytes
5K bytes
8 bits x 10,
7 bits x 1
_______
1 bit x 1 (NMI pin level judgment)
1 bit x 1
16 bits x 5 channels (TA0, TA1, TA2, TA3, TA40)
16 bits x 6 channels (TB0, TB1, TB2, TB3, TB4, TB5)
3 channels (UART0, UART1, UART2)
UART, clock synchronous, I2C bus1 (option3), or IE bus2 (option3)
2 channels (SI/O3, SI/O4)
Clock synchronous
8 bits x (8 + 2) channels
2 channels (trigger: 24 sources)
CRC-CCITT
15 bits x 1 (with prescaler)
25 internal and 8 external sources, 4 software sources, 7 levels
2 circuits

• Main clock  (These circuits contain a built-in feedback
4
• Sub-clock  resistor and external ceramic or crystal oscillator)
4.75 V to 5.25 V (at f(XIN)=10MHZ)
2.60 V to 5.25 V (at f(XCIN)=32MHZ, only low-power comsumption)
5.0 V ± 0.25 V
100 times
–20 to 70 °C
CMOS high performance silicon gate
116-pin plastic mold QFP
864 bytes (48 ✕ 18 ✕ 8-bit)
Correspnts to PDC, VPS, EPG-J, XDS and WSS
Program/erase voltage
Number of program/erase
Operating ambient temperature
Device configuration
Package
Data acquisition Slice RAM
Data acquisition circuit
Notes:
1. I2C Bus is a registered trademark of Koninklijke Philips Electronics N.V.
2. IE Bus is a registered trademark of NEC Electronics Corporation.
3. If you desire this option, please so specify.
4. If you use Dara acquisition, use external crystal oscillator.
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M306H3MC-XXXFP/FCFP
Figure 1.4.2 Product table
Type No.
ROM capacity
RAM capacity
Package type
M306H3MC-XXXFP
128K bytes
5K bytes
116P6A-A
M306H3FCFP
Type No.
Remarks
Mask ROM version
Flash Memory version
M306H 3 MC –
XXX FP
Package type:
FP : Package
116P6A-A
ROM No.
Omitted for flash memory version
ROM capacity:
C: 128K bytes
Memory type:
M: Mask ROM version
F: Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/6H Group
M16C Family
Figure 1.4.1 Type No, Memory Size, and Package
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M306H3MC-XXXFP/FCFP
1.5 Block Diagram
Figure 1.5.1 is a block diagram.
8
8
8
Port P0
Port P1
8
Port P2
Port P4
Port P5
XIN-XOUT
XCIN-XCOUT
UART or
clock synchronous serial I/O
Clock synchronous serial I/O
(8 bits X 2 channels)
R0H
R1H
R0L
R1L
R2
R3
USP
ISP
INTB
Memory
ROM
(128K bytes)
RAM
(5K bytes)
PC
FLG
Multiplier
Port P11
Figure 1.5.1 Block diagram
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8
Port P10
A0
A1
FB
SB
8
DMAC
(2 channels)
M16C/60 series16-bit CPU core
Port P9
(15 bits)
Port P85
Slicer
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
7
Expandable up to 10 channels)
8
System clock generator
A-D converter
(8 bits X 8 channels
(8 bits X 3 channels)
Watchdog timer
Port P6
Port P8
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
8
8
Port P7
Internal peripheral functions
Port P3
8
M306H3MC-XXXFP/FCFP
Table 1.5.1 Pin Description
Pin name
Signal name
I/O type
Function
VCC, VSS
Power supply
input
CNVSS
CNVSS
Input
This pin switches between processor modes. Connect this pin to VSS pin
when after a reset you want to start operation in single-chip mode
(memory expansion mode) or the VCC pin when starting operation in
microprocessor mode.
RESET
Reset input
Input
“L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit input/
output. Connect a ceramic resonator or crystal between the XIN and the
XOUT pins. To use an externally derived clock, input it to the XIN pin and
leave the XOUT pin open.
Apply 4.75 V to 5.25 V to the Vcc pin. Apply 0 V to the Vss pin.
XIN
Clock input
Input
XOUT
Clock output
Output
BYTE
External data
bus width
select input
Input
AV CC
Analog power
supply input
Analog power
supply input
Reference
voltage input
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this input
is “H”. This input must be fixed to either “H” or “L”. Connect this pin to
the VSS when single-chip mode.
This pin is a power supply input for the A-D converter. Connect this
pin to VCC.
This pin is a power supply input for the A-D converter. Connect this
pin to VSS.
Input
This pin is a reference voltage input for the A-D converter.
AV SS
VREF
P00 to P07
I/O port P0
Input/output
This is an 8-bit CMOS I/O port. This port has an input/output select
direction register, allowing each pin in that port to be directed for input or
output individually.
If any port is set for input, selection can be made for it in a program
whether or not to have a pull-up resistor in 4 bit units. This selection is
unavailable in memory extension and microprocessor modes.
This port can function as input pins for the A-D converter when so
selected in a program.
Input/output
When set as a separate bus, these pins input and output data (D0 to D7).
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as INT interrupt input pins as selected by software.
Input/output
When set as a separate bus, these pins input and output data (D8 to D15).
Input/output
This is an 8-bit I/O port equivalent to P0. This port can function as input
pins for the A-D converter when so selected in a program.
A0 to A 7
Output
These pins output 8 low-order address bits (A0 to A7).
A0/D0 to
A 7/D7
Input/output
A0, A 1/D0
to A 7/D6
Output
Input/output
If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D0 to D7) and output 8 low-order address bits
(A0 to A7) separated in time by multiplexing.
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D0 to D6) and output address (A1 to A7) separated
in time by multiplexing. They also output address (A0).
D0 to D7
P10 to P17
I/O port P1
D8 to D15
P20 to P27
P30 to P37
I/O port P2
Input/output
This is an 8-bit I/O port equivalent to P0.
A8 to A 15
Output
These pins output 8 middle-order address bits (A8 to A15).
A8/D7,
A 9 to A 15
Input/output
Output
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D7) and output address (A8) separated in time
by multiplexing. They also output address (A9 to A15).
Input/output
This is an 8-bit I/O port equivalent to P0.
Output
Output
These pins output CS0 to CS3 signals and A16 to A19. CS0 to CS3 are
chip select signals used to specify an access space. A16 to A19 are 4
high-order address bits.
P40 to P47
I/O port P3
I/O port P4
CS0 to CS3,
A 16 to A 19
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M306H3MC-XXXFP/FCFP
Table 1.5.2 Pin Description
Pin name
P50 to P57
Signal name
I/O port P5
I/O type
Function
Input/output
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by program.
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
program.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the wait state.
Output
Output
Output
Output
Output
Input
Output
Input
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
P60 to P67
I/O port P6
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as UART0 and UART1 I/O pins as selected by program.
P70 to P77
I/O port P7
Input/output
This is an 8-bit I/O port equivalent to P0 (P70 and P71 are N channel
open-drain output). This port can function as input/output pins for timers
A0 to A3 when so selected in a program.
Furthermore, P70 to P75, P71, and P72 to P75 can also function as
input/output pins for UART2, an input pin for timer B5, and output pins
for the three-phase motor control timer, respectively.
P80 to P84,
P86,
I/O port P8
Input/output
Input/output
P80 to P84, P86, and P87 are I/O ports with the same functions as P0.
When so selected in a program, P80 to P81 and P82 to P84 can function
as input/output pins for timer A4 or output pins for the three-phase
motor control timer and INT interrupt input pins, respectively. P86 and
P87, when so selected in a program, both can function as input/output
pins for the subclock oscillator circuit. In that case, connect a crystal
resonator between P86 (XCOUT pin) and P87 (XCIN pin).
P85 is an input-only port shared with NMI. An NMI interrupt is generated
when input on this pin changes state from high to low.
The NMI function cannot be disabled in a program.
A pull-up cannot be set for this pin.
P87,
Input/output
P85
I/O port P85
Input
P90 to P97
I/O port P9
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as SI/O3, 4 I/O pins, Timer B0 to B4 input pins, A-D converter extended
input pins, A-D trigger input pins, or remote control input pins as
selected by program.
P100 to P107
I/O port P10
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins as selected by program. Furthermore, P104
to P107 also function as input pins for the key input interrupt function.
P11
Rev.1.00
Output port P11 Output
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This is a 1-bit output-only port. Pins in this port also function as
SLICEON output pins as selected by program.
M306H3MC-XXXFP/FCFP
Table 1.5.3 Pin Description
Pin name
Signal name
I/O type
Function
VDD2, VSS2
Power supply
input
Analog power supply pin. Apply 4.75 V to 5.25 V to the VDD2 pin.
Apply 0 V to the VSS2 pin
VDD3, VSS3
Power supply
input
Analog power supply pin. Apply 4.75 V to 5.25 V to the VDD3 pin.
Apply 0 V to the VSS3 pin
SVREF
Synchronous
Input
slice level input
When slice the vertical synchronous signal, input slice power.
CVIN1
Composite
video signal
input 1
Input
This pin inputs the external composite video signal. Data slices this
signal internally by setting.
SYNCIN
Composite
video signal
input 2
Oscillation
selection input
Input
This pin inputs the external composite video signal. Synchronous
devides this signal internally.
Input
This pin selects the oscillation circuit. XIN-XOUT circuit is selected when
this pin is "H"; XCIN-XCOUT circuit is selected when this pin is "L".
LP2
Filter output 1
Output
This is a filter output pin 1 (for fSC).
LP3
Filter output 2
Output
This is a filter output pin 2 (for VPS).
LP4
Filter output 3
Output
This is a filter output pin 3 (for PDC).
FSCIN
fsc input pin for Input
synchronous
signal
generation
Sub-carrier (fsc) input pin for synchronous signal generation.
M1
Mode selection Input
input
(M1 input)
In the flash memory version, connect this pin to the VCC when use
microprocessor mode or memory expansion mode. Connect it to the
VSS when use standard serial I/O mode (single-chip mode).
In the mask ROM version, connect this pin to the VSS or the VCC.
TEST1
Test input
Input
This is a test pin. Connect a condencer.
TEST2
Test input
Input
This is a test pin. Connect this pin to the VSS.
START
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M306H3MC-XXXFP/FCFP
2. OPERATION OF FUNCTIONAL BLOCKS
2.1 Memory
Figure 2.1.1 is a memory map of M306H3MC-XXXFP/FCFP. The address space extends the 1M bytes
from address 0000016 to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address FFFFF16. An internal
ROM of M306H3MC-XXXFP/FCFP is allocated to the addresses from E000016 to FFFFF16.
The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. An internal
RAM of M306H3MC-XXXFP/FCFP is allocated to the addresses from 0040016 to 017FF16. In addition to
storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts
are generated.
The SRF is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is
used by the JMPS or JSRS instruction. For details, refer to the “M16C/60 and M16C/20 Series Software
Manual.”
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
0000016
SFR
FFE0016
0040016
Internal RAM
017FF16
1000016
Special page
vector table
Reserved area
(Note 1)
External area
2700016
Reserved area
FFFDC16
Undefined instruction
FFFFF16
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
2800016
Overflow
External area
8000016
Reserved area
E000016
(Note 2)
Internal ROM
FFFFF16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Figure 2.1.1. Memory Map
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M306H3MC-XXXFP/FCFP
2.2 Central Processing Unit (CPU)
Figure 2.2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and
FB comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2
R0H(R0's high bits) R0L(R0's low bits)
R3
R1H(R1's high bits)R1L(R1's low bits)
R2
Data registers (Note)
R3
A0
b19
A1
Address registers (Note)
FB
Frame base registers (Note)
b15
b0
INTBH
INTBL
Interrupt table register
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
AA
AAAAAAA
AA
A
AA
AA
A
AA
AA
AA
AA
AAAAAAAAAAAAAAAA
AAAAA
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.2.1. Central Processing Unit Register
(1) Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
(2) Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as
A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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M306H3MC-XXXFP/FCFP
(3) Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
(4) Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
(5) Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
(6) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
(7) Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
(8) Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
• Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
• Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
• Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
• Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
• Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
• Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
• Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
• Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
Rev.1.00
2004.03.23
page 12 of 320
M306H3MC-XXXFP/FCFP
2.3 Reset
There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset.
2.3.1 Hardware Reset
____________
____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power
supply voltage is within the recommended operating condition, the pins are initialized (see Table 2.3.1).
____________
The oscillation circuit is initialized and the main clock starts oscillating. When the input level at the RESET
pin is released from “L” to “H”, the CPU and SFR are initialized, and the program is executed starting from
____________
the address indicated by the reset vector. The internal RAM is not initialized. If the RESET pin is pulled “L”
while writing to the internal RAM, the internal RAM becomes indeterminate.
Figure 2.3.1 shows the example reset circuit. Figure 2.3.2 shows the reset sequence. Table 2.3.1 shows
____________
the statuses of the other pins while the RESET pin is “L”. Figure 2.3.3 shows the CPU register status after
reset. Refer to “SFR” for SFR status after reset.
1. When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin.
(2) Supply a clock for 20 cycles or more to the XIN pin.
____________
(3) Apply an “H” signal to the RESET pin.
2. Power on
____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Supply a clock for 20 cycles or more to the XIN pin.
____________
(5) Apply an “H” signal to the RESET pin.
Rev.1.00
2004.03.23
page 13 of 320
M306H3MC-XXXFP/FCFP
Recommended
operating
voltage
VCC
0V
RESET
VCC
RESET
0V
Equal to or less
than 0.2VCC
Equal to or less
than 0.2VCC
More than 20 cycles of XIN + td(P-R)
are needed.
Figure 2.3.1. Example Reset Circuit
2.3.2 Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset
vector.
Select the main clock for the CPU clock source, and set the PM03 bit to “1” with main clock oscillation
satisfactorily stable.
At software reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00 bits in the
PM0 register are not initialized, the processor mode remains unchanged.
2.3.3 Watchdog Timer Reset
Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed
starting from the address indicated by the reset vector.
At watchdog timer reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00
bits in the PM0 register are not initialized, the processor mode remains unchanged.
Rev.1.00
2004.03.23
page 14 of 320
M306H3MC-XXXFP/FCFP
VCC
XIN
td(P-R)
More than
20 cycles
are needed
Microprocessor
mode BYTE = “H”
RESET
BCLK
28cycles
BCLK
Content of reset vector
FFFFC16
Address
FFFFD16
FFFFE16
RD
WR
CS0
Microprocessor
mode BYTE = “L”
Content of reset vector
FFFFC16
Address
FFFFE16
RD
WR
CS0
Single chip
mode
FFFFC16
FFFFE16
Address
Figure 2.3.2. Reset Sequence
Rev.1.00
2004.03.23
Content of reset vector
page 15 of 320
M306H3MC-XXXFP/FCFP
____________
Table 2.3.1. Pin Status When RESET Pin Level is “L”
Status
Pin name
CNVSS = VCC (Note)
CNVSS = VSS
BYTE = VSS
BYTE = VCC
P0
Input port
Data input
Data input
P1
Input port
Data input
Input port
P2, P3, P40 to P43
Input port
Address output (undefined)
Address output (undefined)
P44
Input port
CS0 output (“H” is output)
CS0 output (“H” is output)
P45 to P47
Input port
Input port (Pulled high)
Input port (Pulled high)
P50
Input port
WR output (“H” is output)
WR output (“H” is output)
P51
Input port
BHE output (undefined)
BHE output (undefined)
P52
Input port
RD output (“H” is output)
RD output (“H” is output)
P53
Input port
BCLK output
BCLK output
P54
Input port
HLDA output (The output value HLDA output (The output value
depends on the input to the
depends on the input to the
HOLD pin)
HOLD pin)
P55
Input port
HOLD input
HOLD input
P56
Input port
ALE output (“L” is output)
ALE output (“L” is output)
P57
Input port
RDY input
RDY input
P6, P7, P80 to P84, Input port
P86, P87, P9, P10
Input port
Input port
P11
Output port
Output port
Output port
Note : Connect the M1 pin to the Vcc in the flash memory version of microcomputer.
This is the state after internal power supply voltage is stabilized after a power supply voltage.
It is undefined until internal power supply voltage is stabilized.
b15
b0
000016
Data register(R0)
000016
Data register(R1)
000016
Data register(R2)
000016
Data register(R3)
000016
000016
Address register(A0)
Address register(A1)
000016
Frame base register(FB)
b19
b0
0000016
Interrupt table register(INTB)
Content of addresses FFFFE16 to FFFFC16
b15
Program counter(PC)
b0
000016
User stack pointer(USP)
000016
Interrupt stack pointer(ISP)
000016
Static base register(SB)
b15
b0
Flag register(FLG)
000016
AA
AAAAAA
AA
AAA
AA
AAAA
b15
b8
IPL
b7
U I
b0
O B S Z D C
Figure 2.3.3. CPU Register Status After Rreset
Rev.1.00
2004.03.23
page 16 of 320
M306H3MC-XXXFP/FCFP
2.3.4 SFR
Register
Address
Symbol
After reset
000016
000116
000216
000316
000416
Processor mode register 0
(Note 2)
PM0
000516
Processor mode register 1
System clock control register 0
System clock control register 1
Chip select control register
Address match interrupt enable register
Protect register
PM1
CM0
CM1
CSR
AIER
PRCR
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
Address match interrupt register 1
RMAD1
0016
0016
X016
Chip select expansion control register
CSE
0016
001E16
001F 16
Processor mode register 2
PM2
XXX000002
002016
DMA0 source pointer
SAR0
XX16
XX16
XX16
DMA0 destination pointer
DAR0
XX16
XX16
XX16
DMA0 transfer counter
TCR0
XX16
XX16
DMA0 control register
DM0CON
00000X002
DMA1 source pointer
SAR1
XX16
XX16
XX16
DMA1 destination pointer
DAR1
XX16
XX16
XX16
DMA1 transfer counter
TCR1
XX16
XX16
DMA1 control register
DM1CON
00000X002
000000002(the CNVSS pin is “L”)
00000011 2(the CNVSS pin is “H” (Note 5))
000616
000716
000816
000916
000A16
000B16
000010002
010010002(the START pin is “H” (Note 4))
001000002
000000012
XXXXXX002
XX0000002
000C16
000D16
000E16
000F16
001016
0011 16
001216
XX16
00XXXXXX2(Note 3)
0016
0016
X016
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 3: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program.
Note 4: 011110002 when the START pin is “L.”
Note 5: The CNVSS pin and the M1 pin are “H” in the flash memory version.
X : Undefined
Rev.1.00
2004.03.23
page 17 of 320
M306H3MC-XXXFP/FCFP
Register
Address
Symbol
After reset
INT3IC
TB5IC
XX00X0002
XXXXX0002
XXXXX0002
004016
004116
004216
004316
004416
004516
004616
INT3 interrupt control register
Timer B5/SLICE ON interrupt control register
Timer B4/Remote control interrupt control register, UART1 BUS collision detection interrupt
control register
004716
Timer B3/HINT interrupt control register, UART0 BUS collision detection interrupt control register
TB3IC, U0BCNIC
004816
SI/O4 interrupt control register (S4IC), INT5 interrupt control register
SI/O3 interrupt control register, INT4 interrupt control register
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
Key input interrupt control register
A-D conversion interrupt control register
S4IC, INT5IC
S3IC, INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Note :The blank areas are reserved and cannot be accessed by users.
X : Undefined
Rev.1.00
TB4IC, U1BCNIC
2004.03.23
page 18 of 320
XXXXX0002
XX00X0002
XX00X0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XX00X0002
XX00X0002
XX00X0002
M306H3MC-XXXFP/FCFP
Register
Address
Symbol
After reset
008016
008116
008216
008316
008416
008516
008616
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
Flash memory control register 1
(Note 2)
FMR1
0X00XX0X2
Flash memory control register 0
Address match interrupt register 2
(Note 2)
FMR0
RMAD2
XX0000012
0016
0016
X016
XXXXXX002
0016
0016
X016
01B616
01B716
01B816
01B916
01BA16
01BB16
Address match interrupt enable register 2
01BC16
Address match interrupt register 3
AIER2
RMAD3
01BD16
01BE16
01BF16
~
~
020E16
020F16
Slice RAM address control register
SA
0016
021016
021116
Slice RAM data control register
SD
0016
021216
021316
021416
021516
Address control register for CRC registers
CA
0016
Data control register for CRC registers
CD
0016
021616
021716
Address control register for extended registers
DA
0016
021816
021916
Data control register for extended registers
DD
0016
021A16
021B16
Humming 8/4 register
HM8
0016
021C16
021D16
Humming 24/18 register 0
HM0
0016
021E16
021F16
Humming 24/18 register 1
HM1
0016
025016
~
~
025916
025A16
025B16
025C16
025D16
025E16
Peripheral clock select register
PCLKR
000000112
025F16
~
~
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: This register is included in the flash memory version.
X : Undefined
Rev.1.00
2004.03.23
page 19 of 320
M306H3MC-XXXFP/FCFP
Address
034016
Register
Symbol
After reset
Timer B3, 4, 5 count start flag
TBSR
000XXXXX2
Timer B3 register
TB3
Timer B4 register
TB4
Timer B5 register
TB5
XX16
XX16
XX16
XX16
XX16
XX16
Timer B3 mode register
Timer B4 mode register
Timer B5 mode register
Interrupt cause select register 2
Interrupt cause select register
SI/O3 transmit/receive register
TB3MR
TB4MR
TB5MR
IFSR2A
IFSR
S3TRR
00XX00002
00XX00002
00XX00002
00XXXXXX2
0016
XX16
SI/O3 control register
SI/O3 bit rate generator
SI/O4 transmit/receive register
S3C
S3BRG
S4TRR
010000002
XX16
XX16
SI/O4 control register
SI/O4 bit rate generator
S4C
S4BRG
010000002
XX16
UART0 special mode register 4
UART0 special mode register 3
UART0 special mode register 2
UART0 special mode register
UART1 special mode register 4
UART1 special mode register 3
UART1 special mode register 2
UART1 special mode register
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
UART2 transmit buffer register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
0016
000X0X0X2
X00000002
X00000002
0016
000X0X0X2
X00000002
X00000002
0016
000X0X0X2
X00000002
X00000002
0016
XX16
XXXXXXXX2
XXXXXXXX2
000010002
000000102
XXXXXXXX2
XXXXXXXX2
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B 16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Note : The blank areas are reserved and cannot be accessed by users.
X : Undefined
Rev.1.00
2004.03.23
page 20 of 320
M306H3MC-XXXFP/FCFP
Count start flag
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After reset
0016
0XXXXXXX2
0016
0016
0016
Timer A0 register
TA0
Timer A1 register
TA1
Timer A2 register
TA2
Timer A3 register
TA3
Timer A4 register
TA4
Timer B0 register
TB0
Timer B1 register
TB1
Timer B2 register
TB2
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
00XX00002
00XX00002
00XX00002
03A016
UART0 transmit/receive mode register
03A116
UART0 bit rate generator
UART0 transmit buffer register
U0MR
U0BRG
U0TB
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03AD16
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
03AE16
UART1 receive buffer register
U1C0
U1C1
U1RB
UART transmit/receive control register 2
UCON
0016
XX16
XXXXXXXX2
XXXXXXXX2
000010002
000000102
XXXXXXXX2
XXXXXXXX2
0016
XX16
XXXXXXXX2
XXXXXXXX2
000010002
000000102
XXXXXXXX2
XXXXXXXX2
X00000002
DMA0 request cause select register
DM0SL
0016
DMA1 request cause select register
DM1SL
0016
CRC data register
CRCD
CRC input register
CRCIN
XX16
XX16
XX16
03A216
03A316
03A416
03A516
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
03A616
UART0 receive buffer register
U0C0
U0C1
U0RB
03A716
03A816
UART1 transmit/receive mode register
03A916
UART1 bit rate generator
UART1 transmit buffer register
03AA16
U1MR
U1BRG
U1TB
03AB16
03AC 16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Note : The blank areas are reserved and cannot be accessed by users.
X : Undefined
Rev.1.00
2004.03.23
page 21 of 320
M306H3MC-XXXFP/FCFP
Address
03C016
Register
A-D register 0
Symbol
AD0
After reset
XXXXXXXX2
A-D register 1
AD1
XXXXXXXX2
A-D register 2
AD2
XXXXXXXX2
A-D register 3
AD3
XXXXXXXX2
A-D register 4
AD4
XXXXXXXX2
A-D register 5
AD5
XXXXXXXX2
A-D register 6
AD6
XXXXXXXX2
A-D register 7
AD7
XXXXXXXX2
A-D control register 2
ADCON2
0016
A-D control register 0
A-D control register 1
ADCON0
ADCON1
00000XXX2
0016
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
XX16
XX16
0016
0016
XX16
XX16
0016
0016
XX16
XX16
0016
0016
XX16
XX16
0016
0016
XX16
XX16
00X000002
0016
XX16
Port P10 direction register
PD10
0016
Pull-up control register 0
Pull-up control register 1
PUR0
PUR1
000000002
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
0016
000000102
03FE16
03FF16
Pull-up control register 2
Port control register
PUR2
PCR
0016
0016
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: At hardware reset 1 or hardware reset 2, the register is as follows:
• “000000002” where “L” is inputted to the CNVSS pin
• “000000102” where “H” is inputted to the CNVSS pin and the M1 pin (flash memory version of microcomputer)
• “000000102” where “H” is inputted to the CNVSS pin (mask ROM version).
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
• “000000002” where the PM01 to PM00 bits in the PM0 register are “002” (single-chip mode)
• “000000102” where the PM01 to PM00 bits in the PM0 register are “012” (memory expansion mode) or
“11 2” (microprocessor mode)
X : Undefined
Rev.1.00
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(Note 2)
M306H3MC-XXXFP/FCFP
2.4 Processor Mode
(1) Types of Processor Mode
Three processor modes are available to choose from: single-chip mode, memory expansion mode, and
microprocessor mode. Table 2.4.1 shows the features of these processor modes.
Table 2.4.1. Features of Processor Modes
Access space
Processor modes
Pins which are assigned I/O ports
All pins are I/O ports or peripheral
function I/O pins
Some pins serve as bus control pins (Note)
Single-chip mode
SFR, internal RAM, internal ROM
Memory expansion mode
SFR, internal RAM, internal ROM,
external area (Note)
SFR, internal RAM, external area (Note) Some pins serve as bus control pins (Note)
Microprocessor mode
Note : Refer to “Bus”.
(2) Setting Processor Modes
Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register.
Table 2.4.2 shows the processor mode after hardware reset. Table 2.4.3 shows the PM01 to PM00 bit set
values and processor modes.
In the flash memory version, after hardware reset, apply the CNVSS pin and the M1 pin to VCC when use
microprocessor. In the mask ROM version, after hardware reset, apply the CNVSS pin to VCC when use
microprocessor.
Table 2.4.2. Processor Mode After Hardware Reset
CNVSS pin input level
VSS
VCC (Note 1, Note 2)
Processor mode
Single-chip mode
Microprocessor mode
Note 1: If the microcomputer is reset in hardware by applying VCC to the CNVSS pin and the M1 pin in
the flash memory version (by applying VCC to the CNVSS pin in the mask ROM version) the
internal ROM cannot be accessed regardless of PM10 to PM00 bits.
Note 2: The multiplexed bus cannot be assigned to the entire CS space.
Table 2.4.3. PM01 to PM00 Bits Set Values and Processor Modes
PM01 to PM00 bits
Processor modes
Single-chip mode
002
012
Memory expansion mode
102
Must not be set
112
Microprocessor mode
Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regardless of whether the input level on the CNVSS pin is “H” or “L”. Note, however, that the PM01 to PM00 bits
cannot be rewritten to “012” (memory expansion mode) or “112” (microprocessor mode) at the same time
the PM07 to PM02 bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor
mode in the internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the
internal ROM.
If the microcomputer is reset in hardware by applying VCC to the CNVSS pin and the M1 pin in the flash
memory version (by applying VCC to the CNVSS pin in the mask ROM version), the internal ROM cannot
be accessed regardless of PM01 to PM00 bits.
Figures 2.4.1 and 2.4.2 show the registers associated with processor modes. Figure 2.4.3 show the
memory map in single chip mode.
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M306H3MC-XXXFP/FCFP
Processor mode register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
Symbol
PM0
b0
Bit symbol
PM00
Address
000416
After reset (Note 4)
000000002 (CNVSS pin = “L”)
00000011 2 (CNVSS pin = “H”) (Note 5)
Bit name
Processor mode bit
(Note 4)
PM01
PM02
R/W mode select bit
(Note 2)
PM03
Software reset bit
PM04
Multiplexed bus space
select bit (Note 2)
PM05
PM06
PM07
Function
b1 b0
RW
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
1 1: Microprocessor mode
RW
0 : RD,BHE,WR
1 : RD,WRH,WRL
RW
Setting this bit to “1” resets the
microcomputer. When read, its content
is “0”.
RW
RW
b5 b4
0 0 : Multiplexed bus is unused
(Separate bus in the entire CS
space)
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to the entire CS space
(Note 3)
RW
RW
Port P40 to P43 function
select bit (Note 2)
0 : Address output
1 : Port function
(Address is not output)
RW
BCLK output disable bit
(Note 2)
0 : BCLK is output
1 : BCLK is not output
(high impedance)
RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: Effective when the PM01 to PM00 bits are set to “012” (memory expansion mode) or “11 2” (microprocessor
mode).
Note 3: To set the PM01 to PM00 bits are “012” and the PM05 to PM04 bits are “112” (multiplexed bus assigned to
the entire CS space), apply an “H” signal to the BYTE pin (external data bus is 8 bits wide). While the
CNVSS pin and the M1 pin are held “H” (= VCC) in the flash memory version (the CNVSS pin is held “H” in the
mask ROM version), do not rewrite the PM05 to PM04 bits to “112” after reset.
If the PM05 to PM04 bits are set to “112” during memory expansion mode, P31 to P37 and P40 to P43
become I/O ports, in which case the accessible area for each CS is 256 bytes.
Note 4: The PM01 to PM00 bits do not change at software reset, watchdog timer reset and oscillation stop
detection reset.
Note 5: In the flash memory version, the value is at the CNVSS pin = VCC and the M1 pin = VCC. In the mask ROM version,
the CNVSS pin = VCC.
Figure 2.4.1. PM0 Register
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M306H3MC-XXXFP/FCFP
Processor mode register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PM1
0 0 0
Bit symbol
Address
000516
After reset
0X0010002
Bit name
Function
RW
0: 0800016 to 26FFF16
(block A disable)
1: 1000016 to 26FFF16
(block A enable)
RW
PM10
CS2 area switch bit
(data block enable bit)
(Note 2)
PM11
0 : Address output
Port P37 to P34
function select bit (Note 3) 1 : Port function
PM12
Watchdog timer function
select bit
0 : Watchdog timer interrupt
1 : Watchdog timer reset (Note 4)
RW
PM13
Internal reserved area
expansion bit (Note 6)
See Note 7
RW
Reserved bit
Should be set to “0”.
RW
Wait bit (Note 5)
0 : No wait state
1 : With wait state (1 wait)
RW
(b6-b4)
PM17
RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
Note 2: For the mask ROM version, this bit must be set to “0” .
The PM10 bit is automatically set to “1” when the FMR01 bit in the FMR0 register is “1” (CPU rewrite mode).
Note 3: Effective when the PM01 to PM00 bits are set to “012” (memory expansion mode) or “11 2” (microprocessor
mode).
Note 4: PM12 bit is set to “1” by writing a “1” in a program. (Writing a “0” has no effect.)
Note 5: When PM17 bit is set to “1” (with wait state), one wait state is inserted when accessing the internal RAM,
internal ROM, or an external area. If the CSiW bit (i = 0 to 3) in the CSR register is “0” (with wait state), the
CSi area is always accessed with one or more wait states regardless of whether the PM17 bit is set or not.
Where the RDY signal is used or multiplex bus is used, set the CSiW bit to “0” (with wait state).
Note 6: The PM13 bit is automatically set to “1” when the FMR01 bit in the FMR0 register is “1” (CPU rewrite mode).
Note 7: The access area is changed by the PM13 bit as listed in the table below.
Access area
PM13=0
Internal RAM Up to addresses 0040016 to 03FFF16 (15 Kbytes)
PM13=1
The entire area is usable
ROM Up to addresses D000016 to FFFFF16 (192 Kbytes) The entire area is usable
External
Addresses 0400016 to 07FFF16 are usable
Addresses 0400016 to 07FFF16 are reserved
Addresses 8000016 to CFFFF16 are usable
Addresses 8000016 to CFFFF16 are reserved
Figure 2.4.2. PM1 Register
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M306H3MC-XXXFP/FCFP
Single-chip mode
0000016
SFR
0040016
Internal RAM
017FF16
Can not
use
E000016
Internal ROM
FFFFF16
Note 1: Set the PM10 bit to “0” (0800016 to 26FFF16 for CS2 area).
Figure 2.4.3. Memory Map in Single Chip Mode
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M306H3MC-XXXFP/FCFP
2.4.1 Bus
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform
_______
data input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0
_______ _____ ________ ______ ________ ________
________ __________ _________
to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.
Bus Mode
The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits in the PM0
register.
Separate Bus
In this bus mode, data and address are separate.
Multiplexed Bus
In this bus mode, data and address are multiplexed.
• When the input level on BYTE pin is high (8-bit data bus)
D0 to D7 and A0 to A7 are multiplexed.
• When the input level on BYTE pin is low (16-bit data bus)
D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15.
External buses connecting to a multiplexed bus are allocated to only the even addresses of the microcomputer. Odd addresses cannot be accessed.
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M306H3MC-XXXFP/FCFP
2.4.2 Bus Control
The following describes the signals needed for accessing external devices and the functionality of software
wait.
(1) Address Bus
The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or
20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 2.4.4
shows the PM06 and PM11 bit set values and address bus widths.
Table 2.4.4. PM06 and PM11 Bits Set Value and Address Bus Width
Set value(Note)
PM11=1
PM06=1
Pin function
P34 to P37
P40 to P43
PM11=0
A12 to A15
PM06=1
P40 to P43
PM11=0
A12 to A15
PM06=0
A16 to A19
Address bus wide
12 bits
16 bits
20 bits
Note 1: No values other than those shown above can be set.
When processor mode is changed from single-chip mode to memory extension mode, the address
bus is indeterminate until any external area is accessed.
(2) Data Bus
When input on the BYTE pin is high(data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus;
when input on the BYTE pin is low(data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
(3) Chip Select Signal
______
______
The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins.
_____
These pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 2.4.4 shows the CSR register.
______
During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
______
______
from the CSi pin. Figure 2.4.5 shows the example of address bus and CSi signal output in 1 Mbyte
_____
mode. Figure 2.4.6 to 2.4.7 show CS area in 1 Mbyte mode.
Chip select control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CSR
Bit symbol
CS0
Address
000816
Bit name
CS1
CS0 output enable bit
CS1 output enable bit
CS2
CS2 output enable bit
CS3
CS3 output enable bit
CS0W
CS0 wait bit
CS1W
CS1 wait bit
CS2W
CS2 wait bit
CS3W
CS3 wait bit
After reset
000000012
Function
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
RW
RW
RW
RW
RW
0 : With wait state
1 : Without wait state
(Note 1, Note 2, Note 3)
RW
RW
RW
RW
Note 1: Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set
the CSiW bit to “0” (Wait state).
Note 2: If the PM17 bit in the PM1 register is set to “1” (with wait state), the external area indicated by CS0 to
CS3 is always accessed with one wait state even when the CSiW bit is “1” (without wait state).
Note 3: When the CSiW bit = “0” (with wait state), the number of wait states (interms of clock cycles) can be
selected using the CSEi1W to CSEi0W bits in the CSE register.
Figure 2.4.4. CSR Register
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M306H3MC-XXXFP/FCFP
Example 2
Example 1
To access the external area indicated by CSj in the next cycle after
accessing the external area indicated by CSi
To access the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi
The address bus and the chip select signal both change state between
these two cycles.
The chip select signal changes state but the address bus does not
change state
Access to the external
area indicated by CSi
Access to the external
area indicated by CSi
Access to the external
area indicated by CSj
BCLK
BCLK
Read signal
Read signal
Data bus
Address bus
Data
Data bus
Address Address
Address bus
Data
Access to the internal
ROM or internal RAM
Data
Address
CSi
CSi
CSj
Example 3
Example 4
To access the external area indicated by CSi in the next cycle after
accessing the external area indicated by the same CSi
Not to access any area (nor instruction prefetch generated) in the next cycle after
accessing the external area indicated by CSi
The address bus changes state but the chip select signal does not
change state
Neither the address bus nor the chip select signal changes state between
these two cycles
Access to the external
area indicated by CSi
Access to the external
area indicated by CSi
Access to the same
external area
BCLK
BCLK
Read signal
Read signal
Data bus
Address bus
Data
Data bus
Data
Address Address
Address bus
CSi
No access
Data
Address
CSi
Note : These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
may be extended more than two cycles depending on a combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3
(not including i, however)
______
Figure 2.4.5. Example of Address Bus and CSi Signal Output in 1 Mbyte Mode
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Memory expansion mode
0000016
SFR
Microprocessor mode
SFR
0040016
Internal RAM
Internal RAM
Reserved area
Reserved area
017FF16
0400016
CS3(16 Kbytes)
0800016 Reserved, External area
1000016
2700016
2800016
3000016
Reserved area
Reserved, external area
CS2(PM10=0: 124 Kbytes)
CS2 (PM10=1: 92 Kbytes)
Reserved area
CS1(32 Kbytes)
External area
External area
CS0(Memory expansion mode:640 Kbytes )
D000016
Reserved area
CS0(Microprocessor mode:832 Kbytes)
E000016
Internal ROM
FFFFF16
PM13=0
CS0
Memory expansion mode
3000016–CFFFF16
External area
CS1
CS2
2800016–
When PM10=0
2FFFF16
0800016–26FFF16
CS3
0400016–
07FFF16
When PM10=1
1000016–26FFF16
Microprocessor mode
3000016–FFFFF16
______
Figure 2.4.6. CS Area in 1 Mbyte Mode (PM13=0)
Memory expansion mode
0000016
Microprocessor mode
SFR
SFR
0040016
Internal RAM
Internal RAM
017FF16
Reserved area
0800016 Reserved, external area
Reserved, external area
1000016
Reserved area
2700016
2800016
Reserved area
CS1(32 Kbytes)
3000016
External
area
8000016
CS0(Memory expansion mode:320 Kbytes )
External area
Reserved area
CS0(Microprocessor mode:832 Kbytes)
E000016
Internal ROM
FFFFF16
PM13=1
CS0
Memory expansion mode
3000016–7FFFF16
External area
CS1
CS2
2800016–
When PM10=0
2FFFF16
0800016–26FFF16
Microprocessor mode
3000016–FFFFF16
CS3
No area
When PM10=1
1000016–26FFF16
______
Figure 2.4.7. CS Area in 1 Mbyte Mode (PM13=1)
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CS2 (PM10=1: 92 Kbytes)
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M306H3MC-XXXFP/FCFP
(4) Read and Write Signals
_____
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD,
________
______
_____ ________
________
BHE and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When
_____ ______
________
the data bus is 8 bits wide, use a combination of RD, WR and BHE.
_____ ________
_________
Table 2.4.5 shows the operation of RD, WRL, and WRH signals. Table 2.4.6 shows the operation of
_____ ______
________
operation of RD, WR, and BHE signals.
_____
________
_________
Table 2.4.5. Operation of RD, WRL and WRH Signals
Data bus width
RD
L
H
H
H
16-bit
( BYTE pin input
= “L”)
WRL
H
L
H
L
_____
______
Status of external data bus
Read data
Write 1 byte of data to an even address
Write 1 byte of data to an odd address
Write data to both even and odd addresses
WRH
H
H
L
L
________
Table 2.4.6. Operation of RD, WR and BHE Signals
Data bus width
16-bit
(BYTE pin input
= “L”)
8-bit (BYTE pin
input = “H”)
RD
H
L
H
L
H
L
H
L
WR
L
H
L
H
L
H
L
H
BHE
L
L
H
H
L
L
(Note)
(Note)
A0
H
H
L
L
L
L
H or L
H or L
Status of external data bus
Write 1 byte of data to an odd address
Read 1 byte of data from an odd address
Write 1 byte of data to an even address
Read 1 byte of data from an even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
Note : Do not use.
(5) ALE Signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin input = “H”
When BYTE pin input = “L”
ALE
ALE
A0/D0 to A7/D7
A8 to A19
Address
Address
A0
Data
A1/D0 to A8/D7
Address
A9 to A19
Note : If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
Figure 2.4.8. ALE Signal, Address Bus, Data Bus
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Address (Note)
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Address
M306H3MC-XXXFP/FCFP
________
(6) The RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on
________
the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in
________
the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.
______
______
______ ________
________
______
________
__________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
________
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 2.4.9 shows example in which the wait state was inserted into the read cycle by the
________
________
RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register
________
________
to “0” (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.
In an instance of separate bus
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
: Wait using RDY signal
Accept timing of RDY signal
: Wait using software
Shown above is the case where CSEiW to CSEi1W (i = 0 to 3) bits in the CSE register are “00 2” (one wait state).
________
Figure 2.4.9. Example in which Wait State was Inserted into Read Cycle by RDY Signal
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(7) Hold Signal
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the
__________
input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in
__________
process finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during
__________
which time the HLDA pin outputs a low-level signal.
Table 2.4.7 shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However,
if the CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two
separate accesses.
__________
HOLD > DMAC > CPU
Figure 2.4.10. Bus-using Priorities
Table 2.4.7. Microcomputer Status in Hold State
Item
Status
BCLK
Output
_______
_______
_____
________
_________ _______ _______
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE
I/O ports
P0, P1, P3, P4(Note 1)
P6 to P10
High-impedance
High-impedance
Maintains status when hold signal is received
__________
HLDA
Internal peripheral circuits
ALE signal
Output “L”
ON (but watchdog timer stops)
Undefined
Note 1: When I/O port function is selected.
(8) BCLK Output
If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that
of the CPU clock is output as BCLK from the BCLK pin. Refer to “CPU clock and pheripheral clock”.
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M306H3MC-XXXFP/FCFP
Table 2.4.8. Pin Functions for Each Processor Mode
Processor mode
Memory expansion mode or microprocessor mode
012(CS2 is for multiplexed bus and
others are for separate bus)
102(CS1 is for multiplexed bus and
others are for separate bus)
002(separate bus)
PM05–PM04 bits
Data bus width
16 bits
“L”
8 bits
“H”
BYTE pin
Memory expansion
mode
11 2(multiplexed bus
for the entire space)
(Note 1)
16 bits
“L”
8 bits
“H”
8 bits
“H”
P00 to P07
D0 to D7
D0 to D7
D0 to D7(Note 4) D0 to D7(Note 4)
P10 to P17
I/O ports
D8 to D15
I/O ports
D8 to D15(Note 4) I/O ports
A0
I/O ports
P20
A0
A0
A0/D0(Note 2)
P21 to P27
A1 to A 7
A1 to A 7
A1 to A 7/D1 to D7 A1 to A 7/D0 to D6 A1 to A 7/D1 to D7
(Note 2)
(Note 2)
P30
A8
A8
A8
P31 to P33
A9 to A 11
I/O ports
I/O ports
P34 to P37
P40 to P43
PM11=0
A12 to A 15
PM11=1
I/O ports
PM06=0
A16 to A 19
PM06=1
I/O ports
P44
CS0=0
I/O ports
CS0=1
CS0
P45
CS1=0
I/O ports
CS1=1
CS1
P46
CS2=0
I/O ports
CS2=1
CS2
CS3=0
I/O ports
CS3=1
CS3
PM02=0
WR
P47
P50
PM02=1
P51
PM02=0
A8/D7(Note 2)
A0/D0
A8
I/O ports
(Note 3)
WRL
(Note 3)
WRL
(Note 3)
(Note 3)
WRH
(Note 3)
WRH
(Note 3)
BHE
PM02=1
P52
RD
P53
BCLK
P54
HLDA
P55
P56
HOLD
ALE
P57
RDY
I/O ports: Function as I/O ports or peripheral function I/O pins.
Note 1: To set the PM01 to PM00 bits are set to “012” and the PM05 to PM04 bits are set to “112” (multiplexed bus assigned to the entire CS
space), apply “H” to the BYTE pin (external data bus 8 bits wide). While the CNVSS pin and the M1 pin are held “H” (= VCC) in the flash
memory version (the CNVSS pin is held “H” in the mask ROM version), do not rewrite the PM05 to PM04 bits to “112” after reset.
If the PM05 to PM04 bits are set to “112” during memory expansion mode, P31 to P37 and P40 to P43 become I/O ports, in which case
the accessible area for each CS is 256 bytes.
Note 2: In separate bus mode, these pins serve as the address bus.
Note 3: If the data bus is 8 bits wide, make sure the PM02 bit is set to “0” (RD, BHE, WR).
Note 4: When accessing the area that uses a multiplexed bus, these pins output an indeterminate value during a write.
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M306H3MC-XXXFP/FCFP
(9) External Bus Status When Internal Area Accessed
Table 2.4.9 shows the external bus status when the internal area is accessed.
Table 2.4.9. External Bus Status When Internal Area Accessed
Item
SFR accessed
Internal ROM, RAM accessed
A0 to A19
Address output
Maintain status before accessed
address of external area or SFR
D0 to D15
When read
High-impedance
High-impedance
When write
Output data
Undefined
RD, WR, WRL, WRH
RD, WR, WRL, WRH output
Output “H”
BHE
BHE output
Maintain status before accessed
status of external area or SFR
CS0 to CS3
Output “H”
Output “H”
ALE
Output “L”
Output “L”
(10) Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0”(with wait state). Figure 2.4.11
shows the CSE register. Table 2.4.10 shows the software wait related bits and bus cycles. Figure 2.4.12
and 2.4.13 show the typical bus timings using software wait.
Chip select expansion control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CSE
Bit symbol
CSE00W
CSE01W
CSE10W
CSE11W
CSE20W
CSE21W
CSE30W
CSE31W
Address
001B16
Bit name
After reset
0016
Function
b1 b0
CS0 wait expansion bit
(Note) 0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
RW
RW
RW
b3 b2
CS1 wait expansion bit
(Note) 0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
RW
b5 b4
CS2 wait expansion bit
0 0: 1 wait
(Note) 0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
RW
b7 b6
CS3 wait expansion bit
0 0: 1 wait
(Note)
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
RW
RW
RW
RW
Note: Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (with wait state) before writing to the CSEi1W to
CSEi0W bits. If the CSiW bit needs to be set to “1” (without wait state), set the CSEi1W to CSEi0W bits to “
002” before setting it.
Figure 2.4.11. CSE Register
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Table 2.4.10. Bit and Bus Cycle Related to Software Wait
Area
PM1 register
PM17 bit
Bus mode
CSR register
CS3W bit (Note 1)
CS2W bit (Note 1)
CS1W bit (Note 1)
CS0W bit (Note 1)
CSE register
CSE31W to CSE30W bit
CSE21W to CSE20W bit
CSE11W to CSE10W bit
CSE01W to CSE00W bit
Software wait
SFR
Bus cycle
2 BCLK cycle
Internal
RAM, ROM
0
No wait
1
1 wait
1 BCLK cycle (Note 3)
2 BCLK cycles
1 BCLK cycle (read)
0
1
002
No wait
2 BCLK cycles (write)
Separate bus
External
area
1
Multiplexed
bus (Note 2)
1
0
002
1 wait
2 BCLK cycles (Note 3)
0
012
2 waits
3 BCLK cycles
0
102
3 waits
4 BCLK cycles
1
002
1 wait
2 BCLK cycles
0
002
1 wait
3 BCLK cycles
0
012
2 waits
3 BCLK cycles
0
102
3 waits
4 BCLK cycles
0
002
1 wait
3 BCLK cycles
Note 1: To use the RDY signal, set this bit to “0” (with wait state).
Note 2: To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait state).
Note 3: After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0” (with wait state), and the CSE register is set to
“0016” (one wait state for CS0 to CS3). Therefore, the internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.
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M306H3MC-XXXFP/FCFP
(1) Separate bus, No wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Output
Data bus
Address bus
Address
Input
Address
CS
(2) Separate bus, 1-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Address bus
Output
Input
Address
Address
CS
(3) Separate bus, 2-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Output
Data bus
Address bus
Address
Input
Address
CS
Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 2.4.12. Typical Bus Timings Using Software Wait (1)
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M306H3MC-XXXFP/FCFP
(1) Separate bus, 3-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Input
Output
Address
Address bus
Address
CS
(2)Multiplexed bus, 1- or 2-wait setting
Bus cycle (Note)
Bus cycle (Note)
Address
Address
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus
Address
Data output
Address
Input
CS
(3)Multiplexed bus, 3-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus
Address
Address
Address
Data output
Address
Input
CS
Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 2.4.13. Typical Bus Timings Using Software Wait (2)
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M306H3MC-XXXFP/FCFP
2.5 Clock Generation Circuit
The clock generation circuit contains two oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
Table 2.5.1 lists the clock generation circuit specifications. Figure 2.5.1 shows the clock generation circuit. Figures 2.5.2 to 2.5.4 show the clock-related registers.
Table 2.5.1. Clock Generation Circuit Specifications
Main clock
oscillation circuit
Use of clock
Sub clock
oscillation circuit
• CPU clock source •CPU clock source
• Peripheral function • Timer A, B's clock
source
clock source
Clock frequency
0 to 10 MHz
32.768 kHz
Usable oscillator
• Ceramic oscillator
• Crystal oscillator
(Note 2)
• Crystal oscillator
Pins to connect
oscillator
XIN, XOUT
XCIN, XCOUT
Oscillation stop,
restart function
Presence
Presence
Item
Oscillator status Oscillating
after reset (Note)
Stopped
Externally derived clock can be input
Other
Note 1. The state that the START pin is held "H" after reset is shown.
The state that the START pin is held "L" after reset is following.
Main clock oscillation circuit: Stoped
Sub clock oscillation circuit: Oscillating
Note 2. If you use "2.14 Expansion Function (Data acquisition)", be sure to connect a crystal oscillator
between the XIN and XOUT pins.
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M306H3MC-XXXFP/FCFP
CM01–CM00=002
Sub-clock
generating circuit
XCIN
I/O ports
PM01–PM00=002, CM01–CM00=012
CLKOUT
PM01–PM00=002,
CM01–CM00=11 2
PM01–PM00=002, CM01–CM00=102
XCOUT
fC32
1/32
CM04
f1
PCLK0=1
Sub-clock
f2
PCLK0=0
fC
f8
START
f32
S Q
fAD
R
f1SIO
PCLK1=1
CM07
f2SIO
Main clock
CM06
CM10=1(stop mode)
PCLK1=0
f8SIO
S Q
XIN
XOUT
f32SIO
e b c
R
a
CM05
CM07=0
d
Divider
CPU clock
fC
Main clock
generating circuit
BCLK
CM07=1
CM02
S
WAIT instruction
Q
R
e
a
RESET
c
b
1/2
1/2
1/2
1/32
1/2
1/4
1/8
Software reset
CM06=1
CM06=0
CM17–CM16=102
Interrupt request level judgment output
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d
CM06=0
CM17–CM16=012
CM06=0
CM17–CM16=002
Figure 2.5.1. Clock Generation Circuit
1/16
CM06=0
CM17–CM16=11 2
NMI
CM02, CM04, CM05, CM06, CM07: CM0 register bits
CM10, CM11, CM16, CM17: CM1 register bits
PCLK0, PCLK1: PCLK register bits
1/2
1/2
Details of divider
M306H3MC-XXXFP/FCFP
System clock control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Bit symbol
Address
000616
After reset (Note 14)
010010002 (START pin = Vcc)
01111000 2 (START pin = Vss)
Bit name
Function
RW
b1 b0
Clock output function
select bit
(Valid only in single-chip
mode)
0 0 : I/O port P57
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
CM02
WAIT peripheral function
clock stop bit (Note 10)
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8) RW
CM03
XCIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
0 : I/O port P86, P87
Port XC select bit
1 : XCIN-XCOUT generation function(Note 9)
(Note 2)
Main clock stop bit
0 : On
1 : Off (Note 4, Note5)
(Notes 3, 10, 12, 13)
CM00
CM01
CM04
CM05
RW
RW
RW
RW
RW
CM06
Main clock division select
bit 0 (Notes 7, 13)
0 : CM16 and CM17 valid
1 : Division by 8 mode
RW
CM07
System clock select bit
(Notes 6, 10, 11, 12)
0 : Main clock
1 : Sub-clock
RW
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: The CM03 bit is set to “1” (high) when the CM04 bit is set to “0” (I/O port) or the microcomputer goes to a stop mode.
Note 3: This bit is provided to stop the main clock when the low power dissipation mode is selected. This bit cannot be used for
detection as to whether the main clock stopped or not. To stop the main clock, the following setting is required:
(1) Set the CM07 bit to “1” (Sub-clock select) with the sub-clock stably oscillating.
(2) Set the CM05 bit to “1” (Stop).
Note 4: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted if the sub clock is not
chosen as a CPU clock.
Note 5: When CM05 bit is set to “1, the XOUT pin goes “H”. Furthermore, because the internal feedback resistor remains connected,
the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.
Note 6: After setting the CM04 bit to “1” (X CIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from “0” to “1” (sub-clock).
Note 7: When entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divide-by-8 mode).
Note 8: The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to “1” (peripheral clock
turned off when in wait mode).
Note 9: To use a sub-clock, set this bit to “1”. Also make sure ports P8 6 and P87 are directed for input, with no pull-ups.
Note 10: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM02, CM05, and CM07 bits has
no effect.
Note 11: If the PM21 bit needs to be set to “1”, set the CM07 bit to “0”(main clock) before setting it.
Note 12: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to “0” (oscillate).
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM07 bit all to “0”.
Note 13: When the CM05 bit is set to “1” (main clock turned off), the CM06 bit is fixed to “1” (divide-by-8 mode) and the
CM15 bit is fixed to “1” (drive capability high).
Note 14: Keep in mind that the values after reset differ by the input voltage at the START pin.
Figure 2.5.2. CM0 Register
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M306H3MC-XXXFP/FCFP
System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
0 0
0
0
b0
Symbol
CM1
Bit symbol
Address
000716
Bit
name
All clock stop control bit
After reset
001000002
Function
RW
(Notes 4, 5)
0 : Clock on
1 : All clocks off (stop mode)
RW
(b4-b1)
Reserved bit
Must set to “0”
RW
CM15
XIN-XOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
RW
CM16
Main clock division
select bit 1 (Note 3)
CM10
b7 b6
CM17
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
RW
RW
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).
Note 3: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
Note 4: If the CM10 bit is “1” (stop mode), X OUT goes “H” and the internal feedback resistor is disconnected. The X CIN and XCOUT
pins are placed in the high-impedance state.
Note 5: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM10 bits has no effect.
Figure 2.5.3. CM1 Register
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M306H3MC-XXXFP/FCFP
Peripheral clock select register (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0
Symbol
PCLKR
Address
025E16
When reset
000000112
Bit symbol
Bit name
PCLK0
Timers A, B clock select bit
(Clock source for the
timers A and B
0 : f2
1 : f1
RW
SI/O clock select bit
(Clock source for UART0
to UART2, SI/O3, SI/O4)
0 : f 2SIO
1 : f 1SIO
RW
Reserved bit
Must set to “0”
PCLK1
(b7-b2)
Function
RW
RW
Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Processor mode register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
0
Symbol
PM2
Bit symbol
(b0)
PM21
(b4-b2)
(b7-b5)
Address
001E16
Bit name
Reserved bit
System clock protective
bit
(Note 2, Note 3)
Reserved bit
After reset
XXX000002
Function
Must set to “0”
0 : Clock is protected by PRCR
register
1 : Clock modification disabled
Must set to “0”
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: Once this bit is set to “1”, it cannot be cleared to “0” in a program.
Note 3: If the PM21 bit is set to “1,” writing to the following bits has no effect.
CM02 bit of CM0 register
CM05 bit of CM0 register (main clock is not halted)
CM07 bit of CM0 register (CPU clock source does not change)
CM10 bit of CM1 register (stop mode is not entered)
Figure 2.5.4. PCLKR Register and PM2 Register
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RW
RW
RW
RW
M306H3MC-XXXFP/FCFP
2.5.1 Oscillator Circuit
The following describes the clocks generated by the clock generation circuit.
Two oscillation circuits are built in the clock generating circuit, and a main clock or a sub clock can be
chosen as a CPU clock by setup of the START pin after reset.
(1) Main Clock
This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop
mode in order to reduce the amount of power consumed in the chip. The main clock oscillator circuit may
also be configured by feeding an externally generated clock to the XIN pin. Figure 2.5.5 shows the examples of main clock connection circuit.
When the level on the START pin is “H”, the main clock divided by 8 is selected for the CPU clock (Sub
clock turned off) after reset.
The power consumption in the chip can be reduced by setting the CM05 bit of CM0 register to “1” (main
clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock. In this
case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains on, XIN is pulled “H” to
XOUT via the feedback resistor. Note that if an externally generated clock is fed into the XIN pin, the main
clock cannot be turned off by setting the CM05 bit to “1” without selecting sub clock fot the CPU clock. If
necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to “power control”.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XIN
XOUT
XOUT
Open
(Note)
Rd
Externally derived clock
CIN
COUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 2.5.5. Examples of Main Clock Connection Circuit
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M306H3MC-XXXFP/FCFP
(2) Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same
frequency as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and
XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the
oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub
clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 2.5.6 shows the examples of sub clock connection circuit.
When the level on the START pin is “H ”, the sub clock is turned off after reset. At this time, the feedback
resistor is disconnected from the oscillator circuit.
To use the sub clock for the CPU clock, set the CM07 bit of CM0 register to “1 ” (sub clock) after the sub
clock becomes oscillating stably.
When a START pin is “L ”, the sub clock (XCIN) divided by 8 becomes the CPU clock after reset (the main
clock stops). When you use a main clock after this, please shift according to the procedure shown in Fig.
2.5.7.
During stop mode, all clocks including the sub clock are turned off. Refer to “power control”.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 2.5.6. Examples of Sub Clock Connection Circuit
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M306H3MC-XXXFP/FCFP
Using the main clock from the sub clock as CPU clock
source.
Set the CM07 bit to “1” (sub clock).
Set the CM05 bit to “0” (oscillating).
Waits until the main clock becomes sable.
Set the CM07 bit to “0” (main clock). (note1)
Set the main clock division ratio.
Set the CM17 to the CM16 bits to “002,” set the CM06 bit to
“0.” (CM16 bit and CM17 bit are effective) (notes 2.)
END
Note 1: Change After the oscillation of the main clock becomes stable enough.
Note 2: Setting No division of the main clock is shown.
Change CM06 after changing CM17 and CM16.
Figure 2.5.7. Procedure to Use the Main Clock from the Sub Clock as CPU Clock Source
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M306H3MC-XXXFP/FCFP
2.5.2 CPU Clock and Peripheral Function Clock
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral
functions.
(1) CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock or sub clock.
If the main clock is selected as the clock source for the CPU clock, the selected clock source can be
divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in CM0 register and the
CM17 to CM16 bits in CM1 register to select the divide-by-n value.
When the level on the START pin is “H”, the main clock divided by 8 provides the CPU clock after reset.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU
clock can be output from the BCLK pin by setting the PM07 bit of PM0 register to “0” (output enabled).
Note that when entering stop mode from high or middle speed mode, or when the CM05 bit of CM0
register is set to “1” (main clock turned off) in low-speed mode, the CM06 bit of CM0 register is set to “1”
(divide-by-8 mode).
(2) Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock by dividing them by i. The clock fi is
used for timers A and B, and fiSIO is used for serial I/O. The f8 and f32 clocks can be output from the
CLKOUT pin.
The fAD clock is produced from the main clock, and is used for the A-D converter.
When the WAIT instruction is executed after setting the CM02 bit of CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used
when the sub clock is on.
Clock Output Function
During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to
CM00 bits of CM0 register to select.
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M306H3MC-XXXFP/FCFP
2.5.3 Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes
are referred to as normal operation mode here.
(1) Normal Operation Mode
Normal operation mode is further classified into four modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock or sub clock, allow a sufficient wait
time in a program until it becomes oscillating stably.
• High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
• Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used
as the count source for timers A and B.
• Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock.
The fC32 clock can be used as the count source for timers A and B.
• Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides
the CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit of CM0 register becomes “1” (divided by 8
mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divided by 8) mode is to be selected when the main clock is operated next.
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M306H3MC-XXXFP/FCFP
(2) Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. Because the main clock and sub clock, are on, the peripheral functions using these
clocks keep operating.
• Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,
f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced
that much. However, fC32 remains on.
• Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
• Pin Status During Wait Mode
Table 2.5.2 lists pin status during wait mode
• Exiting Wait Mode
______
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral function interrupt.
______
If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before executing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait
mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions clocked
by external signals can be used to exit wait mode.
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M306H3MC-XXXFP/FCFP
Table 2.5.2. Pin Status During Wait Mode
Pin
Memory expansion mode
Microprocessor mode
_______
Single-chip mode
_______
A0 to A19, D0 to D15, CS0 to CS3,
Retains status before wait mode
________
BHE
_____
______
________ _________
RD, WR, WRL, WRH
“H”
__________
HLDA,BCLK
ALE
I/O ports
CLKOUT
“H”
“H”
Retains status before wait mode
When fC selected
When f8, f32 selected
Retains status before wait mode
Does not stop
Does not stop when the CM02
bit is “0”.
When the CM02 bit is “1”, the
status immediately prior to
entering wait mode is maintained.
Table 2.5.3. Interrupts to Exit Wait Mode
Interrupt
NMI interrupt
Serial I/O interrupt
CM02=0
Can be used
Can be used when operating
with internal or external clock
CM02=1
Can be used
Can be used when operating
with external clock
key input interrupt
A-D conversion
interrupt
Can be used
Can be used in one-shot mode
or single sweep mode
Can be used
(Do not use)
Timer A interrupt
Timer B interrupt
Can be used in all modes
Can be used in event counter
mode or when the count
source is fC32
INT interrupt
Can be used
Can be used
Table 2.5.3 lists the interrupts to exit wait mode.
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph
eral function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt routine is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.
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M306H3MC-XXXFP/FCFP
(3) Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to Vcc pins is VRAM or more, the internal
RAM is retained.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
______
• NMI interrupt
• Key interrupt
______
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is seleted)
The internal oscillator circuit of expansion function (Data acquisition / humming function) stops oscillation
when expansion register XTAL_VCO, PDC_VCO_ON, VPS_VCO_ON = "L".
• Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit of CM10 register is set to “1” (main clock oscillator circuit drive capability high).
• Pin Status in Stop Mode
Table 2.5.4 lists pin status during stop mode
• Exiting Stop Mode
______
The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral function interrupt.
______
If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the
CM10 bit to “1”.
If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the
following before setting the CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt service routine is executed.
______
Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is
determined by the CPU clock that was on when the microcomputer was placed into stop mode as
follows:
If the CPU clock before entering stop mode was derived from the sub clock: sub clock
If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8
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M306H3MC-XXXFP/FCFP
Table 2.5.4. Pin Status in Stop Mode
Pin
_______
Memory expansion mode
Microprocessor mode
Single-chip mode
_______
A0 to A19, D0 to D15, CS0 to CS3,
Retains status before stop mode
________
BHE
_____
______
________ _________
RD, WR, WRL, WRH
“H”
__________
HLDA, BCLK
ALE
I/O ports
CLKOUT
When fc selected
When f8, f32 selected
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“H”
“H”
Retains status before stop mode Retains status before stop mode
“H”
Retains status before stop mode
M306H3MC-XXXFP/FCFP
Figure 2.5.8 shows the state transition from normal operation mode to stop mode and wait mode. Figure
2.5.9 shows the state transition in normal operation mode.
Reset
All oscillators stopped
WAIT
instruction
CM10=1
Stop mode
Interrupt
Medium-speed mode
(divided-by-8 mode)
Wait mode
Interrupt
Interrupt
CM07=0
CM06=1
CM05=0
CM10=1
(Note 2)
WAIT
instruction
High-speed, mediumspeed mode
Stop mode
CM10=1
When
low power When
dissipation lowmode
speed
mode
Interrupt
Wait mode
Interrupt
Notes 1, 2
PLL operation
mode
CM10=1
Stop mode
Low-speed, low power
dissipation mode
WAIT
instruction
Interrupt
Normal mode
Note 1: When the PM21 bit = 0 (system clock protective function unused).
Note 2: Write to the CM0 register and CM1 register simultaneously by accessing in word units.
Figure 2.5.8. State Transition to Stop Mode and Wait Mode
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CPU operation stopped
Wait mode
M306H3MC-XXXFP/FCFP
Main clock oscillation
High-speed mode
CPU clock: f(XIN)
Middle-speed mode
(divide by 2)
CPU clock: f(XIN)/2
Middle-speed mode
(divide by 4)
CPU clock: f(XIN)/4
CM07=0
CM07=0
CM07=0
CM06=0
CM06=0
CM06=0
CM17=0
CM17=0
CM17=1
CM16=0
CM16=1
CM16=0
Middle-speed mode Middle-speed mode
(divide by 8)
(divide by 16)
CPU clock: f(XIN)/8
CPU clock: f(XIN)
Middle-speed mode
(divide by 2)
CM16=1
CPU clock: f(XIN)/2
Middle-speed mode Middle-speed mode
(divide by 8)
(divide by 16)
CPU clock: f(XIN)/4
CPU clock: f(XIN)/8
CM07=0
CM07=0
CM07=0
CM06=0
CM06=0
CM06=0
CM17=0
CM17=0
CM17=1
CM16=0
CM16=1
CM16=0
CPU clock: f(XIN)/16
CM07=0
CM06=1
CM07=0
(Note 1, Note 3)
Low-speed mode
CM07=0
CM05=1
CM05=0
Low power dissipation mode
CPU clock: f(XCIN)
CM07=0
CM06=1
CM15=1
Sub clock oscillation
Notes:
1: Switch clock after oscillation of main clock is sufficiently stable.
2: Switch clock after oscillation of sub-clock is sufficiently stable.
3: Change CM17 and CM16 before changing CM06.
4: Transit in accordance with arrow.
Figure 2.5.9. State Transition in Normal Mode
page 54 of 320
CM17=1
Middle-speed mode
(divide by 4)
CPU clock: f(XCIN)
2004.03.23
CM06=0
CM04=0
CM07=1
(Note 2)
Rev.1.00
CM07=0
CM06=1
CM04=1
High-speed mode
CPU clock: f(XIN)/16
CM07=0
CM07=0
CM06=0
CM17=1
CM16=1
M306H3MC-XXXFP/FCFP
2.5.4 System Clock Protective Function
When the main clock is selected for the CPU clock source, this function disables the clock against modifications in order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit of PM2 register is set to “1” (clock modification disabled), the following bits are protected
against writes:
• CM02, CM05, and CM07 bits in CM0 register
• CM10, CM11 bits in CM1 register
Before the system clock protective function can be used, the following register settings must be made
while the CM05 bit of CM0 register is “0” (main clock oscillating) and CM07 bit is “0” (main clock selected
for the CPU clock source):
(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM2 register).
(2) Set the PM21 bit of PM2 register to “1” (disable clock modification).
(3) Set the PRC1 bit of PRCR register to “0” (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is “1”.
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M306H3MC-XXXFP/FCFP
2.6 Protection
In the event that a program runs out of control, this function protects the important registers so that they
will not be rewritten easily. Figure 2.6.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1 and PCLKR registers
• Registers protected by PRC1 bit: PM0, PM1 and PM2 registers
• Registers protected by PRC2 bit: PD9, S3C and S4C registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to
“0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction
after setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to “1” and the next instruction. The PRC0 and PRC1 bits are not automatically cleared to “0” by writing to any address. They can only be cleared in a program.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol9
PRCR9
Address9
000A 169
Bit symbol
Bit name
0 0 0
PRC0
Protect bit 0
After reset9
XX000000 29
Function
Enable write to CM0, CM1 and
PCLKR registers
0 : Write protected
1 : Write enabled
PRC1
Protect bit 1
Protect bit 2
Enable write to PD9, S3C and
S4C registers
0 : Write protected
1 : Write enabled
(b5-b3)
(b7-b6)
Reserved bit
RW
Enable write to PM0, PM1 and
PM2 registers
0 : Write protected
1 : Write enabled
PRC2
RW
Must set to “0”
RW
RW
RW
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
Note: The PRC2 bit is set to “0” by writing to any address after setting it to “1”. Other bits are not set to “0”
by writing to any address, and must therefore be set in a program.
Figure 2.6.1. PRCR Register
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M306H3MC-XXXFP/FCFP
2.7 Interrupts
2.7.1 Type of Interrupts
Figure 2.7.1 shows types of interrupts.












Hardware
Special
(Non-maskable interrupt)














Interrupt
Software
(Non-maskable interrupt)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
_______
NMI
DBC (Note 2)
Watchdog timer
Single step (Note 2)
Address match
________
Peripheral function (Note 1)
(Maskable interrupt)
Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions.
Note 2: Do not normally use this interrupt because it is provided exclusively for use by development
support tools.
Figure 2.7.1. Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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M306H3MC-XXXFP/FCFP
2.7.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63
can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be
executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not
change state during instruction execution, and the SP then selected is used.
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M306H3MC-XXXFP/FCFP
2.7.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
(1) Special Interrupts
Special interrupts are non-maskable interrupts.
_______
• NMI Interrupt
_______
_______
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details
_______
about the NMI interrupt, refer to the section "NMI interrupt".
________
• DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer".
• Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 to RMAD3 register that corresponds to one of the AIER register’s AIER0 or
AIER1 bit or the AIER2 register’s AIER20 or AIER21 bit which is "1" (address match interrupt enabled). For details about the address match interrupt, refer to the section "address match interrupt".
(2) Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in Table 2.7.2. For details
about the peripheral functions, refer to the description of each peripheral function in this manual.
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M306H3MC-XXXFP/FCFP
2.7.4 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 2.7.2 shows the interrupt vector.
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
MSB
Vector address (L)
LSB
Low address
Mid address
Vector address (H)
0000
High address
0000
0000
Figure 2.7.2. Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 2.7.1 lists the
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to the section "flash memory rewrite
disabling function".
Table 2.7.1. Fixed Vector Tables
Interrupt source
Vector table addresses
Remarks
Reference
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16
Interrupt on UND instruction
M16C/60, M16C/20
Overflow
FFFE016 to FFFE316
Interrupt on INTO instruction
series software
If the contents of address maual
BRK instruction
FFFE416 to FFFE716
FFFE716 is FF16, program execution starts from the address
shown by the vector in the
relocatable vector table.
Address match
FFFE816 to FFFEB16
Address match interrupt
Single step (Note)
FFFEC16 to FFFEF16
Watchdog timer
FFFF016 to FFFF316
Watchdog timer
________
DBC (Note)
FFFF416 to FFFF716
_______
_______
NMI
FFFF816 to FFFFB16
NMI interrupt
Reset
FFFFC16 to FFFFF16
Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development support tools.
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M306H3MC-XXXFP/FCFP
• Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector
table area. Table 2.7.2 lists the relocatable vector tables. Setting an even address in the INTB register
results in the interrupt sequence being executed faster than in the case of odd addresses.
Table 2.7.2. Relocatable Vector Tables
Interrupt source
BRK instruction (Note 5)
Vector address (Note 1)
Address (L) to address (H)
+0 to +3 (000016 to 000316)
Software interrupt
number
0
1 to 3
(Reserved)
Reference
M16C/60, M16C/20
series software
manual
INT3
+16 to +19 (001016 to 001316)
4
INT interrupt
Timer B5/SLICE ON (Note 7)
+20 to +23 (001416 to 001716)
5
Timer
Timer B4/Remote control, UART1 bus
collision detect (Note 4/Note 6/Note 7)
+24 to +27 (001816 to 001B16)
6
Timer B3/HINT, UART0 bus collision
detect (Note 4/Note 6/Note 7)
+28 to +31 (001C16 to 001F16)
7
Timer
Serial I/O
SI/O4, INT5
(Note 2)
+32 to +35 (002016 to 002316)
8
SI/O3, INT4
(Note 2)
+36 to +39 (002416 to 002716)
9
INT interrupt
Serial I/O
Serial I/O
UART 2 bus collision detection
+40 to +43 (002816 to 002B16)
10
DMA0
+44 to +47 (002C16 to 002F16)
11
DMA1
+48 to +51 (003016 to 003316)
12
Key input interrupt
+52 to +55 (003416 to 003716)
13
Key input interrupt
A-D
+56 to +59 (003816 to 003B16)
14
A-D convertor
UART2 transmit, NACK2 (Note 3)
+60 to +63 (003C16 to 003F16)
15
UART2 receive, ACK2 (Note 3)
+64 to +67 (004016 to 004316)
16
UART0 transmit, NACK0 (Note 3)
+68 to +71 (004416 to 004716)
17
UART0 receive, ACK0 (Note 3)
+72 to +75 (004816 to 004B16)
18
UART1 transmit, NACK1(Note 3)
+76 to +79 (004C16 to 004F16)
19
UART1 receive, ACK1 (Note 3)
+80 to +83 (005016 to 005316)
20
Timer A0
+84 to +87 (005416 to 005716)
21
Timer A1
+88 to +91 (005816 to 005B16)
22
Timer A2
+92 to +95 (005C16 to 005F16)
23
Timer A3
+96 to +99 (006016 to 006316)
24
Timer A4
+100 to +103 (006416 to 006716)
25
Timer B0
+104 to +107 (006816 to 006B16)
26
Timer B1
+108 to +111 (006C16 to 006F16)
27
Timer B2
+112 to +115 (007016 to 007316)
28
INT0
+116 to +119 (007416 to 007716)
29
INT1
+120 to +123 (007816 to 007B16)
30
INT2
+124 to +127 (007C16 to 007F16)
31
+128 to +131 (008016 to 008316)
32
to
63
Software interrupt (Note 5)
to
+252 to +255 (00FC16 to 00FF16)
DMAC
Serial I/O
Timer
INT interrupt
M16C/60, M16C/20
series software
manual
Note 1: Address relative to address in INTB.
Note 2: Use the IFSR register's IFSR6 and IFSR7 bits to select.
Note 3: During I2C mode, NACK and ACK interrupts comprise the interrupt source.
Note 4: Use the IFSR2A register’s IFSR26 and IFSR27 bits to select.
Note 5: These interrupts cannot be disabled using the I flag.
Note 6: Bus collision detection : During IE mode, this bus collision detection constitutes the cause of an interrupt.
During I2C mode, however, a start condition or a stop condition detection
constitutes the cause of an interrupt.
Note 7: When use SLICEON, remote control, and HINT interruption, refer to address 3616 expansion
register of “2.14 Expansion Function.”
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M306H3MC-XXXFP/FCFP
2.7.5 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in
which order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each
interrupt control register.
Figure 2.7.3 shows the interrupt control registers.
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M306H3MC-XXXFP/FCFP
Interrupt control register (Note 2)
AAA
A
AA
AAA
AA
A
b7
b6
b5
b4
b3
b2
b1
Symbol
TB5IC
TB4IC/U1BCNIC (Note 3)
TB3IC/U0BCNIC (Note 3)
BCNIC
DM0IC, DM1IC
KUPIC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
b0
Bit symbol
ILVL0
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
(b7-b4)
Address
004516
004616
004716
004A16
004B16, 004C16
004D16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
Interrupt request bit
After reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Function
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
RW
RW
RW
RW
RW
(Note 1)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
Note 1: This bit can only be reset by writing "0" (Do not write "1").
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the precautions for interrupts.
Note 3: Use the IFSR2A register to select.
AA
b7
b6
b5
b4
b3
b2
b1
Symbol
INT3IC (Note 4)
S4IC/INT5IC
S3IC/INT4IC
INT0IC to INT2IC
b0
0
Bit symbol
ILVL0
Address
004416
004816
004916
005D16 to 005F16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
Function
RW
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
RW
b2 b1 b0
RW
RW
Interrupt request bit
0: Interrupt not requested
1: Interrupt requested
Polarity select bit
0 : Selects falling edge (Notes 3, 5)
1 : Selects rising edge
RW
Must always be set to “0”
RW
Reserved bit
(b7-b6)
After reset
XX00X0002
XX00X0002
XX00X0002
XX00X0002
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
RW
(Note 1)
RW
Note 1: This bit can only be reset by writing "0" (Do not write "1").
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, see the precautions for interrupts.
Note 3: If the IFSR register’s IFSRi bit (i = 0 to 5) is "1" (both edges), set the INTiIC register’s POL bit to "0 "(falling
edge).
Note 4: During memory expansion and microprocessor modes, set the INT3IC register’s ILVL2 to ILVL0 bits to ‘0002’
(interrupt disabled).
Note 5: Set the S3IC or S4IC register’s POL bit to "0" (falling edge) when the IFSR register’s IFSR6 bit = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
Figure 2.7.3. Interrupt Control Registers
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M306H3MC-XXXFP/FCFP
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the
maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 2.7.3 shows the settings of interrupt priority levels and Table 2.7.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = “1”
· IR bit = “1”
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 2.7.3. Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 bits
Interrupt priority
level
0002
Level 0 (interrupt disabled)
0012
Level 1
0102
Rev.1.00
Priority
order
Table 2.7.4. Interrupt Priority Levels
Enabled by IPL
IPL
Enabled interrupt priority levels
0002
Interrupt levels 1 and above are enabled
0012
Interrupt levels 2 and above are enabled
Level 2
0102
Interrupt levels 3 and above are enabled
0112
Level 3
0112
Interrupt levels 4 and above are enabled
1002
Level 4
1002
Interrupt levels 5 and above are enabled
1012
Level 5
1012
Interrupt levels 6 and above are enabled
1102
Level 6
1102
Interrupt levels 7 and above are enabled
1112
Level 7
1112
All maskable interrupts are disabled
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Low
High
M306H3MC-XXXFP/FCFP
2.7.6 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 2.7.4 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the
address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not requested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
temporary register(Note 1).
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The CPU’s internal temporary register (Note 1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note: This register cannot be used by user.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock
Address
000016
Address bus
Interrupt
information
Data bus
RD
WR
Indeterminate (Note 1)
Indeterminate (Note 1)
SP-2
SP-2
contents
SP-4
SP-4
contents
vec
vec
contents
vec+2
PC
vec+2
contents
Indeterminate (Note 1)
(Note 2)
Note 1 : The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
Note 2 : The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Figure 2.7.4. Time Required for Executing Interrupt Sequence
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M306H3MC-XXXFP/FCFP
Interrupt Response Time
Figure 2.7.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) in Figure 2.7.5) and a time during which the interrupt
sequence is executed ((b) in Figure 2.7.5).
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
Interrupt sequence
(a)
Instruction in
interrupt routine
(b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address SP value 16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
18 cycles
20 cycles
Even
Odd
19 cycles
20 cycles
Odd
Even
19 cycles
20 cycles
Odd
Odd
20 cycles
20 cycles
Figure 2.7.5. Interrupt response time
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 2.7.5 is set in the IPL. Shown in Table 2.7.5 are the IPL values of software and special interrupts
when they are accepted.
Table 2.7.5. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Level that is set to IPL
_______
Watchdog timer, NMI
_________
Software, address match, DBC, single-step
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7
Not changed
M306H3MC-XXXFP/FCFP
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
2.7.6 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Stack
Address
MSB
LSB
m–4
Address
MSB
Stack
m–4
PC
LSB
[SP]
New SP value
L
m–3
m–3
PC
M
m–2
FLGL
m–2
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
SPvalue before
interrupt occurs
FLGH
PCH
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 2.7.6. Stack StatusBefore and After Acceptance of Interrupt Request
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M306H3MC-XXXFP/FCFP
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
SP(Note), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is
even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits
at a time. Figure 2.7.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
Sequence in which order
registers are saved
Stack
[SP] – 5 (Odd)
[SP] – 4 (Even)
PCL
[SP] – 3(Odd)
PCM
[SP] – 2 (Even)
FLGL
[SP] – 1(Odd)
[SP]
FLGH
(2) Saved simultaneously,
all 16 bits
PCH
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
PCL
(3)
[SP] – 3 (Even)
PCM
(4)
[SP] – 2(Odd)
FLGL
(1)
Saved, 8 bits at a time
[SP] – 1 (Even)
[SP]
FLGH
PCH
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 2.7.7. Operation of Saving Register
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M306H3MC-XXXFP/FCFP
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 2.7.8
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
High
NMI
DBC
Watchdog timer
Peripheral function
Single step
Address match
Low
Figure 2.7.8. Hardware Interrupt Priority
Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 2.7.9 shows the circuit that judges the interrupt priority level.
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M306H3MC-XXXFP/FCFP
Priority level of each interrupt
Level 0 (initial value)
INT1
Timer B2
High
Timer B0
Timer A3
Timer A1
Timer B4/Remote control,
UART1 bus collision
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer B3/HINT, UART0 bus collision
Timer B5/SLICEON
UART1 reception, ACK1
UART0 reception, ACK0
Priority of peripheral fucntion interrupts
(if priority levels are same)
UART2 reception, ACK2
A-D conversion
DMA1
UART 2 bus collision
SI/O4, INT5
Timer A0
UART1 transmission, NACK1
UART0 transmissionm, NACK0
UART2 transmission, NACK2
Key input interrupt
DMA0
Low
SI/O3, INT4
IPL
I flag
Address match
Watchdog timer
DBC
NMI
Figure 2.7.9. Interrupts Priority Select Circuit
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Interrupt request level resolution output
to clock generating circuit (Fig.2.5.1)
Interrupt
request
accepted
M306H3MC-XXXFP/FCFP
______
2.7.7 INT Interrupt
_______
INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR register's IFSRi bit.
_______
_______
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
_______
_______
_______
To use the INT4 interrupt, set the IFSR register’s IFSR6 bit to “1” (= INT4). To use the INT5 interrupt, set
_______
the IFSR register’s IFSR7 bit to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested)
before enabling the interrupt.
Figure 2.7.10 shows the IFSR and IFSR2A registers.
AA
A
AA
AA
AA
AAA
AA
Interrupt request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR
Address
035F16
After reset
0016
Bit name
Bit symbol
IFSR0
Function
RW
INT0 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
IFSR2
INT2 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
IFSR3
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
IFSR4
INT4 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
IFSR5
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
IFSR6
Interrupt request cause
select bit
(Note 2)
0 : SI/O3
1 : INT4
(Note 3)
IFSR7
Interrupt request cause
select bit
(Note 2)
0 : SI/O4
1 : INT5
(Note 3)
IFSR1
RW
RW
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT5IC register’s POL bit
is set to “0” (= falling edge).
Note 2: During memory expansion and microprocessor modes, set this bit to “0” (= SI/O3, SI/O4)
Note 3: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
Interrupt request cause select register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR2A
Bit symbol
(b5-b0)
IFSR26
IFSR27
Address
035E16
Bit name
After reset
00XXXXXX2
Function
RW
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
Interrupt request cause
select bit (Note 1)
0 : Timer B3/HINT
1 : UART0 bus collision
detection
RW
Interrupt request cause
select bit (Note 2)
0 : Timer B4/Remote control
1 : UART1 bus collision
detection
RW
Note 1: Timer B3/HINT and UART0 bus collision detection share the vector and interrupt control register. When using
the timer B3/HINT interrupt, clear the IFSR26 bit to “0” (timer B3/HINT). When using UART0 bus collision
detection, set the IFSR26 bit to “1”.
Note 2: Timer B4/Remote control and UART1 bus collision detection share the vector and interrupt control register.
When using the timer B4/Remote control interrupt, clear the IFSR27 bit to “0” (timer B4/Remote control).
When using UART1 bus collision detection, set the IFSR27 bit to “1”.
Figure 2.7.10. IFSR Register and IFSR2A Register
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M306H3MC-XXXFP/FCFP
______
2.7.8 NMI Interrupt
_______
_______
______
An NMI interrupt is generated when input on the NMI pin changes state from high to low. The NMI
interrupt is a non-maskable interrupt.
_______
The input level of this NMI interrupt input pin can be read by accessing the P8 register’s P8_5 bit.
This pin cannot be used as an input port.
2.7.9 Key Input Interrupt
Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has
had the PD10 register’s PD10_4 to PD10_7 bits set to “0” (= input) goes low. Key input interrupts can be
used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode.
However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports.
Figure 2.7.11 shows the block diagram of the key input interrupt. Note, however, that while input on any
pin which has had the PD10_4 to PD10_7 bits set to “0” (= input mode) is pulled low, inputs on all other
pins of the port are not detected as interrupts.
PUR2 register's PU25 bit
Pull-up
transistor
KUPIC register
PD10 register's
PD10_7 bit
PD10 register's PD10_7 bit
KI3
Pull-up
transistor
PD10 register's
PD10_6 bit
Interrupt control circuit
KI2
Pull-up
transistor
PD10 register's
PD10_5 bit
KI1
Pull-up
transistor
PD10 register's
PD10_4 bit
KI0
Figure 2.7.11. Key Input Interrupt
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Key input interrupt
request
M306H3MC-XXXFP/FCFP
2.7.10 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits
to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
For address match interrupts, the value of the PC that is saved to the stack area varies depending on the
instruction being executed (refer to “Saving Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 2.7.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Note that when using the external bus in 8 bits width, no address match interrupts can be used for external
areas.
Figure 2.7.13 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 2.7.6. Instruction Just Before Execution and Address Stored in Stack When There Occurs
Interrupts
Value of the PC that is
saved to the stack area
Instruction at the address indicated by the RMADi register
• 16-bit op-code instruction
• Instruction shown below among 8-bit operation code instructions
ADD.B:S
#IMM8,dest
SUB.B:S
#IMM8,dest
AND.B:S #IMM8,dest
OR.B:S
#IMM8,dest
MOV.B:S
#IMM8,dest
STZ.B:S
#IMM8,dest
STNZ.B:S #IMM8,dest
STZX.B:S #IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest
PUSHM
src
POPM dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (However, dest=A0 or A1)
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
Instructions other than the above
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Table 2.7.7. Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources
Address match interrupt 0
Address match interrupt 1
Address match interrupt 2
Address match interrupt 3
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Address match interrupt enable bit
AIER0
AIER1
AIER20
AIER21
Address match interrupt register
RMAD0
RMAD1
RMAD2
RMAD3
M306H3MC-XXXFP/FCFP
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Address
000916
After reset
XXXXXX002
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Bit symbol
Function
RW
AIER0
Address match interrupt 0
enable bit
Bit name
0 : Interrupt disabled
1 : Interrupt enabled
RW
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
(b7-b2)
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Address match interrupt enable register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER2
Address
01BB16
After reset
XXXXXX002
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Bit symbol
Bit name
Function
RW
AIER20
Address match interrupt 2
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
AIER21
Address match interrupt 3
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
(b7-b2)
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Address match interrupt register i (i = 0 to 3)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
Address
001216 to 001016
001616 to 001416
01BA16 to 01B816
01BE16 to 01BC16
Function
Address setting register for address match interrupt
Setting range
RW
0000016 to FFFFF16
RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Figure 2.7.12. AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers
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After reset
X0000016
X0000016
X0000016
X0000016
M306H3MC-XXXFP/FCFP
2.8 Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit of PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it cannot
be set to “0” (watchdog timer interrupt) in a program.
Refer to “Watchdog Timer Reset” for the details of watchdog timer reset.
When the main clock is selected for CPU clock, the divide-by-N value for the prescaler can be chosen to
be 16 or 128 using the WDC7 bit of WDC register. If a sub-clock is selected for CPU clock, the divide-byN value for the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can
be calculated as given below. The period of watchdog timer is, however, subject to an error due to the
prescaler.
With main clock chosen for CPU clock
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Watchdog timer period =
CPU clock
With sub-clock chosen for CPU clock
Watchdog timer period =
Prescaler dividing (2) X Watchdog timer count (32768)
CPU clock
For example, when CPU clock = 10 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 52.4 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released.
Figure 2.8.1 shows the block diagram of the watchdog timer. Figure 2.8.2 shows the watchdog timerrelated registers.
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M306H3MC-XXXFP/FCFP
Prescaler
1/16
CM07 = 0
WDC7 = 0
PM12 = 0
CPU
clock
1/128
CM07 = 0
WDC7 = 1
Watchdog timer
interrupt request
PM22 = 0
HOLD
Watchdog timer
CM07 = 1
1/2
PM12 = 1
Reset
Set to
“7FFF16”
Write to WDTS register
RESET
Figure 2.8.1. Watchdog Timer Block Diagram
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
WDC
Address
After reset
000F16 00XXXXXX2(Note2)
Bit symbol
Function
Bit name
RW
(b4-b0)
High-order bit of watchdog timer
RO
WDC5
Cold start / warm start
0 : Cold start
discrimination flag (Note 1) 1 : Warm start
RW
Reserved bit
Must set to “0”
RW
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
RW
(b6)
WDC7
Note 1: The WDC5 bit is always “1” (warm start) no matter how it is set by writing a “0” or “1”.
Note 2: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program.
Watchdog timer start register (Note)
b7
b0
Symbol
WDTS
Address
000E16
After reset
Indeterminate
Function
RW
The watchdog timer is initialized and starts counting after a write instruction to
WO
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
Note : Write to the WDTS register after the watchdog timer interrupt occurs.
Figure 2.8.2. WDC Register and WDTS Register
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M306H3MC-XXXFP/FCFP
2.9 DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or
16-bit) data from the source address to the destination address. The DMAC uses the same data bus as
used by the CPU. Because the DMAC has higher priority of bus control than the CPU and because it
makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within
a very short time after a DMA request is generated. Figure 2.9.1 shows the block diagram of the DMAC.
Table 2.9.1 shows the DMAC specifications. Figures 2.9.2 to 2.9.4 show the DMAC-related registers.
AA
AAAAAAAAAAAAAAAAAAAAAAAAAA
A
AAAAAAA
AA
A
AAA
AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAA
AA
A
AAA A
AAA
AAA A
AA
AAA A AA
AA
AA
AA
A
A
AA
A
AA
AA
A
A
AAAA A
AA
AAAA AA AA
AA
AA
AA
A
A
AA
AA
A
A
A
AA
A
A AA
AA
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016)
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016)
(addresses 002916, 002816)
DMA0 transfer counter TCR0 (16)
DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 003916, 003816)
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
DMA latch high-order bits
DMA latch low-order bits
AA
AA
Note: Pointer is incremented by a DMA request.
Figure 2.9.1. DMAC Block Diagram
A DMA request is generated by a write to the DMiSL register (i = 0 to 1)’s DSR bit, as well as by an interrupt
request which is generated by any function specified by the DMiSL register’s DMS and DSEL3 to DSEL0
bits. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the
interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be
accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts,
the interrupt control register’s IR bit does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMiCON register’s DMAE bit =
“1” (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
not match. For details, refer to “DMA Requests”.
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Table 2.9.1. DMAC Specifications
Item
No. of channels
Transfer memory space
Maximum No. of bytes transferred
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________
DMA request factors
(Note 1, Note 2)
Falling edge of
INT0 or
INT1
________
________
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrpt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 > DMA1 (DMA0 takes precedence)
Transfer unit
8 bits or 16 bits
Transfer address direction
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer mode •Single transfer Transfer is completed when the DMAi transfer counter (i = 0–1)
underflows after reaching the terminal count.
•Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is con
tinued with it.
DMA interrupt request generation timing When the DMAi transfer counter underflowed
DMA startup
Data transfer is initiated each time a DMA request is generated when the
DMAiCON register’s DMAE bit = “1” (enabled).
DMA shutdown •Single transfer • When the DMAE bit is set to“0” (disabled)
• After the DMAi transfer counter underflows
•Repeat transfer When the DMAE bit is set to “0” (disabled)
Reload timing for forward ad- When a data transfer is started after setting the DMAE bit to “1” (en
abled), the forward address pointer is reloaded with the value of the
dress pointer and transfer
SARi or the DARi pointer whichever is specified to be in the forward
counter
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
Notes:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC.
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M306H3MC-XXXFP/FCFP
DMA0 request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM0SL
Address
03B816
Bit symbol
DSEL0
DSEL1
After reset
0016
Function
Bit name
DMA request cause
select bit
Refer to note
RW
DSEL2
RW
DSEL3
(b5-b4)
DMS
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .
RW
DSR
Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0
0 0 0 02
0 0 0 12
0 0 1 02
0 0 1 12
0 1 0 02
0 1 0 12
0 1 1 02
0 1 1 12
1 0 0 02
1 0 0 12
1 0 1 02
1 0 1 12
1 1 0 02
1 1 0 12
1 1 1 02
1 1 1 12
DMS=0(basic cause of request)
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
A-D conversion
UART1 transmit
DMS=1(extended cause of request)
–
–
–
–
–
–
Two edges of INT0 pin
Timer B3
Timer B4
Timer B5
–
–
–
–
–
–
Note 2: In VINTi, INTTMTi, and HINTi (i=0-3) of address 3616 expansion register of expansion function, when use
them by the following setup, DMA request cause extension select bit = "1" (extended cause of request) cannot be used.
• VINTi=10112
• INTRMTi=10102
• HINTi=10012
(i=0 to 3)
Figure 2.9.2. DM0SL Register
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M306H3MC-XXXFP/FCFP
DMA1 request cause select register
b7
b6
b5
b4
b3
b2
b1
Symbol
DM1SL
b0
Address
03BA16
DSEL1
DSEL2
Function
Bit name
Bit symbol
DSEL0
After reset
0016
DMA request cause
select bit
Refer to note
RW
RW
DSEL3
(b5-b4)
DMS
RW
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .
RW
DSR
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0
0 0 0 02
0 0 0 12
0 0 1 02
0 0 1 12
0 1 0 02
0 1 0 12
0 1 1 02
0 1 1 12
1 0 0 02
1 0 0 12
1 0 1 02
1 0 1 12
1 1 0 02
1 1 0 12
1 1 1 02
1 1 1 12
DMS=0(basic cause of request)
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive/ACK0
UART2 transmit
UART2 receive/ACK2
A-D conversion
UART1 receive/ACK1
DMS=1(extended cause of request)
–
–
–
–
–
SI/O3
SI/O4
Two edges of INT1
–
–
–
–
–
–
–
–
DMAi control register(i=0,1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM0CON
DM1CON
Bit symbol
Address
002C16
003C16
After reset
00000X002
00000X002
Bit name
Function
RW
DMBIT
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
RW
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
RW
DMAS
DMA request bit
0 : DMA not requested
1 : DMA requested
DMAE
DMA enable bit
0 : Disabled
1 : Enabled
RW
DSD
Source address direction
select bit (Note 2)
0 : Fixed
1 : Forward
RW
DAD
Destination address
0 : Fixed
direction select bit (Note 2) 1 : Forward
RW
(b7-b6)
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
RW
(Note 1)
Note 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
Note 2: At least one of the DAD and DSD bits must be “0” (address direction fixed).
Figure 2.9.3. DM1SL Register, DM0CON Register, and DM1CON Registers
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DMAi source pointer (i = 0, 1) (Note)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
Function
Set the source address of transfer
After reset
Indeterminate
Indeterminate
Setting range
RW
0000016 to FFFFF16
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DSD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0” (DMA disabled).
If the DSD bit is “1” (forward direction), this register can be written to at any time.
If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi destination pointer (i = 0, 1)(Note)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
Function
Set the destination address of transfer
After reset
Indeterminate
Indeterminate
Setting range
RW
0000016 to FFFFF16
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DAD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0”(DMA disabled).
If the DAD bit is “1” (forward direction), this register can be written to at any time.
If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
Function
Set the transfer count minus 1. The written value
is stored in the DMAi transfer counter reload
register, and when the DMAE bit of DMiCON
register is set to “1” (DMA enabled) or the DMAi
transfer counter underflows when the DMASL bit
of DMiCON register is “1” (repeat transfer), the
value of the DMAi transfer counter reload register
is transferred to the DMAi transfer counter.
When read, the DMAi transfer counter is read.
Figure 2.9.4. SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers
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After reset
Indeterminate
Indeterminate
Setting range
RW
000016 to FFFF16
RW
M306H3MC-XXXFP/FCFP
2.9.1 Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination
write) bus cycle. The number of read and write bus cycles is affected by the source and destination
addresses of transfer. During memory extension and microprocessor modes, it is also affected by the
________
BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.
(a) Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd
address, the source read cycle consists of one more bus cycle than when the source address of
transfer begins with an even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer
begins with an odd address, the destination write cycle consists of one more bus cycle than when the
destination address of transfer begins with an even address.
(b) Effect of BYTE Pin Level
During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data
twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data.
Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike
in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.
(c) Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required for that access increases by an amount equal to software wait states.
_______
(d) Effect of RDY Signal
During memory extension and microprocessor modes, DMA transfers to and from an external area
________
________
are affected by the RDY signal. Refer to “RDY signal”.
Figure 2.9.5 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality,
the destination write cycle is subject to the same conditions as the source read cycle, with the transfer
cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for
the source read and the destination write cycle, respectively. For example, when data is transferred in 16
bit units using an 8-bit bus ((2) in Figure 2.9.5), two source read bus cycles and two destination write bus
cycles are required.
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(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
CPU use
Dummy
cycle
Destination
Source
CPU use
RD signal
WR signal
Data
bus
CPU use
Dummy
cycle
Destination
Source
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source + 1
Source
Destination
Dummy
cycle
CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
bus
CPU use
Destination
Source
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 2.9.5. Transfer Cycles for Source Read
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M306H3MC-XXXFP/FCFP
2.9.2 DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 2.9.2 shows the
number of DMA transfer cycles. Table 2.9.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 2.9.2. DMA Transfer Cycles
Single-chip mode
Memory expansion mode
Bus width
Access address
Microprocessor mode
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
Even
1
1
1
1
(BYTE= “L”)
Odd
1
1
1
1
8-bit
Even
—
—
1
1
(BYTE = “H”)
Odd
—
—
1
1
16-bit
Even
1
1
1
1
(BYTE = “L”)
Odd
2
2
2
2
8-bit
Even
—
—
2
2
(BYTE = “H”)
Odd
—
—
2
2
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Table 2.9.3. Coefficient j, k
Internal area
Internal ROM, RAM
No wait
External area
SFR
With wait
Separate bus
Multiplex bus
With wait1
No wait
With wait1
1 wait
2 waits
3 waits
1wait
2 waits
3 waits
j
1
2
2
1
2
3
4
3
3
4
k
1
2
2
2
2
3
4
3
3
4
Notes:
1. Depends on the set value of CSE register.
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M306H3MC-XXXFP/FCFP
2.9.3 DMA Enable
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register
is “1” (forward) or the DARi register value when the DAD bit of DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
2.9.4 DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the
DMS and DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 2.9.4 shows the
timing at which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is
set to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in
a program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 2.9.4. Timing at Which the DMAS Bit Changes State
DMAS bit of the DMiCON register
DMA factor
Timing at which the bit is set to “1” Timing at which the bit is set to “0”
Software trigger
When the DSR bit of DMiSL
register is set to “1”
Peripheral function
When the interrupt control register
for the peripheral function that is
selected by the DSEL3 to DSEL0
and DMS bits of DMiSL register
has its IR bit set to “1”
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• Immediately before a data transfer starts
• When set by writing “0” in a program
M306H3MC-XXXFP/FCFP
2.9.5 Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the
DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes
DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period.
Figure 2.9.6 shows an example of DMA transfer effected by external factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request
are generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is returned to the
CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is
completed, the bus arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 2.9.6, occurs more than one time, the DMAS bit is set to “0” as soon as
getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
Refer to “(7) Hold Signal in 2.4.2 Bus Control” for details about bus arbitration between the CPU and
DMA.
An example where DMA requests for external causes are detected active at the same
BCLK
DMA0
Bus
arbitration
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 2.9.6. DMA Transfer by External Factors
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M306H3MC-XXXFP/FCFP
2.10 Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function
as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such
timer operations as counting, reloading, etc. Figures 2.10.1 and 2.10.2 show block diagrams of timer A
and timer B configuration, respectively.
1/2
• Main clock
f2 PCLK0 bit = 0
Clock prescaler
f1 or f2
f1
f8
1/8
1/4
f1 or f2 f8 f32 fC32
1/32
XCIN
PCLK0 bit = 1
f32
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
fC32
Reset
• Timer mode
• One-shot timer mode
• Pulse Width Measuring (PWM) mode
Timer A0 interrupt
Noise
filter
TA0 IN
Timer A0
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Noise
filter
TA1 IN
Timer A1 interrupt
Timer A1
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A2 interrupt
Noise
filter
TA2 IN
Timer A2
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A3 interrupt
Noise
filter
TA3 IN
Timer A3
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A4 interrupt
Noise
filter
TA4 IN
Timer A4
• Event counter mode
Timer B2 overflow or underflow
Note: Be aware that TA0 IN shares the pin with RxD2 and TB5 IN.
Figure 2.10.1. Timer A Configuration
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M306H3MC-XXXFP/FCFP
1/2
• Main clock
f2 PCLK0 bit = 0
Clock prescaler
f1 or f2
f1
f8
1/8
1/4
f32
fC32
1/32
XCIN
PCLK0 bit = 1
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
Reset
f1 or f2 f8 f32 fC32
Timer B2 overflow or underflow ( to Timer A count source)
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB0IN
Timer B0 interrupt
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB1IN
Timer B1 interrupt
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB2IN
Timer B2 interrupt
Timer B2
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB3IN
Timer B3 interrupt
Timer B3
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB4IN
Timer B4 interrupt
Timer B4
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB5IN
Timer B5
• Event counter mode
Note: Be aware that TB5 IN shares the pin with RxD2 and TA0 IN.
Figure 2.10.2. Timer B Configuration
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Timer B5 interrupt
M306H3MC-XXXFP/FCFP
2.10.1 Timer A
Figure 2.10.3 shows a block diagram of the timer A. Figures 2.10.4 to 2.10.6 show registers related to the
timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Data bus high-order bits
Clock source
selection
f1 or f2
f8
f32
fC32
AAAA
A
A
Data bus low-order bits
• Timer
• One shot
• PWM
Low-order
8 bits
• Timer
(gate function)
High-order
8 bits
Reload register
Clock selection
• Event counter
Counter
Polarity
selection
Up-count/down-count
TAiIN
(i = 0 to 4)
Always counts down except
in event counter mode
TABSR register
Clock selection
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
(Note)
TB2 overflow
To external
trigger circuit
(Note)
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
Down count
Addresses
038716 038616
038916 038816
038B16 038A16
038D16 038C16
038F16 038E16
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
UDF register
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Note: Overflow or underflow
Figure 2.10.3. Timer A Block Diagram
Timer Ai mode register (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TA0MR to TA4MR
Bit symbol
TMOD0
Address
039616 to 039A16
Bit name
Operation mode select bit
TMOD1
MR0
MR1
After reset
0016
Function
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
RW
Function varies with each
operation mode
RW
Function varies with each
operation mode
RW
MR2
MR3
TCK0
Count source select bit
TCK1
Figure 2.10.4. TA0MR to TA4MR Registers
Rev.1.00
2004.03.23
page 89 of 320
RW
b1 b0
RW
RW
RW
RW
RW
M306H3MC-XXXFP/FCFP
Timer Ai register (i= 0 to 4) (Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA0
TA1
TA2
TA3
TA4
Address
038716, 038616
038916, 038816
038B16, 038A16
038D16, 038C16
038F16, 038E16
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting range
RW
Timer
mode
Event
counter
mode
Divide the count source by n + 1 where n =
set value
000016 to FFFF16
RW
Divide the count source by FFFF16 – n + 1
where n = set value when counting up or
by n + 1 when counting down (Note 5)
000016 to FFFF16
One-shot
timer mode
Divide the count source by n where n = set
value and cause the timer to stop
000016 to FFFF16
(Notes 2, 4)
Mode
Function
Pulse width Modify the pulse width as follows:
modulation PWM period: (216 – 1) / fj
High level PWM pulse width: n / fj
mode
(16-bit PWM) where n = set value, fj = count source
frequency
Pulse width Modify the pulse width as follows:
modulation PWM period: (28 – 1) x (m + 1)/ fj
mode
High level PWM pulse width: (m + 1)n / fj
(8-bit PWM) where n = high-order address set value,
m = low-order address set value, fj =
count source frequency
RW
WO
000016 to FFFE16
(Note 3, 4)
WO
0016 to FE16
(High-order address)
0016 to FF16
(Low-order address) WO
(Note 3, 4)
Note 1: The register must be accessed in 16 bit units.
Note 2: If the TAi register is set to ‘000016,’ the counter does not work and timer Ai interrupt
requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are
output from the TAiOUT pin.
Note 3: If the TAi register is set to ‘000016,’ the pulse width modulator does not work, the output
level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated
either. The same applies when the 8 high-order bits of the timer TAi register are set to ‘001
6’ while operating as an 8-bit pulse width modulator.
Note 4: Use the MOV instruction to write to the TAi register.
Note 5: The timer counts pulses from an external device or overflows or underflows in other timers.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit symbol
Address
038016
After reset
0016
Bit name
Function
RW
RW
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
RW
TA3S
Timer A3 count start flag
RW
TA4S
Timer A4 count start flag
RW
TB0S
Timer B0 count start flag
RW
TB1S
Timer B1 count start flag
RW
TB2S
Timer B2 count start flag
RW
0 : Stops counting
1 : Starts counting
RW
Up/down flag (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UDF
Bit symbol
Address
038416
Bit name
TA0UD
Timer A0 up/down flag
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
TA4UD
Timer A4 up/down flag
TA2P
TA3P
TA4P
After reset
0016
F unction
0 : Down count
1 : Up count
Enabled by setting the TAiMR
register’s MR2 bit to “0”
(= switching source in UDF
register) during event counter
mode.
RW
RW
RW
RW
RW
RW
Timer A2 two-phase pulse 0 : two-phase pulse signal
WO
processing disabled
signal processing select bit
1 : two-phase pulse signal
processing enabled
Timer A3 two-phase pulse
WO
(Notes 2, 3)
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
WO
Note 1: Use MOV instruction to write to this register.
Note 2: Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set
to “0” (input mode).
Note 3: When not using the two-phase pulse signal processing function, set the bit corresponding to
timer .A2 to timer A4 to “0”
Figure 2.10.5. TA0 to TA4 Registers, TABSR Register, and UDF Register
Rev.1.00
2004.03.23
page 90 of 320
M306H3MC-XXXFP/FCFP
One-shot start flag
b7
b6
b5
b4
b3
b2
b1
Symbol
ONSF
b0
Address
038216
After reset
0016
0
Function
RW
The timer starts counting by setting
this bit to “1” while the TMOD1 to
TMOD0 bits of TAiMR register (i =
0 to 4) = ‘102’ (= one-shot timer
mode) and the MR2 bit of TAiMR
register = “0” (=TAiOS bit enabled).
When read, its content is “0”.
RW
Reserved bit
Must be set to “0”
RW
Timer A0 event/trigger
select bit
RW
0 0 : Input on TA0IN is selected (Note 1)
0 1 : TB2 overflow is selected (Note 2)
1 0 : TA4 overflow is selected (Note 2) RW
1 1 : TA1 overflow is selected (Note 2)
Bit symbol
Bit name
TA0OS
Timer A0 one-shot start flag
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
(b5)
TA0TGL
TA0TGH
RW
RW
RW
RW
b7 b6
Note 1: Make sure the PD7_1 bit of PD7 register is set to “0” (= input mode).
Note 2: Overflow or underflow
Trigger select register
b7
b6
b5
b4
b3
b2
b1
Symbol
TRGSR
b0
Bit symbol
TA1TGL
Address
038316
Bit name
Timer A1 event/trigger
select bit
TA1TGH
TA2TGL
Timer A2 event/trigger
select bit
TA2TGH
TA3TGL
Timer A3 event/trigger
select bit
TA3TGH
TA4TGL
Timer A4 event/trigger
select bit
TA4TGH
After reset
0016
Function
RW
0 0 : Input on TA1IN is selected (Note 1)
0 1 : TB2 is selected
1 0 : TA0 is selected
1 1 : TA2 is selected
RW
b1 b0
b3 b2
0 0 : Input on TA2IN is selected (Note 1)
0 1 : TB2 is selected
1 0 : TA1 is selected
1 1 : TA3 is selected
RW
RW
RW
b5 b4
0 0 : Input on TA3IN is selected (Note 1)
0 1 : TB2 is selected
1 0 : TA2 is selected
1 1 : TA4 is selected
b7 b6
0 0 : Input on TA4IN is selected (Note 1)
0 1 : TB2 is selected
1 0 : TA3 is selected
1 1 : TA0 is selected
RW
RW
RW
RW
Note 1: Make sure the port direction bits for the TA1IN to TA4IN pins are set to “0” (= input mode).
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Bit symbol
Address
038116
After reset
0XXXXXXX2
(b6-b0)
Bit name
Function
Nothing is assigned.
When write, set to “0”. When read, their contents are
indeterminate.
CPSR
Clock prescaler reset flag
Setting this bit to “1” initializes the
prescaler for the timekeeping clock. (
When read, its content is “0”.)
Figure 2.10.6. ONSF Register, TRGSR Register, and CPSRF Register
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2004.03.23
page 91 of 320
RW
RW
M306H3MC-XXXFP/FCFP
(1) Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 2.10.1). Figure 2.10.7
shows TAiMR register in timer mode.
Table 2.10.1. Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and continues counting
1/(n+1) n: set value of TAiMR register (i= 0 to 4)
000016 to FFFF16
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Timer underflow
I/O port or gate input
I/O port or pulse output
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Gate function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When not counting, the pin outputs a low.
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function
Timer Ai mode register (i=0 to 4)
b7
b6
b5
0
b4
b3
b2
b1
b0
0 0
Symbol
TA0MR to TA4MR
Bit symbol
TMOD0
TMOD1
MR0
MR1
Address
039616 to 039A16
Bit name
Operation mode
select bit
TCK0
Function
b1 b0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
Gate function select bit
b4 b3
MR2
MR3
After reset
0016
0 0 : Gate function not available
} (TAiIN pin functions as I/O port)
01:
1 0 : Counts while input on the TAiIN pin
is low (Note 2)
1 1 : Counts while input on the TAiIN pin
is high (Note 2)
Must be set to “0” in timer mode
Count source select bit
TCK1
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page 92 of 320
RW
RW
RW
RW
RW
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 2.10.7. Timer Ai Mode Register in Timer Mode
RW
RW
RW
RW
M306H3MC-XXXFP/FCFP
(2) Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 2.10.2 lists specifications in event counter mode (when not processing two-phase pulse signal). Table 2.10.3 lists specifications in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4).
Figure 2.10.8 shows TAiMR register in event counter mode (when not processing two-phase pulse signal). Figure 2.10.9 shows TA2MR to TA4MR registers in event counter mode (when processing twophase pulse signal with the timers A2, A3 and A4).
Table 2.10.2. Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item
Specification
Count source
• External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected
in program)
• Timer B2 overflows or underflows,
timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,
timer Ak (k=i+1, except k=0 if i=4) overflows or underflows
Count operation
• Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divided ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Set TAiS bit of TABSR register to “1” (= start counting)
Count stop condition
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
I/O port or count source input
TAiOUT pin function
I/O port, pulse output, or up/down-count select input
Read from timer
Count value can be read by reading TAi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Whenever the timer underflows or underflows, the output polarity of TAiOUT
pin is inverted . When not counting, the pin outputs a low.
Rev.1.00
2004.03.23
page 93 of 320
M306H3MC-XXXFP/FCFP
Timer Ai mode register (i=0 to 4)
(When not using two-phase pulse signal processing)
b7
b6
b5
b4
b3
b2
0
b1
b0
Symbol
TA0MR to TA4MR
0 1
Bit symbol
TMOD0
Address
039616 to 039A16
Bit name
Operation mode select bit
Function
b1 b0
0 1 : Event counter mode (Note 1)
TMOD1
MR0
After reset
0016
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output (Note 2)
RW
R
W
RW
RW
RW
(TAiOUT pin functions as pulse output pin)
MR1
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge RW
1 : Counts external signal's rising edge
MR2
Up/down switching
cause select bit
0 : UDF register
1 : Input signal to TAiOUT pin (Note 4)
MR3
Must be set to “0” in event counter mode
RW
TCK0
Count operation type
select bit
RW
TCK1
Can be “0” or “1” when not using two-phase pulse signal
processing
0 : Reload type
1 : Free-run type
RW
RW
Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR
registers.
Note 2: TA0OUT pin is N-channel open drain output.
Note 3: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 4: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port
direction bit for TAiOUT pin must be set to “0” (= input mode).
Figure 2.10.8. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
Rev.1.00
2004.03.23
page 94 of 320
M306H3MC-XXXFP/FCFP
Table 2.10.3. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)
Item
Count source
Count operation
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function (Note)
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4)
• Up-count or down-count can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Timer overflow or underflow
Two-phase pulse input
Two-phase pulse input
Count value can be read by reading timer A2, A3 or A4 register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
• Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN pin
when input signals on TAjOUT pin is “H”.
TAjOUT
TAjIN
(j=2,3)
Upcount
Upcount
Upcount
Downcount
Downcount
Downcount
• Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the
input signal on TAkOUT pin is “H”, the timer counts up rising and falling
edges on TAkOUT and TAkIN pins. If the phase relationship is such that
TAkIN pin goes “L” when the input signal on TAkOUT pin is “H”, the timer
counts down rising and falling edges on TAkOUT and TAkIN pins.
TAkOUT
Count up all edges
Count down all edges
TAkIN
(k=3,4)
Count up all edges
Count down all edges
• Counter initialization by Z-phase input (timer A3)
The timer count value is initialized to 0 by Z-phase input.
Notes:
1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to
multiply-by-4 processing operation.
Rev.1.00
2004.03.23
page 95 of 320
M306H3MC-XXXFP/FCFP
Timer Ai mode register (i=2 to 4)
(When using two-phase pulse signal processing)
b6
b5
b4
b3
b2
b1
b0
0 1 0 0 0 1
Symbol
TA2MR to TA4MR
Address
039816 to 039A16
Function
RW
0 1 : Event counter mode
RW
RW
Bit name
TMOD0
Operation mode select bit
TMOD1
MR0
After reset
0016
b1 b0
To use two-phase pulse signal processing, set this bit to “0”.
RW
To use two-phase pulse signal processing, set this bit to “0”.
RW
MR2
To use two-phase pulse signal processing, set this bit to “1”.
RW
MR3
To use two-phase pulse signal processing, set this bit to “0”.
RW
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
RW
TCK1
Two-phase pulse signal
processing operation
select bit (Note 1)(Note 2)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
RW
MR1
Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
• Set the UDF register’s TAiP bit to “1” (two-phase pulse signal processing function enabled).
• Set the TRGSR register’s TAiGH and TAiGL bits to ‘002’ (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).
Figure 2.10.9. TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase
pulse signal processing with timer A2, A3 or A4)
Rev.1.00
2004.03.23
page 96 of 320
M306H3MC-XXXFP/FCFP
(3) One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. (See Table 2.10.4.) When the
trigger occurs, the timer starts up and continues operating for a given period. Figure 2.10.10 shows the
TAiMR register in one-shot timer mode.
Table 2.10.4. Specifications in One-shot Timer Mode
Item
Count source
Count operation
Specification
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function
Rev.1.00
2004.03.23
f1, f2, f8, f32, fC32
• Down-count
• When the counter reaches 000016, it stops counting after reloading a new value
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
1/n
n : set value of TAi register 000016 to FFFF16
However, the counter does not work if the divide-by-n value is set to 000016.
TAiS bit of TABSR register = “1” (start counting) and one of the following
triggers occurs.
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit of ONSF register is set to “1” (= timer starts)
• When the counter is reloaded after reaching “000016”
• TAiS bit is set to “0” (= stop counting)
When the counter reaches “000016”
I/O port or trigger input
I/O port or pulse output
An indeterminate value is read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Pulse output function
The timer outputs a low when not counting and a high when counting.
page 97 of 320
M306H3MC-XXXFP/FCFP
Timer Ai mode register (i=0 to 4)
b7
b6
b5
b4
b3
0
b2
b1
b0
1 0
Symbol
TA0MR to TA4MR
Bit symbol
TMOD0
Address
039616 to 039A16
After reset
0016
Bit name
Function
RW
RW
Operation mode select bit
b1 b0
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
RW
1 : Pulse is output (Note 1)
(TAiOUT pin functions as a pulse output pin)
MR1
External trigger select
bit (Note 2)
0 : Falling edge of input signal to TAiIN pin (Note 3)
1 : Rising edge of input signal to TAiIN pin (Note 3) RW
MR2
Trigger select bit
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
TMOD1
1 0 : One-shot timer mode
MR3
Must be set to “0” in one-shot timer mode
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
RW
RW
RW
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘00 2’ (TAiIN pin input).
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 2.10.10. TAiMR Register in One-shot Timer Mode
Rev.1.00
2004.03.23
page 98 of 320
M306H3MC-XXXFP/FCFP
(4) Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 2.10.5). The counter
functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 2.10.11 shows
TAiMR register in pulse width modulation mode. Figures 2.10.12 and 2.10.13 show examples of how a
16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates.
Table 2.10.5. Specifications in PWM Mode
Item
Specification
Count source
Count operation
16-bit PWM
8-bit PWM
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Rev.1.00
2004.03.23
f1, f2, f8, f32, fC32
• Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new value at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs during counting
• High level width
n / fj
n : set value of TAi register (i=o to 4)
• Cycle time (216-1) / fj fixed
fj: count source frequency (f1, f2, f8, f32, fC32)
• High level width n x (m+1) / fj n : set value of TAiMR register high-order address
• Cycle time (28-1) x (m+1) / fj m : set value of TAiMR register low-order address
• TAiS bit of TABSR register is set to “1” (= start counting)
• The TAiS bit = 1 and external trigger input from the TAiIN pin
• The TAiS bit = 1 and one of the following external triggers occurs
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
TAiS bit is set to “0” (= stop counting)
PWM pulse goes “L”
I/O port or trigger input
Pulse output
An indeterminate value is read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
page 99 of 320
M306H3MC-XXXFP/FCFP
Timer Ai mode register (i= 0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
1
Symbol
TA0MR to TA4MR
Bit symbol
TMOD0
TMOD1
Address
039616 to 039A16
After reset
0016
Bit name
Operation mode
select bit
RW
Function
RW
b1 b0
1 1 : PWM mode
(Note 1) RW
RW
MR0
Must be set to “1” in PWM mode
MR1
External trigger select
bit (Note 2)
0: Falling edge of input signal to TAiIN pin(Note 3)
RW
1: Rising edge of input signal to TAiIN pin(Note 3)
MR2
Trigger select bit
0 : Write “1” to TAiS bit in the TASF register RW
1 : Selected by TAiTGH to TAiTGL bits
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
TCK0
Count source select bit
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
b7 b6
TCK1
RW
RW
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are “002” (TAi IN pin input).
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 2.10.11. TAiMR Register in PWM Mode
Rev.1.00
2004.03.23
page 100 of 320
M306H3MC-XXXFP/FCFP
1 / fi X (2
16
– 1)
Count source
“H”
Input signal to
TAiIN pin
“L”
Trigger is not generated by this signal
1 / fj X n
PWM pulse output
from TAiOUT pin
“H”
IR bit of TAiIC
register
“1”
“L”
“0”
fj : Frequency of count source
(f1, f2, f8, f32, fC32)
Set to “0” upon accepting an interrupt request or by writing in program
i = 0 to 4
Note 1: n = 000016 to FFFE16.
Note 2: This timing diagram is for the case where the TAi register is ‘000316,’ the TAiTGH and TAiTGL bits of ONSF
or TRGSR register = ‘002’ (TAiIN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and the MR2
bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 2.10.12. Example of 16-bit Pulse Width Modulator Operation
1 / fj X (m + 1) X (2 8 – 1)
Count source (Note1)
“H”
Input signal to
TAiIN pin
“L”
1 / fj X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2) “L”
1 / fj X (m + 1) X n
PWM pulse output
from TAiOUT pin
IR bit of TAiIC
register
“H”
“L”
“1”
“0”
fj : Frequency of count source
(f1, f2, f8, f32, fC32)
i = 0 to 4
Set to “0” upon accepting an interrupt request or by writing in program
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FE16.
Note 4: This timing diagram is for the case where the TAi register is ‘020216,’ the TAiTGH and TAiTGL bits of ONSF or
TRGSR register = ‘002’ (TAiIN pin input), the MR1 bit of TAiMR register = 0 (falling edge), and the MR2 bit of
TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 2.10.13. Example of 8-bit Pulse Width Modulator Operation
Rev.1.00
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M306H3MC-XXXFP/FCFP
2.10.2 Timer B
Figure 2.10.14 shows a block diagram of the timer B. Figures 2.10.15 and 2.10.16 show registers related
to the timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to
5) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
• Timer
• Pulse period measuremnet,
pulse width measurement
f1 or f2
f8
f32
fC32
Reload register
Clock selection
Counter
• Event counter
TABSR register
TBSR register
Polarity switching,
edge pulse
TBiIN
(i = 0 to 5)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
TBj overflow (Note)
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Note: Overflow or underflow.
Address
039116 039016
039316 039216
039516 039416
035116 035016
035316 035216
035516 035416
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Figure 2.10.14. Timer B Block Diagram
Timer Bi mode register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Bit symbol
TMOD0
Address
039B16 to 039D16
035B16 to 035D16
After reset
00XX00002
00XX00002
Function
Bit name
Operation mode select bit
TMOD1
MR0
MR1
b1 b0
RW
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
RW
Function varies with each operation
mode
RW
RW
RW
MR2
RW
(Note 1)
(Note 2)
RO
MR3
TCK0
Count source select bit
TCK1
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 2.10.15. TB0MR to TB5MR Registers
Rev.1.00
2004.03.23
page 102 of 320
Function varies with each operation
mode
RW
RW
M306H3MC-XXXFP/FCFP
Timer Bi register (i=0 to 5)(Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
039116, 039016
039316, 039216
039516, 039416
035116, 035016
035316, 035216
035516, 035416
Function
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting range
RW
Timer mode
Divide the count source by n + 1
where n = set value
000016 to FFFF16
RW
Event counter
mode
Divide the count source by n + 1
where n = set value (Note 2)
000016 to FFFF16
RW
Mode
Pulse period
Measures a pulse period or width
modulation mode,
Pulse width
modulation mode
RO
Note 1: The register must be accessed in 16 bit units.
Note 2: The timer counts pulses from an external device or overflows or underflows of other timers.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Address
038016
After reset
0016
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Bit name
Bit symbol
Function
RW
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
RW
TA3S
Timer A3 count start flag
RW
TA4S
Timer A4 count start flag
RW
TB0S
Timer B0 count start flag
RW
TB1S
Timer B1 count start flag
RW
TB2S
Timer B2 count start flag
RW
0 : Stops counting
1 : Starts counting
RW
RW
Timer B3, B4, B5 count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TBSR
Address
034016
After reset
000XXXXX2
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Bit symbol
(b4-b0)
Bit name
Function
RW
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
TB3S
Timer B3 count start flag
TB4S
Timer B4 count start flag
TB5S
Timer B5 count start flag
0 : Stops counting
1 : Starts counting
RW
RW
RW
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Bit symbol
Address
038116
Bit name
After reset
0XXXXXXX2
Function
RW
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
(b6-b0)
CPSR
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
Clock prescaler reset flag Setting this bit to “1” initializes the
RW
prescaler for the timekeeping clock.
(When read, the value of this bit is “0”.)
Figure 2.10.16. TB0 to TB5 Registers, TABSR Register, TBSR Register, CPSRF Register
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2004.03.23
page 103 of 320
M306H3MC-XXXFP/FCFP
(1) Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 2.10.6). Figure 2.10.17
shows TBiMR register in timer mode.
Table 2.10.6. Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1) n: set value of TBiMR register (i= 0 to 5)
000016 to FFFF16
(Note)
Count start condition
Set TBiS bit
to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
I/O port
Read from timer
Count value can be read by reading TBi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S
bits are assigned to the TBSR register bit 5 to bit 7.
AAA
AAA
Timer Bi mode register (i= 0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Bit symbol
TMOD0
Address
039B16 to 039D16
035B16 to 035D16
Bit name
Operation mode select bit
TMOD1
MR0
MR1
MR2
After reset
00XX00002
00XX00002
Function
b1 b0
0 0 : Timer mode
RW
RW
RW
RW
Has no effect in timer mode
Can be set to “0” or “1”
RW
TB0MR, TB3MR registers
Must be set to “0” in timer mode
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate.
TCK0
Count source select bit
TCK1
Figure 2.10.17. TBiMR Register in Timer Mode
Rev.1.00
2004.03.23
page 104 of 320
RO
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
M306H3MC-XXXFP/FCFP
(2) Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 2.10.7) . Figure 2.10.20 shows TBiMR register in event counter mode.
Table 2.10.7. Specifications in Event Counter Mode
Item
Specification
Count source
• External signals input to TBiIN pin (i=0 to 5) (effective edge can be selected
in program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
Count operation
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBi register
000016 to FFFF16
1
Count start condition
Set TBiS bit to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Count source input
Read from timer
Count value can be read by reading TBi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Notes:
1. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
AA
Timer Bi mode register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039B16 to 039D16
035B16 to 035D16
Bit symbol
Bit name
TMOD0
Operation mode select bit
TMOD1
MR0
Count polarity select
bit (Note 1)
MR1
MR2
After reset
00XX00002
00XX00002
Function
b1 b0
0 1 : Event counter mode
RW
RW
RW
b3 b2
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set
TB0MR, TB3MR registers
Must be set to “0” in timer mode
RW
RW
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
MR3
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
RO
TCK0
Has no effect in event counter mode.
Can be set to “0” or “1”.
RW
TCK1
Event clock select
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0,
j = 5 if i = 3)
RW
Note 1: Effective when the TCK1 bit = “0” (input from TBiIN pin). If the TCK1 bit = “1” (TBj overflow or underflow), these
bits can be set to “0” or “1”.
Note 2: The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Figure 2.10.20. TBiMR Register in Event Counter Mode
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2004.03.23
page 105 of 320
M306H3MC-XXXFP/FCFP
(3) Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 2.10.8). Figure 2.10.21 shows TBiMR register in pulse period and pulse width
measurement mode. Figure 2.10.22 shows the operation timing when measuring a pulse period. Figure
2.10.23 shows the operation timing when measuring a pulse width.
Table 2.10.8. Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of measurement pulse. The counter value is set to “000016” to continue counting.
Count start condition
Set TBiS (i=0 to 5) bit3 to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing • When an effective edge of measurement pulse is input1
• Timer overflow. When an overflow occurs, MR3 bit of TBiMR register is set
to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no overflow) by
writing to TBiMR register at the next count timing or later after MR3 bit was
set to “1”. At this time, make sure TBiS bit is set to “1” (start counting).
TBiIN pin function
Measurement pulse input
Read from timer
Contents of the reload register (measurement result) can be read by reading TBi register2
Write to timer
Value written to TBi register is written to neither reload register nor counter
Notes:
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits are assigned
to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Bit symbol
TMOD0
TMOD1
MR0
Address
039B16 to 039D16
035B16 to 035D16
Bit name
Operation mode
select bit
Measurement mode
select bit
MR1
MR2
MR3
TCK0
TCK1
After reset
00XX00002
00XX00002
Function
b1 b0
1 0 : Pulse period / pulse width
measurement mode
RW
RW
b3 b2
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Must not be set.
TB0MR and TB3MR registers
Must be set to “0” in pulse period and pulse width measurement mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
Timer Bi overflow
0 : Timer did not overflow
flag ( Note)
1 : Timer has overflowed
Count source
select bit
RW
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
RW
RO
RW
RW
Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow) by writing
to the TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to
“1” in a program. The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits are
assigned to the TBSR register's bit 5 to bit 7.
Figure 2.10.21. TBiMR Register in Pulse Period and Pulse Width Measurement Mode
Rev.1.00
2004.03.23
page 106 of 320
M306H3MC-XXXFP/FCFP
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
TBiS bit
“0”
TBiIC register's
IR bit
“1”
TBiMR register's
MR3 bit
“1”
“0”
Set to “0” upon accepting an interrupt request or by writing in
program
“0”
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
i = 0 to 5
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “002” (measure the interval
from falling edge to falling edge of the measurement pulse).
Figure 2.10.22. Operation timing when measuring a pulse period
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
counter
Transfer
(indeterminate
value)
(Note 1)
Transfer
(measured value)
(Note 1)
Transfer
(measured
value)
(Note 1)
Transfer
(measured value)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
TBiS bit
“1”
“0”
TBiIC register's
IR bit
“1”
“0”
“1”
TBiMR register's
MR3 bit
i = 0 to 5
Set to “0” upon accepting an interrupt request or by
writing in program
“0”
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “102” (measure the interval
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
Figure 2.10.23. Operation timing when measuring a pulse width
Rev.1.00
2004.03.23
page 107 of 320
M306H3MC-XXXFP/FCFP
2.11 Serial I/O
Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4.
2.11.1 UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each
other.
Figure 2.11.1 shows the block diagram of UARTi. Figures 2.11.2 shows the block diagram of the UARTi
transmit/receive.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
• Special mode 1 (I2C mode)
• Special mode 2
• Special mode 3 (Bus collision detection function, IE mode) : UART0, UART1
• Special mode 4 (SIM mode) : UART2
Figures 2.11.3 to 2.11.8 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
Rev.1.00
2004.03.23
page 108 of 320
M306H3MC-XXXFP/FCFP
1/2
f2SIO
PCLK1=0
f1SIO or f2SIO
f1SIO
Main clock
PCLK1=1
1/8
f8SIO
1/4
(UART0)
f32SIO
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD0
Clock source selection
f1SIO or f2SIO
f8SIO
f32SIO
UART reception
1/16
CLK1 to CLK0
002
Internal CKDIR=0
012
102
Reception
control circuit
Clock synchronous
type
U0BRG
register
1 / (n0+1)
1/16
UART transmission
Transmission control
Clock synchronous
circuit
type
Clock synchronous type
(when internal clock is selected)
1/2
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
External
TxD0
Receive
clock
Transmit
clock
Transmit/
receive
unit
CKDIR=1
CKPOL
CLK
polarity
reversing
circuit
CLK0
CTS/RTS selected
CRS=1
CTS0 / RTS0
CTS/RTS disabled
RTS0
“H”
CRS=0
CTS/RTS disabled
CRD=1
RCSP=0
CTS0
CRD=0
CTS0 from UART1
RCSP=1
(UART1)
Clock source selection
CLK1 to CLK0
002
f1SIO or f2SIO
Internal CKDIR=0
012
f8SIO
102
f32SIO
External
UART reception
1/16
1 / (n1+1)
CTS1 / RTS1/
CTS0/ CLKS1
UART transmission
1/16
CLKMD0=0
Clock output
pin select
CLKMD1=1
TxD1
Receive
clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
1/2 (when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
CLKMD0=1
CTS/RTS selected
CRS=1
CLKMD1=0
CRS=0
CTS/RTS disabled
RTS1
“H”
CTS/RTS disabled
RCSP=0
CRD=1
CTS1
CRD=0
CTS0 from UART0
RCSP=1
(UART2)
Clock source selection
CLK1 to CLK0
002
f1SIO or f2SIO
012
Internal CKDIR=0
f8SIO
102
f32SIO
External
CKPOL
CLK2
CLK
polarity
reversing
circuit
CTS/RTS
selected
CRS=1
CTS2 / RTS2
CRS=0
1/16
1 / (n2+1)
UART reception
Clock synchronous
type
U2BRG
register
1/16
CKDIR=1
Clock synchronous type
1/2 (when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
CTS/RTS disabled
RTS2
“H”
CTS2
CRD=0
i = 0 to 2
ni: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: UiMR register's bits
CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register's bits
CLKMD0, CLKMD1, RCSP: UCON register's bits
Note: UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Figure 2.11.1. UARTi Block Diagram
page 109 of 320
Reception
control circuit
UART transmission
Clock synchronous
type
CTS/RTS disabled
CRD=1
2004.03.23
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD2
Rev.1.00
Transmission
control circuit
Clock synchronous
type
CKDIR=1
CLK
polarity
reversing
circuit
Reception
control circuit
Clock synchronous
type
U1BRG
register
CKPOL
CLK1
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD1
Transmission
control circuit
Receive
clock
Transmit
clock
(Note)
Transmit/
receive
unit
TxD2
M306H3MC-XXXFP/FCFP
No reverse
IOPOL=0
RxD data
reverse circuit
RxDi
Reverse IOPOL=1
Clock
synchronous type
1SP
PAR
disabled
STPS= 0
PRYE=0
SP
2SP
SP
Clock
synchronous
type
UARTi receive register
UART(7 bits)
PAR
PRYE=1
PAR
enabled
STPS= 1
0
UART
(7 bits)
UART
(8 bits)
0
0
0
UART
0
Clock
synchronous type
UART
(9 bits)
0
0
UART
(8 bits)
UART
(9 bits)
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D7
D8
UART
(9 bits)
D6
D5
D4
D3
D2
D1
D0
UiTB register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
PAR
2SP STPS= 1 enabled PRYE=1 UART
SP
SP
PAR
STPS
=0
1SP
PRYE=0
PAR
disabled
“0”
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous type
i=0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: UiMR register's bits
UiERE: UiC1 register's bit
Figure 2.11.2. UARTi Transmit/Receive Unit
Rev.1.00
2004.03.23
page 110 of 320
UARTi transmit register
UART(7 bits)
Error signal output
disable
UiERE=1
No reverse
IOPOL=0
UiERE=0
Error signal
output circuit
Error signal output
enable
IOPOL=1
TxD data
reverse circuit
Reverse
TxDi
M306H3MC-XXXFP/FCFP
UARTi transmit buffer register (i=0 to 2)(Note)
(b15)
b7
(b8)
b0 b7
Symbol
U0TB
U1TB
U2TB
b0
Address
03A316-03A216
03AB16-03AA16
037B16-037A16
After reset
Indeterminate
Indeterminate
Indeterminate
Function
RW
WO
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register (i=0 to 2)
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
U2RB
b0
Bit
symbol
Address
03A716-03A616
03AF16-03AE16
037F16-037E16
Function
Bit name
(b7-b0)
(b8)
(b10-b9)
After reset
Indeterminate
Indeterminate
Indeterminate
RW
Receive data (D7 to D0)
RO
Receive data (D8)
RO
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
ABT
Arbitration lost detecting
flag (Note 2)
OER
Overrun error flag (Note 1) 0 : No overrun error
1 : Overrun error found
FER
Framing error flag (Note 1)
0 : No framing error
1 : Framing error found
RO
PER
Parity error flag (Note 1)
0 : No parity error
1 : Parity error found
RO
SUM
Error sum flag (Note 1)
0 : No error
1 : Error found
RO
0 : Not detected
1 : Detected
RW
RO
Note 1: When the UiMR register’s SMD2 to SMD0 bits = “000 2” (serial I/O disabled) or the UiC1 register’s RE bit = “0” (reception disabled), all of the SUM,
PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER bits = “0” (no error).
Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
Note 2: The ABT bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.)
UARTi bit rate generator (i=0 to 2)(Notes 1, 2)
b7
Symbol
U0BRG
U1BRG
U2BRG
b0
Address
03A116
03A916
037916
After reset
Indeterminate
Indeterminate
Indeterminate
Function
Setting range
RW
Assuming that set value = n, UiBRG divides the count source
by n + 1
0016 to FF16
WO
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
Figure 2.11.3. U0TB to U2TB Register, U0RB to U2RB Register, and U0BRG to U2BRG Register
Rev.1.00
2004.03.23
page 111 of 320
M306H3MC-XXXFP/FCFP
UARTi transmit/receive mode register (i=0 to 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0MR to U2MR
Bit
symbol
SMD0
Address
03A016, 03A816, 037816
After reset
0016
Function
Bit name
Serial I/O mode select bit
(Note 2)
RW
b2 b1 b0
RW
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
(Note 3)
0 1 0 : I2C mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
RW
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
RW
STPS
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
RW
PRY
Odd/even parity select bit Effective when PRYE = 1
SMD1
SMD2
RW
0 : Odd parity
1 : Even parity
RW
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
RW
IOPOL
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
RW
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).
UARTi transmit/receive control register 0 (i=0 to 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0C0 to U2C0
Bit
symbol
CLK0
Address
After reset
03A416, 03AC16, 037C16 000010002
Bit name
BRG count source
select bit
CLK1
CRS
TXEPT
CRD
CTS/RTS function
select bit
(Note 4)
Function
b1 b0
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Must not be set
Effective when CRD = 0
0 : CTS function is selected (Note 1)
1 : RTS function is selected
Transmit register empty 0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
flag
(transmission completed)
CTS/RTS disable bit
RW
RW
RW
RW
RO
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60, P64 and P73 can be used as I/O ports)
RW
NCH
Data output select bit
(Note 2)
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N-channel open-drain output
RW
CKPOL
CLK polarity select bit
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
RW
UFORM Transfer format select bit 0 : LSB first
(Note 3)
1 : MSB first
RW
Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: TXD2/SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0
register to “0”.
Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long.
Note 4: CTS1/RTS1 can be used when the UCON register’s CLKMD1 bit = “0” (only CLK1 output) and the UCON register’s RCSP bit =
“0” (CTS0/RTS0 not separated).
Figure 2.11.4. U0MR to U2MR Register and U0C0 to U2C0 Register
Rev.1.00
2004.03.23
page 112 of 320
M306H3MC-XXXFP/FCFP
UARTi transmit/receive control register 1 (i=0, 1)
b7
b6
b5
b4
b3
b2
b1
Symbol
U0C1, U1C1
b0
Bit
symbol
Address
03A516,03AD16
After reset
000000102
Function
Bit name
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI
Transmit buffer
empty flag
0 : Data present in UiTB register
1 : No data present in UiTB register
RO
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive complete flag
0 : No data present in UiRB register
1 : Data present in UiRB register
RO
(b5-b4)
Nothing is assigned.
When write, set “0”. When read, these contents are “0”.
UiLCH
Data logic select bit
0 : No reverse
1 : Reverse
RW
UiERE
Error signal output
enable bit
0 : Output disabled
1 : Output enabled
RW
UART2 transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
U2C1
b0
Bit
symbol
Address
037D16
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI
Transmit buffer
empty flag
0 : Data present in U2TB register
1 : No data present in U2TB register
RO
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive complete flag
0 : No data present in U2RB register
1 : Data present in U2RB register
RO
0 : Transmit buffer empty (TI = 1)
1 : Transmit is completed (TXEPT = 1)
RW
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
RW
U2ERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
RW
Figure 2.11.5. U0C1 to U2C1 Registers
2004.03.23
Function
Bit name
U2IRS UART2 transmit interrupt
cause select bit
Rev.1.00
After reset
000000102
page 113 of 320
M306H3MC-XXXFP/FCFP
UART transmit/receive control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UCON
Bit
symbol
Address
03B016
After reset
X00000002
Function
RW
Bit
name
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
RW
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
CLKMD0 UART1 CLK/CLKS
select bit 0
Effective when CLKMD1 = “1”
0 : Clock output from CLK1
1 : Clock output from CLKS1
RW
CLKMD1 UART1 CLK/CLKS
select bit 1 (Note)
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
RW
RCSP
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
RW
U0IRS
U1IRS
Separate UART0
CTS/RTS bit
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)
UART2 special mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
U0SMR to U2SMR 036F16, 037316, 037716
0
Bit
symbol
After reset
X00000002
Function
Bit
name
RW
IICM
I2C mode select bit
0 : Other than I2C mode
1 : I2C mode
RW
ABC
Arbitration lost detecting
flag control bit
0 : Update per bit
1 : Update per byte
RW
BBS
Bus busy flag
0 : STOP condition detected
1 : START condition detected (busy)
RW
(Note1)
Reserved bit
Set to “0”
RW
ABSCS
Bus collision detect
sampling clock select bit
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj (Note 2)
RW
ACSE
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
RW
SSS
Transmit start condition
select bit
0 : Not synchronizedi to RxDi
1 : Synchronized to RxDi (Note 3)
RW
(b3)
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
Note 2: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
Note 3: When a transfer begins, the SSS bit is set to “0” (Not synchronized .to RxDi)
Figure 2.11.6. UCON Register and U0SMR to U2SMR Registers
Rev.1.00
2004.03.23
page 114 of 320
M306H3MC-XXXFP/FCFP
UARTi special mode register 2 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
U0SMR2 to U2SMR2 036E16, 037216, 037616
Bit
symbol
Bit name
After reset
X00000002
Function
RW
IICM2
I 2C mode select bit 2
Refer to Table 2.11.12
CSC
Clock-synchronous bit
0 : Disabled
1 : Enabled
RW
SWC
SCL wait output bit
0 : Disabled
1 : Enabled
RW
ALS
SDA output stop bit
0 : Disabled
1 : Enabled
RW
STAC
UARTi initialization bit
0 : Disabled
1 : Enabled
RW
SWC2
SCL wait output bit 2
0: Transfer clock
1: “L” output
RW
SDHI
SDA output disable bit
0: Enabled
1: Disabled (high impedance)
RW
RW
Nothing is assigned. When write, set “0”. When read, its content is
indeterminate.
(b7)
UARTi special mode register 3 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR3 to U2SMR3
Bit
symbol
(b0)
CKPH
(b2)
NODC
(b4)
DL0
DL1
DL2
Address
036D16, 037116, 037516
Bit name
After reset
000X0X0X2
Function
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Clock phase set bit
0 : Without clock delay
1 : With clock delay
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Clock output select bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
SDAi digital delay
setup bit
(Note 1, Note 2)
b7 b6 b5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Without delay
1 : 1 to 2 cycle(s) of UiBRG count source
0 : 2 to 3 cycles of UiBRG count source
1 : 3 to 4 cycles of UiBRG count source
0 : 4 to 5 cycles of UiBRG count source
1 : 5 to 6 cycles of UiBRG count source
0 : 6 to 7 cycles of UiBRG count source
1 : 7 to 8 cycles of UiBRG count source
RW
RW
RW
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C
mode, set these bits to “0002” (no delay).
Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
Figure 2.11.7. U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
Rev.1.00
2004.03.23
page 115 of 320
M306H3MC-XXXFP/FCFP
UARTi special mode register 4 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
U0SMR4 to U2SMR4 036C16, 037016, 037416
Bit
symbol
Bit name
RW
0 : Clear
1 : Start
RW
RSTAREQ Restart condition
generate bit (Note)
0 : Clear
1 : Start
RW
STPREQ
Stop condition
generate bit (Note)
0 : Clear
1 : Start
RW
STSPSEL
SCL,SDA output
select bit
0 : Start and stop conditions not output
1 : Start and stop conditions output
RW
ACKD
ACK data bit
0 : ACK
1 : NACK
RW
ACKC
ACK data output
enable bit
0 : Serial I/O data output
1 : ACK data output
RW
SCLHI
SCL output stop
enable bit
0 : Disabled
1 : Enabled
RW
SWC9
SCL wait bit 3
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled
RW
Note: Set to “0” when each condition is generated.
Figure 2.11.8. U0SMR4 to U2SMR4 Registers
2004.03.23
Function
Start condition
generate bit (Note)
STAREQ
Rev.1.00
After reset
0016
page 116 of 320
M306H3MC-XXXFP/FCFP
2.11.2 Clock Synchronous serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 2.11.1
lists the specifications of the clock synchronous serial I/O mode. Table 2.11.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
Table 2.11.1. Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
0016 to FF16
Transmission, reception control
Transmission start condition
Reception start condition
• CKDIR bit = “1” (external clock) : Input from CLKi pin
_______
_______
_______ _______
• Selectable from CTS function, RTS function or CTS/RTS function disable
• Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in UiTB register)
_
If CTS function is selected, input on the CTSi pin = “L”
_______
_______
• Before reception can start, the following requirements must be met (Note 1)
_
_
The RE bit of UiC1 register= 1 (reception enabled)
The TE bit of UiC1 register= 1 (transmission enabled)
_
Interrupt request
generation timing
The TI bit of UiC1 register= 0 (data present in the UiTB register)
• For transmission, one of the following conditions can be selected
_
The UiIRS bit (Note 3) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
Error detection
completion of reception)
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function
• CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______ _______
• Separate CTS/RTS pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 3: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Rev.1.00
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page 117 of 320
M306H3MC-XXXFP/FCFP
Table 2. 11. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
UiTB(Note3)
Bit
0 to 7
UiRB(Note3) 0 to 7
UiBRG
Reception data can be read
OER
Overrun error flag
0 to 7
Set a transfer rate
UiMR(Note3) SMD2 to SMD0
UiC0
Function
Set transmission data
Set to “0012”
CKDIR
Select the internal clock or external clock
IOPOL
Set to “0”
CLK1 to CLK0
Select the count source for the UiBRG register
CRS
Select CTS or RTS to use
TXEPT
Transmit register empty flag
CRD
Enable or disable the CTS or RTS function
NCH
Select TxDi pin output mode (Note 2)
CKPOL
Select the transfer clock polarity
UFORM
Select the LSB first or MSB first
TE
Set this bit to “1” to enable transmission/reception
_______
_______
_______
UiC1
_______
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (Note 1)
Select the source of UART2 transmit interrupt
U2RRM (Note 1)
Set this bit to “1” to use continuous receive mode
UiLCH
Set this bit to “1” to use inverted data logic
UiERE
Set to “0”
UiSMR
0 to 7
Set to “0”
UiSMR2
0 to 7
Set to “0”
UiSMR3
0 to 2
Set to “0”
NODC
Select clock output mode
4 to 7
Set to “0”
UiSMR4
0 to 7
Set to “0”
UCON
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM
Set this bit to “1” to use continuous receive mode
CLKMD0
Select the transfer clock output pin when CLKMD1 = 1
CLKMD1
Set this bit to “1” to output UART1 transfer clock from two pins
RCSP
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7
Set to “0”
_________
Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
i=0 to 2
Rev.1.00
2004.03.23
page 118 of 320
M306H3MC-XXXFP/FCFP
Table 2.11.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
2.11.3 shows pin functions for the case where the multiple transfer clock output pin select function is
deselected. Table 2.11.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that
for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs
an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)
Table 2.11.3. Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name
Function
Method of selection
TxDi (i = 0 to 2) Serial data output
(P63, P67, P70)
(Outputs dummy data when performing reception only)
Serial data input
RxDi
(P62, P66, P71)
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
CLKi
Transfer clock output
(P61, P65, P72)
Transfer clock input
UiMR register’s CKDIR bit=0
CTSi/RTSi
CTS input
(P60, P64, P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
RTS output
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
I/O port
UiC0 register’s CRD bit=1
Table 2.11.4. P64 Pin Functions
Pin function
P64
CTS1
RTS1
CTS0(Note1)
CLKS1
Bit set value
U1C0 register
CRS
CRD
1
0
0
0
1
0
0
RCSP
0
0
0
1
UCON register
CLKMD1 CLKMD0
0
0
0
0
1(Note 2)
PD6 register
PD6_4
Input: 0, Output: 1
0
0
1
Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0
C0 register’s CRS bit to “1” (RTS0 selected).
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the U1C0 register’s CLKPOL bit = 0
• Low if the U1C0 register’s CLKPOL bit = 1
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(1) Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
“1”
“0”
Write data to the UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
CTSi
“L”
TCLK
Stopped pulsing because CTSi = “H”
Stopped pulsing because the TE bit = “0”
CLKi
TxDi
D0 D 1 D2 D3 D4 D5 D6 D7
UiC0 register
TXEPT bit
“1”
SiTIC register
IR bit
“1”
D 0 D 1 D 2 D3 D4 D 5 D 6 D 7
D 0 D 1 D 2 D 3 D 4 D 5 D6 D 7
“0”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
i: 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register CKDIR bit = 0 (internal clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
(2) Example of receive timing (when external clock is selected)
“1”
UiC1 register
RE bit
“0”
UiC1 register
TE bit
“0”
UiC1 register
TI bit
“1”
“0”
“H”
RTSi
Write dummy data to UiTB register
“1”
Transferred from UiTB register to UARTi transmit register
“L”
Even if the reception is completed, the RTS
does not change. The RTS becomes “L”
when the RI bit changes to “0” from “1”.
1 / fEXT
CLKi
Receive data is taken in
D0 D1 D 2 D3 D 4 D5 D6 D 7
RxDi
UiC1 register
RI bit
“1”
SiRIC register
IR bit
“1”
Transferred from UARTi receive register
to UiRB register
D0 D 1 D 2
D3 D 4 D 5
Read out from UiRB register
“0”
“0”
Cleared to “0” when interrupt request is
accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
Make sure the following conditions are met when input
as follows:
to the CLKi pin before receiving data is high:
• UiMR register CKDIR bit = 1 (external clock)
• UiC1 register TE bit = 1 (transmit enabled)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
• UiC1 register RE bit = 1 (Receive enabled)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive • Write dummy data to the UiTB register
data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock
Figure 2.11.9. Transmit and Receive Operation
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M306H3MC-XXXFP/FCFP
(a) CLK Polarity Select Function
Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 2.11.10
shows the polarity of the transfer clock.
(1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLKi
(Note 2)
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
(Note 3)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
R XD i
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: This applies to the case where the UiC0 register’s UFORM bit = 0
(LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).
Note 2: When not transferring, the CLKi pin outputs a high signal.
Note 3: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 2.11.10. Transfer Clock Polarity
(b) LSB First/MSB First Select Function
Use the UiC0 register (i = 0 to 2)’s UFORM bit to select the transfer format. Figure 2.11.11 shows the
transfer format.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
R XD i
D7
D6
D5
D4
D3
D2
D1
D0
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register’s
UiLCH bit = 0 (no reverse).
i = 0 to 2
Figure 2.11.11. Transfer Format
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M306H3MC-XXXFP/FCFP
(c) Continuous Receive Mode
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “0”
(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not
write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON
register bit 2 and bit 3, respectively, and the U2RRM bit is the U2C1 register bit 5.
(d) Serial Data Logic Switching Function
When the UiC1 register (i = 0 to 2)’s UiLCH bit = 1 (reverse), the data written to the UiTB register has
its logic reversed before being transmitted. Similarly, the received data has its logic reversed when
read from the UiRB register. Figure 2.11.12 shows serial data logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(no reverse) “L”
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(reverse)
“L”
D0
D1
D2
D3
D4
D5
D6
D7
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
i = 0 to 2
Figure 2.11.12. Serial Data Logic Switching
(e) Transfer Clock Output From Multiple Pins (UART1)
Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins.
(See Figure 2.11.13.) This function can be used when the selected transfer clock for UART1 is an
internal clock.
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
IN
CLK
CLK
Transfer enabled
when the UCON
register's
CLKMD0 bit = 0
Transfer enabled
when the UCON
register's
CLKMD0 bit = 1
Note: This applies to the case where the U1MRregister's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1 (
transfer clock output from multiple pins).
Figure 2.11.13. Transfer Clock Output From Multiple Pins
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M306H3MC-XXXFP/FCFP
_______ _______
(f) CTS/RTS Separate Function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
TXD0 (P63)
RXD0 (P62)
IN
OUT
CLK0 (P61)
CLK
RTS0 (P60)
CTS
CTS0 (P64)
RTS
_______ _______
Figure 2.11.14. CTS/RTS Separat Function
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M306H3MC-XXXFP/FCFP
2.11.3 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 2.11.5 lists the specifications of the UART mode.
Table 2.11.5. UART Mode Specifications
Item
Transfer data format
Transfer clock
Transmission, reception control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Specification
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
• UiMR(i=0 to 2) register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
0016 to FF16
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
fEXT: Input from CLKi pin. n :Setting value of UiBRG register
0016 to FF16
_______
_______
_______ _______
• Selectable from CTS function, RTS function or CTS/RTS function disable
• Before transmission can start, the following requirements must be met
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______
_______
_ If CTS function is selected, input on the CTSi pin = “L”
• Before reception can start, the following requirements must be met
_ The RE bit of UiC1 register= 1 (reception enabled)
_ Start bit detection
• For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
_______ _______
• Separate CTS/RTS pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
Note 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
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M306H3MC-XXXFP/FCFP
Table 2. 11. 6. Registers to Be Used and Settings in UART Mode
Register
UiTB
UiRB
Bit
Function
0 to 8
Set transmission data (Note 1)
0 to 8
Reception data can be read (Note 1)
OER,FER,PER,SUM Error flag
UiBRG
0 to 7
Set a transfer rate
UiMR
SMD2 to SMD0
Set these bits to ‘1002’ when transfer data is 7 bits long
Set these bits to ‘1012’ when transfer data is 8 bits long
Set these bits to ‘1102’ when transfer data is 9 bits long
UiC0
CKDIR
Select the internal clock or external clock
STPS
Select the stop bit
PRY, PRYE
Select whether parity is included and whether odd or even
IOPOL
Select the TxD/RxD input/output polarity
CLK0, CLK1
Select the count source for the UiBRG register
CRS
Select CTS or RTS to use
TXEPT
Transmit register empty flag
CRD
Enable or disable the CTS or RTS function
NCH
Select TxDi pin output mode (Note 2)
CKPOL
Set to “0”
UFORM
LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
_______
_______
_______
_______
bit to “0” when transfer data is 7 or 9 bits long.
UiC1
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (Note 2)
Select the source of UART2 transmit interrupt
U2RRM (Note 2)
Set to “0”
UiLCH
Set this bit to “1” to use inverted data logic
UiERE
Set to “0”
UiSMR
0 to 7
Set to “0”
UiSMR2
0 to 7
Set to “0”
UiSMR3
0 to 7
Set to “0”
UiSMR4
0 to 7
Set to “0”
UCON
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM
Set to “0”
CLKMD0
Invalid because CLKMD1 = 0
CLKMD1
Set to “0”
RCSP
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7
Set to “0”
_________
Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long;
bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
Note 3: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
i=0 to 2
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M306H3MC-XXXFP/FCFP
Table 2.11.7 lists the functions of the input/output pins during UART mode. Table 2.11.8 lists the P64 pin
functions during UART mode. Note that for a period from when the UARTi operation mode is selected to
when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin
is in a high-impedance state.)
Table2.11.7. I/O Pin Functions
Pin name
Function
Method of selection
TxDi (i = 0 to 2) Serial data output
(P63, P67, P70)
(Outputs dummy data when performing reception only)
Serial data input
RxDi
(P62, P66, P71)
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
CLKi
Input/output port
(P61, P65, P72)
Transfer clock input
UiMR register’s CKDIR bit=0
CTSi/RTSi
CTS input
(P60, P64, P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
RTS output
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
Input/output port
UiC0 register’s CRD bit=1
Table 2.11.8. P64 Pin Functions
Pin function
Bit set value
U1C0 register
CRS
CRD
P64
CTS1
RTS1
CTS0 (Note)
1
0
0
0
0
1
0
UCON register
RCSP CLKMD1
0
0
0
1
0
0
0
0
PD6 register
PD6_4
Input: 0, Output: 1
0
0
Note: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0
enabled) and the U0C0 register’s CRS bit to “1” (RTS0 selected).
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M306H3MC-XXXFP/FCFP
(1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
Tc
Transfer clock
UiC1 register
TE bit
“1”
“0”
UiC1 register
TI bit
Write data to the UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
CTSi
“L”
Start
bit
TxDi
ST D0 D1 D2 D3 D4 D5 D6 D7
UiC0 register
TXEPT bit
Stopped pulsing
because the TE bit
= “0”
Parity Stop
bit bit
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1
“1”
“0”
SiTIC register
IR bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 1 (parity enabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
(2) Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
“1”
Write data to the UiTB register
“0”
“1”
“0”
Start
bit
TxDi
Stop Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
UiC0 register
TXEPT bit
“1”
SiTIC register
IR bit
“1”
Transferred from UiTB register to UARTi
transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
“0”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
The above timing diagram applies to the case where the register bits are set
as follows:
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
• UiMR register PRYE bit = 0 (parity disabled)
fEXT : frequency of UiBRG count source (external clock)
• UiMR register STPS bit = 1 (2 stop bits)
n : value set to UiBRG
• UiC0 register CRD bit = 1 (CTS/RTS disabled)
i: 0 to 2
• UiRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 2.11.15. Transmit Operation
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M306H3MC-XXXFP/FCFP
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
UiC1 register
RE bit
“1”
“0”
Stop bit
Start bit
RxDi
D7
D1
D0
Sampled “L”
Receive data taken in
Transfer clock
UiC1 register
RI bit
RTSi
SiRIC register
IR bit
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Transferred from UARTi receive
register to UiRB register
“0”
“H”
“L”
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 2.11.16. Receive Operation
(a) LSB First/MSB First Select Function
As shown in Figure 2.11.17, use the UiC0 register’s UFORM bit to select the transfer format. This
function is valid when transfer data is 8 bits long.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi
TXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
RXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiC1 register’s UiLCH
bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and
UiMR register's PRYE bit = 1 (parity enabled).
Figure 2.11.17. Transfer Format
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ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
M306H3MC-XXXFP/FCFP
(b) Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register. Figure 2.11.18 shows serial
data logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(no reverse)
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
D5
D6
D7
P
SP
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(reverse)
“L”
ST
D0
D1
D2
D3
D4
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge of the transfer clock), the
UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's
STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity
enabled).
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Figure 2.11.18. Serial Data Logic Switching
(c) TxD and RxD I/O Polarity Inverse Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all
input/output data (including the start, stop and parity bits) are inversed. Figure 2.11.19 shows the TXD
pin output and RXD pin input polarity inverse.
(1) When the UiMR register's IOPOL bit = 0 (no reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(no reverse) “L”
RxDi
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(no reverse) “L”
(2) When the UiMR register's IOPOL bit = 1 (reverse)
Transfer clock
“H”
“L”
TxDi
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(reverse)
RxDi
(reverse)
Note: This applies to the case where the UiC0 register's UFORM bit = 0
(LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and the
UiMR register's PRYE bit = 1 (parity enabled).
Figure 2.11.19. TXD and RXD I/O Polarity Inverse
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ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
M306H3MC-XXXFP/FCFP
_______ _______
(d) CTS/RTS Separate Function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
TXD0 (P63)
RXD0 (P62)
IN
OUT
RTS0 (P60)
CTS
CTS0 (P64)
RTS
_______ _______
Figure 2.11.20. CTS/RTS Separate Function
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M306H3MC-XXXFP/FCFP
2.11.4 Special Mode 1 (I2C mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Table 2.11.9 lists the specifications of the I2C mode. Table 2.11.10 lists the registers used in the I2C mode and the register values
set. Figure 2.11.21 shows the block diagram for I2C mode. Figure 2.11.22 shows SCLi timing.
As shown in Table 2.11.12, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits
to ‘0102’ and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output
does not change state until SCLi goes low and remains stably low.
Table 2.11.9. I2C Mode Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• During master
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• During slave
CKDIR bit = “1” (external clock) : Input from SCLi pin
Transmission start condition
• Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_
Reception start condition
The TI bit of UiC1 register = 0 (data present in UiTB register)
• Before reception can start, the following requirements must be met (Note 1)
_
_
The RE bit of UiC1 register= 1 (reception enabled)
The TE bit of UiC1 register= 1 (transmission enabled)
_
Interrupt request
generation timing
Error detection
The TI bit of UiC1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
Select function
• Arbitration lost
Timing at which the UiRB register’s ABT bit is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the
high state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC
register does not change.
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M306H3MC-XXXFP/FCFP
Start and stop condition generation block
SDAi
STSPSEL=1
Delay
circuit
SDASTSP
SCLSTSP
STSPSEL=0
ACK=1
IICM2=1
Transmission
register
ACK=0
IICM=1 and
IICM2=0
UARTi
SDHI
ACKD register
D
DMA0
(UART0, UART2)
Arbitration
Q
IICM2=1
Reception register
UARTi
IICM=1 and
IICM2=0
Start condition
detection
S
R
Q
NACK
D Q
T
Falling edge
detection
IICM=0
R
I/O port
Q
STSPSEL=0
IICM=1 UARTi
Noise
Filter
UARTi receive,
ACK interrupt request,
DMA1 request
Bus
busy
Stop condition
detection
SCLi
UARTi transmit,
NACK interrupt
request
ALS
T
Noise
Filter
DMA0, DMA1 request
(UART1: DMA0 only)
D Q
T
Port register
(Note)
Internal clock
SWC2
STSPSEL=1 External
clock
ACK
9th bit
Start/stop condition detection
interrupt request
CLK
control
UARTi
R
S
9th bit falling edge
SWC
This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1.
IICM
: UiSMR register bit
IICM2, SWC, ALS, SWC2, SDHI : UiSMR2 register bit
STSPSEL, ACKD, ACKC
: UiSMR4 register bit
i=0 to 2
Note: If the IICM bit = 1, the pin can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
Figure 2.11.21. I2C Mode Block Diagram
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M306H3MC-XXXFP/FCFP
Table2.11.10. Registers to Be Used and Settings in I2C Mode (1) (Continued)
Register
UiTB3
UiRB3
UiBRG
UiMR3
UiC0
UiC1
UiSMR
Bit
0 to 7
0 to 7
8
ABT
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS1
U2RRM1,
UiLCH, UiERE
IICM
ABC
BBS
3 to 7
UiSMR2 IICM2
CSC
SWC
ALS
STAC
Function
Master
Slave
Set transmission data
Set transmission data
Reception data can be read
Reception data can be read
ACK or NACK is set in this bit
ACK or NACK is set in this bit
Arbitration lost detection flag
Invalid
Overrun error flag
Overrun error flag
Set a transfer rate
Invalid
Set to ‘0102’
Set to ‘0102’
Set to “0”
Set to “1”
Set to “0”
Set to “0”
Select the count source for the UiBRG
Invalid
register
Invalid because CRD = 1
Invalid because CRD = 1
Transmit buffer empty flag
Transmit buffer empty flag
Set to “1”
Set to “1”
Set to “1”2
Set to “1”2
Set to “0”
Set to “0”
Set to “1”
Set to “1”
Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission
Transmit buffer empty flag
Transmit buffer empty flag
Set this bit to “1” to enable reception
Set this bit to “1” to enable reception
Reception complete flag
Reception complete flag
Invalid
Invalid
Set to “0”
Set to “0”
Set to “1”
Select the timing at which arbitration-lost
is detected
Bus busy flag
Set to “0”
Refer to Table 2.11.12
Set this bit to “1” to enable clock
synchronization
Set this bit to “1” to have SCLi output
fixed to “L” at the falling edge of the 9th
bit of clock
Set this bit to “1” to have SDAi output
stopped when arbitration-lost is detected
Set to “0”
SWC2
Set this bit to “1” to have SCLi output
forcibly pulled low
SDHI
Set this bit to “1” to disable SDAi output
7
Set to “0”
UiSMR3 0, 2, 4 and NODC Set to “0”
CKPH
Refer to Table 2.11.12
DL2 to DL0
Set the amount of SDAi digital delay
Set to “1”
Invalid
Bus busy flag
Set to “0”
Refer to Table 2.11.12
Set to “0”
Set this bit to “1” to have SCLi output
fixed to “L” at the falling edge of the 9th
bit of clock
Set to “0”
Set this bit to “1” to initialize UARTi at
start condition detection
Set this bit to “1” to have SCLi output
forcibly pulled low
Set this bit to “1” to disable SDAi output
Set to “0”
Set to “0”
Refer to Table 2.11.12
Set the amount of SDAi digital delay
i=0 to 2
Notes:
1. Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TxD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C mode.
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M306H3MC-XXXFP/FCFP
Table 2.11.11. Registers to Be Used and Settings in I2C Mode (2) (Continued)
Register
Bit
UiSMR4 STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
IFSR2A IFSR26, ISFR27
UCON U0IRS, U1IRS
2 to 7
Function
Master
Slave
Set this bit to “1” to generate start
Set to “0”
condition
Set this bit to “1” to generate restart
Set to “0”
condition
Set this bit to “1” to generate stop
Set to “0”
condition
Set this bit to “1” to output each condition Set to “0”
Select ACK or NACK
Select ACK or NACK
Set this bit to “1” to output ACK data
Set this bit to “1” to output ACK data
Set this bit to “1” to have SCLi output
Set to “0”
stopped when stop condition is detected
Set to “0”
Set this bit to “1” to set the SCLi to “L”
hold at the falling edge of the 9th bit of
clock
Set to “1”
Set to “1”
Invalid
Invalid
Set to “0”
Set to “0”
i=0 to 2
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M306H3MC-XXXFP/FCFP
Table 2.11.12. I2C Mode Functions
Clock synchronous serial I/O
I2C mode (SMD2 to SMD0 = 0102, IICM = 1)
mode (SMD2 to SMD0 = 0012, IICM2 = 0
IICM2 = 1
IICM = 0)
(NACK/ACK interrupt)
(UART transmit/ receive interrupt)
CKPH = 1
CKPH = 0
CKPH = 0
CKPH = 1
(Clock delay)
(No clock delay) (Clock delay) (No clock delay)
Function
Factor of interrupt number
6, 7 and 10 (Note 1, 5, 7)
Start condition detection or stop condition detection
(Refer to “Table 2.11.13. STSPSEL Bit Functions”)
Factor of interrupt number UARTi transmission
15, 17 and 19 (Note 1, 6) Transmission started or
completed (selected by UiIRS)
Factor of interrupt number UARTi reception
16, 18 and 20 (Note 1, 6) When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Timing for transferring data CKPOL = 0 (rising edge)
from the UART reception CKPOL = 1 (falling edge)
shift register to the UiRB
register
UARTi transmission output Not delayed
delay
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
Acknowledgment detection
(ACK)
Rising edge of SCLi 9th bit
Rising edge of SCLi 9th bit
UARTi transmission UARTi transmission
Falling edge of SCLi
Rising edge of
next to the 9th bit
SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Falling edge of
SCLi 9th bit
Falling and rising
edges of SCLi 9th
bit
Delayed
Functions of P63, P67 and TxDi output
P70 pins
SDAi input/output
Functions of P62, P66 and RxDi input
P71 pins
SCLi input/output
(Cannot be used in I2C mode)
Functions of P61, P65 and
P72 pins
CLKi input or output selected
Noise filter width
15ns
Read RxDi and SCLi pin
levels
Always possible no matter how the corresponding port direction bit is set
Possible when the
corresponding port direction bit
=0
CKPOL = 0 (H)
The value set in the port register before setting I2C mode (Note 2)
CKPOL = 1 (L)
Initial value of TxDi and
SDAi outputs
Initial and end values of
SCLi
H
DMA1 factor (Refer to Fig
2.11.22)
UARTi reception
Store received data
1st to 8th bits are stored in
UiRB register bit 0 to bit 7
Read received data
200ns
UiRB register status is read
directly as is
L
Acknowledgment detection
(ACK)
1st to 8th bits are stored in
UiRB register bit 7 to bit 0
H
L
UARTi reception
Falling edge of SCLi 9th bit
1st to 7th bits are stored in UiRB register
bit 6 to bit 0, with 8th bit stored in UiRB
register bit 8
1st to 8th bits are
stored in UiRB
register bit 7 to bit 0
(Note 3)
Read UiRB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 (Note 4)
i = 0 to 2
Note 1: If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to “precautions for interrupts” of the Usage Notes Reference Book.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
Note 2: Set the initial value of SDAi output while the UiMR register’s SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
Note 3: Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
Note 4: First data transfer to UiRB register (Falling edge of SCLi 9th bit)
Note 5: Refer to “Figure 2.11.24. STSPSEL Bit Functions”.
Note 6: Refer to “Figure 2.11.22. Transfer to UiRB Register and Interrupt Timing”
.
Note 7: When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (cause of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR26 bit in the IFSR2A register to “1” (cause of interrupt: UART1 bus collision).
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M306H3MC-XXXFP/FCFP
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
D7
SDAi
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
•••
b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
D3
D2
D1
UiRB register
(2) IICM2= 0, CKPH= 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
D7
SDAi
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
•••
b8
b7
D8
D7
b0
D6
D5
D4
D3
UiRB register
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
D7
SDAi
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transmit interrupt
Transfer to UiRB register
b15
b9
b8
b7
b0
D0
•••
D7
D6
D5
D4
UiRB register
(4) IICM2= 1, CKPH= 1
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transfer to UiRB register
b15
b9
•••
b8
D0
b7
b0
D7
D6
D5
D4
D3
D2
D1
Transmit interrupt
Transfer to UiRB register
b15
b9
•••
UiRB register
i=0 to 2
This diagram applies to the case where the following condition is met.
• UiMR register CKDIR bit = 0 (Slave selected)
Figure 2.11.22. Transfer to UiRB Register and Interrupt Timing
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b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
UiRB register
D1
D0
M306H3MC-XXXFP/FCFP
• Detection of Start and Stop Condtion
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated
when the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the UiSMR register’s BBS bit to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
Duration for
setting up
Duration for
holding
SCLi
SDAi
(Start condition)
SDA i
(Stop condition)
i = 0 to 2
Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of
f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.
Figure 2.11.23. Detection of Start and Stop Condition
• Output of Start and Stop Condition
A start condition is generated by setting the UiSMR4 register (i = 0 to 2)’s STAREQ bit to “1” (start).
A restart condition is generated by setting the UiSMR4 register’s RSTAREQ bit to “1” (start).
A stop condition is generated by setting the UiSMR4 register’s STPREQ bit to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the UiSMR4 register to “1” (output).
The function of the STSPSEL bit is shown in Table 2.11.13 and Figure 2.11.24.
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M306H3MC-XXXFP/FCFP
Table 2.11.13. STSPSEL Bit Functions
STSPSEL = 0
Function
Output of transfer clock and
Output of SCLi and SDAi pins
data
Output of start/stop condition is
accomplished by a program
using ports (not automatically
generated in hardware)
Start/stop condition detection
Star/stop condition interrupt
request generation timing
STSPSEL = 1
Output of a start/stop condition
according to the STAREQ,
RSTAREQ and STPREQ bit
Finish generating start/stop condition
(1) When slave
CKDIR=1 (external clock)
STSPSEL bit 0
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi
SDAi
Start condition
detection interrupt
Stop condition
detection interrupt
(2) When master
CKDIR=0 (internal clock), CKPH=1 (clock delayed)
STSPSEL bit
Set to “1” in
a program
Set to “0” in
a program
Set to “1” in
a program
Set to “0” in
a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi
SDAi
Set STAREQ=
1 (start)
Start condition
detection interrupt
Set STPREQ=
1 (start)
Stop condition
detection interrupt
Figure 2.11.24. STSPSEL Bit Functions
• Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising
edge of SCLi. Use the UiSMR register’s ABC bit to select the timing at which the UiRB register’s ABT
bit is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time
unmatching is detected during check, and is cleared to “0” when not detected. In cases when the ABC
bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to “1” (unmatching
detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise,
clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte, before transferring
the next byte.
Setting the UiSMR2 register’s ALS bit to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit
is set to “1” (unmatching detected).
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M306H3MC-XXXFP/FCFP
• Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 2.11.24.
The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi)
and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchronization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the
internal SCLi goes low, at which time the UiBRG register value is reloaded with and starts counting in
the low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low,
counting stops, and when the SCLi pin goes high, counting restarts.
In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi
pin signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st
bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The UiSMR2 register’s SWC bit allows to select whether the SCLi pin should be fixed to or freed from
low-level output at the falling edge of the 9th clock pulse.
If the UiSMR4 register’s SCLHI bit is set to “1” (enabled), SCLi output is turned off (placed in the highimpedance state) when a stop condition is detected.
Setting the UiSMR2 register’s SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level
signal from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to “0” (transfer
clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a
low-level signal.
If the UiSMR4 register’s SWC9 bit is set to “1” (SCL hold low enabled) when the UiSMR3 register’s
CKPH bit = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the
ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
• SDA Output
The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.
The ninth bit (D8) is ACK or NACK.
The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the UiMR
register’s SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
The UiSMR3 register’s DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 UiBRG count source
clock cycles to SDAi output.
Setting the UiSMR2 register’s SDHI bit = 1 (SDA output disabled) forcibly places the SDAi pin in the
high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi
transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).
• SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit
7 to bit 0. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit
6 to bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing
the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB
register after the rising edge of the corresponding clock pulse of 9th bit.
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• ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and
the ACKC bit in the UiSMR4 register is se to “1” (ACK data output), the value of the ACKD bit in the
UiSMR4 register is output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising
edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low
at the rising edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
• Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O
operates as described below.
- The transmit shift register is initialized, and the content of the UiTB register is transferred to the
transmit shift register. In this way, the serial I/O starts sending data synchronously with the next
clock pulse applied. However, the UARTi output value does not change state and remains the same
as when a start condition was detected until the first bit of data is output synchronously with the input
clock.
- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
next clock pulse applied.
- The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
falling edge of the ninth clock pulse.
Note that when UARTi transmission/reception is started using this function, the TI does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.
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M306H3MC-XXXFP/FCFP
2.11.5 Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 2.11.14 lists the specifications of Special Mode 2. Table 2.11.15 lists the registers used
in Special Mode 2 and the register values set. Figure 2.11.25 shows communication control example for
Special Mode 2.
Table 2.11.14. Special Mode 2 Specifications
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• Master mode
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
• Slave mode
Transmit/receive control
Transmission start condition
0016 to FF16
CKDIR bit = “1” (external clock selected) : Input from CLKi pin
Controlled by input/output ports
• Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_
Reception start condition
The TI bit of UiC1 register = 0 (data present in UiTB register)
• Before reception can start, the following requirements must be met (Note 1)
_
The RE bit of UiC1 register= 1 (reception enabled)
The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register= 0 (data present in the UiTB register)
_
Interrupt request
generation timing
Error detection
Select function
• For transmission, one of the following conditions can be selected
The UiIRS bit of UiC1 register = 0 (transmit buffer empty): when transferring data
from the UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
_
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low
state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does
not change.
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M306H3MC-XXXFP/FCFP
P13
P12
P93
P72(CLK2)
P72(CLK2)
P71(RxD2)
P71(RxD2)
P70(TxD2)
P70(TxD2)
Microcomputer
(Master)
Microcomputer
(Slave)
P93
P72(CLK2)
P71(RxD2)
P70(TxD2)
Microcomputer
(Slave)
Figure 2.11.25. Serial Bus Communication Control Example (UART2)
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M306H3MC-XXXFP/FCFP
Table 2.11.15. Registers to Be Used and Settings in Special Mode 2
Register
Bit
UiTB(Note3) 0 to 7
UiRB(Note3) 0 to 7
OER
UiBRG
0 to 7
UiMR(Note3) SMD2 to SMD0
CKDIR
IOPOL
UiC0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
U2IRS (Note 1)
U2RRM(Note 1),
U2LCH, UiERE
UiSMR
0 to 7
UiSMR2
0 to 7
UiSMR3
CKPH
NODC
0, 2, 4 to 7
UiSMR4
0 to 7
UCON
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7
Function
Set transmission data
Reception data can be read
Overrun error flag
Set a transfer rate
Set to ‘0012’
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
Select TxDi pin output format(Note 2)
Clock phases can be set in combination with the UiSMR3 register's CKPH bit
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select UART2 transmit interrupt cause
Set to “0”
Set to “0”
Set to “0”
Clock phases can be set in combination with the UiC0 register's CKPOL bit
Set to “0”
Set to “0”
Set to “0”
Select UART0 and UART1 transmit interrupt cause
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Note 1: Set the U0C0 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in Special
Mode 2.
i = 0 to 2
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M306H3MC-XXXFP/FCFP
• Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3
register’s CKPH bit and the UiC0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
(a) Master (Internal Clock)
Figure 2.11.26 shows the transmission and reception timing in master (internal clock).
(b) Slave (External Clock)
Figure 2.11.27 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 2.11.28 shows the transmission and reception timing (CKPH=1) in slave (external clock).
"H"
Clock output
(CKPOL=0, CKPH=0) "L"
"H"
Clock output
(CKPOL=1, CKPH=0) "L"
Clock output
"H"
(CKPOL=0, CKPH=1) "L"
"H"
Clock output
(CKPOL=1, CKPH=1) "L"
Data output timing
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Figure 2.11.26. Transmission and Reception Timing in Master Mode (Internal Clock)
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M306H3MC-XXXFP/FCFP
"H"
Slave control input
"L"
"H"
Clock input
(CKPOL=0, CKPH=0) "L"
"H"
Clock input
(CKPOL=1, CKPH=0) "L"
Data output timing
"H"
(Note)
"L"
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Indeterminate
Note :UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 2.11.27. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
"H"
Slave control input
"L"
"H"
Clock input
(CKPOL=0, CKPH=1) "L"
"H"
Clock input
(CKPOL=1, CKPH=1) "L"
Data output timing
(Note)
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Note :UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 2.11.28. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
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M306H3MC-XXXFP/FCFP
2.11.6 Special Mode 3 (IE mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 2.11.16 lists the registers used in IE mode and the register values set. Figure 2.11.29 shows the
functions of bus collision detect function related bits.
If the TxDi pin (i = 0 to 2) output level and RxDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR2A register’s IFSR26 and IFSR27 bits to enable the UART0/UART1 bus collision detect
function.
Table 2.11.16. Registers to Be Used and Settings in IE Mode
Register
Bit
UiTB
0 to 8
UiRB(Note3) 0 to 8
OER,FER,PER,SUM
UiBRG
0 to 7
UiMR
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
UiC0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
U2IRS (Note 1)
UiRRM (Note 1),
UiLCH, UiERE
UiSMR
0 to 3, 7
ABSCS
ACSE
SSS
UiSMR2
0 to 7
UiSMR3
0 to 7
UiSMR4
0 to 7
IFSR2A
IFSR26, IFSR27
UCON
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1,RCSP,7
Function
Set transmission data
Reception data can be read
Error flag
Set a transfer rate
Set to ‘1102’
Select the internal clock or external clock
Set to “0”
Invalid because PRYE=0
Set to “0”
Select the TxD/RxD input/output polarity
Select the count source for the UiBRG register
Invalid because CRD=1
Transmit register empty flag
Set to “1”
Select TxDi pin output mode (Note 2)
Set to “0”
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
Select the transmit start condition
Set to “0”
Set to “0”
Set to “0”
Set to “1”
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Note 1: Set the U0C0 and U1C1 registers bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in IEmode.
i= 0 to 2
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M306H3MC-XXXFP/FCFP
(1) UiSMR register ABSCS bit (bus collision detect sampling clock select)
(i=0 to 2)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
Input to TAjIN
Timer Aj
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
(2) UiSMR register ACSE bit (auto clear of transmit enable bit)
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
UiBCNIC register
IR bit (Note)
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to “0”
(transmission disabled) when
the UiBCNIC register’s IR bit = 1
(unmatching detected).
UiC1 register
TE bit
Note: BCNIC register when UART2.
(3) UiSMR register SSS bit (Transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
D6
D7
D8
SP
TxDi
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi
CLKi
ST
TxDi
D0
D1
D2
D3
D4
D5
(Note 2)
RxDi
Note 1: The falling edge of RxDi when IOPOL=0; the rising edge of RxDi when IOPOL =1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 2.11.29. Bus Collision Detect Function-Related Bits
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M306H3MC-XXXFP/FCFP
2.11.7 Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TxD2 pin when a parity error is detected.
Tables 2.11.17 lists the specifications of SIM mode. Table 2.11.18 lists the registers used in the SIM
mode and the register values set.
Table 2.11.17. SIM Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
generation timing
(Note 2)
Error detection
Specification
• Direct format
• Inverse format
• U2MR register’s CKDIR bit = “0” (internal clock) : fi/ 16(n+1)
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register
0016 to FF16
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
fEXT: Input from CLK2 pin. n: Setting value of U2BRG register
0016 to FF16
• Before transmission can start, the following requirements must be met
_ The TE bit of U2C1 register= 1 (transmission enabled)
_ The TI bit of U2C1 register = 0 (data present in U2TB register)
• Before reception can start, the following requirements must be met
_ The RE bit of U2C1 register= 1 (reception enabled)
_ Start bit detection
• For transmission
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit =1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Note 1: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change.
Note 2: A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM
mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
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Table 2.11.18. Registers to Be Used and Settings in SIM Mode
Register
Bit
U2TB(Note) 0 to 7
U2RB(Note) 0 to 7
OER,FER,PER,SUM
U2BRG
0 to 7
U2MR
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
Function
Set transmission data
Reception data can be read
Error flag
Set a transfer rate
Set to ‘1012’
Select the internal clock or external clock
Set to “0”
Set this bit to “1” for direct format or “0” for inverse format
Set to “1”
Set to “0”
U2C0
CLK1, CLK0
Select the count source for the U2BRG register
CRS
Invalid because CRD=1
U2C1
TXEPT
Transmit register empty flag
CRD
Set to “1”
NCH
Set to “0”
CKPOL
Set to “0”
UFORM
Set this bit to “0” for direct format or “1” for inverse format
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS
Set to “1”
U2RRM
Set to “0”
U2LCH
Set this bit to “0” for direct format or “1” for inverse format
U2ERE
Set to “1”
U2SMR(Note) 0 to 3
Set to “0”
U2SMR2
0 to 7
Set to “0”
U2SMR3
0 to 7
Set to “0”
U2SMR4
0 to 7
Set to “0”
Note: Not all register bits are described above. Set those bits to “0” when writing to the registers in SIM mode.
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M306H3MC-XXXFP/FCFP
(1) Transmission
Tc
Transfer clock
U2C1 register “1”
TE bit “0”
Write data to U2TB register
U2C1 register “1”
TI bit
“0”
Transferred from U2TB register to UART2 transmit register
Parity Stop
bit
bit
Start
bit
TxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
Parity error signal sent
back from receiver
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
An “L” level returns due to the
occurrence of a parity error.
RxD2 pin level
(Note)
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
The level is detected by the
interrupt routine.
U2C0 register “1”
TXEPT bit “0”
The level is
detected by the
interrupt routine.
The IR bit is set to “1” at the
falling edge of transfer clock
S2TIC register “1”
IR bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where data is transferred in
the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Note : Because TxD2 and RxD2 are connected, this is composite waveform consisting of the TxD2 output and the parity error signal
sent back from receiver.
(1) Reception
Tc
Transfer clock
U2C1 register “1”
RE bit
“0”
ParityStop
bit bit
Start
bit
Transmitter's
transmit waveform
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
TxD2
An “L” level is output from TxD2 due to
the occurrence of a parity error
RxD2 pin level
(Note)
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
U2C0 register “1”
RI bit
“0”
Read the U2RB register
S2RIC register “1”
IR bit
Read the U2RB register
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where data is received in
direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Note : Because TxD2 and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the
parity error signal received.
Figure 2.11.30. Transmit and Receive Timing in SIM Mode
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M306H3MC-XXXFP/FCFP
Figure 2.11.31 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Microcomputer
SIM card
TxD2
RxD2
Figure 2.11.31. SIM Interface Connection
(a) Parity Error Signal Output
The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 2.11.32. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
Transfer
clock
“H”
RxD2
“H”
TxD2
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
“L”
Note: The output of microcomputer is in the high-impedance state
(pulled up externally).
Figure 2.11.32. Parity Error Signal Output Timing
2004.03.23
P
SP
(Note)
U2C1 register “1”
RI bit “0”
This timing diagram applies to the case where the direct format is
implemented.
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D7
“L”
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ST : Start bit
P : Even Parity
SP : Stop bit
M306H3MC-XXXFP/FCFP
(b) Format
• Direct Format
Set the U2MR register's PRY bit to “1”, U2C0 register's UFORM bit to “0” and U2C1 register's U2LCH
bit to “0”.
• Inverse Format
Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”.
Figure 2.11.33 shows the SIM interface format.
(1) Direct format
Transfer
clcck
“H”
TxD2
“H”
“L”
“L”
D0
D1
D2
D3
D4
D5
D6
D7
P
P : Even parity
(2) Inverse format
Transfer
clcck
TxD2
“H”
“L”
“H”
“L”
D7
D6
D5
D4
D3
D2
D1
D0
P
P : Odd parity
Figure 2.11.33. SIM Interface Format
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M306H3MC-XXXFP/FCFP
2.11.8 SI/O3 and SI/O4
SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os.
Figure 2.11.34 shows the block diagram of SI/O3 and SI/O4, and Figure 2.11.35 shows the SI/O3 and SI/O4related registers.
Table 2.11.19 shows the specifications of SI/O3 and SI/O4.
1/2
Main clock
f2SIO
Clock source select
SMi1 to SMi0
002
PCLK1=0
f1SIO
1/8
PCLK1=1
1/4
f8SIO
012
f32SIO
102
Synchronous
circuit
SMi3
SMi6
SMi4
CLKi
CLK
polarity
reversing
circuit
Data bus
1/(n+1)
1/2
SiBRG register
SMi6
SI/O counter i
SMi2
SMi3
SMi5 LSB
SOUTi
MSB
SiTRR register
SINi
8
Note: i = 3, 4.
n = A value set in the SiBRG register.
Figure 2.11.34. SI/O3 and SI/O4 Block Diagram
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SI/Oi
interrupt request
M306H3MC-XXXFP/FCFP
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3C
S4C
Bit
symbol
SMi0
Address
036216
036616
After reset
010000016
010000016
Description
Bit name
Internal synchronous
clock select bit
SMi1
b1 b0
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Must not be set.
RW
RW
RW
SMi2
SOUTi output disable bit
(Note 4)
0 : SOUTi output
1 : SOUTi output disable(high impedance)
RW
SMi3
S I/Oi port select bit
0 : Input/output port
1 : SOUTi output, CLKi function
RW
SMi4
CLK polarity select bit
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
RW
SMi5
Transfer direction select
bit
0 : LSB first
1 : MSB first
RW
SMi6
Synchronous clock
select bit
0 : External clock (Note 2)
1 : Internal clock (Note 3)
RW
SMi7
SOUTi initial value
set bit
Effective when SMi3 = 0
0 : “L” output
1 : “H” output
RW
Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to “1”
(write enable).
Note 2: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Note 3: Set the SMi3 bit to “1” (SOUTi output, CLKi function).
Note 4: When the SMi2 bit is set to “1”, the target pin goes to a high-impedance state regardless of which function of the
pin is being used.
SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)
b7
Symbol
S3BRG
S4BRG
b0
Address
036316
036716
After reset
Indeterminate
Indeterminate
Description
Setting range
RW
0016 to FF16
WO
Assuming that set value = n, BRGi divides the count
source by n + 1
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)
b7
Symbol
S3TRR
S4TRR
b0
Address
036016
036416
After reset
Indeterminate
Indeterminate
Description
RW
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
RW
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for SINi to “0” (input mode).
Figure 2.11.35. S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers
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M306H3MC-XXXFP/FCFP
Table 2.11.19. SI/O3 and SI/O4 Specifications
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f8SIO, f32SIO. n=Setting value of SiBRG register
0016 to FF16.
Transmission/reception
start condition
Interrupt request
• SMi6 bit = “0” (external clock) : Input from CLKi pin (Note 1)
• Before transmission/reception can start, the following requirements must be met
Write transmit data to the SiTRR register (Notes 2, 3)
• When SiC register's SMi4 bit = 0
generation timing
The rising edge of the last transfer clock pulse (Note 4)
• When SMi4 = 1
CLKi pin fucntion
SOUTi pin function
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
SINi pin function
Select function
I/O port, receive data input
• LSB first or MSB first selection
The falling edge of the last transfer clock pulse (Note 4)
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Function for setting an SOUTi initial value set function
When the SiC register's SMi6 bit = 0 (external clock), the SOUTi pin output level while
not tranmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
Note 1: To set the SiC register’s SMi6 bit to “0” (external clock), follow the procedure described below.
• If the SiC register’s SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is
high. The same applies when rewriting the SiC register’s SMi7 bit.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same
applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the
transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically
stops.
Note 2: Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. Therefore, do not write the next transmit data to the SiTRR register during transmission.
Note 3: When the SiC register’s SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period
after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the
data hold time thereby reduced.
Note 4: When the SiC register’s SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit
= 0, or stops in the low state if the SMi4 bit = 1.
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M306H3MC-XXXFP/FCFP
(a) SI/Oi Operation Timing
Figure 2.11.36 shows the SI/Oi operation timing
1.5 cycle (max) (Note 3)
SI/Oi internal clock
"H"
"L"
CLKi output
"H"
"L"
Signal written to the
SiTRR register
"H"
"L"
(Note 2)
SOUTi output
"H"
"L"
SINi input
"H"
"L"
SiIC register
IR bit
"1"
"0"
D0
D1
D2
D3
D4
D5
D6
D7
i= 3, 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the
rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
Figure 2.11.36. SI/Oi Operation Timing
(b) CLK Polarity Selection
The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 2.11.37 shows
the polarity of the transfer clock.
(1) When SiC register's SMi4 bit = “0”
(Note 2)
CLKi
SINi
D0
D1
D2
D3
D4
D5
D6
D7
SOUTi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When SiC register's SMi4 bit = “1”
(Note 3)
CLKi
SINi
D0
D1
D2
D3
D4
D5
D6
D7
SOUTi
D0
D1
D2
D3
D4
D5
D6
D7
i=3 and 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.
Figure 2.11.37. Polarity of Transfer Clock
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M306H3MC-XXXFP/FCFP
(c) Functions for Setting an SOUTi Initial Value
If the SiC register’s SMi6 bit = 0 (external clock), the SOUTi pin output can be fixed high or low when not
transferring. Figure 2.11.38 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) When “H” selected for SOUTi initial value (Note 1)
Setting of the initial value of SOUTi
output and starting of transmission/
reception
Signal written to
SiTRR register
SMi7 bit
Set the SMi3 bit to “0”
(SOUTi pin functions as an I/O port)
SMi3 bit
Set the SMi7 bit to “1”
(SOUTi initial value = “H”)
D0
SOUTi (internal)
D0
Port output
Set the SMi3 bit to “1”
(SOUTi pin functions as SOUTi output)
SOUTi pin output
Initial value = “H” (Note 3)
(i = 3, 4)
Setting the SOUTi
initial value to “H”
(Note 2)
Port selection switching
(I/O port
SOUTi)
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi5=0 (LSB first) and SMi6=0 (external clock)
Note 2: SOUTi can only be initialized when input on the CLKi pin is in the high state if the SiC
register’s SMi4 bit = 0 (transmit data output at the falling edge of the transfer clock) or
in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the
transfer clock).
Note 3: If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled),
this output goes to the high-impedance state.
Figure 2.11.38. SOUTi’s Initial Value Setting
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“H” level is output
from the SOUTi pin
Write to the SiTRR register
Serial transmit/reception starts
M306H3MC-XXXFP/FCFP
2.12 A-D Converter
The microcomputer contains one A-D converter circuit based on 8-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107, P95
___________
and P96. Similarly, ADTRG input shares the pin with P97. Therefore, when using these inputs, make sure
the corresponding port direction bits are set to “0” (= input mode).
When not using the A-D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will
flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A-D conversion result is stored in the ADi register bits for ANi, AN0i pins (i = 0 to 7).
Table 2.12.1 shows the performance of the A-D converter. Figure 2.12.1 shows the block diagram of the
A-D converter, and Figures 2.12.2 and 2.12.3 show the A-D converter-related registers.
Table 2.12.1. Performance of A-D Converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of
fAD/divide-by-12 of fAD
Resolution
8-bit
Integral nonlinearity error When AVCC = VREF = 5V
• With 8-bit resolution: ±3LSB
- ANEX0 and ANEX1 input (including mode in which external operation
amp is connected) : ±4LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1)
A-D conversion start condition • Software trigger
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
• External trigger___________
(retriggerable)
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: The fAD frequency must be 10 MHz or less.
Without sample-and-hold function, limit the fAD frequency to 250kHZ or less.
With the sample and hold function, limit the fAD frequency to 1MHZ or less.
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M306H3MC-XXXFP/FCFP
A-D conversion rate
selection
CKS1=1
CKS2=0
1/2
fAD
1/2
1/3
øAD
CKS0=1
CKS1=0
CKS0=0
CKS2=1
TRG=0
Software trigger
A-D trigger
ADTRG
TRG=1
VREF
Resistor ladder
VCUT=0
AV SS
VCUT=1
Successive conversion register
ADCON1 register
ADCON0 register
AD register 0(8)
AD register 1(8)
AD register 2(8)
AD register 3(8)
AD register 4(8)
AD register 5(8)
AD register 6(8)
AD register 7(8)
Data bus low-order
Decoder
for A-D register
ADCON2 register
(address 03D416)
Vref
Decoder
for channel
selection
VIN
Port P10 group
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
CH2 to CH0
=0002
=0012
=0102
=011 2
=1002
=1012
=110 2
=111 2
OPA1 to OPA0=00 2
PM01 to PM00=002
ADGSEL1 to ADGSEL0=10 2
OPA1 to OPA0=00 2
OPA1 to OPA0=11 2
ANEX0
ANEX1
OPA0=1
OPA1 to OPA0
=012
OPA1=1
OPA1=1
Figure 2.12.1. A-D Converter Block Diagram
Rev.1.00
2004.03.23
page 159 of 320
Comparator
M306H3MC-XXXFP/FCFP
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
Bit symbol
Bit name
F unction
RW
CH0
Analog input pin select bit
Function varies with each operation mode
RW
CH1
RW
CH2
RW
MD0
A-D operation mode
select bit 0
MD1
b4 b3
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
RW
RW
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
RW
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
RW
CKS0
Frequency select bit 0
See Note 3 for the ADCON2 register
RW
TRG
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
b4
b3
0
b2
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
Bit name
A-D sweep pin select bit
After reset
0016
Function
RW
Function varies with each operation mode
SCAN0
RW
SCAN1
RW
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
RW
Reserved bit
Must always be set to “0”
RW
CKS1
Frequency select bit 1
See Note 3 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 2)
0 : Vref not connected
1 : Vref connected
RW
OPA0
External op-amp
connection mode bit
Function varies with each operation mode
MD2
(b3)
OPA1
RW
RW
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 2.12.2. ADCON0 to ADCON1 Registers
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M306H3MC-XXXFP/FCFP
A-D control register 2 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
Symbol
Address
After reset
ADCON2
03D416
0016
Bit symbol
Bit name
Function
RW
A-D conversion method
select bit
0 : Without sample and hold
1 : With sample and hold
RW
(b3-b1)
Reserved bit
Must always be set to “0”
RW
CKS2
Frequency select bit 2
(Note 2)
0: Selects fAD, fAD divided by 2, or fAD
divided by 4.
1: Selects fAD divided by 3, fAD divided
by 6, or fAD divided by 12.
(b7-b5)
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”.
SMP
RW
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: The ØAD frequency must be 10 MHz or less. The selected ØAD frequency is determined by a combination of
the ADCON0 register's CKS0 bit, ADCON1 register's CKS1 bit, and ADCON2 register's CKS2 bit.
CKS0
CKS1
CKS2
0
0
0
ØAD
0
0
1
Divide-by-2 of fAD
0
1
0
fAD
0
1
1
1
0
0
Ddivide-by-12 of fAD
1
0
1
Divide-by-6 of fAD
1
1
0
Divide-by-3 of fAD
1
1
1
Divide-by-4 of fAD
Symbol
A-D register i (i=0 to 7)
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
b7
Address
03C0 16
03C2 16
03C4 16
03C6 16
03C8 16
03CA 16
03CC 16
03CE 16
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
Function
A-D conversion result
Figure 2.12.3. ADCON2 Register, and AD0 to AD7 Registers
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RW
RO
M306H3MC-XXXFP/FCFP
(1) One-shot Mode
In this mode, the input voltage on one selected pin is A-D converted once. Table 2.12.2 shows the
specifications of one-shot mode. Figure 2.12.4 shows the ADCON0 to ADCON1 registers in one-shot
mode.
Table 2.12.2. One-shot Mode Specifications
Item
Function
A-D conversion start condition
A-D conversion stop condtision
Interrupt request generation timing
Analog input pin
Reading of result of A-D converter
Rev.1.00
2004.03.23
Specification
The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and the ADCON1 register's OPA1 to OPA0 bits is A-D converted once.
• When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
• Completion of A-D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A-D conversion halted).)
• Set the ADST bit to “0”
Completion of A-D conversion
Select one pin from AN0 to AN7, ANEX0 to ANEX1
Read one of the AD0 to AD7 registers that corresponds to the selected pin
page 162 of 320
M306H3MC-XXXFP/FCFP
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
Bit name
Analog input pin select
bit
CH1
CH2
MD0
MD1
TRG
After reset
00000XXX2
A-D operation mode
select bit 0
Trigger select bit
Function
RW
b2 b1 b0
0 0 0 : AN 0 is selected
0 0 1 : AN 1 is selected
0 1 0 : AN 2 is selected
0 1 1 : AN 3 is selected
1 0 0 : AN 4 is selected
1 0 1 : AN 5 is selected
1 1 0 : AN 6 is selected
1 1 1 : AN 7 is selected
RW
RW
(Note 2)
b4 b3
0 0 : One-shot mode
(Note 2)
0 : Software trigger
1 : AD TRG trigger
RW
RW
RW
RW
ADST
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
RW
CKS0
Frequency select bit 0
RW
See Note 3 for the ADCON2 register
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A-D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
0 0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
After reset
0016
Bit name
A-D sweep pin
select bit
Function
Invalid in one-shot mode
SCAN1
RW
RW
RW
MD2
A-D operation mode
select bit 1
Set to “0” when one-shot mode is selected
RW
(b3)
Reserved bit
Must always be set to “0”
RW
CKS1
Frequency select bit1
See Note 2 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 2) 1 : Vref connected
OPA0
OPA1
External op-amp
connection mode bit
RW
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
RW
RW
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 2.12.4. ADCON0 Register and ADCON1 Register (One-shot Mode)
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M306H3MC-XXXFP/FCFP
(2) Repeat mode
In this mode, the input voltage on one selected pin is A-D converted repeatedly. Table 2.12.3 shows the
specifications of repeat mode. Figure 2.12.5 shows the ADCON0 to ADCON1 registers in repeat mode.
Table 2.12.3. Repeat Mode Specifications
Item
Function
A-D conversion start condition
A-D conversion stop condtision
Interrupt request generation timing
Analog input pin
Reading of result of A-D converter
Rev.1.00
2004.03.23
Specification
The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and the ADCON1 register's OPA1 to OPA0 bits is A-D converted
repeatdly.
• When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
Set the ADST bit to “0” (A-D conversion halted)
None generated
Select one pin from AN0 to AN7, ANEX0 to ANEX1
Read one of the AD0 to AD7 registers that corresponds to the selected pin
page 164 of 320
M306H3MC-XXXFP/FCFP
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
After reset
00000XXX2
Bit name
Analog input pin
select bit
CH1
CH2
Function
RW
b2 b1 b0
0 0 0 : AN 0 is selected
0 0 1 : AN 1 is selected
0 1 0 : AN 2 is selected
0 1 1 : AN 3 is selected
1 0 0 : AN 4 is selected
1 0 1 : AN 5 is selected
1 1 0 : AN 6 is selected
1 1 1 : AN 7 is selected
RW
RW
(Note 2)
RW
RW
RW
b4 b3
MD1
A-D operation mode
select bit 0
TRG
Trigger select bit
ADST
A-D conversion start flag
0 : Software trigger
1 : AD TRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
RW
CKS0
Frequency select bit 0
See Note 3 for the ADCON2 register
RW
MD0
0 1 : Repeat mode
(Note 2)
RW
Note 1: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A-D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
0 0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
After reset
0016
Bit name
A-D sweep pin
select bit
Function
Invalid in repeat mode
SCAN1
MD2
(b3)
RW
RW
RW
A-D operation mode
select bit 1
Reserved bit
Set to “0” when this mode is selected
Must always be set to “0”
RW
RW
CKS1
Frequency select bit 1
VCUT
Vref connect bit (Note 2) 1 : Vref connected
RW
OPA0
External op-amp
connection mode bit
RW
OPA1
See Note 2 for the ADCON2 register
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
RW
RW
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 2.12.5. ADCON0 Register and ADCON1 Register (Repeat Mode)
Rev.1.00
2004.03.23
page 165 of 320
M306H3MC-XXXFP/FCFP
(3) Single Sweep Mode
In this mode, the input voltages on selected pins are A-D converted, one pin at a time. Table 2.12.4 shows
the specifications of single sweep mode. Figure 2.12.6 shows the ADCON0 to ADCON1 registers in
single sweep mode.
Table 2.12.4. Single Sweep Mode Specifications
Item
Specification
Function
The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits are A-D converted, one pin at a time.
A-D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
A-D conversion stop condtision • Completion of A-D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A-D conversion halted).)
• Set the ADST bit to “0”
Interrupt request generation timing Completion of A-D conversion
Analog input pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins)
Reading of result of A-D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
Rev.1.00
2004.03.23
page 166 of 320
M306H3MC-XXXFP/FCFP
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
After reset
00000XXX2
Bit name
Analog input pin
select bit
Function
RW
Invalid in single sweep mode
RW
RW
CH1
RW
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 0 : Single sweep mode
MD1
TRG
ADST
CKS0
RW
RW
Trigger select bit
A-D conversion start flag
Frequency select bit 0
0 : Software trigger
1 : AD TRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
RW
See Note 3 for the ADCON2 register
RW
RW
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
0 0
b1
b0
Symbol
ADCON1
Address
03D716
Bit symbol
Bit name
SCAN0
A-D sweep pin select bit
After reset
0016
Function
When single sweep mode is selected
RW
RW
b1 b0
0 0 : AN 0 to AN 1 (2 pins)
0 1 : AN 0 to AN 3 (4 pins)
1 0 : AN 0 to AN 5 (6 pins)
1 1 : AN 0 to AN 7 (8 pins)
SCAN1
MD2
A-D operation mode
select bit 1
Set to “0” when single sweep mode is selected
RW
(b3)
Reserved bit
Must always be set to “0”
RW
Frequency select bit 1
See Note 3 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 3)
1 : Vref connected
RW
OPA0
External op-amp
connection mode
bit
b7 b6
CKS1
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 2.12.6. ADCON0 Register and ADCON1 Register (Single Sweep Mode)
Rev.1.00
2004.03.23
RW
page 167 of 320
RW
RW
M306H3MC-XXXFP/FCFP
(4) Repeat Sweep Mode 0
In this mode, the input voltages on selected pins are A-D converted repeatedly. Table 2.12.5 shows the
specifications of repeat sweep mode 0. Figure 2.12.7 shows the ADCON0 to ADCON1 registers in repeat
sweep mode 0.
Table 2.12.5. Repeat Sweep Mode 0 Specifications
Item
Function
A-D conversion start condition
A-D conversion stop condtision
Interrupt request generation timing
Analog input pin
Reading of result of A-D converter
Rev.1.00
2004.03.23
Specification
The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits are A-D converted repeatdly.
• When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
Set the ADST bit to “0” (A-D conversion halted)
None generated
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins)
Read one of the AD0 to AD7 registers that corresponds to the selected pin
page 168 of 320
M306H3MC-XXXFP/FCFP
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
After reset
00000XXX2
Bit name
Analog input pin
select bit
Function
Invalid in repeat sweep mode 0
RW
CH2
A-D operation mode
select bit 0
MD1
TRG
ADST
CKS0
RW
RW
CH1
MD0
RW
Trigger select bit
A-D conversion start flag
Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
RW
0 : Software trigger
1 : AD TRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
RW
See Note 3 for the ADCON2 register
RW
RW
RW
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
0 0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
After reset
0016
Bit name
A-D sweep pin select bit
Function
b1 b0
0 0 : AN 0, AN 1 (2 pins)
0 1 : AN 0 to AN 3 (4 pins)
1 0 : AN 0 to AN 5 (6 pins)
1 1 : AN 0 to AN 7 (8 pins)
SCAN1
MD2
(b3)
A-D operation mode
select bit 1
Reserved bit
RW
Set to “0” when repeat sweep mode 0 is
selected
RW
Must always be set to “0”
RW
Frequency select bit 1
See Note 2 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 2)
1 : Vref connected
RW
OPA0
External op-amp
connection mode
bit
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Figure 2.12.7. ADCON0 Register and ADCON1 Registers (Repeat Sweep Mode 0)
2004.03.23
RW
CKS1
OPA1
Rev.1.00
RW
When repeat sweep mode 0 is selected
page 169 of 320
RW
RW
M306H3MC-XXXFP/FCFP
(5) Repeat Sweep Mode 1
In this mode, the input voltages on all pins are A-D converted repeatedly, with priority given to the selected pins. Table 2.12.6 shows the specifications of repeat sweep mode 1. Figure 2.12.8 shows the
ADCON0 to ADCON1 registers in repeat sweep mode 1.
Table 2.12.6. Repeat Sweep Mode 1 Specifications
Item
Function
A-D conversion start condition
A-D conversion stop condtision
Interrupt request generation timing
Analog input pins to be given
priority when A-D converted
Reading of result of A-D converter
Rev.1.00
2004.03.23
Specification
The input voltages on all selected pins are A-D converted repeatdly, with priority given to pins selected by the ADCON1 register's SCAN1 to SCAN0 bits.
Example : If AN0 selected, input voltages are A-D converted in order of
AN0
AN1
AN0
AN2
AN0
AN3, and so on.
• When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A-D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A-D conversion starts)
Set the ADST bit to “0” (A-D conversion halted)
None generated
Select from AN0 (1 pins), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3
(4 pins)
Read one of the AD0 to AD7 registers that corresponds to the selected pin
page 170 of 320
M306H3MC-XXXFP/FCFP
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
After reset
00000XXX2
Bit name
Analog input pin
select bit
Function
Invalid in repeat sweep mode 1
RW
RW
CH1
RW
CH2
RW
MD0
A-D operation mode
select bit 0
MD1
TRG
ADST
CKS0
Trigger select bit
A-D conversion start flag
Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
RW
RW
0 : Software trigger
1 : AD TRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
RW
See Note 3 for the ADCON2 register
RW
RW
Note: If the ADCON0 register is rewritten during A-D conversion, the conversion result will be indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
0 1
b1
b0
Symbol
ADCON1
Address
03D716
Bit symbol
Bit name
SCAN0
A-D sweep pin select bit
After reset
0016
Function
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN 0 (1 pin)
0 1 : AN 0, AN 1 (2 pins)
1 0 : AN 0 to AN 2 (3 pins)
1 1 : AN 0 to AN 3 (4 pins)
SCAN1
MD2
(b3)
A-D operation mode
select bit 1
Reserved bit
Must always be set to “0”
RW
Frequency select bit 1
VCUT
Vref connect bit (Note 2)
1 : Vref connected
OPA0
External op-amp
connection mode
bit
b7 b6
See Note 2 for the ADCON2 register
0 0 : ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 : External op-amp connection mode
Figure 2.12.8. ADCON0 Register and ADCON1 Register (Repeat Sweep Mode 1)
2004.03.23
page 171 of 320
RW
RW
Note 1: If the ADCON1 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A-D conversion.
Rev.1.00
RW
Set to “1” when repeat sweep mode 1 is
selected
CKS1
OPA1
RW
RW
RW
RW
RW
M306H3MC-XXXFP/FCFP
(a) Sample and Hold
If the ADCON2 register’s SMP bit is set to “1” (with sample-and-hold), the conversion speed per pin is
increased to 28 ØAD cycles for 8-bit resolution. Sample-and-hold is effective in all operation modes.
Select whether or not to use the sample-and-hold function before starting A-D conversion.
(b) Extended Analog Input Pins
In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the
ADCON1 register’s OPA1 to OPA0 bits to select whether or not use ANEX0 and ANEX1.
The A-D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers,
respectively.
(c) External Operation Amp Connection Mode
Multiple analog inputs can be amplified using a single external op-amp via the ANXE0 and ANEX1 pins.
Set the ADCON1 register’s OPA1 OPA0 bits to ‘112’ (external op-amp connection mode). The inputs from
ANi (i = 0 to 7) are output from the ANEX0 pin. Amplify this output with an external op-amp before sending
it back to the ANEX1 pin. The A-D conversion result is stored in the corresponding ADi register. The A-D
conversion speed depends on the response characteristics of the external op-amp. Note that the ANXE0
and ANEX1 pins cannot be directly connected to each other. Figure 2.12.9 is an example of how to
connect the pins in external operation amp.
Microcomputer
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Resistor ladder
Successive conversion
register
ANEX0
ANEX1
Comparator
External opamp
Figure 2.12.9. External Op-amp Connection
Rev.1.00
2004.03.23
page 172 of 320
M306H3MC-XXXFP/FCFP
(d) Current Consumption Reducing Function
When not using the A-D converter, its resistor ladder and reference voltage input pin (VREF) can be
separated using the ADCON1 register’s VCUT bit. When separated, no current will flow from the VREF pin
into the resistor ladder, helping to reduce the power consumption of the chip.
To use the A-D converter, set the VCUT bit to “1” (VREF connected) and then set the ADCON0 register’s
ADST bit to “1” (A-D conversion start). The VCUT and ADST bits cannot be set to “1” at the same time.
Nor can the VCUT bit be set to “0” (VREF unconnected) during A-D conversion.
(e) Analog Input Pin and External Sensor Equivalent Circuit Example
Figure 2.12.10 shows analog input pin and external sensor equivalent circuit example.
Microcomputer
Sensor equivalent
circuit
R0
R (7.8kΩ)
VIN
Sampling time
C (1.5pF)
VC
3
fAD
2
Sample-and-hold function disabled:
fAD
Sample-and-hold function enabled:
Figure 2.12.10. Analog Input Pin and External Sensor Equivalent Circuit
Rev.1.00
2004.03.23
page 173 of 320
M306H3MC-XXXFP/FCFP
(f) Caution of Using A-D Converter
(1) Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit
___________
for the ADTRG pin is set to “0” (input mode).
(2) When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A-D input voltage goes low.)
(3) To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi (i=0 to 7)) each and the AVSS pin.
Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 2.12.11 is an example
connection of each pin.
(4) If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A-D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for
CPU clock.
• When operating in one-shot or single-sweep mode
Check to see that A-D conversion is completed before reading the target ADi register. (Check the IR
bit in the ADIC register to see if A-D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
(5) If A-D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit
to “0” (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The contents of ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D conversion is underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.
Microcomputer
VCC (15pin) AV CC
C4
VSS
VREF
C1
C2
AV SS
VCC (69pin)
C5
C3
ANi
VSS
ANi: ANi (i=0 to 7)
Note 1: C1≥0.47µF, C2 ≥0.47µF, C3 ≥100pF, C4 ≥0.1µF, C5≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
Figure 2.12.11. VCC, VSS, AVCC, AVSS, VREF and ANi Connection
Rev.1.00
2004.03.23
page 174 of 320
M306H3MC-XXXFP/FCFP
2.13 CRC Calculation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer
uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code consists of 16 bits which are generated for each data block in given length, separated in
8 bit units. After the initial value is set in the CRCD register, the CRC code is set in that register each time
one byte of data is written to the CRCIN register. CRC code generation for one-byte data is finished in two
cycles.
Figure 2.13.1 shows the block diagram of the CRC circuit. Figure 2.13.2 shows the CRC-related registers. Figure 2.13.3 shows the calculation example using the CRC operation.
Data bus high-order
AAAAA
AAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAA
AAAAAA
Data bus low-order
Eight low-order bits
Eight high-order bits
CRCD register
CRC code generating circuit
x16 + x12 + x5 + 1
CRCIN register
Figure 2.13.1. CRC Circuit Block Diagram
CRC data register
(b15)
b7
(b8)
b0 b7
b0
Symbol
CRCD
Address
03BD16 to 03BC16
After reset
Indeterminate
Setting range
Function
When data is written to the CRCIN register after setting
the initial value in the CRCD register, the CRC code can
be read out from the CRCD register.
RW
000016 to FFFF16 RW
CRC input register
b7
Symbo
CRCIN
b0
Function
Data input
Figure 2.13.2. CRCD Register and CRCIN Register
Rev.1.00
2004.03.23
page 175 of 320
Address
03BE16
After reset
Indeterminate
Setting range
RW
0016 to FF16
RW
M306H3MC-XXXFP/FCFP
Setup procedure and CRC operation when generating CRC code “80C416”
(a) CRC operation performed by the M16C
CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is
divided by the generator polynomial
Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 00012)
(b) Setting procedure
(1) Reverse the bit positions of the value “80C416” bytewise in a program.
“8016” → “0116”, “C416” → “2316”
b15
b0
(2) Write 000016 (initial value)
CRCD register
b7
b0
(3) Write 0116
CRCIN register
Two cycles later, the CRC code for “8016,” i.e.,
918816, has its bit positions reversed to become
“118916” which is stored in the CRCD register.
b0
b15
CRCD register
118916
b7
b0
(4) Write 2316
CRCIN register
Two cycles later, the CRC code for “80C416,” i.e.,
825016, has its bit positions reversed to become
“0A4116” which is stored in the CRCD register.
b15
b0
CRCD register
0A4116
(c) Details of CRC operation
In the case of (3) above, the value written to the CRCIN register “0116 (000000012)” has its bit positions reversed to
become “100000002.” The value “1000 0000 0000 0000 0000 00002” derived from that by adding 16 digits and the
CRCD register’s initial value “000016” are added, the result of which is divided by the generator polynomial using
modulo-2 arithmetic.
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001 1000 0000 0000 0000
1000 1000 0001 0000
Generator polynomial
1000 0001 0000
1000 1000 0001
1001 0001
0000
1
1000
0000
1000
0000
0
1
1000
Data
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
CRC code
The value “0001 0001 1000 10012 (118916)” derived from the remainder “1001 0001 1000 10002 (918816)” by
reversing its bit positions may be read from the CRCD register.
If operation (4) above is performed subsequently, the value written to the CRCIN register “2316 (001000112)” has its bit
positions reversed to become “110001002. The value “1100 0100 0000 0000 0000 00002” derived from that by adding
16 digits and the remainder in (3) “1001 0001 1000 10002” which is left in the CRCD register are added, the result of
which is divided by the generator polynomial using modulo-2 arithmetic.
The value “0000 1010 0100 00012 (0A4116)” derived from the remainder by reversing its bit positions may be read
from the CRCD register.
Figure 2.13.3. CRC Calculation
Rev.1.00
2004.03.23
page 176 of 320
M306H3MC-XXXFP/FCFP
2.14 Expansion Function
2.14.1 Expansion function description
Expansion function cousists of CRC operation function, data slice function and humming decoder
function. Each function is controled by expansion memories.
(1) CRC operation function
It performs error detection of a code, and error correction.
(2) Data slice function
It performs data acquisition to get such format data as below.
Hardware : TELETEXT, PDC, VPS, VBI, EPG-J, XDS and WSS
Software : CCD, WSS and VBI-ID
(3) Humming decoder function
It performs 8/4 humming and 24/18 humming
FSCIN
SYNCIN
Clock
generator
Vertical
Syncseparate
circuit
Clock
generator
Clock
generator
Vertical
Syncseparate
circuit
Timing
generator
Port
control
circuit
CVIN1
CRC
register
Expansion
register
24/18
humming
8/4
humming
Data bus (16bit)
CPU block
Figure 2.14.1 Block diagram of expansion function
Rev.1.00
2004.03.23
Serial/pararell
conversion
circuit
Data slicer circuit
page 177 of 320
Slice
RAM
Arbitration
circuit
P11/SLICEON
M306H3MC-XXXFP/FCFP
2.14.2 Expansion memory
Expansion function memory is divided by 3 patterns ; Slice RAM, CRC registers and expansion registers (Humming decoder operates by the register placed on SFR). Data writing and read out to the
Slice RAM, CRC registers and the expansion registers are carried out per 16 bit unit by the data
setting register (addresses 020E16, 021016, 021216, 021416, 021616 and 021816) placed on SFR.
Contents of each memory and data setting register are shown in Table 2.14.1.
Table 2.14.1 Expansion memory composition
Contents
Expansion memory
Data setting register
Slice RAM
This register holds acquired data.
Slice RAM address control register (020E16)
Slice RAM data control register (021016)
CRC register
This register controls a set up generation
polynomial and code data.
This register performs data slicer control and
CRC register address control register (021216)
CRC register data control register (021416)
Expansion register address control register (021616)
VBI encoder control.
Expansion register data control register (021816)
Expansion register
Rev.1.00
2004.03.23
page 178 of 320
M306H3MC-XXXFP/FCFP
2.14.3 Slice RAM
Slice RAM stores 18-line slice data. There are several types of Slice data : PDC, VPS, VBI, XDS,
WSS, etc. All data are stored to addresses which corresponds to slice line (ex. 22 line' data is stored
to addresses 20016 to 21716 ). 24 addresses (SR00x to SR17x) are prepared for 1 line, slice data is
stored in order from LSB side. Then, slice data and field information are stored to the top address of
each line.
Slice RAM composition is shown in Table 2.14.2.
Table 2.14.2 Slice RAM composition
Slice RAM addresses
SD15 SD14 SD13 SD12 SD11 SD10
(SA9 to SA0)
01616
01716
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1 SD0
Remarks
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 6th line or 318th line
SR01F SR01E SR01D SR01C SR01B SR01A SR019 SR018 SR017 SR016 SR015 SR014 SR013 SR012 SR011 SR010 slice data
...
...
00016
00116
SD9
SR16F SR16E SR16D SR16C SR16B SR16A SR169 SR168 SR167 SR166 SR165 SR164 SR163 SR162 SR161 SR160
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
...
01816
03716
Unused area
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 7th line or 319th line
slice data
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
...
...
01F16
02016
8th line to 21th line
or 320th line to 333 line
slice data
23716
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
...
...
...
...
...
...
...
...
...
...
...
...
...
...
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 23th line or 335th line
slice data
...
...
21716
22016
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 22th line or 334th line
slice data
...
...
1F716
20016
...
...
04016
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
For accessing to Slice RAM data, set accessing address (SA9 to SA0) (shown in Table 2.14.2) to
Slice RAM address control register (address 020E16 ). Then read out data from Slice RAM data
control register (address 021016 ). When end the data reading, Slice RAM address control register
increments address automatically. Then, next address data reading is possible. Do not access to
unused area of each character codes. Must set address to each line because unused area has no
address' automatically increment.
Slice RAM bit composition is shown in Figure 2.14.2, Slice RAM access registers are shown in Figure
2.14.3 and Slice RAM access block diagram is shown in Figure 2.14.4.
Rev.1.00
2004.03.23
page 179 of 320
M306H3MC-XXXFP/FCFP
The each head address of the address is corresponded to slice line following slice information.
Line register 1
Line register 2
Line register 3
Other
SR00F to SR004
0
0
0
0
SR002
0
0
0
0
SR003
field * (Note)
field * (Note)
field * (Note)
0
SR001
0
1
0
0
SR000
1
0
1
0
Note : * the first field : 1
the second field : 0
(1) PDC
In case of the PDC data, 16 bits (2 data) are stored for the 1 address from the LSB side.
Clock run-in
+ flaming code
Data 1
Data 3
Data 2
L
S
B
Data 5
Data 4
Data 39
Data 41
M
S
B
ML
S S
B B
SR010
Data 42
Data 40
Data 6
SR01F
SR020
SR030
S02F
S03F
SR140
S14F
SR150
S15F
SR16x to SR17x are unused area.
(2) VPS
In case of the VPS data or the VBI data, 8 bits (a data) are stored for an address from the LSB side.
Low-order 8 bits hold the slice data. And, high-order 8 bits hold warning bit, when the send data is not recognized as bi-phase
type.
The case of bi-phase data ="1,0" or "0,1" (the bi-phase type) becomes "0" for this warning bit, and it becomes "1" in bi-phase data
="0,0" or "1,1" (it is not the bi-phase type). (For example, bi-phase data of SR011 is "0,0" or "1,1", "1" is set to SR019.)
Clock run-in
+ flaming code
Data 1
Data 3
Data 2
L
S
B
SR010
Data 12
Data 4
M L
S S
B B
M
S
B
SR017
SR020
SR030
SR027
SR037
SR040
Data 11
SR0B7SR0D0
SR0B0
SR047
Data 13
SR0C0
SR0D7
SR0C7
SR0Ex to SR17x are unused area.
(3) VBI
Clock run-in
+ flaming code
Data 1
L
S
B
SR010
Data 2
Data 3
M L
S S
B B
M
S
B
SR017
SR020
SR030
SR027
Data 4
SR037
SR040
Data 5
SR050
SR047
SR057
SR06x to SR17x are unused area.
Figure 2.14.2 Slice RAM bit composition
Rev.1.00
2004.03.23
page 180 of 320
M306H3MC-XXXFP/FCFP
Slice RAM address control register
b15
b9
b8
b7
b0
Symbol
SA
Address
020E16
When reset
000016
Setting possible value R W
Function
Specify accessing Slice RAM address
00016 to 23716
Nothing is assigned.
When write, set to “0.”
When read, its content is indeterminate.
Note 1 : When access to Slice RAM, Slice RAM address control register (021016) should be
set at first.
Slice RAM address control register increments by accessing Slice RAM
data control register. So, it is not neccesary to setting the next Slice RAM address.
Note 2 : When read Slice RAM data by software during slicer operation, access to Slice RAM
after 1 horizontal synchronous period from the completion of a SLICEON output
(refer to 2.14.6 Expansion Register Construction Composition for a SLICEON
output period).
Slice RAM data control register
b15
b9
b8
b7
b0
Symbol
SD
Address
021016
When reset
000016
Function
RW
Read out the data of Slice RAM.
Read out data of Slice RAM which is specified by Slice RAM address control register
(address 020E16) by reading this register.
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.14.3 Slice RAM access registers
Data bus (16-bit)
(address 020E16)
Slice RAM address control register
(10) (SA9 to SA0)
Slice RAM data control
register (16) (SD15 to SD0)
Increment automatically
after data access
Slice RAM
Figure 2.14.4 Slice RAM access block diagram
Rev.1.00
2004.03.23
page 181 of 320
(address 021016)
M306H3MC-XXXFP/FCFP
2.14.4 CRC Operation Circuit (EPG-J)
CRC operation circuit (EPG-J) is a circuit for performing error detection and error correction by the
272-190 shortening difference set cyclic code which is a coding system in a data multiplex broadcast.
CRC register consists of registers shown in Figure 2.14.5. CRC register can perform error detection
and error correction by majority logic by setting up a generator polinomial, code data, etc. CRC
register composition is shown in Table 2.14.3.
Table 2.14.3 CRC register composition
CA3 to CA0
0016
0116
0216
0316
0416
0516
0616
0716
0816
0916
0A16
0B16
0C16
0D16
CD15
DAOUT15
_
CRC_66
CRC_50
CRC_34
CRC_18
CRC_02
_
REG_C81
REG_C65
REG_C49
REG_C33
REG_C17
REG_C01
CD14
DAOUT14
_
CRC_67
CRC_51
CRC_35
CRC_19
CRC_03
_
REG_C80
REG_C64
REG_C48
REG_C32
REG_C16
REG_C00
CD13
DAOUT13
_
CRC_68
CRC_52
CRC_36
CRC_20
CRC_04
_
REG_C79
REG_C63
REG_C47
REG_C31
REG_C15
_
CD12
DAOUT12
_
CRC_69
CRC_53
CRC_37
CRC_21
CRC_05
_
REG_C78
REG_C62
REG_C46
REG_C30
REG_C14
_
CD11
DAOUT11
_
CRC_70
CRC_54
CRC_38
CRC_22
CRC_06
_
REG_C77
REG_C61
REG_C45
REG_C29
REG_C13
_
CD0
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
CD10
DAOUT0
DAOUT1
DAOUT2
DAOUT3
DAOUT4
DAOUT5
DAOUT6
DAOUT7
DAOUT8
DAOUT9
DAOUT10
CRC_ERR10 CRC_ERR09 CRC_ERR08 CRC_ERR07 CRC_ERR06 CRC_ERR05 CRC_ERR04 CRC_ERR03 CRC_ERR02 CRC_ERR01 CRC_ERR00
CRC_71
CRC_72
CRC_73
CRC_76
CRC_77
CRC_78
CRC_79
CRC_80
CRC_81
CRC_75
CRC_74
CRC_55
CRC_56
CRC_57
CRC_60
CRC_61
CRC_62
CRC_63
CRC_64
CRC_65
CRC_59
CRC_58
CRC_49
CRC_48
CRC_47
CRC_46
CRC_45
CRC_44
CRC_43
CRC_42
CRC_41
CRC_40
CRC_39
CRC_33
CRC_32
CRC_31
CRC_30
CRC_29
CRC_28
CRC_27
CRC_26
CRC_25
CRC_24
CRC_23
CRC_07
CRC_17
CRC_16
CRC_15
CRC_14
CRC_13
CRC_12
CRC_11
CRC_10
CRC_09
CRC_08
CRC_01
CRC_00
_
_
_
_
_
_
_
_
_
REG_C66
REG_C67
REG_C68
REG_C69
REG_C70
REG_C71
REG_C72
REG_C73
REG_C74
REG_C75
REG_C76
REG_C58
REG_C50
REG_C51
REG_C52
REG_C53
REG_C54
REG_C55
REG_C56
REG_C57
REG_C59
REG_C60
REG_C34
REG_C35
REG_C36
REG_C37
REG_C38
REG_C39
REG_C40
REG_C41
REG_C42
REG_C43
REG_C44
REG_C25
REG_C18
REG_C19
REG_C20
REG_C21
REG_C22
REG_C23
REG_C24
REG_C26
REG_C27
REG_C28
REG_C02
REG_C03
REG_C04
REG_C05
REG_C06
REG_C07
REG_C08
REG_C09
REG_C10
REG_C11
REG_C12
_
CRCLSB
CRCCK0
CRCCK1
_
_
_
_
_
_
_
CRC register address control register
b15 b14 b13
b8 b7
b5 b4 b3
b0
Symbol
CA
address
021216
at Reset
000016
The value which R W
can be set up
Function
0016 to 0D16
Specify accessing CRC register address.
CRC register address automatic increment.
0: enable / 1 : disable (Notes 2)
–
Nothing is assigned.
When write, set to "0." When read, its content is determinate.
CRCLOOP 0 to 5
CRCCHANGE
– –
The number of times of a CRC
operation repetition.
0016 to 3F16
Error detection / error correction
Selection setting
–
0:error detection mode / 1: Error correction mode
CRC operation
CRCON
–
0: Stop/1 : Operation (Note 3)
Notes 1: When access to CRC register, must be set CRC register address at first, then use
CRC register data control register (021416).
Notes 2: When bit 4 = "0" setting, CRC register data control register increments by accessing
CRC register data control register, so it is not neccesary to setting the next CRC
register address. When bit 4 = "1" setting, the address is fixed.
Notes 3: When bit 15 = "0" setting, the value of a CRC data register
(address (CA3 to CA0) =01 to 07) is cleared.
CRC register data control register
b15
b8b7
b0
Symbol
CD
address
021416
Function
Write and read out the data of CRC register which is
specified by CRC register address control register
(address 021216)
at Reset
000016
The value which
can be set up
000016 to FFFF16
Note: Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.14.5 Composition of CRC register access related register
Rev.1.00
2004.03.23
page 182 of 320
RW
Remarks
M306H3MC-XXXFP/FCFP
For accessing to CRC register data, set accessing address (CA3 to CA0) (shown in Table 2.14.3) to
CRC register address control register (address 021216). Then write data (CD15 to CD0) by CRC
register data control register (address 021416). When end the data accessing, CRC register address
control register increments address automatically. Then, next address data writing is possible.
CRC register access registers are shown in Figure 2.14.5, expansion register access block diagram is
shown in Figure 2.14.6. The operation example of CRC operation circuit is shown in Figure 2.14.7. The
example of program is shown in Figure 2.14.8, and expansion register bit compositions are shown in
p185 to 197.
Data bus (16-bit)
(address 021216)
(CA13 to CA8)
(CA4)
CRC register address control register (4)
(CA3 to CA0)
CRC register data control register (16)
(CD15 to CD0)
Increment automatically
after data access
Shift counter
Code data
shift register
Generator polinomial register
Shift control circuit
82 bit CRC operation circuit
Error correction
mode
remainder polynomial register
Error judging
circuit
CRC error detection register
(Majority circuit)
Figure 2.14.6 Access block diagram for CRC registers
Rev.1.00
2004.03.23
page 183 of 320
(address 021416)
M306H3MC-XXXFP/FCFP
b82 b81
(1) Setting a generator
polinomial
1
0 0 0 0 1 1 0
b0
•••
0 0 0 1 0 0 0 1
CRC register
REG_C81 to 00
[address 0816 to 0D16]
b82 is fixed to "1"
The generator polinomial used on the data multiplex broadcast is following.
X82+X77+X76+X71+X67+X66+X56+X52+X48+X40+X36+X34+X24+X22+X18+X10+X4+1
b81
(2) Reset of CRC
remainder bit
0 0 0 0 0 0 0
b0
•••
0 0 0 0 0 0 0 0
CRC register
CRC_81 to 00
[address 0216 to 0716]
CRC remainder bit is automatically reset by CRCON=0 (address control register for CRC registers).
b15
b0
CRC register
(3) Setting 0016
ADOUT
[address 0016]
After CRC operation end
b0
b81
CRC register
CRC_81 to 00
[address 0216 to 0716]
The CRC code is stored
The data set as the DAOUT register is shifted from the low rank side of CRC remainder bit one by one (b0).
MOJURO-2 operation is
operation that complies
with the law given below.
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
•••
1000 01
•••
100 0011 0000 • • • 0001 0001 0000 0000 0000 0001 0000 0000 • • • 0000 0000 0000 • • • 0000 0000
1 0000 1100 • • • 0010 001
b0
b82 b81
1100 • • • 0010 0010 0000
1000
•••
0001 0001
Remainder
b81
Figure 2.14.7 Example of operation of CRC operation circuit
Rev.1.00
2004.03.23
page 184 of 320
b0
M306H3MC-XXXFP/FCFP
;
;
Equations (Constant definition)
;
_CRC_ADRS
00212h
; SFR address of CRC register address control register
_CRC_DATA
.equ
00214h
; SFR address of CRC register data control register
SLICE_WORD_NUM
.equ
.equ
17
; Code data length (in nuits of word)
;
;
Macro definition
;
_wait
.macro
nop
nop
nop
.endm
;
;
CRC operation routine
;
;--------- A setup of a generator polinomial
mov.w
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
#0008H
, _CRC_ADRS
; Set up of the header address of the generator polinomial registers.
mov.w
0000110000100011B
, _CRC_DATA
; Set up of the 82th to 66th generator polinomial coefficient ( x^77 +x~76 +x^71 +x^67 +x^66)
mov.w
0000000001000100B
, _CRC_DATA
; Set up of the 65th to 50th generator polinomial coefficient (+x^56 +x^52)
mov.w
0100000001000101B
, _CRC_DATA
; Set up of the 49th to 34th generator polinomial coefficient (+x^48 +x^40 +x^36 +x^34)
mov.w
0000000001010001B
, _CRC_DATA
; Set up of the 33th to 18th generator polinomial coefficient (+x^24 +x^22 +x^18)
mov.w
0000000100000100B
, _CRC_DATA
; Set up of the 17th to 2nd generator polinomial coefficient (+x^10 +x^4)
mov.w
0100000000000000B
, _CRC_DATA
; Set up of the 1st to 0th generator polinomial coefficient (+x^0),
no division of the shift clock and LSB first.
_wait
; Wait
;------ Writing of code data ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------mov.w
#0000H
, _CRC_ADRS
; Initialization of CRC register address control register
mov.w
#9010H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=0, CRCLOOP=10H, Increment=ON, and CRC address=00H.
mov.w
#0000H
, A0
; Initialization of a loop variable (A0)
cmp.w
#SLICE_WORD_NUM*2
, A0
; Comparison of the loop variable
jgeu
L20
lde.w
_CrcCodeData[A0]
, _CRC_DATA
; Writing code data to the code data shift register.
add.w
#0002H
,A0
; Increment of the address storing code data.
jmp
L18
L18:
; Branch label
; Go to L20 if writing code data is finished.
; Return to the head of this loop.
L20:
; Branch label
;--------- Dummy shift --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------; After finishing writing 272-bit code data,
; shift a bit for dummy surely in error correction mode.
; Specifying 1-bit is set up by CRCLOOP=01H.
mov.w
#8100H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=0, CRCLOOP=10H, Increment=OFF, and CRC address=00H.
#0000H
, _CRC_DATA
; Writing data to the code data shift register for dummy shift.
_wait
mov.w
; Wait
;--------- Error detection ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------; Since the address automatic increment in dummy shift (Increment=OFF), set CRC address=01H here.
; When accessing other CRC registers, the processing shown in the following two lines is necessary.
;
mov.w
;
_wait
#9001H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=0, CRCLOOP=10H, Incremet=OFF and CRC address=01H.
; Wait
mov.w
_CRC_DATA
, R0
; Read of CRC error detection register.
cmp.w
#0000H
, R0
; Judgement of CRC error.
jeq
L16
; In the case of R0=0, branch to L16 since CRC error has not occurred (CRC error correction is skipped).
;--------- Error correction --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------mov.w
#0D010H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=1, CRCLOOP=10H, Increment=ON and CRC address=00H.
mov.w
#0000H
, A0
; Initialization of a loop variable (A0)
cmp.w
#SLICE_WORD_NUB
, A0
; Comparison of the loop variable
, _CRC_DATA
; Writing code data to the code data shift register.
_wait
; Wait
L22:
; Branch label
jgeu
L24
; Go to L24 if correction of error data is finished.
lde.w
_CrcCodeData[A0]
jsr
_waitlong
mov.w
_CRC_DATA
, _CrcCodeData[A0]
; Read of error correction data in the address storing code data.
add.w
#0002H
, A0
; Increment of the address storing code data.
jmp
L22
; Wait for finish of error correction.
; Return to the head of this loop.
L24:
; Branch label
;------- The check of error correction data-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------mov.w
#8111H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=0, CRCLOOP=10H, Increment=ON and CRC address=00H
_CRC_DATA
, R0
; Error check after error correction. R0=000H if correction is performed.
_wait
mov.w
; Wait
L16:
;
; The function sample for weight for error correction
;
.align
.glb
_waitlong
_waitlong:
; Function label
rts
Figure 2.14.8 Example of program
Rev.1.00
2004.03.23
page 185 of 320
M306H3MC-XXXFP/FCFP
Bit composition of a CRC register
(1) Address 0016 (=CA3 to 0)
CD15
CD8CD7
CD0
Function
Bit symbol
Bit name
DAOUT0
The code data shift register
write-in bit 0
When write, data is written to "code
data shift register" (Note).
DAOUT1
The code data shift register
write-in bit 1
DAOUT2
The code data shift register
write-in bit 2
When read, data differs bitween in
error detection mode and in error
correction mode.
DAOUT3
The code data shift register
write-in bit 3
DAOUT4
The code data shift register
write-in bit 4
DAOUT5
The code data shift register
write-in bit 5
DAOUT6
The code data shift register
write-in bit 6
DAOUT7
The code data shift register
write-in bit 7
DAOUT8
The code data shift register
write-in bit 8
DAOUT9
The code data shift register
write-in bit 9
DAOUT10
The code data shift register
write-in bit 10
DAOUT11
The code data shift register
write-in bit 11
DAOUT12
The code data shift register
write-in bit 12
DAOUT13
The code data shift register
write-in bit 13
DAOUT14
The code data shift register
write-in bit 14
DAOUT15
The code data shift register
write-in bit 15
• In error detection mode
(CRCCHANGE=0)
000016 is read after shift end.
• In error correction mode
(CRCCHANGE=1)
Corrected data is read after the
original data is written in and some
interval of data shift.
Note: Refer to 2.14.16 Expansion Register Construction Composition.
Rev.1.00
2004.03.23
page 186 of 320
R W
M306H3MC-XXXFP/FCFP
(2) Address 0116 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
CRC_ERR00
The CRC bit 81 to 74 error
detection bit
Logical OR of the CRC remainder bits
81 to 74 (address 0216)
CRC_ERR01
The CRC bit 73 to 66 error
detection bit
Logical OR of the CRC remainder bits
73 to 66 (address 0216)
CRC_ ERR02
The CRC bit 65 to 58 error
detection bit
Logical OR of the CRC remainder bits
65 to 58 (address 0316)
CRC_ERR03
The CRC bit 57 to 50 error
detection bit
Logical OR of the CRC remainder bits
57 to 50 (address 0316)
CRC_ERR04
The CRC bit 49 to 42 error
detection bit
Logical OR of the CRC remainder bits
49 to 42 (address 0416)
CRC_ERR05
The CRC bit 41 to 34 error
detection bit
Logical OR of the CRC remainder bits
41 to 34 (address 0416)
CRC_ERR06
The CRC bit 33 to 26 error
detection bit
Logical OR of the CRC remainder bits
33 to 26 (address 0516)
CRC_ERR07
The CRC bit 25 to 18 error
detection bit
Logical OR of the CRC remainder bits
25 to 18 (address 0516)
CRC_ERR08
The CRC bit 17 to 10 error
detection bit
Logical OR of the CRC remainder bits
17 to 10 (address 0616)
CRC_ERR09
The CRC bit 09 to 02 error
detection bit
Logical OR of the CRC remainder bits
09 to 02 (address 0616)
CRC_ERR10
The CRC bit 01 to 00 error
detection bit
Logical OR of the CRC remainder bits
01 to 00 (address 0716)
Nothing is assigned.
The value is "0" when it reads.
Rev.1.00
2004.03.23
page 187 of 320
Function
R W
M306H3MC-XXXFP/FCFP
(3) Address 0216 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
Function
CRC_81
81th remainder polynomial
coefficient bit
CRC_80
80th remainder polynomial
coefficient bit
The coefficient of each degree of a
remainder polynomial is set up.
It is shown in below when a remainder
polynomial is made into CRC_MOD.
CRC_79
79th remainder polynomial
coefficient bit
CRC_78
78th remainder polynomial
coefficient bit
CRC_77
77th remainder polynomial
coefficient bit
CRC_76
76th remainder polynomial
coefficient bit
CRC_75
75th remainder polynomial
coefficient bit
CRC_74
74th remainder polynomial
coefficient bit
CRC_73
73th remainder polynomial
coefficient bit
CRC_72
72th remainder polynomial
coefficient bit
CRC_71
71th remainder polynomial
coefficient bit
CRC_70
70th remainder polynomial
coefficient bit
CRC_69
69th remainder polynomial
coefficient bit
CRC_68
68th remainder polynomial
coefficient bit
CRC_67
67th remainder polynomial
coefficient bit
CRC_66
66th remainder polynomial
coefficient bit
81
Rev.1.00
2004.03.23
page 188 of 320
R W
n
CRC_MOD = Σ CRC_n • X
n=0
M306H3MC-XXXFP/FCFP
(4) Address 0316 (=CA3 to 0)
CD15
Rev.1.00
CD8CD7
2004.03.23
CD0
page 189 of 320
Bit symbol
Bit name
CRC_65
65th remainder polynomial
coefficient bit
CRC_64
64th remainder polynomial
coefficient bit
CRC_63
63th remainder polynomial
coefficient bit
CRC_62
62th remainder polynomial
coefficient bit
CRC_61
61th remainder polynomial
coefficient bit
CRC_60
60th remainder polynomial
coefficient bit
CRC_59
59th remainder polynomial
coefficient bit
CRC_58
58th remainder polynomial
coefficient bit
CRC_57
57th remainder polynomial
coefficient bit
CRC_56
56th remainder polynomial
coefficient bit
CRC_55
55th remainder polynomial
coefficient bit
CRC_54
54th remainder polynomial
coefficient bit
CRC_53
53th remainder polynomial
coefficient bit
CRC_52
52th remainder polynomial
coefficient bit
CRC_51
51th remainder polynomial
coefficient bit
CRC_50
50th remainder polynomial
coefficient bit
Function
Refer to CRC_81 to 66
(address 0216).
R W
M306H3MC-XXXFP/FCFP
(5) Address 0416 (=CA3 to 0)
CD15
Rev.1.00
CD8CD7
2004.03.23
CD0
page 190 of 320
Bit symbol
Bit name
CRC_49
49th remainder polynomial
coefficient bit
CRC_48
48th remainder polynomial
coefficient bit
CRC_47
47th remainder polynomial
coefficient bit
CRC_46
46th remainder polynomial
coefficient bit
CRC_45
45th remainder polynomial
coefficient bit
CRC_44
44th remainder polynomial
coefficient bit
CRC_43
43th remainder polynomial
coefficient bit
CRC_42
42th remainder polynomial
coefficient bit
CRC_41
41th remainder polynomial
coefficient bit
CRC_40
40th remainder polynomial
coefficient bit
CRC_39
39th remainder polynomial
coefficient bit
CRC_38
38th remainder polynomial
coefficient bit
CRC_37
37th remainder polynomial
coefficient bit
CRC_36
36th remainder polynomial
coefficient bit
CRC_35
35th remainder polynomial
coefficient bit
CRC_34
34th remainder polynomial
coefficient bit
Function
Refer to CRC_81 to 66
(address 0216).
R W
M306H3MC-XXXFP/FCFP
(6) Address 0516 (=CA3 to 0)
CD15
Rev.1.00
CD8CD7
2004.03.23
CD0
page 191 of 320
Bit symbol
Bit name
CRC_33
33th remainder polynomial
coefficient bit
CRC_32
32th remainder polynomial
coefficient bit
CRC_31
31th remainder polynomial
coefficient bit
CRC_30
30th remainder polynomial
coefficient bit
CRC_29
29th remainder polynomial
coefficient bit
CRC_28
28th remainder polynomial
coefficient bit
CRC_27
27th remainder polynomial
coefficient bit
CRC_26
26th remainder polynomial
coefficient bit
CRC_25
25th remainder polynomial
coefficient bit
CRC_24
24th remainder polynomial
coefficient bit
CRC_23
23th remainder polynomial
coefficient bit
CRC_22
22th remainder polynomial
coefficient bit
CRC_21
21th remainder polynomial
coefficient bit
CRC_20
20th remainder polynomial
coefficient bit
CRC_19
19th remainder polynomial
coefficient bit
CRC_18
18th remainder polynomial
coefficient bit
Function
Refer to CRC_81 to 66
(address 0216).
R W
M306H3MC-XXXFP/FCFP
(7) Address 0616 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
CRC_17
17th remainder polynomial
coefficient bit
CRC_16
16th remainder polynomial
coefficient bit
CRC_15
15th remainder polynomial
coefficient bit
CRC_14
14th remainder polynomial
coefficient bit
CRC_13
13th remainder polynomial
coefficient bit
CRC_12
12th remainder polynomial
coefficient bit
CRC_11
11th remainder polynomial
coefficient bit
CRC_10
10th remainder polynomial
coefficient bit
CRC_09
09th remainder polynomial
coefficient bit
CRC_08
08th remainder polynomial
coefficient bit
CRC_07
07th remainder polynomial
coefficient bit
CRC_06
06th remainder polynomial
coefficient bit
CRC_05
05th remainder polynomial
coefficient bit
CRC_04
04th remainder polynomial
coefficient bit
CRC_03
03rd remainder polynomial
coefficient bit
CRC_02
02nd remainder polynomial
coefficient bit
Function
R W
Refer to CRC_81 to 66
(address 0216).
(8) Address 0716 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
CRC_01
01st remainder polynomial
coefficient bit
CRC_00
00th remainder polynomial
coefficient bit
Nothing is assigned.
The value is "0" when it reads.
Rev.1.00
2004.03.23
page 192 of 320
Function
Refer to CRC_81 to 66
(address 0216).
R W
M306H3MC-XXXFP/FCFP
(9) Address 0816 (=CA3 to 0)
CD15
Rev.1.00
CD8CD7
2004.03.23
CD0
page 193 of 320
Bit symbol
Bit name
REG_C66
66th generator polinomial
coefficient bit
REG_C67
67th generator polinomial
coefficient bit
REG_C68
68th generator polinomial
coefficient bit
REG_C69
69th generator polinomial
coefficient bit
REG_C70
70th generator polinomial
coefficient bit
REG_C71
71th generator polinomial
coefficient bit
REG_C72
72th generator polinomial
coefficient bit
REG_C73
73th generator polinomial
coefficient bit
REG_C74
74th generator polinomial
coefficient bit
REG_C75
75th generator polinomial
coefficient bit
REG_C76
76th generator polinomial
coefficient bit
REG_C77
77th generator polinomial
coefficient bit
REG_C78
78th generator polinomial
coefficient bit
REG_C79
79th generator polinomial
coefficient bit
REG_C80
80th generator polinomial
coefficient bit
REG_C81
81th generator polinomial
coefficient bit
Function
R W
The coefficient of each degree of a
generator polinomial is set up. It is
shown in below when a generator
polinomial is made into GP.
81
n
GP = Σ REG_Cn • X + X
n=0
82
M306H3MC-XXXFP/FCFP
(10) Address 0916 (=CA3 to 0)
CD15
Rev.1.00
CD8CD7
2004.03.23
CD0
page 194 of 320
Bit symbol
Bit name
REG_C50
50th generator polinomial
coefficient bit
REG_C51
51th generator polinomial
coefficient bit
REG_C52
52th generator polinomial
coefficient bit
REG_C53
53th generator polinomial
coefficient bit
REG_C54
54th generator polinomial
coefficient bit
REG_C55
55th generator polinomial
coefficient bit
REG_C56
56th generator polinomial
coefficient bit
REG_C57
57th generator polinomial
coefficient bit
REG_C58
58th generator polinomial
coefficient bit
REG_C59
59th generator polinomial
coefficient bit
REG_C60
60th generator polinomial
coefficient bit
REG_C61
61th generator polinomial
coefficient bit
REG_C62
62th generator polinomial
coefficient bit
REG_C63
63th generator polinomial
coefficient bit
REG_C64
64th generator polinomial
coefficient bit
REG_C65
65th generator polinomial
coefficient bit
Function
Refer to REG_C66 to REG_C81
(address 0816).
R W
M306H3MC-XXXFP/FCFP
(11) Address 0A16 (=CA3 to 0)
CD15
Rev.1.00
CD8CD7
2004.03.23
CD0
page 195 of 320
Bit symbol
Bit name
REG_C34
34th generator polinomial
coefficient bit
REG_C35
35th generator polinomial
coefficient bit
REG_C36
36th generator polinomial
coefficient bit
REG_C37
37th generator polinomial
coefficient bit
REG_C38
38th generator polinomial
coefficient bit
REG_C39
39th generator polinomial
coefficient bit
REG_C40
40th generator polinomial
coefficient bit
REG_C41
41th generator polinomial
coefficient bit
REG_C42
42th generator polinomial
coefficient bit
REG_C43
43th generator polinomial
coefficient bit
REG_C44
44th generator polinomial
coefficient bit
REG_C45
45th generator polinomial
coefficient bit
REG_C46
46th generator polinomial
coefficient bit
REG_C47
47th generator polinomial
coefficient bit
REG_C48
48th generator polinomial
coefficient bit
REG_C49
49th generator polinomial
coefficient bit
Function
Refer to REG_C66 to REG_C81
(address 0816).
R W
M306H3MC-XXXFP/FCFP
(12) Address 0B16 (=CA3 to 0)
CD15
Rev.1.00
CD8CD7
2004.03.23
CD0
page 196 of 320
Bit symbol
Bit name
REG_C18
18th generator polinomial
coefficient bit
REG_C19
19th generator polinomial
coefficient bit
REG_C20
20th generator polinomial
coefficient bit
REG_C21
21th generator polinomial
coefficient bit
REG_C22
22th generator polinomial
coefficient bit
REG_C23
23th generator polinomial
coefficient bit
REG_C24
24th generator polinomial
coefficient bit
REG_C25
25th generator polinomial
coefficient bit
REG_C26
26th generator polinomial
coefficient bit
REG_C27
27th generator polinomial
coefficient bit
REG_C28
28th generator polinomial
coefficient bit
REG_C29
29th generator polinomial
coefficient bit
REG_C30
30th generator polinomial
coefficient bit
REG_C31
31th generator polinomial
coefficient bit
REG_C32
32th generator polinomial
coefficient bit
REG_C33
33th generator polinomial
coefficient bit
Function
Refer to REG_C66 to REG_C81
(address 0816).
R W
M306H3MC-XXXFP/FCFP
(13) Address 0C16 (=CA3 to 0)
CD15
Rev.1.00
CD8CD7
2004.03.23
CD0
page 197 of 320
Bit symbol
Bit name
REG_C02
02nd generator polinomial
coefficient bit
REG_C03
03rd generator polinomial
coefficient bit
REG_C04
04th generator polinomial
coefficient bit
REG_C05
05th generator polinomial
coefficient bit
REG_C06
06th generator polinomial
coefficient bit
REG_C07
07th generator polinomial
coefficient bit
REG_C08
08th generator polinomial
coefficient bit
REG_C09
09th generator polinomial
coefficient bit
REG_C10
10th generator polinomial
coefficient bit
REG_C11
11th generator polinomial
coefficient bit
REG_C12
12th generator polinomial
coefficient bit
REG_C13
13th generator polinomial
coefficient bit
REG_C14
14th generator polinomial
coefficient bit
REG_C15
15th generator polinomial
coefficient bit
REG_C16
16th generator polinomial
coefficient bit
REG_C17
17th generator polinomial
coefficient bit
Function
Refer to REG_C66 to REG_C81
(address 0816).
R W
M306H3MC-XXXFP/FCFP
(14) Address 0D16 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
CRCLSB
CRCCK0
Function
Bit name
Code data shift register LSB/MSB
first selection bit.
Code data shift register clock
selection bit
0
LSB first
1
MSB first
REG_CRCCK1 REG_CRCCK0
0
0
1
1
CRCCK1
0
1
0
1
divided value
no division
divided by 2
divided by 4
divided by 8
Nothing is assigned.
The value is unfixed when it reads.
Rev.1.00
2004.03.23
page 198 of 320
REG_C00
00th generator polinomial
coefficient bit
REG_C01
01st generator polinomial
coefficient bit
Refer to REG_C66 to REG_C81
(address 0816).
R W
Rev.1.00
2004.03.23
_
_
GETPEEK3
0916
0A16
_
page 199 of 320
_
MPAL
_
_
_
_
_
_
HM84SEL
1E16
1F16
2016
2116
2216
_
_
_
_
2916
2A16
_
_
_
3616
_
_
_
_
_
EXAOFF
3316
3416
3516
YUKOU2
_
RMTSEL
3116
3216
_
_
_
STB_RES
3016
_
HCOUNT14
_
HCOUNT15
2E16
2F16
_
2D16
_
2C16
_
_
_
2816
SEL_PDEC
_
_
_
_
2716
2B16
DIVV_CK6
DIVV_CK7
2616
_
_
_
STBY0
YUKOU1
_
_
_
HCOUNT13
_
_
SEL_VPSH
_
_
DIVV_CK5
_
_
_
_
_
_
_
_
_
2316
2516
_
_
NXP
_
_
2416
_
_
_
_
_
_
ADSTART
1C16
1D16
_
_
_
_
_
FRAM
_
_
_
1916
GETPEEK1
_
CHK_FLC13
FLC13
SELVCO
_
_
GETPEEK1
_
CHK_FLC13
FLC13
SELVCO
_
_
GETPEEK1
_
CHK_FLC13
FLC13
SELVCO
LN13_OD1
LN13_OD0
_
_
LN13_EV1
1B16
_
GETPEEK2
_
GETPEEK3
1716
1816
DD13
LN13_EV0
1A16
FLC14
CHK_FLC14
FLC15
CHK_FLC15
1516
1616
_
DIVS0
_
DIVS1
1316
FRAM
GETPEEK2
1416
_
_
_
GETPEEK3
1016
1116
1216
FLC14
CHK_FLC14
FLC15
CHK_FLC15
0E16
0F16
DIVS0
FRAM
_
_
DIVS1
0C16
GETPEEK2
0D16
0B16
CHK_FLC14
CHK_FLC15
0816
DIVS0
FLC14
DIVS1
LN14_OD1
LN14_OD0
FLC15
LN15_OD1
0516
LN14_EV1
LN16_EV0
LN16_EV1
0616
LN15_OD0
0416
DD14
LN14_EV0
0716
LN15_EV1
LN17_EV0
LN17_EV1
0116
0216
0016
0316
DD15
LN15_EV0
DA5 to DA0
DD12
DD11
DD10
_
_
FLC12
FLC11
FLC10
_
_
_
FLC10
_
_
_
_
_
VERTX
YUKOU0
_
_
_
HCOUNT12
_
_
SEL_PDCH
_
_
_
_
DIVV_CK4
_
_
HORAX_ON
_
_
_
_
_
_
_
_
INTDA
_
DIVV_CK2
_
_
DIV_VPS7
DIV_PDC7
DIVF_CK2
_
_
_
_
HINT3
HINT2
PTD8
_
FILDIV1
_
STBY1
_
JSTCKDIV1
_
_
_
HCOUNT10
_
_
JSTCKON
_
_
_
HCOUNT11
_
_
_
_
_
_
STBSYNCSEP SYNCSEP_ON0
_
_
DIVV_CK3
_
_
DIV_VPS8
DIV_PDC8
DIVF_CK3
_
_
_
_
_
_
_
_
_
_
_
_
SLSLVL
_
CHK_FLC10
BIFON
CHK_FLC11
FLC11
_
_
SLSLVL
_
_
_
CHK_FLC10
BIFON
CHK_FLC11
_
GETPEEK0
_
CHK_FLC12
FLC12
_
_
_
GETPEEK0
_
CHK_FLC12
_
_
_
_
_
GET_HP0
_
CHK_FLC8
HINT1
PTC8
_
FILDIV0
JSTCKDIV0
_
_
_
HCOUNT9
_
_
_
_
SLI_GO
INTAD
_
DIVV_CK1
_
_
DIV_VPS6
DIV_PDC6
DIVF_CK1
_
_
_
HINT0
HINT_LINE8
_
RMTHD1(8)
RMTHD0(8)
_
_
_
HCOUNT8
PLSNEG8
PLSPOS8
_
_
VPS_VP8
ADON
_
DIVV_CK0
_
_
DIV_VPS5
DIV_PDC5
DIVF_CK0
NORMAL
_
_
VPS_VCO_ON PDC_VCO_R1
_
_
_
_
GET_HP1
CHK_FLC9
FLC8
_
FLC9
_
_
_
GET_HP0
_
CHK_FLC8
FLC8
_
_
_
GET_HP0
_
CHK_FLC8
_
_
GET_HP1
_
CHK_FLC9
FLC9
_
_
_
GET_HP1
_
_
_
_
FLC8
LN8_OD1
LN8_OD0
_
_
LN8_EV1
_
FLC9
SLSLVL
_
DD8
LN8_EV0
LN9_OD1
LN9_OD0
_
_
LN9_EV1
CHK_FLC9
_
_
DD9
LN9_EV0
CHK_FLC10
FLC10
_
LN10_OD1
LN10_OD0
_
_
LN10_EV1
LN10_EV0
_
_
BIFON
CHK_FLC11
FLC11
_
LN11_OD1
LN11_OD0
_
_
LN11_EV1
LN11_EV0
_
GETPEEK0
_
CHK_FLC12
FLC12
_
LN12_OD1
LN12_OD0
_
_
LN12_EV1
LN12_EV0
DD7
DD6
INTRMT3
HINT_LINE7
_
RMTHD1(7)
RMTHD0(7)
_
_
_
HCOUNT7
PLSNEG7
PLSPOS7
_
MASK7
VPS_VP7
_
_
DIVP_CK7
_
_
DIV_VPS4
DIV_PDC4
DIV_FSC7
_
MACRO_ON
_
PDC_VCO_R0
_
_
SLS7
_
SLS_HP7
SEKI7
CHK_FLC7
FLC7
_
DD5
_
DIV_FSC6
DIV_FSC5
INTRMT2
HINT_LINE6
_
RMTHD1(6)
RMTHD0(6)
_
_
_
HCOUNT6
PLSNEG6
PLSPOS6
_
MASK6
VPS_VP6
_
_
INTRMT1
HINT_LINE5
_
RMTHD1(5)
RMTHD0(5)
_
_
_
HCOUNT5
PLSNEG5
PLSPOS5
_
MASK5
VPS_VP5
_
_
DIVP_CK5
_
DIVP_CK6
_
_
DIV_VPS2
DIV_PDC2
_
DIV_VPS3
DIV_PDC3
SELXT2
_
INTRMT0
HINT_LINE4
_
RMTHD1(4)
RMTHD0(4)
_
_
_
HCOUNT4
PLSNEG4
PLSPOS4
_
MASK4
VPS_VP4
_
_
DIVP_CK4
SLION_TIM
_
DIV_VPS1
DIV_PDC1
DIV_FSC4
SELXT1
FLD1V
_
_
_
_
_
SLS4
_
SLS_HP4
SEKI4
CHK_FLC4
FLC4
_
SLS4
_
SLS_HP4
SEKI4
CHK_FLC4
FLC4
_
SLS4
_
SLS_HP4
SEKI4
CHK_FLC4
FLC4
_
LN4_OD1
LN4_OD0
_
_
LN4_EV1
_
_
SEPV0
DD4
LN4_EV0
_
SLS5
_
SLS_HP5
SEKI5
CHK_FLC5
FLC5
_
SLS5
_
SLS_HP5
SEKI5
CHK_FLC5
FLC5
_
SLS5
_
SLS_HP5
SEKI5
CHK_FLC5
FLC5
_
LN5_OD1
LN5_OD0
_
_
LN5_EV1
LN5_EV0
_
PDC_VCO_ON
SELSEP0
_
SLS6
_
SLS_HP6
SEKI6
CHK_FLC6
FLC6
_
SLS6
_
SLS7
SLS_HP6
_
SEKI6
CHK_FLC6
FLC6
_
SLS6
_
SLS_HP6
SEKI6
CHK_FLC6
FLC6
_
LN6_OD1
LN6_OD0
SLS_HP7
SEKI7
CHK_FLC7
FLC7
_
SLS7
_
SLS_HP7
SEKI7
CHK_FLC7
FLC7
_
LN7_OD1
LN7_OD0
LN6_EV1
LN16_OD0
LN16_OD1
LN7_EV1
LN17_OD0
LN6_EV0
LN17_OD1
LN7_EV0
DD3
DD2
PLSNEG3
VINT3
HINT_LINE3
_
RMTHD1(3)
RMTHD0(3)
_
_
_
HCOUNT3
VINT2
HINT_LINE2
_
RMTHD1(2)
RMTHD0(2)
_
_
_
HCOUNT2
PLSNEG2
PLSPOS2
_
PLSPOS3
MASK2
_
VPS_VP2
_
_
DIVP_CK2
REG_FLD1V
_
DIV_VPSS2
DIV_PDCS2
DIV_FSC2
_
_
_
_
_
_
SLS2
_
SLS_HP2
SEKI2
CHK_FLC2
FLC2
_
SLS2
_
SLS_HP2
SEKI2
CHK_FLC2
FLC2
_
SLS2
_
SLS_HP2
SEKI2
CHK_FLC2
FLC2
_
LN2_OD1
LN2_OD0
_
_
LN2_EV1
LN2_EV0
MASK3
VPS_VP3
6BITOFF
_
DIVP_CK3
REG_FLD2V
_
DIV_VPS0
DIV_PDC0
DIV_FSC3
SELXT0
_
_
XTAL_VCO
_
_
SLS3
_
SLS_HP3
SEKI3
CHK_FLC3
FLC3
_
SLS3
_
SLS_HP3
SEKI3
CHK_FLC3
FLC3
_
SLS3
_
SLS_HP3
SEKI3
CHK_FLC3
FLC3
_
LN3_OD1
LN3_OD0
_
_
LN3_EV1
LN3_EV0
DD1
VINT1
HINT_LINE1
_
RMTHD1(1)
RMTHD0(1)
_
_
_
HCOUNT1
PLSNEG1
PLSPOS1
_
MASK1
VPS_VP1
START
_
DIVP_CK1
ADON_TIM
_
DIV_VPSS1
DIV_PDCS1
DIV_FSC1
_
_
_
_
_
_
SLS1
_
SLS_HP1
SEKI1
CHK_FLC1
FLC1
_
SLS1
_
SLS_HP1
SEKI1
CHK_FLC1
FLC1
_
SLS1
_
SLS_HP1
SEKI1
CHK_FLC1
FLC1
_
LN1_OD1
LN1_OD0
_
_
LN1_EV1
LN1_EV0
DD0
VINT0
HINT_LINE0
_
RMTHD1(0)
RMTHD0(0)
_
_
_
HCOUNT0
PLSNEG0
PLSPOS0
_
MASK0
VPS_VP0
ADLAT
_
DIVP_CK0
ADSEL
_
DIV_VPSS0
DIV_PDCS0
DIV_FSC0
_
_
_
_
_
_
SLS0
_
SLS_HP0
SEKI0
CHK_FLC0
FLC0
_
SLS0
_
SLS_HP0
SEKI0
CHK_FLC0
FLC0
_
SLS0
_
SLS_HP0
SEKI0
CHK_FLC0
FLC0
_
LN0_OD1
LN0_OD0
_
_
LN0_EV1
LN0_EV0
for read
for read
for read
Status register 3
Status register 2
Status register 1
Line register
Remarks
M306H3MC-XXXFP/FCFP
2.14.5 Expansion Register
Control Data slice function. Expansion register composition is shown in Table 2.14.4.
Table 2.14.4 Expansion register composition
M306H3MC-XXXFP/FCFP
For accessing to expansion register data, set accessing address (DA5 to DA0) (shown in Table
2.14.4) to expansion register address control register (address 021616). Then write data (DD15 to
DD0) by expansion register data control register (address 021816). When end the data accessing,
expansion register address control register increments address automatically. Then, next address
data writing is possible.
Expansion register access registers are shown in Figure 2.14.9, expansion register access block
diagram is shown in Figure 2.14.10, and expansion register bit compositions are shown in p201 to 228.
Expansion register address control register
b15
b8
b7
b5
b0
Symbol
DA
Address
021616
Function
When reset
000016
Setting possible value
Specify accessing expansion register address
RW
0016 to 2216
Nothing is assigned.
When write, set to “0”.
When read, its content is indeterminate.
Expansion register address automatic increment
0:enable / 1:disable (Note2)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note1 : When access to expansion register, must be set expansion register address
at first, then use expansion register data control register (021816).
Note2 : When bit 8 = “0” setting,expansion register data control register increments by
accessing expansion register data control register,so it is not neccesary to
setting the next expansion register address.When bit 8 = “1” setting, the address
is fixed.
Expansion register data control register
b15
b8
b7
b0
Symbol
DD
Address
021816
Function
When reset
000016
Setting possible value
Write and read out the data of expansion register which is
specified by expansion register address control register
(address 021616)
RW
000016 to FFFF16
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 2.14.9 Expansion register access registers composition
Data bus (16-bit)
(address 021616) (DA8)
Expansion register address
control register (6) (DA5 to DA0)
Expansion register data control
register (16) (DD15 to DD0)
Increment automatically
after data access
Expansion register
Figure 2.14.10 Expansion register access block diagram
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(address 021816)
M306H3MC-XXXFP/FCFP
Bit composition of an expansion register
(1) Address 0016 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
Bit name
R W
LN0_EV0
The 0th line state register
selection bit
LN1_EV0
The 1st line state register
selection bit
LN2_EV0
The 2nd line state register
selection bit
As for the slicing method of the n-th line
(Notes 1), it is chosen which set of the
state register settings of the three sets
(Notes 2) is used with the combination
of LNn_EV0 (address 0016 and 0216,
n = 0 to 17) and LNn_EV1 (addresss
0116 and 0316, n= 0 to 17.)
LN3_EV0
The 3rd line state register
selection bit
Four kinds of following state registers
can be chosen for every line (Notes 3.)
LN4_EV0
The 4th line state register
selection bit
LN5_EV0
The 5th line state register
selection bit
LN6_EV0
The 6th line state register
selection bit
LN7_EV0
The 7th line state register
selection bit
LN8_EV0
The 8th line state register
selection bit
LN9_EV0
The 9th line state register
selection bit
LN10_EV0
The 10th line state register
selection bit
LN11_EV0
The 11th line state register
selection bit
LN12_EV0
The 12th line state register
selection bit
LN13_EV0
The 13th line state register
selection bit
LN14_EV0
The 14th line state register
selection bit
LN15_EV0
The 15th line state register
selection bit
LNn_EV1 LNn_EV0 State register(Notes 2)
Do not set up
0
0
State register 1
1
0
State register 2
0
1
State register 3
1
1
Notes 1. The n-th line: The number of lines after a slice start.
Please refer to the supplement (3) of 2.14.6 extension register composition
(P230) for details.
Notes 2. 06h to 0Ch address: State register 1
0Dh to 13h address: State register 2
14h to 1Ah address: State register 3
Notes 3. The example of a setting.
V after sync separation
The 0th line The 1st line The 2nd line
H after sync separation
line 1
line 2
•••
line n
line (n+1)
line (n+2)
LN0_EV1=0 LN1_EV1=0 LN2_EV1=1
LN0_EV0=1 LN1_EV0=1 LN2_EV0=0
slice
slice
slice
processing by processing by processing by
setup of the
setup of the
setup of the
state register 1. state register 1. state register 2.
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M306H3MC-XXXFP/FCFP
(2) Address 0116 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
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Bit name
LN0_EV1
The 0th line state register
selection bit
LN1_EV1
The 1st line state register
selection bit
LN2_EV1
The 2nd line state register
selection bit
LN3_EV1
The 3rd line state register
selection bit
LN4_EV1
The 4th line state register
selection bit
LN5_EV1
The 5th line state register
selection bit
LN6_EV1
The 6th line state register
selection bit
LN7_EV1
The 7th line state register
selection bit
LN8_EV1
The 8th line state register
selection bit
LN9_EV1
The 9th line state register
selection bit
LN10_EV1
The 10th line state register
selection bit
LN11_EV1
The 11th line state register
selection bit
LN12_EV1
The 12th line state register
selection bit
LN13_EV1
The 13th line state register
selection bit
LN14_EV1
The 14th line state register
selection bit
LN15_EV1
The 15th line state register
selection bit
Function
Refer to LNn_EV0 (address 0016)
R W
M306H3MC-XXXFP/FCFP
(3) Address 0216 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
Function
Nothing is assigned.
R W
✕ ✕
LN16_OD0
The 16th line state register
selection bit
LN17_OD0
The 17th line state register
selection bit
Refer to LNn_OD0 (address 0416)
Nothing is assigned.
✕ ✕
LN16_EV0
The 16th line state register
selection bit
LN17_EV0
The 17th line state register
selection bit
Refer to LNn_EV0 (address 0016)
(4) Address 0316 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
Function
Nothing is assigned.
LN16_OD1
The 16th line state register
selection bit
LN17_OD1
The 17th line state register
selection bit
✕ ✕
Refer to LNn_OD0 (address 0416)
Nothing is assigned.
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LN16_EV1
The 16th line state register
selection bit
LN17_EV1
The 17th line state register
selection bit
R W
✕ ✕
Refer to LNn_EV0 (address 0016)
M306H3MC-XXXFP/FCFP
(5) Address 0416 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
Bit name
R W
LN0_OD0
The 0th line state register
selection bit
LN1_OD0
The 1st line state register
selection bit
LN2_OD0
The 2nd line state register
selection bit
As for the slicing method of the n-th line
(Notes 1), it is chosen which set of the
state register settings of the three sets
(Notes 2) is used with the combination
of LNn_OD0 (address 0416 and 0216,
n = 0 to 17) and LNn_OD1 (addresss
0516 and 0316, n= 0 to 17.)
LN3_OD0
The 3rd line state register
selection bit
Four kinds of following state registers
can be chosen for every line. (Notes 3)
LN4_OD0
The 4th line state register
selection bit
LN5_OD0
The 5th line state register
selection bit
LN6_OD0
The 6th line state register
selection bit
LN7_OD0
The 7th line state register
selection bit
LN8_OD0
The 8th line state register
selection bit
LN9_OD0
The 9th line state register
selection bit
LN10_OD0
The 10th line state register
selection bit
LN11_OD0
The 11th line state register
selection bit
LN12_OD0
The 12th line state register
selection bit
LN13_OD0
The 13th line state register
selection bit
LN14_OD0
The 14th line state register
selection bit
LN15_OD0
The 15th line state register
selection bit
LNn_EV1 LNn_EV0 State register(Notes 2)
Do not set up
0
0
State register 1
1
0
State register 2
0
1
State register 3
1
1
Notes 1. The n-th line: The number of lines after a slice start.
Please refer to the supplement (3) of 2.14.6 extension register composition,
and (P230) for details.
Notes 2. 06h to 0Ch address: State register 1
0Dh to 13h address: State register 2
14h to 1Ah address: State register 3
Notes 3. The example of a setting.
V after sync separation
The 0th line The 1st line The 2nd line
H after sync separation
line 1
line 2
•••
line n
line (n+1)
line (n+2)
LN0_OD1=0 LN1_OD1=0 LN2_OD1=1
LN0_OD0=1 LN1_OD0=1 LN2_OD0=0
slice
slice
slice
processing by processing by processing by
setup of the
setup of the
setup of the
state register 1. state register 1. state register 2.
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M306H3MC-XXXFP/FCFP
(6) Address 0516 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Rev.1.00
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Bit name
LN0_OD1
The 0th line state register
selection bit
LN1_OD1
The 1st line state register
selection bit
LN2_OD1
The 2nd line state register
selection bit
LN3_OD1
The 3rd line state register
selection bit
LN4_OD1
The 4th line state register
selection bit
LN5_OD1
The 5th line state register
selection bit
LN6_OD1
The 6th line state register
selection bit
LN7_OD1
The 7th line state register
selection bit
LN8_OD1
The 8th line state register
selection bit
LN9_OD1
The 9th line state register
selection bit
LN10_OD1
The 10th line state register
selection bit
LN11_OD1
The 11th line state register
selection bit
LN12_OD1
The 12th line state register
selection bit
LN13_OD1
The 13th line state register
selection bit
LN14_OD1
The 14th line state register
selection bit
LN15_OD1
The 15th line state register
selection bit
Function
Refer to LNn_OD0 (address 0416)
R W
M306H3MC-XXXFP/FCFP
(7) Address 0616, 0D16, 1416 (=DA5 to 0)
DD15
DD8DD7
DD0
1 1 0 0 0 0 0 0 0 0
Bit symbol
Function
Bit name
Reserved bit
Must set to "0."
✕
Reserved bit
Must set to "1."
✕
✕ ✕
Nothing is assigned.
SELVCO
DIVS0
DIVS1
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R W
The PLL selection bit for
slice
The clock division bit for slice
0
1
PDC
VPS
DIVS1
0
0
1
1
DIVS0
0
1
0
1
divided value
no division
divided by 2
divided by 3
divided by 5
M306H3MC-XXXFP/FCFP
(8) Address 0716, 0E16, 1516 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
FLC0
FLC1
Function
Bit name
Framing code selection bit
R W
Framing code is set up
Clock
run-in
Framing
code
Data
Setup
FLC2
FLC3
FLC4
FLC5
FLC6
FLC7
FLC8
FLC9
FLC10
FLC11
FLC12
FLC13
FLC14
FLC15
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FLC0
to
FLC15
16 bits are checked at maximum.
However, the bit of CHK_FLCn
(addresses 0816, 0F16 and 1516)
= "1" is not checked.
M306H3MC-XXXFP/FCFP
(9) Address 0816, 0F16, 1616 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
CHK_FLC0
CHK_FLC1
Function
Bit name
Framing code check
selection bit
When acquiring data, it sets up whether
framing code set up by FLC 0 to 15
(addresses 0716, 0E16, and 1516) is
checked or not per bit.
Data will be acquired if the n-th bit
which is set as check is in agreement.
CHK_FLC2
CHK_FLC3
CHK_FLC4
CHK_FLC5
CHK_FLC6
CHK_FLC7
CHK_FLC8
CHK_FLC9
CHK_FLC10
CHK_FLC11
CHK_FLC12
CHK_FLC13
CHK_FLC14
CHK_FLC15
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CHK_FLCn
n-th bit
0
check
1
No check
R W
M306H3MC-XXXFP/FCFP
(10) Address 0916, 1016, 1716 (=DA5 to 0)
DD8DD7
DD15
0 1
1 0
DD0
1
Bit symbol
SEKI0
SEKI1
0
0
1
1
Data slicer control bit 1
Data slicer control bit 2
SEKI3
SEKI2
0
0
1
1
0
1
0
1
N
4
3
1
No differentiation
It differentiates from the digitized data
in front of N/8 cycles (clock line cycle)
to the digital value after SEKI0 and 1.
Data slicer control bit 3
SEKI5
SEKI4
0
0
1
1
0
1
0
1
N
4
3
1
No differentiation
It differentiates from the digitized data
in front of N/8 cycles (clock line cycle)
to the digital value after SEKI3 and 2.
SEKI5
SEKI6
N
SEKI0
5
0
4
1
3
0
With no differentiation
1
N-times the digital value after SEKI7.6.
SEKI3
SEKI4
R W
(Note 1)
SEKI1
SEKI2
Function
Bit name
Data slicer control bit 4
SEKI7
SEKI6
0
0
1
1
0
1
0
1
N
4
3
5
1
A digital value is averaged after AD
for N clock.
SEKI7
✕ ✕
Nothing is assigned.
Must set to "1."
Reserved bit
SLSLVL
Slice level measurement
period selection bit
0
1
2 cycles of Clock run-in
4 cycles of Clock run-in
BIFON
Data format selection bit
0
1
Non Return Zero
Bi-phase type
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✕
Reserved bit
Must set to "0."
✕
Reserved bit
Must set to "1."
✕
Reserved bit
Must set to "0."
✕
Note 1. Multiplying factor set up by SEKI6 and SEKI7.
However, do not set it with (SEKI7, SEKI6) = (1, 1).
Rev.1.00
✕
M306H3MC-XXXFP/FCFP
(11) Address 0A16, 1116, 1816 (=DA5 to 0)
DD8DD7
DD15
DD0
0 1
Bit symbol
SLS_HP0
Function
Bit name
R W
It will become below if data slice start
position is made into SLS_HS.
Slice check start position
selection bit
7
SLS_HS = T2✕Σ2n SLS_HPn
SLS_HP1
n=0
T2 : Clock run-in cycle /2
SLS_HP2
SLS_HP3
SLS_HP4
SLS_HP5
The position where framing code
begins to be checked is set up.
SLS_HP6
Setup in a 1-bit unit is possible.
SLS_HP7
GET_HP0
Phase fine-tuning bit
Slice data 0/1 judging clock is tuned
finely.
GET_HP1
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Reserved bit
Must set to "1."
✕
Reserved bit
Must set to "0."
✕
GETPEEK1 GETPEEK0
Clook run-in period
2
3
6
8
GETPEEK0
Peak detection period
selection bit 0
GETPEEK1
Peak detection period
selection bit 1
GETPEEK2
Peak detection period
selection bit 2
0
1
GETPEEK3
Peak detection period
selection bit 3
0
Only a mountain is detected.
1
A mountain and a valley are detected.
0
0
1
1
0
1
0
1
With clock compensation
With no clock compensation
M306H3MC-XXXFP/FCFP
(12) Address 0B16, 1216, 1916 (=DA5 to 0)
DD15
0
DD8DD7
DD0
1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit symbol
R W
Function
Bit name
Reserved bit
Must set to "0."
✕
Reserved bit
Must set to "1."
✕
FRAM
The number selection bit of
framing code check bits
Reserved bit
0
15-bit check
1
16-bit check
✕
Must set to "0."
(13) Address 0C16, 1316, 1A16 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0
Bit symbol
SLS0
Bit name
Slice level selection bit
Function
R W
It will become below if a slice level is
made into SLS_LVL.
SLS_LVL
SLS1
SLS2
Data
SLS3
SLS4
At the time of SLS7 ="H"
6
SLS5
SLS6
SLS_LVL = Σ2n SLSn–128
n=0
At the time of SLS7 ="L"
6
SLS_LVL = Σ2n SLSn
n=0
SLS7
Reserved bit
Nothing is assigned.
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Must set to "0."
✕
✕ ✕
M306H3MC-XXXFP/FCFP
(14) Address 1B16 (=DA5 to 0)
DD8DD7
DD15
0 0 0
DD0
0 0 1 1 0 0 0 0 0 0
Bit symbol
Function
Bit name
R W
Reserved bit
Must set to "0."
✕
Reserved bit
Must set to "1."
✕
Reserved bit
Must set to "0."
✕
Nothing is assigned.
✕ ✕
Reserved bit
Must set to "0."
✕
(15) Address 1C16 (=DA5 to 0)
DD8DD7
DD15
0 0 0 0 0 0 0 0
DD0
0 0 0 0 0 0
Bit symbol
Must set to "0."
Reserved bit
SELSEP0
H•V input selection bit
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0
1
A/D conversion completion bit
0
1
R W
✕
Separated H•V is used.
H•V of an external input is used.
Must set to "0."
Reserved bit
ADSTART
Function
Bit name
Conversion completion
Under conversion
✕
M306H3MC-XXXFP/FCFP
(16) Address 1D16 (=DA5 to 0)
DD8DD7
DD15
0 0 0
DD0
0 0
Bit symbol
Function
Bit name
✕ ✕
Nothing is assigned.
XTAL_VCO
Synchronous clock oscillation 0
selection bit
1
Reserved bit
Clock for insides stop
Clock for insides oscillation
✕
Must set to "0."
PDC_VCO_ON
PDC clock oscillation
selection bit
PDC_VCO_R0
PDC clock oscillation
change bit
PDC_VCO_R1
VPS_VCO_ON
R W
VPS clock oscillation
selection bit
Reserved bit
0
1
PDC clock stop
PDC clock oscillation
PDC_VCO PDC_VCO
_R1
_R0
0
0
0
1
1
0
1
1
0
1
Select PDC clock
Select EPG-J clock
Do not set up
Do not set up
✕
VPS clock stop
VPS clock oscillation
Must set to "0."
✕
✕ ✕
Nothing is assigned.
(17) Address 1E16 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0
Bit symbol
Function
Bit name
Reserved bit
R W
Must set to "0."
Nothing is assigned.
(18) Address 1F16 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0
Bit symbol
Function
Bit name
Nothing is assigned.
FLD1V
Field state flag
Reserved bit
MACRO_ON
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Even field
Odd field
Must set to "0."
Synchronized signal seaech flag
Nothing is assigned.
Rev.1.00
0
1
0
1
normal
unusual
R W
M306H3MC-XXXFP/FCFP
(19) Address 2016 (=DA5 to 0)
DD15
0
DD8DD7
0 0 0 0
0
DD0
1 0 0 0 0
Bit symbol
Function
Bit name
Reserved bit
✕
Must set to "0."
Synchronous (fsc) clock
phase adjustment control bit
Set up (SELXT1, SELXT0) = (1, 0)
Synchronous (fsc) clock division
control bit (Note1)
0
1
Divided by 32
SELXT2
Vertical synchronous
separation standard selection bit
0
1
Detected in L period of 15µs/22µs.
SEPV0
SELXT0
R W
SELXT1
Reserved bit
Reserved bit
NXP
Broadcast method selection bit
MPAL
Reserved bit
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Detected in L period of 22µs.
✕
Must set to "0."
Framing code check control bit
NORMAL
Setup divided value (refer to address 2116 DIV_FSC)
0
1
Check (Data is acquired if Framing code is in agreement).
No check (All data is acquired).
✕
Must set to "0."
NXP
0
0
1
1
MPAL
0
1
0
1
Must set to "0."
Broadcast method
NTSC
M-PAL
PAL
Do not set up
✕
M306H3MC-XXXFP/FCFP
(20) Address 2116 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
DIV_FSC0
The divided value selection
bit of PLL for fsc
Function
R W
The divided clock frequency fsc is
adjusted to the phase comparison
with a main clock.
DIV_FSC1
7
n
f fsc = f P1 ✕ Σ 2 DIV_FSCn
n=0
DIV_FSC2
f P1 : Divided main clock frequency
DIV_FSC3
DIV_FSC4
Set up with DIV_FSC7 to 0
=(00111010) 2.
DIV_FSC5
When set these bits, set the SELXT2
bit (address 2016) to “1.”
DIV_FSC6
DIV_FSC7
DIVF_CK0
The main clock devision
value selection bit for phase
comparison
DIVF_CK1
Using for the phase comparison with
fsc PLL, the divided main clock
frequency fP1 is adjusted.
3
n
10MHz = f P1 ✕ Σ 2 DIVF_CKn
n=0
DIVF_CK2
Set up with DIVF_CK3 to 0
=(0101)2.
DIVF_CK3
Nothing is assigned.
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✕ ✕
M306H3MC-XXXFP/FCFP
(21) Address 2216 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
DIV_PDCS0
The PLL fine-tuning bit for
PDC
Function
Slice clock frequency fPDC for PDC
is adjusted.
DIV_PDCS1
f PDC = f H ✕
DIV_PDCS2
8 n
( n=0
Σ 2 DIV_PDCn
2
+Σ2
m=0
DIV_PDC0
R W
The divided value selection bit
of PLL for PDC
m-3
DIV_PDCSm
)
f H : Horizontal synchronized
signal frequency
DIV_PDC1
When select synchronization with main
clock, set these bits as follows.
• When teletext (PDC) data is acquired
DIV_PDC8 to 0, DIV_PDCS2 to 0
= (00000100011)2
• When EPG-J is acquired
DIV_PDC8 to 0, DIV_PDCS2 to 0
= (00000101000)2
DIV_PDC2
DIV_PDC3
DIV_PDC4
(
)
(
)
DIV_PDC5
DIV_PDC6
DIV_PDC7
DIV_PDC8
✕ ✕
Nothing is assigned.
HM84SEL
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8/4 humming polarity
selection bit
0
Normal
1
The 4-bit data of 8/4 humming is
reversal-outputted.
M306H3MC-XXXFP/FCFP
(22) Address 2316 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0
Bit symbol
Function
Bit name
Slice clock frequency fPDC for VPS
is adjusted.
DIV_VPSS0 The PLL fine-tuning bit for
VPS
DIV_VPSS1
f VPS = f H ✕
8 n
( n=0
Σ 2 DIV_VPSn
2
DIV_VPSS2
+ Σ2
m=0
DIV_VPS0
R W
The divided value selection
bit of PLL for VPS
m-3
DIV_VPSSm
)
f H : Horizontal synchronized
signal frequency
DIV_VPS1
Usually, 30 is specified.
DIV_VPS8 to 0,
DIV_VPSS2 to 0
= (00000011110)2
(
DIV_VPS2
)
DIV_VPS3
DIV_VPS4
DIV_VPS5
DIV_VPS6
DIV_VPS7
DIV_VPS8
HORAX_ON
Horizontal synchronized signal 0
selection bit
1
Reserved bit
Rev.1.00
2004.03.23
page 217 of 320
Analog input
The digital input of HOR
Must set to "0."
✕
M306H3MC-XXXFP/FCFP
(23) Address 2416 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit symbol
Function
Bit name
Reserved bit
R W
✕
Must set to "0."
(24) Address 2516 (=DA5 to 0)
DD15
0
DD8DD7
DD0
0 1 0 0 1 1 0 0 0
Bit symbol
Function
Bit name
R W
0 Normal
ADSEL
A/D conversion slice bit
ADON_TIM
A/D operation control bit
0
1
Programmable
Slice period
REG_FLD1V
The 1st field slice start line
compensation bit
0
1
REG_FLD2V
The 2nd field slice start line
compensation bit
0
1
Slice starts from the line specified by
VPS_VP 8 to 0.
Slice starts from (the line specified by V
PS_VP 8 to 0 +1).
Slice starts from the line specified by
VPS_VP 8 to 0.
Slice starts from (the line specified by
VPS_VP 8 to 0 +1).
SLICEON_TIM
Slice selection bit
0
1
Every line (CHECK_START)
Programmable (PRE_START)
digital value after A/D conversion is
1 The
given from outside (with register).
Reserved bit
Must set to "0."
✕
Reserved bit
Must set to "1."
✕
Reserved bit
Must set to "0."
✕
Reserved bit
Must set to "1."
✕
Reserved bit
Must set to "0."
✕
Nothing is assigned.
Reserved bit
Rev.1.00
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✕ ✕
Must set to "0."
✕
M306H3MC-XXXFP/FCFP
(25) Address 2616 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
DIVP_CK0
Function
Bit name
R W
The clock division value
The divided clock used for the phase
selection bit for phase
comparison with a PDC clock is set up.
comparison with a PDC clock
DIVP_CK1
7
n
ffSC = fPDC ✕ Σ 2 DIVS_CKn
n=0
DIVP_CK2
fPDC : The slice clock frequency
for PDC (please refer to
DIV_PDCS0 to 2 and
DIV_PDC0 to 8
(address 2216).)
DIVP_CK3
DIVP_CK4
When teletext (PDC) data is acquired
DIVP_CK7 to 0 = (00100110)2
DIVP_CK5
When EPG-J is acquired
DIVP_CK7 to 0 = (00110101)2
DIVP_CK6
DIVP_CK7
DIVV_CK0
The clock division value
selection bit for phase
comparison with a VPS clock
The divided clock used for the phase
comparison with a VPS clock is set up.
7
DIVV_CK1
n
ffSC = fVPS ✕ Σ 2 DIVV_CKn
n=0
DIVV_CK2
fVPS : The slice clock frequency
for VPS (refer to
DIV_VPSS0 to 2 and
DIV_VPS0 to 8
(address 2316).)
DIVV_CK3
DIVV_CK4
Usually, 46 is specified.
DIVV_CK7 to 0 = (00101110)2
DIVV_CK5
DIVV_CK6
DIVV_CK7
(26) Address 2716 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0
Bit symbol
Bit name
Function
✕ ✕
Nothing is assigned.
Reserved bit
Rev.1.00
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R W
Must set to "0."
✕
M306H3MC-XXXFP/FCFP
(27) Address 2816 (=DA5 to 0)
DD8DD7
DD15
0 0 0 0 0
0 0 0 0
DD0
0
Bit symbol
ADLAT
START
Function
Bit name
Data acquisition selection bit
0
1
Acquisition of slice data
Acquisition of A/D data
Slice data selection bit
0:
Buffer memory
Control data
Data
1:
Control data
Offset to a start
(8 bits)
Reserved bit
6BITOFF
Rev.1.00
2004.03.23
page 220 of 320
Data
Data
Data
Data
Slice level
(8 bits)
Must set to "0."
A/D lower bit selection bit
0
1
Reserved bit
0
1
Data slicer control bit
INTAD
The amplifier control bit for
data slicers
INTDA
The rudder resistance control 0
bit for data slicers
1
✕
Normal
Stop by 6th bit of A/D
Must set to "0."
ADON
Reserved bit
R W
✕
Data slicer OFF.
(The amplifier for slicer is also turned off).
Data slicer ON (see INTAD and the INTDA
about the amplifier for slicer)
0 Always data slicer ON.
1
On 3 to 23 lines and 315 to 335 line amplifier ON.
On other line amplifier OFF
Always rudder resistance for data slicer ON.
On 3 to 23 lines and 315 to 335 line Rudder resistance
ON. On other line Rudder resistance OFF
Must set to "0."
✕
M306H3MC-XXXFP/FCFP
(28) Address 2916 (=DA5 to 0)
DD8DD7
DD15
DD0
0 0 0 0
Bit symbol
VPS_VP0
VPS_VP1
VPS_VP2
Function
Bit name
Setup of a slice start line
(Shared by the first field and
the second field)
Usually, 18-line slice data
from 6th line is stored.
(VPS_VP8 to VPS_VP0
= "316" fixed)
R W
If a slice start line is made into SLI_VS
<The first field>
n
8
SLI_VS = Σ 2 VPS_VPn + 2
n=0
<the second field>
8
n
SLI_VS = Σ 2 VPS_VPn + 314
n=0
VPS_VP3
The data for 18 lines is stored in
Slice RAM from the line set up by
this register.
VPS_VP4
VPS_VP5
VPS_VP6
VPS_VP7
VPS_VP8
Slice ON/OFF control bit
0
1
Slice OFF
Slice ON
SYNCSEP_ON0
Synchronous separate
selection bit
0
1
Synchronous separate circuit OFF
Synchronous separate circuit ON
STBSYNCSEP
Synchronous separate input
control bit
0
1
SYNCIN analog input
SYNCIN digital input
SLI_GO
Reserved bit
Rev.1.00
2004.03.23
page 221 of 320
Must set to "0."
✕
M306H3MC-XXXFP/FCFP
(29) Address 2A16 (=DA5 to 0)
DD15
DD8DD7
DD0
1 0 0 0 0 0 0 0
Bit symbol
MASK0
R W
Function
Bit name
PAL
NTSC
Mask width for time bases
selection bit.
1135
910
284
MASK1
MASK2
MASK3
The position of mask release is set up
256 steps of setup can be performed in one
fourth of the periods of the back between 1H
18H
to
256H
MASK4
=
Order of 0H to 17H
MASK5
PAL
It cannot set up
MASK6
0H
to
256H
NTSC
MASK7
Usually, please make it 80
Reserved bit
Must set to "0."
✕
Reserved bit
Must set to "1."
✕
(30) Address 2B16 (=DA5 to 0)
DD15
0
DD8DD7
0 0 0 0
DD0
0 0 0 0 0 0 0
Bit symbol
Function
Bit name
Must set to "0."
Reserved bit
✕
✕ ✕
Nothing is assigned.
Must set to "0."
Reserved bit
SEL_PDCH
The internal H selection bit
for data slicers
SEL_PDEC The clock selection bit for a PLL lock
Rev.1.00
2004.03.23
page 222 of 320
✕
SEL_PDCG SEL_VPSH
0
0
1
1
SEL_VPSH
Reserved bit
R W
0
1
0
1
External Hsync
From PLL for VPS
From PLL for PDC
VPS or PDC
Must set to "0."
0
VPS and a PLL lock from Hsync.
1
VPS and a PLL lock from a X'tal system.
✕
M306H3MC-XXXFP/FCFP
(31) Address 2C16 (=DA5 to 0)
DD8DD7
DD15
DD0
1 0 0 0 0 0 0
Bit symbol
PLSPOS0
Function
Bit name
Slice A/D ON period
selection bit
R W
Slice A/D ON period is counted.
V
PLSPOS1
H
PLSPOS2
PLSPOS3
8
H of
PLSPOS4
n
(n=0
Σ 2 PLSPOSn)– th shot
8
PLSPOS5
H of
n
(n=0
Σ 2 PLSNEGn)– th shot
PLSPOS6
PLSPOS7
PLSPOS8
Reserved bit
Must set to "0."
✕
Reserved bit
Must set to "1."
✕
(32) Address 2D16 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
PLSNEG0
Bit name
Slice-ON period selection bit
Function
R W
Refer to PLSPOS0 to 8
(Address 2C16)
PLSNEG1
PLSNEG2
PLSNEG3
PLSNEG4
PLSNEG5
PLSNEG6
PLSNEG7
PLSNEG8
Nothing is assigned.
Rev.1.00
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✕ ✕
M306H3MC-XXXFP/FCFP
(33) Address 2E16 (=DA5 to 0)
DD15
DD8DD7
DD0
Function
Bit symbol
Bit name
HCOUNT0
Synchronous detection bit
A horizontal synchronized signal is
counted. These bits are reset by set
the VERTX bit (address 3316) to "0."
Bit name
Function
R W
HCOUNT1
HCOUNT2
HCOUNT3
HCOUNT4
HCOUNT5
HCOUNT6
HCOUNT7
HCOUNT8
HCOUNT9
HCOUNT10
HCOUNT11
HCOUNT12
HCOUNT13
HCOUNT14
HCOUNT15
(34) Address 2F16 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
✕ ✕
Nothing is assigned.
STB_RES
Rev.1.00
2004.03.23
page 224 of 320
Extended register all reset bit
R W
0
1
Normal
It resets to address 0016 to the address
2E16 extended register.
M306H3MC-XXXFP/FCFP
(35) Address 3016 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit symbol
Function
Bit name
Reserved bit
R W
✕
Set to "0" usually
(36) Address 3116 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit symbol
Function
Bit name
Reserved bit
R W
✕
Set to "0" usually
(37) Address 3216 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
RMHTD0(0)
Remote control header length
selection bit
Function
R W
In order to detect a remote control
pulse in standby mode, the header
length to the oscillation for clocks
(address 3216) is chosen.
RMHTD0(1)
Remote
control
pulse
RMHTD0(2)
B
RMHTD0(3)
A
RMHTD0(4)
D
C
Effective
pulse
width
Header part
RMHTD0(5)
8
n
A = TXCIN ✕ Σ 2 RMHTD0(n)
n=0
8 n
C = TXCIN ✕ Σ 2 RMHTD1(n)
RMHTD0(6)
n=0
1 m
B = TXCIN ✕ Σ 2 •FILDIVm
RMHTD0(7)
m=0
2 n
✕ Σ 2 •YUKOUn
n=0
RMHTD0(8)
JSTCKDIV0
TXCIN : XCIN pin input cycle
Clock division value of JUST
CLOCK filter selection bit.
JSTCKDIV1 JSTCKDIV0 Sub clock divided value
0
0
1
1
JSTCKDIV1
JSTCKON
ON/OFF of JUST CLOCK
filter selection bit.
YUKOU0
Remote control header
judging pulse length
selection bit
0
1
0
1
0
1
Filter OFF
Filter ON
Refer to RMHTD0 (0) to (8).
YUKOU1
YUKOU2
RMTSEL
Rev.1.00
2004.03.23
page 225 of 320
Remote control header
polarity selection bit
32 divided
64 divided
128 divided
256 divided
0
1
No reverse
reverse
M306H3MC-XXXFP/FCFP
(38) Address 3316 (=DA5 to 0)
DD8DD7
DD15
DD0
0
Bit symbol
RMHTD1(0)
Function
Bit name
R W
Refer to RMHTD0 (0) to
(8)(address 3216).
Remote control header length
selection bit
RMHTD1(1)
RMHTD(2)
RMHTD1(3)
RMHTD1(4)
RMHTD1(5)
RMHTD1(6)
RMHTD1(7)
RMHTD1(8)
FILDIV0
Clock division value of remote Clock division value for Remote control
control pulse selection bit
torelance period measurement is
selected. (Note 1)
FILDIV1 FILDIV0
FILDIV1
0
0
1
1
Reserved bit
0
1
0
1
Sub clock divided value
2
4
8
16
Must set to “0.”
VERTX
Synchronous detection
reset bit
STBY0
Standby mode selection bit
✕
0
1
Horizontal synchronized signal count
Reset
0
Normal mode
1
Standby mode
Nothing is assigned
✕ ✕
Note 1. Refer to RMHTD0 (0) to (8) (address 3216)
(39) Address 3416 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit symbol
Reserved bit
Rev.1.00
2004.03.23
page 226 of 320
Bit name
Function
Must set to "0."
R W
✕
M306H3MC-XXXFP/FCFP
(40) Address 3516 (=DA5 to 0)
DD8DD7
DD15
DD0
0 0 0
Bit symbol
Bit name
HINT_LINE0
H_INT interruption position
selection bit
Function
A period after V is inputted until
H_INT rises is counted.
HINT_LINE1
V
HINT_LINE2
H
HINT_LINE3
R W
H_INT
HINT_LINE4
8 n
Σ 2 HINT_LINEn
n=0
HINT_LINE5
HINT_LINE6
HINT_LINE7
HINT_LINE8
PTC8
Port P11 output control bit
PTD8
STBY1
OSCIN input control bit
Reserved bit
EXAOFF
0
1
PTC8
PTD8
0
0
1
1
0
1
0
1
Normal mode
Standby mode
Must set to "0."
P11 output signal selection bit
(Note 2)
0
SLICEON signal
1
H_INT signal (Note 3)
Note 1. Signal selected by the EXAOFF bit is output.
Note 2. For PTC8 = “1” setting.
Note 3. Refer to HINT_LINEn.
Rev.1.00
2004.03.23
page 227 of 320
Fixed to “L”
Fixed to “H”
reverse (Note 1)
No reverse (Note 1)
✕
M306H3MC-XXXFP/FCFP
(41) Address 3616 (=DA5 to 0)
DD8DD7
DD15
DD0
0 0 0 0
Bit symbol
VINT0
Bit name
SLICEON interruption control test bit
R W
0000 : Interrupt disabled (Note 3)
1011 : Interrupt enabled
Others : Do not set up
VINT1
When the period of data acquisition
expires, the interrupt occurs by setting
these bits to 1011.
Set up the TB5IC register (Note 4)
when use by “Interrupt enabled.”
VINT2
VINT3
INTRMT0
Function
Remote control interruption
control bit (Note 1)
0000 : Interrupt disabled (Note 3)
1010 : Interrupt enabled
INTRMT1
Others : Do not set up
INTRMT2
Set up the TB4IC register (Note 4)
when use by “Interrupt enabled.”
INTRMT3
HINT0
HINT1
HINT2
HINT interruption control test
bit (Note 2)
0000 : Interrupt disabled (Note 3)
1001 : Interrupt enabled
Others : Do not set up
Set up the TB3IC register (Note 4)
when use by “Interrupt enabled.”
HINT3
Reserved bit
Must set to "0."
✕
Note 1. Refer to 2.14.6 Expansion Register Construction Composition.
Note 2. Refer to the function of HINT_LINEn (Address 3516.)
Note 3. Set these bits to 0000 when use the interrupt of Timer B3, Timer B4, or Timer B5.
Note 4. Refer to Figure 2.7.3 Interrupt Control Registers.
Rev.1.00
2004.03.23
page 228 of 320
M306H3MC-XXXFP/FCFP
2.14.6 Expansion Register Construction Composition
(1) Acquisition timming
The SLICEON signal is output in the acquisition possible period.
Vertical blanking erase period pulse
The first field
Acquisition possible period
622 623 624 625 1
2
3
4
5
6
7
8
9
19
20
21
22
23
24
SLICEON output period
The second field
310 311 312 313 314 315 316 317 318 319 320 321
331 332 333 334 335 336
The scanning lines number in figure is corresponds to slice RAM .
Figure 2.14.11 Acquisition timing
(2) Synchronized signal detection circuit
The vertical synchronous period count of the number of pulses of the horizontal synchronized signal of
a compound video signal is carried out during a fixed period. The horizontal synchronous number of
pulses can always be read from an expansion register.
A block diagram is shown in Figure. 2.14.12.
Address bus
Data bus
The arbitration circuit for
expansion registers
Latch
Q
HOR
T
16bit counter
Possible to count C00016 at maximum.
Figure 2.14.12 Block diagram of Synchronized detection circuit
Rev.1.00
2004.03.23
page 229 of 320
M306H3MC-XXXFP/FCFP
(3) Register related to Slicer
The relation between V, H signal, and the register related to slicer is shown in Figure. 2.14.13 and
Figure. 2.14.14.
V after
SYNC separation
VPS_VP 0 to 8 (address 2916)
Setting the slice start line
After V input
The first line The second line
•••
The nth line The (n+1)th line The (n+17)th line
H after
SYNC separation
After slice start
The 0th line The 1th line
On the odd field
LN0_OD1
LN0_OD0
On the even field
LN0_EV1
LN0_EV0
On the odd field
LN1_OD1
LN1_OD0
On the even field
LN1_EV1
LN1_EV0
The 17th line
On the odd field
LN17_OD1
LN17_OD0
On the even field
LN17_EV1
LN17_EV0
•••
Selection of a state register (addresses 00 to 0516)
(18 lines)
Figure 2.14.13 Register related to slicer (1)
Clock
GETPEEK2
SELVCO, DIVS0 to 1
(Addresses 0A, 11, 1816)
(Addresses 06, 0D, 1416)
Selection of the clock
Selection of the clock for slice
GET_HP0 to 1
compensation after
HOGO2(Addresses 09, 10, 1716)
(Addresses 0A, 11, 1816)
a peak detection
Selection of the clock for
Phase adjustment
period end
data acquisition
Clock run-in
Framing code
Data
H after
sync separation
SLSLVL0 to 1(Addresses 09, 10, 1716)
Slice level measurement period selection
GETPEEK0 to 1(Addresses 0A, 11, 1816)
Peak detection period selection
GETPEEK3
Fixed
(Addresses 0A, 11, 1816)
A mountain and valley
detection selection
SLS_HP0 to 7(Addresses 0A, 11, 1816)
Setting slice check start position
Figure 2.14.14 Register related to slicer (2)
Rev.1.00
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page 230 of 320
Fixed
FLC0 to 15
(Addresses 07, 0C, 1316)
Framing code selection
CHK_FLC0 to 15
(Addresses 08, 0D, 1416)
Framing code check selection
BIFON(Addresses 07, 0C, 1316)
Data formal selection
M306H3MC-XXXFP/FCFP
(4) Remote control pattern recognition
Pattern matching of remote control is performed using a sub clock oscillation. Remote control input is
input from RMTIN terminal. Interruption is generated when pattern matching is in agreement.
The example of a waveform of pattern watching is shown in Figure.2.14.15.
The flow of pattern watching is shown in Figure.2.14.16.
RMTIN
B
D
C
A
Header
0 data
1 data
The number of registers
"L" check programmable
9 bit
B
Check of a rising edge
3 bit
3.2ms
C
"H" check programmable
9 bit
15.6ms
D
Check of a falling edge
3 bit
3.2ms
Notes 1. 1bit unit 32.768kHz (a part for one clock)
Notes 2. B and D become the same value.
Figure 2.14.15 Example of waveform of pattern matching
Initial pulse waiting state
Detect a
falling edge?
No
Yes
Retain
the "L" state
during A?
No
Yes
Detect
a rising edge
during B?
No
Yes
Retain
the "H" state
during C?
No
Yes
Detect
a falling edge
during D?
No
Yes
Interruption generatin
Figure 2.14.16 Flow of pattern matching
Rev.1.00
2004.03.23
At maximum check time
A
page 231 of 320
15.6ms
M306H3MC-XXXFP/FCFP
2.14.7 8/4 Humming Decoder
8/4 humming decoder opetates only by written the data which is 8/4 humming- decoded to 8/4 humming register (address 021A16). 8/4 humming register consists of 16 bits, can decode two data at
once. Can obtain the decoded result by reading 8/4 humming register, and the decoded value and
error information are output. Corrects and outputs the decoded value for single error, and outputs only
error information for double error. Decoded result is shown in Figure 2.14.17 and humming 8/4 register
composition is shown in Figure 2.14.18.
Humming data ➁
Humming data ➀
LSB MSB
MSB
LSB
Writing
Address
021A 16
8/4 humming register
Reading
Error information
➁
0
0
Error information
➀
0
0
“1” output when
single error
Decode value
➁
MSB
Decode value
➀
LSB
MSB
LSB
“1” output when single error
“1” output when double error
“1” output when double error
Figure 2.14.17 Decoded result
Humming 8/4 register
b15
b8 b7
b0
Symbol
HM8
Address
021A16
When reset
000016
Function
8/4 humming decoder opetates only by written the data which 8/4 humming-decoded to 8/4
humming register.Can obtain the decoded result by reading this register, and can decode 2
couples of data at the same time.
Figure 2.14.18 Humming 8/4 register composition
Rev.1.00
2004.03.23
page 232 of 320
RW
M306H3MC-XXXFP/FCFP
2.14.8 24/18Humming Decoder
24/18 humming decoder operates only by written the data which is 24/18 humming-encoded to 24/18
humming register 0 (address 021C16) and 1 (address 021E16). Can obtain the decoded result by
reading the same 24/18 humming register. Decoded result is shown in Figure 2.14.19 and humming
24/18 register composition is shown in Figure 2.14.20.
Humming data M
Humming data H
Humming data L
MSB
LSB
Writing
Writing
Address
24/18 humming register 1
021E16
Reading
Reading
Error information
0
0
0
0
0
0
0
0
0
Address
021C16
24/18 humming register 0
0
0
0
Decode
value
MSB
Decode value
LSB
“1” output when single error
Output after correcting single error
“1” output when double error
Figure 2.14.19 Decoded result
Humming 24/18 register 0
b15
b8 b7
b0
Symbol
HM 0
Address
021C16
When reset
000016
R W
Function
24/18 humming decoder opetates by two ways : writing data low-order and middle-order 16
bits to this register and writing data high-order 8 bits to humming 24/18 register 1 (021E16).
Can obtain the decoded result by reading this register and humming 24/18 register 1.
Humming 24/18 register 1
b15
b8 b7
b0
Symbol
HM 1
Address
021E16
When reset
000016
Function
24/18 humming decoder opetates by two ways : writing data low-order and middle-order 16
bits to humming 24/18 register 0 (021C16) to this register and writing data high-order 8 bits
to this register.
Can obtain the decoded result by reading this register and humming 24/18 register 0.
Figure 2.14.20 Humming 24/18 register composition
Rev.1.00
2004.03.23
page 233 of 320
RW
M306H3MC-XXXFP/FCFP
Continuous error correction
When uses humming 8/4 (address 021A16) at tha same time as humming 24/18, can do the continuous error correction.
Continuous error correction sequence is shown in Figure 2.14.21.
A
Humming data➀
M
Humming data➀
L
B
Humming data➁
L
Humming data➀
H
C
Humming data➁
H
Humming data➁
M
D
Humming data ➂
M
Humming data ➂
L
E
Humming data➃
L
Humming data ➂
H
F
Humming data➃
H
Humming data➃
M
1. Writes data A to address 021C16 and writes data B to address
021E16. (Setting the humming data ➀ and L of humming data
➁.)
2. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ➀).
3. Writes data C to address 021A16 (Setting H and M of the humming data ➁).
4. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ➁).
5. Writes data D to address 021C16 and writes data E to 021E16
(Setting the humming data ➂ and L of humming data ➃.)
6. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ➂).
7. Writes data F to address 021A16 (Setting H and M of the humming data ➃).
8. Reads addresses 021C16 and 021E16 data (Obtains the decoded value and error information on the humming data ➃).
Figure 2.14.21 Continuous error correction sequence
Then, because using a part of circuit of humming 8/4 about this operation, cannot use this operation
at the same time.
When using the humming circuit, do the decoded result reading operation at once after the setting
data of humming. And do not access other memories (Including the humming circuit) before reading
of the decoded result.
Rev.1.00
2004.03.23
page 234 of 320
M306H3MC-XXXFP/FCFP
2.14.9 I/O Composition of pins for Expansion Memory
Figure 2.14.22 and figure 2.14.23 show pins for expansion memory.
VCC
CVIN1
input
for slicer
(Note 2)
VSS
SYNCIN
from internal circuit
to internal circuit
VDD2
VCC
from internal circuit
input
(Note 2)
VSS
to internal
circuit
VSS2
P11/SLICEON
VCC
from internal circuit
VCC
output
(Note 2)
VSS
PTD8 (Note 1)
PTC8 (Note 1)
VDD2
LP2, LP3, LP4
VCC
output
from internal circuit
(Note 2)
VSS
to internal circuit
VSS2
Notes 1. Refer to expansion register composition (Address 3516.)
Notes 2.
This is a parasitic diode.
The applied voltage to each port should hot exceed VCC.
Figure 2.14.22 Pins for expansion memory (1)
Rev.1.00
2004.03.23
page 235 of 320
VSS
M306H3MC-XXXFP/FCFP
VCC
FSCIN
to internal circuit
input
(Note 1)
from internal circuit
VSS
VSS2
VDD2
SVREF
VCC
from internal circuit
input
(Note 1)
to internal
circuit
VSS
VSS2
VCC
START
to internal circuit
input
VSS
Note 1.
Z
Z
Figure 2.14.23 Pins for expansion memory (2)
Rev.1.00
2004.03.23
page 236 of 320
This is a parasitic diode.
The applied voltage to each port should hot exceed VCC.
M306H3MC-XXXFP/FCFP
2.15 Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 87 lines P0 to
P10 (except P85). Each port can be set for input or output every line by using a direction register, and can
also be chosen to be or not be pulled high every 4 lines. P85 is an input-only port and does not have a pull_______
______
up resistor. Port P85 shares the pin with NMI, so that the NMI input level can be read from the P8 register
P8_5 bit.
Figures 2.15.1 to 2.15.5 show the I/O ports. Figure 2.15.6 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin
is used as a peripheral function input, set the direction bit for that pin to “0” (input mode). Any pin used as
an output pin for peripheral functions is directed for output no matter how the corresponding direction bit
is set.
When using any pin as a bus control pin, refer to “Bus Control.”
(1) Port Pi Direction Register (PDi Register, i = 0 to 10)
Figure 2.15.7 shows the direction registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
_______
_______ _______ _________ ______ __________________
_________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
No direction register bit for P85 is available.
(2) Port Pi Register (Pi Register, i = 0 to 10)
Figure 2.15.8 show the Pi registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For
ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register,
and data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register. The data written to the port latch is output
from the pin. The bits in the Pi register correspond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
_______
_______ _______ _________ ______ __________________
_________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
(3) Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
Figure 2.15.9 shows the PUR0 to PUR2 registers.
The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high
in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit
is set for input mode.
However, the pull-up control register has no effect on P0 to P3, P40 to P43, and P5 during memory
extension and microprocessor modes. Although the register contents can be modified, no pull-up resistors are connected.
(4) Port Control Register
Figure 2.15.10 shows the port control register.
When the P1 register is read after setting the PCR register’s PCR0 bit to “1”, the corresponding port latch
can be read no matter how the PD1 register is set.
Rev.1.00
2004.03.23
page 237 of 320
M306H3MC-XXXFP/FCFP
Pull-up selection
Direction register
P00 to P07, P20 to P27
P30 to P37, P40 to P47,
P50 to P54, P56,
Data bus
Port latch
(Note 1)
Pull-up selection
Direction register
P10 to P14
Port P1 control register
Data bus
Port latch
(Note 1)
Pull-up selection
Direction register
P15 to P17
Port P1 control register
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction
register
P57, P60, P64, P73 to P76,
P80, P81, P90, P92
"1"
Output
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Note 1:
Figure 2.15.1. I/O Ports (1)
Rev.1.00
2004.03.23
page 238 of 320
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
M306H3MC-XXXFP/FCFP
Pull-up selection
Direction
register
P61, P65, P72
"1"
Output
Port latch
Data bus
Switching
between
CMOS and
Nch
(Note 1)
Input to respective peripheral functions
Pull-up selection
P82 to P84
Direction register
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P55, P77, P91, P97
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Note 1:
Figure 2.15.2. I/O Ports (2)
Rev.1.00
2004.03.23
page 239 of 320
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
M306H3MC-XXXFP/FCFP
Pull-up selection
Direction register
P62, P66
Port latch
Data bus
(Note 1)
Switching
between
CMOS and Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P63, P67
“1”
Port latch
Data bus
Output
(Note 1)
Switching between CMOS and Nch
P85
Data bus
NMI interrupt input
(Note 1)
Direction register
P70, P71
“1”
Output
Data bus
Port latch
(Note 2)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Note 2:
symbolizes a parasitic diode.
Figure 2.15.3. I/O Ports (3)
Rev.1.00
2004.03.23
page 240 of 320
M306H3MC-XXXFP/FCFP
Pull-up selection
P100 to P103
(inside dotted-line
not included)
P104 to P107
(inside dotted-line
included)
Direction register
Port latch
Data bus
(Note)
Analog input
Input to respective peripheral functions
Pull-up selection
Direction register
P93, P94
Data bus
Port latch
(Note)
Input to respective peripheral functions
Pull-up selection
Direction register
P96
“1”
Output
Port latch
Data bus
(Note)
Analog input
Pull-up selection
Direction register
P95
“1”
Output
Data bus
Port latch
(Note)
Input to respective peripheral functions
Analog input
Note:
Figure 2.15.4. I/O Ports (4)
Rev.1.00
2004.03.23
page 241 of 320
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
M306H3MC-XXXFP/FCFP
Pull-up selection
Direction register
P87
Data bus
Port latch
(Note)
fc
Rf
Pull-up selection
Rd
Direction register
P86
"1"
Data bus
Port latch
Output
(Note)
Note:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 2.15.5. I/O Ports (5)
(Note 2)
BYTE
BYTE signal input
(Note 1)
(Note 2)
CNVSS
CNVSS signal input
(Note 1)
RESET
RESET signal input
(Note 1)
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Note 2: A parasitic diode on the VCC side is added to the mask ROM version.
Make sure the input voltage on each port will not exceed Vcc.
Figure 2.15.6. I/O Pins
Rev.1.00
2004.03.23
page 242 of 320
M306H3MC-XXXFP/FCFP
Port Pi direction register (i=0 to 7 and 9 to 10) (Note 1, 2, 3)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PD0 to PD3
PD4 to PD7
PD9 to PD10
Bit symbol
Address
03E216, 03E316, 03E616, 03E716
03EA16, 03EB16, 03EE16, 03EF16
03F316, 03F616
Bit name
PDi_0
PDi_1
Port Pi0 direction bit
Port Pi1 direction bit
PDi_2
Port Pi2 direction bit
PDi_3
Port Pi3 direction bit
PDi_4
Port Pi4 direction bit
PDi_5
Port Pi5 direction bit
PDi_6
PDi_7
Port Pi6 direction bit
Port Pi7 direction bit
After reset
0016
0016
0016
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 7 and 9 to 10)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: Make sure the PD9 register is written to by the next instruction after setting the PRCR
register’s PRC2 bit to “1” (write enabled).
Note 2: During memory extension and microprocessor modes, the PD register for the pins
functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
Port P8 direction register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
03F216
PD8
Bit symbol
PD8_0
Port P80 direction bit
Port P81 direction bit
PD8_2
Port P82 direction bit
PD8_3
Port P83 direction bit
PD8_4
Port P84 direction bit
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
PD8_6
Port P86 direction bit
PD8_7
Port P87 direction bit
Figure 2.15.7. PD0 to PD10 Registers
2004.03.23
Function
PD8_1
(b5)
Rev.1.00
Bit name
After reset
00X000002
page 243 of 320
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
RW
RW
RW
RW
RW
RW
RW
M306H3MC-XXXFP/FCFP
Port Pi register (i=0 to 7 and 9 to 10) (Note 1, 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P0 to P3
P4 to P7
P9 to P10
Bit symbol
Address
03E016, 03E116, 03E416, 03E516
03E816, 03E916, 03EC16, 03ED16
03F116, 03F416
Bit name
Pi_0
Port Pi0 bit
Pi_1
Pi_2
Port Pi1 bit
Port Pi2 bit
Pi_3
Port Pi3 bit
Pi_4
Port Pi4 bit
Pi_5
Port Pi5 bit
Pi_6
Port Pi6 bit
Pi_7
Port Pi7 bit
After reset
Indeterminate
Indeterminate
Indeterminate
Function
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : “L” level
1 : “H” level (Note 1)
(i = 0 to 7 and 9 to 10)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance.
Note 2: During memory extension and microprocessor modes, the Pi register for the pins
functioning as bus control pins (A0 to A 19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
Port P8 register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P8
Bit symbol
2004.03.23
Bit name
P8_0
Port P80 bit
P8_1
Port P81 bit
P8_2
Port P82 bit
P8_3
Port P83 bit
P8_4
Port P84 bit
P8_5
Port P85 bit
P8_6
Port P86 bit
P8_7
Port P87 bit
Figure 2.15.8. P0 to P10 Registers
Rev.1.00
Address
03F016
page 244 of 320
After reset
Indeterminate
Function
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register (except for P85)
0 : “L” level
1 : “H” level
RW
RW
RW
RW
RW
RW
RO
RW
RW
M306H3MC-XXXFP/FCFP
Pull-up control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR0
Address
03FC16
Bit symbol
Bit name
PU00
P00 to P03 pull-up
PU01
P04 to P07 pull-up
PU02
P10 to P13 pull-up
PU03
P14 to P17 pull-up
PU04
P20 to P23 pull-up
PU05
P24 to P27 pull-up
PU06
P30 to P33 pull-up
After reset
0016
Function
0 : Not pulled high
1 : Pulled high (Note 2)
PU07
P34 to P37 pull-up
Note 1: During memory extension and microprocessor modes, the pins are not pulled high although their
corresponding register contents can be modified.
Note 2: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
RW
RW
RW
RW
RW
RW
RW
RW
RW
Pull-up control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Address
03FD16
Bit symbol
PU10
Bit name
P40 to P43 pull-up (Note 2)
PU11
P44 to P47 pull-up (Note 4)
PU12
P50 to P53 pull-up (Note 2)
PU13
P54 to P57 pull-up (Note 2)
PU14
P60 to P63 pull-up
PU15
P64 to P67 pull-up
PU16
P72 to P73 pull-up (Note 1)
After reset(Note 5)
000000002
000000102
Function
0 : Not pulled high
1 : Pulled high (Note 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
PU17
P74 to P77 pull-up
Note 1: The P70 and P71 pins do not have pull-ups.
Note 2: During memory extension and microprocessor modes, the pins are not pulled high although the contents
of these bits can be modified.
Note 3: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Note 4: If the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor mode) in a
program during single-chip mode, the PU11 bit becomes “1”.
Note 5: The values after hardware reset 1 and 2 are as follows:
• 000000002 when input on CNVss pin is “L“
• 000000102 when input on CNVss pin is “H“
(When input on the CNVss pin and the M1 pin are “H“ with the flash memory version)
The values after software reset, watchdog timer reset and oscillation stop detection reset are as follows:
• 000000002 when PM 01 to PM00 bits of PM0 register are “002“ (single-chip mode)
• 000000102 when PM 01 to PM00 bits of PM0 register are “012“ (memory expansion mode) or
“112“ (microprocessor mode)
Pull-up control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR2
Address
03FE16
Bit symbol
Bit name
PU20
P80 to P83 pull-up
PU21
PU22
P84 to P87 pull-up (Note 2)
P90 to P93 pull-up
PU23
PU24
P94 to P97 pull-up
P100 to P103 pull-up
PU25
P104 to P107 pull-up
After reset
0016
Function
0 : Not pulled high
1 : Pulled high (Note 1)
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
Note 1: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Note 2: The P85 pin does not have pull-up.
(b7-b6)
Figure 2.15.9. PUR0 to PUR2 Registers
Rev.1.00
2004.03.23
page 245 of 320
RW
RW
RW
RW
RW
RW
RW
M306H3MC-XXXFP/FCFP
Port control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
PCR
Bit symbol
PCR0
Address
03FF16
Bit name
Port P1 control bit
After reset
0016
Function
Nothing is assigned. In an attempt to write to these bits,
(b7-b1)
Figure 2.15.10. PCR Register
Rev.1.00
2004.03.23
page 246 of 320
RW
Operation performed when the P1
register is read
0: When the port is set for input,
the input levels of P10 to P17 RW
pins are read. When set for
output, the port latch is read.
1: The port latch is read
regardless of whether the port
is set for input or output.
write “0”. The value, if read, turns out to be “0”.
M306H3MC-XXXFP/FCFP
Table 2.15.1. Unassigned Pin Handling in Single-chip Mode
Pin name
Connection
Ports P0 to P7, P80 to P84,
P86 to P87, P9 to P10
After setting for input mode, connect every pin to VSS via a resistor(pull-down);
or after setting for output mode, leave these pins open. (Note 1, 2 ,3)
XOUT (Note 4)
Open
NMI (P85)
Connect via resistor to VCC (pull-up)
AVCC
Connect to VCC
AVSS, VREF, BYTE
Connect to VSS
Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
Note 3: When the ports P70 and P71 are set for output mode, make sure a low-level signal is output from the pins.
The ports P70 and P71 are N-channel open-drain outputs.
Note 4: With external clock input to XIN pin.
Table 2.15.2. Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Pin name
Connection
Ports P0 to P7, P80 to P84,
P86 to P87, P9 to P10
After setting for input mode, connect every pin to VSS via a resistor (pull-down);
or after setting for output mode, leave these pins open. (Note 1, 2, 3, 4)
P45 / CS1 to P47 / CS3
Connect to VCC via a resistor (pulled high) by setting the PD4 register’s
corresponding direction bit for CSi (i=1 to 3) to “0” (input mode) and the
CSR register’s CSi bit to “0” (chip select disabled).
BHE, ALE, HLDA,
XOUT (Note 5), BCLK (Note 6)
Open
HOLD, RDY, NMI (P85)
Connect via resistor to VCC (pull-up)
AV CC
Connect to VCC
AV SS, VREF
Connect to VSS
Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
Note 3: If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor mode
is switched over in a program after reset. For this reason, the voltage levels on these pins become
indeterminate, causing the power supply current to increase while they remain set for input ports.
Note 4: When the ports P70 and P71 are set for output mode, make sure a low-level signal is output from the pins.
The ports P70 and P71 are N-channel open-drain outputs.
Note 5: With external clock input to XIN pin.
Note 6: If the PM07 bit in the PM0 register is set to “1” (BCLK not output), connect this pin to VCC via a resistor
(pulled high).
Rev.1.00
2004.03.23
page 247 of 320
M306H3MC-XXXFP/FCFP
Microcomputer
Microcomputer
Port P0 to P10 (except for P85)
Port P6 to P10 (except for P85)
(Input mode)
·
·
·
(Input mode)
(Output mode)
(Input mode)
·
·
·
(Input mode)
··
·
(Output mode)
Open
AVCC
NMI
BHE
HLDA
ALE
XOUT
BCLK (Note)
BYTE
HOLD
AVSS
RDY
VREF
AVCC
NMI
XOUT
Port P45 / CS1
to P47 / CS3
Open
VCC
··
·
Open
Open
VCC
AVSS
VREF
VSS
VSS
In single-chip mode
In memory expansion mode or
in microprocessor mode
Note 1: If the PM0 register’s PM07 bit is set to “1” (BCLK not output), connect this pin to VCC via a resistor
(pulled high).
Figure 2.15.11. Unassigned Pins Handling
Rev.1.00
2004.03.23
page 248 of 320
M306H3MC-XXXFP/FCFP
3. Electrical Characteristics
Table 3.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Rated value
Unit
VCC
Supply voltage
V CC=AVcc
-0.3 to 5.75
V
AV CC
Analog supply voltage
VCC=AVcc
-0.3 to 5.75
V
Input
voltage
VI
RESET, CNVSS, BYTE,
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P80 to P87,
P90 to P97, P100 to P107,
VREF, XIN, M1, START
-0.3 to VCC + 0.3
P70, P71
Output
voltage
VO
-0.3 to 5.75
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
P11
XOUT
-0.3 to VCC + 0.3
P70, P71
Topr=25 C
V
V
V
-0.3 to 5.75
V
Pd
Power dissipation
900
mW
Topr
Operating ambient temperature
-20 to 70
C
Storage temperature
-20 to 125
C
Tstg
Rev.1.00
2004.03.23
page 249 of 320
M306H3MC-XXXFP/FCFP
Table 3.2. Recommended Operating Conditions (Note 1)
Symbol
VCC
AVcc
Parameter
Min.
Supply voltage
Analog supply voltage
4.75
Vss
Supply voltage
AVss
Analog supply voltage
P31 to P37, P40 to P47, P50 to P57
HIGH input
voltage
P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode)
VIH
LOW input
voltage
VIL
Standard
Typ.
5.0
VCC
Max.
5.25
Unit
V
V
V
0
0
0.8VCC
VCC
V
V
0.8VCC
VCC
V
P00 to P07, P10 to P17, P20 to P27, P30
(data input during memory expansion and microprocessor modes)
0.5VCC
VCC
V
P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107,
XIN, RESET, CNVSS, BYTE, M1, START
0.8VCC
VCC
V
P70 , P71
0.8VCC
5.75
V
P31 to P37, P40 to P47, P50 to P57
0
0.2VCC
V
P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode)
0
0.2VCC
V
P00 to P07, P10 to P17, P20 to P27, P30
(data input during memory expansion and microprocessor modes)
0
0.16VCC
V
0
0.2VCC
V
P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107,
XIN, RESET, CNVSS, BYTE, M1, START
Composite video input voltage
VCVIN
I OH (peak)
I OH (avg)
I OL (peak)
I OL (avg)
CVIN, SYNCIN
V
2V P-P
HIGH peak output
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
current (Note2, Note3) P40 to P47, P50 to P57, P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P11
HIGH average
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
output current
P40 to P47, P50 to P57, P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P11
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
LOW peak output
current
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P11
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
LOW average
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
output current
P80 to P84,P86,P87,P90 to P97,P100 to P107,
P11
f (XIN)
Main clock input oscillation frequency
(Note 4)
VCC =4.75 to 5.25V
f (XCIN)
Sub-clock oscillation frequency
VCC =2.60 to 5.25V
(Note 5)
f (BCLK)
CPU operation clock
0
32.768
0
-10.0
mA
- 5 .0
mA
10.0
mA
5.0
mA
10
MHz
50
kHz
10
MHz
Note 1: Referenced to VCC = 4.75 to 5.25V at Topr = -20 to 70 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, P10 and P11 must be 80mA max. The total IOL (peak)
for ports P3, P4, P5, P6, P7 and P80 to P84 must be 80mA max. The total IOH (peak) for ports P0, P1, and P2
must be -40mA max. The total IOH (peak) for ports P3, P4 and P5 must be -40mA max. The total IOH (peak) for
ports P6, P7, and P80 to P84 must be -40mA max. The total IOH (peak) for ports P86, P87, P9, P10 and P11
must be -40mA max.
Note 4: Program or erase on the flash memory by VCC = 5.0V ± 0.25V.
Note 5: Use in low power dissipation mode. When operating on low voltage (VCC = 3.0V), only single-chip mode can be used.
Rev.1.00
2004.03.23
page 250 of 320
M306H3MC-XXXFP/FCFP
Table 3.3. A-D Conversion Characteristics (Note 1)
Symbol
Parameter
–
Resolution
–
Absolute accuracy
RLADDER
tCONV
tSAMP
VREF
VIA
Ladder resistance
Conversion time(8bit), Sample & hold
function available
Standard
Unit
Min. Typ. Max.
Measuring condition
VREF =VCC
AN0 to AN7 input
VREF= ANEX0, ANEX1 input
VCC = External operation amp
5V
10
2.8
VREF =VCC
VREF =VCC =5V, øAD=10MHz
Sampling time
Reference voltage
8
±3
Bits
LSB
±4
LSB
40
VCC
µs
V
VREF
V
0.3
4.75
0
Analog input voltage
kΩ
µs
Note 1: Referenced to VCC =AVCC=VREF=4.75 to 5.25 V, VSS=AVSS=0V at Topr = -20 to 70 °C unless otherwise specified.
Note 2: AD operation clock frequency (ØAD frequency) must be 10 MHz or less.
Note 3: A case without sample & hold function turn ØAD frequency into 250 kHz.
A case with sample & hold function turn ØAD frequency into 1 MHz.
Table 3.4. Flash Memory Version Electrical Characteristics (Note 1)
Standard
Typ.
Max
Word program time
30
200
µs
Block erase time
1
4
s
1Xn
4Xn
s
30
200
µs
15
µs
Symbol
Parameter
Measuring condition
Min.
Erase all unlocked blocks time
Lock bit program time
tps
Flash memory circuit stabilization wait time
Unit
Note 1: Referenced to VCC =4.75 to 5.25 V at Topr = 0 to 60 °C unless otherwise specified.
Note 2: n denotes the number of block erases.
Table 3.5. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60oC)
Flash program, erase voltage
Flash read operation voltage
VCC = 5.0 ± 0.25 V
VCC = 2.60 to 5.25 V
Table 3.6. Power Supply Circuit Timing Characteristics
Symbol
Measuring condition
Parameter
td(P-R)
Time for internal power supply stabilization during powering-on
td(R-S)
STOP release time
td(W-S)
Low power dissipation mode wait mode release time
td(M-L)
Time for internal power supply stabilization when main clock oscillation starts
(Note)
VCC = 5.0V
Note : At XIN-XOUT generation.
Interrupt for
stop mode
release
CPU clock
td(R-S)
Rev.1.00
2004.03.23
page 251 of 320
Min.
Standard
Typ.
ax.
Unit
2
ms
150
µs
150
µs
50
µs
M306H3MC-XXXFP/FCFP
VCC = 5V
Table 3.7. Electrical Characteristics (1) (Note 1)
Parameter
Symbol
VOH
Measuring condition
HIGH output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
IOH=-5mA
P60 to P67, P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
P11
VOH
HIGH output P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
voltage
P60 to P67, P72 to P77, P80 to P84, IOH=-200µA
P86, P87, P90 to P97, P100 to P107,
P11
VOH
HIGH output
LP2 to LP4
voltage
VOH
HIGH output
voltage
HIGH output
voltage
VOL
VOL
XOUT
XCOUT
LOW output
voltage
XOUT
LOW output
voltage
XCOUT
VT+-VT-
IIH
Vcc
V
3.75
Vcc-2.0
V
Vcc
Vcc
2.5
With no load applied
With no load applied
V
1.6
IOL=5mA
IOL=200µA
2.0
V
0.45
V
V
VCC=4.75V, I OL=0.05mA
0.4
HIGHPOWER
IOL=1mA
2.0
LOWPOWER
IOL=0.5mA
2.0
HIGHPOWER
With no load applied
With no load applied
LOWPOWER
RESET
V
0
V
V
0
0.2
1.0
V
0.2
2.2
V
HIGH input P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
current
P60 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P107,
XIN, RESET, CNVss, BYTE,
M1, START
VI=5V
5.0
µA
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P107,
XIN, RESET, CNVss, BYTE,
M1, START
VI=0V
-5.0
µA
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107
VI=0V
170
kΩ
LOW input
current
I IL
RPULLUP
Vcc-0.3
IOH=-0.5mA
Hysteresis HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, NMI,
ADTRG, CTS0 to CTS2, SCL, SDA,
CLK0 to CLK4,TA2OUT to TA4OUT,
KI0 to KI3, RxD0 to RxD2, SIN3, SIN4
Hysteresis
V
LOWPOWER
LOW output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
P11
VOL
Vcc
Vcc-2.0
HIGHPOWER
Unit
Vcc-2.0
IOH=-1mA
LOW output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
P11
LOW output
LP2 to LP4
voltage
Standard
Typ. Max.
HIGHPOWER
LOWPOWER
VOL
VT+-VT-
VCC=4.75V, I OH=-0.05mA
Min
Pull-up
resistance
50
30
R fXIN
Feedback resistance
XIN
1.5
MΩ
R fXCIN
Feedback resistance
XCIN
15
MΩ
V RAM
RAM retention voltage
Stop mode
V
2.0
V SYNCIN
Sync voltage amplitude
0.3
0.6
1.2
V
V dat(text)
Teletext data voltage amplitude
0.6
0.9
1.4
V
fH
Horizontal synchronous signal frequency
14.6
17.0
kHZ
15.625
Note 1: Referenced to VCC= 4.75 to 5.25 V, VSS=0V at Topr = -20 to 70 °C, f(BCLK)=10 MHz unless otherwise specified.
Rev.1.00
2004.03.23
page 252 of 320
M306H3MC-XXXFP/FCFP
VCC = 3V
Table 3.8. Electrical Characteristics (2) (Note)
Symbol
VOH
VOH
VOL
VOL
Measuring condition
Parameter
HIGH output
voltage
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
P40 to P47,P50 to P57,P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107, P11
HIGH output voltage
XCOUT
HIGHPOWER
LOWPOWER
LOW output
voltage
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
P40 to P47,P50 to P57,P60 to P67,P70 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107, P11
LOW output voltage
Hysteresis
VT+-VT-
XCOUT
IOH=-1mA
Min.
Standard
Typ.
VC C
VCC-0.5
With no load applied
With no load applied
2.5
1 .6
HIGHPOWER
With no load applied
0
LOWPOWER
With no load applied
0
II H
V
V
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI,
CLK0 to CLK4, TA2OUT to TA4OUT, KI0 to KI3
Hysteresis
HIGH input
current
V
V
0 .5
IOL=1mA
0 .2
VT+-VT-
Unit
0 .2
RESET
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
P40 to P47,P50 to P57,P60 to P67,P70 to P77,
P80 to P87,P90 to P97,P100 to P107,
(0.7)
VI=3V
0.8
V
1.8
V
4 .0
µA
XIN, RESET, CNVss, BYTE, M1, START
LOW input
current
II L
RPULLUP
RfXCIN
Pull-up
resistance
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
P40 to P47,P50 to P57,P60 to P67,P70 to P77,
P80 to P87,P90 to P97,P100 to P107,
XIN, RESET, CNVss, BYTE, M1, START
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
P40 to P47,P50 to P57,P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107,
Feedback resistance
VI=0V
VI=0V
XCIN
Note : Referenced to VCC=3.0V, VSS=0V at Topr = -20 to 70 °C, f(XCIN)=32kHz unless otherwise specified.
Use in single-chip mode and low power dissipation mode.
Rev.1.00
2004.03.23
page 253 of 320
50
100
25
-4 . 0
µA
500
kΩ
MΩ
M306H3MC-XXXFP/FCFP
VCC = 5V
Table 3.9. Electrical Characteristics (2) (Note 1)
Symbol
Measuring condition
Parameter
In single-chip mode, the output
pins are open and other pins are
VSS
Mask ROM
Flash memory
Flash memory
Program
Flash memory
Erase
Mask ROM
ICC
Power supply current
Flash memory
Min.
f(BCLK)=10MHz,
VCC =5.0V
f(BCLK)=10MHz,
VCC =5.0V
f(BCLK)=10MHz,
VCC =5.0V
f(BCLK)=10MHz,
VCC =5.0V
Max.
50
100
50
100
Unit
mA
mA
15
mA
25
mA
f(XCIN)=32kHz,
Low power dissipation mode,
ROM(Note 3), (Note4) Vcc=5.0V
25
µA
f(BCLK)=32kHz,
Low power dissipation mode,
RAM(Note 3), (Note4) Vcc=5.0V
25
µA
420
µA
7 .5
µA
f(BCLK)=32kHz
Low power dissipation mode,
Flash memory(Note 3), (Note4)
Vcc=5.0V
f(BCLK)=32kHz,
Wait mode (Note 2), (Note4)
Mask ROM
Flash memory
Standard
Typ.
Oscillation capacity High
f(BCLK)=32kHz,
Wait mode(Note 2), (Note4)
Vcc=5.0V
Oscillation capacity Low
5.0
f(BCLK)=32kHz,
Wait mode (Note 2), (Note4)
Oscillation capacity High
Vcc=3.0V
6.0
f(BCLK)=32kHz,
Wait mode(Note 2), (Note4)
Vcc=3.0V
2.0
8.0
µA
Stop mode, (Note4)
Topr=25°C
Vcc=5.0V
0 .8
5.0
µA
Oscillation capacity Low
10.0
µA
µA
Note 1: Referenced to VCC= 5 V, VSS=0V at Topr = 25 °C, f(BCLK)=10MHz unless otherwise specified.
Note 2: With one timer operated using fC32. (Slicer operation OFF)
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: • All of VDD2 and VDD3 are at the same potential level as VCC.
• Extension register (address 3516 DD13) STBY1 and (address 3316 DD11) STBY0 are set to 1 while all other extension registers (addresses 0016 through 3616)
are set to the initial state.
• Clock input to the FSCIN pin is disabled.
• Inputs to the SYNCIN and CVIN1 pins are disabled.
Tabl 3.10 Video signal input conditions (Note 1)
Parameter
Symbol
VIN-cu
Composite video signal input clamp voltage
Measuring condition
Sync-chip voltage
Note 1: Referenced to Vcc = 5.0 V at Topr = -20 to 70 °C unless otherwise specified.
Rev.1.00
2004.03.23
page 254 of 320
Min
Standard
Typ. Max.
1.0
Unit
V
M306H3MC-XXXFP/FCFP
VCC = 5V
Timing Requirements
(VCC = 5V, VSS = 0V, at Topr = – 20 to 70oC unless otherwise specified)
Table 3.11. External Clock Input (XIN input)
Symbol
Parameter
tc
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
Unit
100
ns
50
50
ns
ns
ns
ns
15
15
Table 3.12. Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
tac1(RD-DB)
Data input access time (for setting with no wait)
tac2(RD-DB)
Data input access time (for setting with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK )
tsu(HOLD-BCLK )
th(RD-DB)
th(BCLK -RDY)
th(BCLK-HOLD )
td(BCLK-HLDA )
Standard
Max.
Min.
(Note 1)
(Note 2)
(Note 3)
40
Unit
ns
ns
ns
40
ns
ns
ns
0
ns
0
ns
30
ns
0
40
ns
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
– 45
[ns]
Note 2: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 45
f(BCLK)
[ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait
setting.
Note 3: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 45
f(BCLK)
[ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
Table 3.13. Remote Control Pulse Input
Symbol
Tw(RMTH)
Tw(RMTL)
Parameter
RMTIN input HIGH pulse width
RMTIN input LOW pulse width
Standard
Min.
Max.
61
61
Unit
µs
µs
Table 3.14. JUST CLOCK Input
Symbol
Tw(JSTH)
Tw(JSTL)
Rev.1.00
Parameter
JSTIN input HIGH pulse width
JSTIN input LOW pulse width
2004.03.23
page 255 of 320
Standard
Min.
Max.
61
61
Unit
µs
µs
M306H3MC-XXXFP/FCFP
VCC = 5V
Timing Requirements
(VCC = 5V, VSS = 0V, at Topr = – 20 to 70oC unless otherwise specified)
Table 3.15. Timer A Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
100
Unit
ns
tc(TA)
TAi IN input cycle time
tw(TAH)
TAi IN input HIGH pulse width
40
ns
tw(TAL)
TAi IN input LOW pulse width
40
ns
Table 3.16. Timer A Input (Gating Input in Timer Mode)
Symbol
Parameter
tc(TA)
TAi IN input cycle time
tw(TAH)
tw(TAL)
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
Standard
Min.
Max.
400
200
200
Unit
ns
ns
ns
Table 3.17. Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Parameter
Standard
Max.
Min.
Unit
tc(TA)
TAi IN input cycle time
200
ns
tw(TAH)
tw(TAL)
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
100
100
ns
ns
Table 3.18. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
tw(TAH)
tw(TAL)
Parameter
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
Standard
Max.
Min.
100
100
Unit
ns
ns
Table 3.19. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
TAi OUT input cycle time
Standard
Max.
Min.
2000
TAi OUT input HIGH pulse width
1000
TAi OUT input LOW pulse width
TAi OUT input setup time
TAi OUT input hold time
1000
400
400
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Rev.1.00
Parameter
2004.03.23
page 256 of 320
Unit
ns
ns
ns
ns
ns
M306H3MC-XXXFP/FCFP
VCC = 5V
Timing Requirements
(VCC = 5V, VSS = 0V, at Topr = – 20 to 70oC unless otherwise specified)
Table 3.20. Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input HIGH pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
40
200
ns
tc(TB)
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
80
ns
ns
Table 3.21. Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
200
200
ns
ns
Table 3.22. Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
tw(TBH)
TBiIN input HIGH pulse width
200
ns
ns
tw(TBL)
TBiIN input LOW pulse width
200
ns
Table 3.23. A-D Trigger Input
Symbol
tc(AD)
Parameter
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
tw(ADL)
Standard
Min.
1000
125
Max.
Unit
ns
ns
Table 3.24. Serial I/O
Symbol
Parameter
Standard
Min.
Max.
Unit
CLKi input cycle time
200
ns
tw(CKH)
CLKi input HIGH pulse width
100
ns
tw(CKL)
CLKi input LOW pulse width
100
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
tsu(D-C)
RxDi input setup time
RxDi input hold time
tc(CK)
th(C-D)
ns
80
ns
0
30
ns
90
ns
ns
_______
Table 3.25. External Interrupt INTi Input
Symbol
Parameter
tw(INH)
INTi input HIGH pulse width
tw(INL)
INTi input LOW pulse width
Rev.1.00
2004.03.23
page 257 of 320
Standard
Min.
250
250
Max.
Unit
ns
ns
M306H3MC-XXXFP/FCFP
VCC = 5V
Switching Characteristics
(VCC = 5V, VSS = 0V, at Topr = – 20 to 70oC unless otherwise specified)
Table 3.26. Memory Expansion and Microprocessor Modes (for setting with no wait)
Standard
Measuring condition
Parameter
Symbol
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
Chip select output hold time (refers to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)(Note 3)
Data output delay time (refers to WR)
Data output hold time (refers to WR)(Note 3)
40
4
0
(Note 2)
40
4
40
Figure 3.1
–4
40
0
40
0
40
4
(Note 1)
(Note 2)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
– 40
[ns]
Note 2: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 10
f(BCLK)
[ns]
Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC )
by a circuit of the right figure.
For example, when VOL = 0.2VCC , C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC )
= 6.7ns.
P0
P1
P2
30pF
P3
P4
P5
P6
P7
P8
P9
P10
Figure 3.1. Ports P0 to P10 Measurement Circuit
Rev.1.00
2004.03.23
page 258 of 320
R
DBi
C
M306H3MC-XXXFP/FCFP
VCC = 5V
Switching Characteristics
(VCC = 5V, VSS = 0V, at Topr = – 20 to 70oC unless otherwise specified)
Table 3.27. Memory Expansion and Microprocessor Modes
(for 1- to 3-wait setting and external area access)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Parameter
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
Chip select output hold time (refers to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)(Note 3)
Data output delay time (refers to WR)
Data output hold time (refers to WR)(Note 3)
Measuring condition
Standard
Min.
Max.
40
4
0
(Note 2)
40
4
40
Figure 3.1
–4
40
0
40
0
40
4
(Note 1)
(Note 2)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 40
f(BCLK)
[ns]
n is “1” for 1-wait setting, “2” for 2-wait
setting and “3” for 3-wait setting.
Note 2: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 10
f(BCLK)
[ns]
Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC )
by a circuit of the right figure.
For example, when VOL = 0.2VCC , C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC )
= 6.7ns.
Rev.1.00
2004.03.23
page 259 of 320
R
DBi
C
M306H3MC-XXXFP/FCFP
VCC = 5V
Switching Characteristics
(VCC = 5V, VSS = 0V, at Topr = – 20 to 70oC unless otherwise specified)
Table 3.28. Memory Expansion and Microprocessor Modes
(for 2- to 3-wait setting, external area access and multiplex bus selection)
Parameter
Symbol
Measuring condition
Standard
Min.
Max.
40
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
th(RD-AD)
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
(Note 1)
ns
ns
th(WR-AD)
Address output hold time (refers to WR)
(Note 1)
ns
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
Chip select output delay time
Chip select output hold time (refers to BCLK)
Chip select output hold time (refers to RD)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
Chip select output hold time (refers to WR)
RD signal output delay time
RD signal output hold time
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
th(BCLK-DB)
td(DB-WR)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
th(WR-DB)
td(BCLK-ALE)
Data output hold time (refers to WR)
ALE signal output delay time (refers to BCLK)
th(BCLK-ALE)
td(AD-ALE)
ALE signal output hold time (refers to BCLK)
ALE signal output delay time (refers to Address)
th(ALE-AD)
td(AD-RD)
ALE signal output hold time (refers to Adderss)
RD signal output delay from the end of Adress
td(AD-WR)
tdZ(RD-AD)
WR signal output delay from the end of Adress
Address output floating start time
4
40
4
(Note 1)
(Note 1)
40
0
Figure 3.1
40
0
40
4
0.5 X 109
f(BCLK)
–10
(Note 1)
40
–4
(Note 4)
(n–0.5) X 109
f(BCLK)
–40
[ns]
0
n is “2” for 2-wait setting, “3” for 3-wait setting.
Note 3: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
–25
[ns]
Note 4: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
Rev.1.00
2004.03.23
–15
[ns]
page 260 of 320
ns
ns
ns
ns
ns
ns
ns
0
Note 2: Calculated according to the BCLK frequency as follows:
ns
ns
ns
ns
ns
(Note 3)
[ns]
ns
ns
ns
ns
ns
(Note 2)
Note 1: Calculated according to the BCLK frequency as follows:
ns
8
ns
ns
M306H3MC-XXXFP/FCFP
VCC = 5V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
th(TIN–UP)
(When count on falling
edge is selected)
tsu(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 3.2. Timing Diagram (1)
Rev.1.00
2004.03.23
page 261 of 320
M306H3MC-XXXFP/FCFP
VCC = 5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
tw(INL)
INTi input
tw(INH)
Figure 3.3. Timing Diagram (2)
Rev.1.00
2004.03.23
page 262 of 320
th(C–D)
M306H3MC-XXXFP/FCFP
VCC = 5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait )
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Common to setting with wait and setting without wait)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
Hi–Z
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
Measuring conditions :
• V CC=5V
• Input timing voltage : Determined with V IL=1.0V, V IH=4.0V
• Output timing voltage : Determined with V OL=2.5V, V OH=2.5V
Figure 3.4. Timing Diagram (3)
Rev.1.00
2004.03.23
page 263 of 320
M306H3MC-XXXFP/FCFP
VCC = 5V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
40ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
40ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
40ns.max
th(BCLK-RD)
0ns.min
RD
tac1(RD-DB)
(0.5 X tcyc-45)ns.max
Hi-Z
DB
tSU(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
40ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
40ns.max
th(WR-AD)
-4ns.min
(0.5 X tcyc-10)ns.min
ALE
td(BCLK-WR)
40ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
1
tcyc=
f(BCLK)
Measuring conditions
• VCC=5V
• Input timing voltage
: VIL=0.8V, V IH=2.0V
• Output timing voltage : VOL=0.4V, V OH=2.4V
Figure 3.5. Timing Diagram (4)
Rev.1.00
2004.03.23
page 264 of 320
th(WR-DB)
(0.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min
M306H3MC-XXXFP/FCFP
VCC = 5V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
40ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
0ns.min
-4ns.min
40ns.max
ALE
td(BCLK-RD)
th(BCLK-RD)
40ns.max
0ns.min
RD
tac2(RD-DB)
(1.5 X tcyc-45)ns.max
Hi-Z
DB
th(RD-DB)
tSU(DB-RD)
0ns.min
40ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
40ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
th(WR-AD)
-4ns.min
40ns.max
(0.5 X tcyc-10)ns.min
ALE
td(BCLK-WR)
40ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
tcyc=
(0.5 X tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
• VCC=5V
• Input timing voltage
: VIL=0.8V, V IH=2.0V
• Output timing voltage : VOL=0.4V, V OH=2.4V
Figure 3.6. Timing Diagram (5)
Rev.1.00
2004.03.23
page 265 of 320
th(WR-DB)
(0.5 X tcyc-10)ns.min
M306H3MC-XXXFP/FCFP
VCC = 5V
(for 2-wait setting and external area access )
Read timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
4ns.min
40ns.max
CSi
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
th(RD-AD)
-4ns.min
0ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
40ns.max
0ns.min
RD
tac2(RD-DB)
(2.5 X tcyc-45)ns.max
DBi
Hi-Z
tSU(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing Memory Expansion Mode, Microprocessor Mode
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
4ns.min
40ns.max
CSi
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
40ns.max
th(WR-AD)
(0.5 X tcyc-10)ns.min
th(BCLK-ALE)
-4ns.min
ALE
td(BCLK-WR)
40ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
DB
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
td(DB-WR)
(1.5 X tcyc-40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
• VCC=5V
• Input timing voltage
: VIL=0.8V, V IH=2.0V
• Output timing voltage : VOL=0.4V, V OH=2.4V
Figure 3.7. Timing Diagram (6)
Rev.1.00
2004.03.23
page 266 of 320
th(WR-DB)
(0.5 X tcyc-10)ns.min
M306H3MC-XXXFP/FCFP
VCC = 5V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
40ns.max
4ns.min
CSi
th(BCLK-AD)
td(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
0ns.min
th(BCLK-ALE)
40ns.max
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
40ns.max
0ns.min
RD
tac2(RD-DB)
(3.5 X tcyc-45)ns.max
DBi
Hi-Z
tSU(DB-RD)
th(RD-DB)
40ns.min
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
40ns.max
th(BCLK-CS)
4ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
CSi
40ns.max
ADi
BHE
td(BCLK-ALE)
40ns.max
th(WR-AD)
(0.5 X tcyc-10)ns.min
th(BCLK-ALE)
-4ns.min
ALE
td(BCLK-WR)
40ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DB
td(DB-WR)
(2.5 X tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
• VCC=5V
• Input timing voltage
: VIL=0.8V, V IH=2.0V
• Output timing voltage : VOL=0.4V, V OH=2.4V
Figure 3.8. Timing Diagram (7)
Rev.1.00
2004.03.23
page 267 of 320
th(WR-DB)
(0.5 X tcyc-10)ns.min
M306H3MC-XXXFP/FCFP
VCC = 5V
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
td(BCLK-CS)
th(RD-CS)
(0.5 X tcyc-10)ns.min
tcyc
40ns.max
th(BCLK-CS)
4ns.min
CSi
td(AD-ALE)
(0.5 X tcyc-25)ns.min
th(ALE-AD)
(0.5 X tcyc-15)ns.min
ADi
/DBi
Address
8ns.max
Address
Data input
tdZ(RD-AD)
tac3(RD-DB)
(1.5 X tcyc-45)ns.max
tSU(DB-RD)
th(RD-DB)
0ns.min
40ns.min
td(AD-RD)
0ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
40ns.max
th(RD-AD)
(0.5 X tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
40ns.max
0ns.min
RD
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
th(WR-CS)
tcyc
40ns.max
4ns.min
(0.5 X tcyc-10)ns.min
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
40ns.max
ADi
/DBi
Address
Data output
td(DB-WR)
td(AD-ALE)
(1.5 X tcyc-40)ns.min
(0.5 X tcyc-25)ns.min
Address
th(WR-DB)
(0.5 X tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-WR)
-4ns.min
0ns.min
40ns.max
th(WR-AD)
(0.5 X tcyc-10)ns.min
ALE
td(BCLK-WR)
40ns.max
WR,WRL,
W RH
tcyc=
1
f(BCLK)
Measuring conditions
• VCC =5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 3.9. Timing Diagram (8)
Rev.1.00
2004.03.23
page 268 of 320
th(BCLK-WR)
0ns.min
M306H3MC-XXXFP/FCFP
VCC = 5V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
th(RD-CS)
(0.5 X tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
4ns.min
40ns.max
CSi
td(AD-ALE)
(0.5 X tcyc-25)ns.min
th(ALE-AD)
(0.5 X tcyc-15)ns.min
ADi
/DB
Address
td(BCLK-AD)
td(AD-RD)
40ns.max
ADi
BHE
Data input
tdZ(RD-AD)
8ns.max
th(RD-DB)
tac3(RD-DB)
(2.5 X tcyc-45)ns.max
0ns.min
tSU(DB-RD)
0ns.min
th(BCLK-AD)
40ns.min
4ns.min
(no multiplex)
td(BCLK-ALE)
40ns.max
th(RD-AD)
th(BCLK-ALE)
(0.5 X tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
40ns.max
RD
Write timing
tcyc
BCLK
th(WR-CS)
(0.5 X tcyc-10)ns.min
td(BCLK-CS)
40ns.max
th(BCLK-CS)
4ns.min
CSi
th(BCLK-DB)
td(BCLK-DB)
40ns.max
ADi
/DB
Address
4ns.min
Data output
td(AD-ALE)
td(DB-WR)
(0.5 X tcyc-25)ns.min
(2.5 X tcyc-40)ns.min
th(WR-DB)
(0.5 X tcyc-10)ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
td(AD-WR)
ALE
td(BCLK-WR)
40ns.max
WR, WRL
WRH
tcyc=
1
f(BCLK)
Measuring conditions
• VCC=5V
• Input timing voltage
: VIL=0.8V, V IH=2.0V
• Output timing voltage : VOL=0.4V, V OH=2.4V
Figure 3.10. Timing Diagram (9)
Rev.1.00
(0.5 X tcyc-10)ns.min
0ns.min
2004.03.23
page 269 of 320
th(BCLK-WR)
0ns.min
M306H3MC-XXXFP/FCFP
4 Flash Memory Version
4.1 Flash Memory Performance
The flash memory version is functionally the same as the mask ROM version except that it internally
contains flash memory.
The flash memory version has three modes—CPU rewrite, standard serial input/output, and parallel input/output modes—in which its internal flash memory can be operated on.
Table 4.1.1 shows the outline performance of flash memory version (see Table 1.4.1 for the items not
listed in Table 4.1.1.).
Table 4.1.1. Flash Memory Version Specifications
Item
Specification
Flash memory operating mode
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
User ROM area
See Figure 4.2.1
Boot ROM area
1 block (4 Kbytes) (Note 1)
Erase block
Method for program
In units of word
Method for erasure
Collective erase, block erase
Program, erase control method
Program and erase controlled by software command
Protect method
Protected for each block by lock bit
Number of commands
8 commands
Number of program and erasure
100 times
Data Retention
10 years
ROM code protection
Parallel I/O and standard serial I/O modes are supported.
Note 1: The boot ROM area contains a standard serial I/O mode rewrite control program which is stored
in it when shipped from the factory. This area can only be rewritten in parallel input/output mode.
Rev.1.00
2004.03.23
page 270 of 320
M306H3MC-XXXFP/FCFP
Table 4.1.2. Flash Memory Rewrite Modes Overview
Flash memory CPU rewrite mode (Note 1)
Standard serial I/O mode
Parallel I/O mode
rewrite mode
The user ROM area is rewrit- The user ROM area is rewrit- The boot ROM and user
Function
ten by executing software ten by using a dedicated se- ROM areas are rewritten by
commands from the CPU.
rial programmer.
using a dedicated parallel
EW0 mode:
Standard serial I/O mode 1: programmer.
Can be rewritten in any
Clock sync serial I/O
area other than the flash Standard serial I/O mode 2:
memory (Note 2)
UART
EW1 mode:
Can be rewritten in the
flash memory
Areas which User ROM area
User ROM area
User ROM area
can be rewritten
Boot ROM area
Operation
Single chip mode
Boot mode
Parallel I/O mode
mode
Boot mode (EW0 mode)
ROM
None
Serial programmer
Parallel programmer
programmer
Note 1: The PM13 bit remains set to “1” while the FMR0 register FMR01 bit = 1 (CPU rewrite mode enabled).
The PM13 bit is reverted to its original value by clearing the FMR01 bit to “0” (CPU rewrite mode
disabled). However, if the PM13 bit is changed during CPU rewrite mode, its changed value is not
reflected until after the FMR01 bit is cleared to “0”.
Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite
control program can only be executed in the internal RAM.
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4.2 Memory Map
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area.
Figure 4.2.1 shows the block diagram of flash momoery.
The user ROM area is divided into several blocks, each of which can individually be protected (locked)
against programming or erasure. The user ROM area can be rewritten in all of CPU rewrite, standard
serial input/output, and parallel input/output modes.
The boot ROM area is located at addresses that overlap the user ROM area, and can only be rewritten in
parallel input/output mode. After a hardware reset that is performed by applying a high-level signal to the
CNVSS and P50 pins and a low-level signal to the M1 pin, the program in the boot ROM area is executed.
After a hardware reset that is performed by applying a low-level signal to the CNVSS pin, the program in
the user ROM area is executed (but the boot ROM area cannot be read).
0F000016
Block 5 : 32K bytes
0F7FFF16
0E000016
0F800016
Block 4 : 8K bytes
Block 6 : 64K bytes
0F9FFF16
0FA000 16
Block 3 : 8K bytes
0EFFFF16
0FBFFF16
0F000016
0FC00016
Block 2 : 8K bytes
Block 0 to Block 5 (32+8+8+8
+4+4)K bytes
0FDFFF16
0FE00016
0FEFFF16
0FF00016
0FFFFF16
0FFFFF16
User ROM area
Note 1: The boot ROM area can only be rewritten in parallel input/output mode.
Note 2: To specify a block, use an even address in that block.
Note 3: Shown here is a block diagram during single-chip mode.
Figure 4.2.1. Flash Memory Block Diagram
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Block 1 : 4K bytes
Block 0 : 4K bytes
0FF00016
0FFFFF16
4K bytes
Boot ROM area (Note 1)
M306H3MC-XXXFP/FCFP
Boot Mode
After a hardware reset which is performed by applying a low-level signal to the M1 pin and a high-level
signal to the CNVSS and P50 pins, the microcomputer is placed in boot mode, thereby executing the program in the boot ROM area.
During boot mode, the boot ROM and user ROM areas are switched over by the FMR05 bit in the FMR0
register.
The boot ROM area contains a standard serial input/output mode based rewrite control program which was
stored in it when shipped from the factory.
The boot ROM area can be rewritten in parallel input/output mode. Prepare an EW0 mode based rewrite
control program and write it in the boot ROM area, and the flash memory can be rewritten as suitable for the
system.
Functions To Prevent Flash Memory from Rewriting
To prevent the flash memory from being read or rewritten easily, parallel input/output mode has a ROM
code protect and standard serial input/output mode has an ID code check function.
• ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel
input/output mode. Figure 4.2.2 shows the ROMCP register.
The ROMCP register is located in the user ROM area.The ROMCP1 bit consists of two bits. The ROM
code protect function is enabled by clearing one or both of two ROMCP1 bits to “0” when the ROMCR bits
are not ‘002,’ with the flash memory thereby protected against reading or rewriting. Conversely, when the
ROMCR bits are ‘002’ (ROM code protect removed), the flash memory can be read or rewritten. Once the
ROM code protect function is enabled, the ROMCR bits cannot be changed during parallel input/output
mode. Therefore, use standard serial input/output or other modes to rewrite the flash memory.
• ID Code Check Function
Use this function in standard serial input/output mode. Unless the flash memory is blank, the ID codes
sent from the programmer and the ID codes written in the flash memory are compared to see if they
match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID
code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316,
0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which the ID codes
are preset at these addresses and write it in the flash memory.
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ROM code protect control address
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
Symbol
ROMCP
Address
0FFFFF16
Bit name
Bit symbol
ROMCR
ROMCP1
Value when shipped
FF16 (Note 4)
Function
RW
Reserved bit
Set this bit to “1”
RW
Reserved bit
Set this bit to “1”
RW
Reserved bit
Set this bit to “1”
RW
Reserved bit
Set this bit to “1”
RW
ROM code protect reset
bit (Note 2, Note 4)
b5 b4
ROM code protect level
1 set bit
(Note 1, Note 3, Note 4)
00: Removes protect
01:
10: Enables ROOMCP1 bit
11:
}
RW
RW
b7 b6
00:
Protect enabled
01:
10:
11: Protect disabled
}
RW
RW
Note 1: If the ROMCR bits are set to other than ‘00 2’ and the ROMCP1 bits are set to other than ‘11 2’ (
ROM code protect enabled), the flash memory is disabled against reading and rewriting in
parallel input/output mode.
Note 2: If the ROMCR bits are set to ‘00 2,’ ROM code protect level 1 is removed. However, because the
ROMCR bits cannot be modified during parallel input/output mode, they need to be modified in
standard serial input/output or other modes.
Note 3: The ROMCP1 bits are effective when the ROMCR bits are ‘01 2,’ ‘10 2,’ or ‘11 2.’
Note 4: Once any of these bits is cleared to “0”, it cannot be set back to “1”. If a memory block that
contains the ROMCP register is erased, the ROMCP register is set to ‘FF 16.’
Figure 4.2.2. ROMCP Register
Address
0FFFDF16 to 0FFFDC16 ID1
0FFFE316 to 0FFFE016
ID2
0FFFE716 to 0FFFE416
0FFFEB16 to 0FFFE816
Undefined instruction vector
Overflow vector
BRK instruction vector
ID3
0FFFEF16 to 0FFFEC16 ID4
Address match vector
Single step vector
0FFFF316 to 0FFFF016
ID5
Watchdog timer vector
0FFFF716 to 0FFFF416
ID6
DBC vector
0FFFFB16 to 0FFFF816
ID7
NMI vector
0FFFFF16 to 0FFFFC16
ROMCP Reset vector
4 bytes
Figure 4.2.3. Address for ID Code Stored
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M306H3MC-XXXFP/FCFP
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board
without having to use a ROM programmer, etc.
In CPU rewrite mode, only the user ROM area shown in Figure 4.2.1 can be rewritten and the boot ROM
area cannot be rewritten. Make sure the Program and the Block Erase commands are executed only on
each block in the user ROM area.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase
Write 1 (EW1) mode. Table 4.2.1 lists the differences between Erase Write 0 (EW0) and Erase Write 1
(EW1) modes.
Table 4.2.1. EW0 Mode and EW1 Mode
Item
EW0 mode
Operation mode
• Single chip mode
• Boot mode
Areas in which a
• User ROM area
rewrite control
• Boot ROM area
program can be located
Areas in which a
Must be transferred to any area other
rewrite control
than the flash memory (RAM)
program can be executed before being executed (Note 2)
Areas which can be
User ROM area
rewritten
Software command
limitations
None
Modes after Program or
Erase
CPU status during Auto
Write and Auto Erase
Read Status Register mode
Operating
Flash memory status
detection
EW1 mode
Single chip mode
User ROM area
Can be executed directly in the user
ROM area
User ROM area
However, this does not include the area
in which a rewrite control program
exists
• Program, Block Erase command
Cannot be executed on any block in
which a rewrite control program exists
• Erase All Unlocked Block command
Cannot be executed when the lock bit
for any block in which a rewrite control
program exists is set to “1” (unlocked)
or the FMR0 register’s FMR02 bit is set
to “1” (lock bit disabled)
• Read Status Register command
Cannot be executed
Read Array mode
Hold state (I/O ports retain the state in
which they were before the command
was executed)(Note 1)
Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in a program
• Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in a
program
• Execute the Read Status Register
command to read the status
register's SR7,
SR5, and SR4 flags.
_______
Note 1: Make sure no interrupts (except NMI and watchdog timer interrupts) and DMA transfers will occur.
Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite
control program can only be executed in the internal RAM.
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• EW0 Mode
The microcomputer is placed in CPU rewrite mode by setting the FMR0 register’s FMR01 bit to “1” (CPU
rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register’s FMR11 bit
= 0, EW0 mode is selected. The FMR01 bit can be set to “1” by writing “0” and then “1” in succession.
Use software commands to control program and erase operations. Read the FMR0 register or status
register to check the status of program or erase operation at completion.
• EW1 Mode
EW1 mode is selected by setting FMR11 bit to “1” (by writing “0” and then “1” in succession) after setting
the FMR01 bit to “1” (by writing “0” and then “1” in succession).
Read the FMR0 register to check the status of program or erase operation at completion. The status
register cannot be read during EW1 mode.
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Figure 4.2.4 shows the FMR0 and FMR1 registers.
FMR00 Bit
This bit indicates the operating status of the flash memory. The bit is “0” when the Program, Erase, or
Lock Bit program is running; otherwise, the bit is “1”.
FMR01 Bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite
mode). During boot mode, make sure the FMR05 bit also is “1” (user ROM area access).
FMR02 Bit
The lock bit set for each block can be disabled by setting the FMR02 bit to “1” (lock bit disabled). (Refer to
the description of the data protect function.) The lock bits set are enabled by setting the FMR02 bit to “0”.
The FMR02 bit only disables the lock bit function and does not modify the lock bit data (lock bit status
flag). However, if the Erase command is executed while the FMR02 bit is set to “1”, the lock bit data
changes state from “0” (locked) to “1” (unlocked) after Erase is completed.
FMSTP Bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of
current consumed in the flash memory. The internal flash memory is disabled against access by setting
the FMSTP bit to “1”. Therefore, make sure the FMSTP bit is modified in other than the flash memory.
In the following cases, set the FMSTP bit to “1”:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00
bit not reset to “1” (ready))
• When entering low power mode or ring low power mode
Figure 4.2.7 shows a flow chart to be followed before and after entering low power mode.
Note that when going to stop or wait mode, the FMR0 register does not need to be set because the power
for the internal flash memory is automatically turned off and is turned back on again after returning from
stop or wait mode.
FMR05 Bit
This bit switches between the boot ROM and user ROM areas during boot mode. Set this bit to “0” when
accessing the boot ROM area (for read) or “1” (user ROM access) when accessing the user ROM area
(for read, write, or erase).
FMR06 Bit
This is a read-only bit indicating the status of auto program operation. The bit is set to “1” when a program
error occurs; otherwise, it is cleared to “0”. For details, tefer to the description of the full status check.
FMR07 Bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to “1” when an erase
error occurs; otherwise, it is cleared to “0”. For details, tefer to the description of the full status check.
Figure 4.2.5 and 4.2.6 show the setting and resetting of EW0 mode and EW1 mode, respectively.
FMR11 Bit
Setting this bit to “1” places the microcomputer in EW1 mode.
FMR16 Bit
This is a read-only bit indicating the execution result of the Read Lock Bit Status command.
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Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
FMR0
01B716
XX0000012
0
Bit name
Bit symbol
Function
RW
FMR00
RY/BY status flag
0: Busy (being written or erased)
1: Ready
FMR01
CPU rewrite mode select bit
(Note 1)
0: Disables CPU rewrite mode
1: Inables CPU rewrite mode
RW
Lock bit disable select bit
(Note 2)
0: Inables lock bit
1: Disables lock bit
RW
Flash memory stop bit
(Note 3, Note 5))
0: Enables flash memory operation
1: Stops flash memory operation
(placed in low power mode,
flash memory initialized)
FMR02
FMSTP
Reserved bit
(b4)
FMR05
FMR06
FMR07
RO
RW
Must always be set to “0”
RW
User ROM area select bit
(Note 3)
(Effective in only boot mode)
0: Boot ROM area is accessed
1: User ROM area is accessed
RW
Program status flag (Note 4)
0: Terminated normally
1: Terminated in error
RO
Erase status flag (Note 4)
0: Terminated normally
1: Terminated in error
RO
Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers
will occur before writing “1” after writing “0”.
Write to this bit when the NMI pin is in the high state. Also, while in EW0 mode, modify this bit in other
than the flash memory.
Note 2: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Note 3: modify this bit in other than the flash memory.
Note 4: This flag is cleared to “0” by executing the Clear Status command.
Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMR03 bit
can be set to “1” by writing “1” in a program, the flash memory is neither placed in low power mode
nor initialized.
Note 6: This status includes writing or reading with the Lock Bit Program or Read Lock Bit Status command.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol
Address
After reset
FMR1
01B516
0X00XX0X2
0
Bit symbol
(b0)
FMR11
Bit name
Reserved bit
EW1 mode select bit (Note)
Function
The value in this bit when read is
indeterminate.
0: EW0 mode
1: EW1 mode
RW
RO
RW
(b3-b2)
Reserved bit
The value in this bit when read is
indeterminate.
(b5-b4)
Reserved bit
Must always be set to “0”
RW
FMR06
Lock bit status flag
0: Lock
1: Unlock
RO
Reserved bit
Must always be set to “0”
RW
(b7)
RO
Note : To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”. Write this bit in the state
the NMI pin = “H”. The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”.
Figure 4.2.4. FIDR Register and FMR0 and FMR1 Registers
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EW0 mode operation procedure
Rewrite control program
Single-chip mode, or boot mode
Set CM0, CM1, and PM1 registers (Note 1)
Transfer a rewrite control program to any area other
than the flash memory (Note 5)
Jump to the rewrite control program which has been
transferred to any area other than the flash memory
(The subsequent processing is executed by the
rewrite control program in any area other than the
flash memory)
For only boot mode
set the FMR05 bit to “1” (user ROM area access)
Set the FMR01 bit by writing “0” and then “1”
(CPU rewrite mode enabled) (Note 2)
Execute software commands
Execute the Read Array command (Note 3)
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
For only boot mode
Write “0” to the FMR05 bit (Boot ROM area
accessed) (Note 4)
Jump to a specified address in the flash memory
Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6
bits. Also, set the PM1 register’s PM17 bit to “1” (with wait state).
Note 2: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or no DMA
transfers will occur before writing “1” after writing “0”.
Write to the FMR01 bit from a program in other than the flash memory. Also write only when the NMI pin is
“H” level.
Note 3: Disables the CPU rewrite mode after executing the Read Array command.
Note 4: User ROM area is accessed when the FMR05 bit is set to “1”.
Note 5: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control
program can only be executed in the internal RAM or in an external area that is enabled for use when the
PM13 bit = 1.
Figure 4.2.5. Setting and Tesetting of EW0 Mode
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EW1 mode operation procedure
Program in ROM
Single-chip mode (Note 1)
Set CM0, CM1, and PM1 registers (Note 2)
Set the FMR01 bit by writing “0” and then “1” (CPU
rewrite mode enabled)
Set the FMR11 bit by writing “0” and then “1” (EW1
mode) (Note 3)
Execute software commands
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Note 1: In EW1 mode, do not set the microcomputer in boot mode.
Note 2: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1
register’s CM17 to 6 bits. Also, set the PM1 register’s PM17 bit to “1” (with wait
state).
Note 3: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Write to the FMR01 bit from a program in other than the flash memory. Also write
only when the NMI pin is “H” level.
Figure 4.2.6. Setting and Resetting of EW1 Mode
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Low power dissipation
mode program
Transfer a low power dissipation mode program
to any area other the flash memory
Jump to the low power dissipation mode program
which has been transferred to any area other the
flash memory.
(The subsequent processing is executed by a
program in any area other than the flash memory.)
Set the FMR01 bit by writing “0” and then “1”
(CPU rewrite mode enabled)
Set FMSTP bit to “1”
(flash memory stopped. Low power state)(Note 1)
Switch the clock source for CPU clock.
Turn main clock off. (Note 2)
Process of low power dissipation mode
Turn main clock on wait until oscillation stabilizes
switch the clock source for CPU clock (Note 2)
Set the FMSTP bit to “0” (flash memory operation)
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes (tps)
(Note 3)
Jump to a specified address in the flash memory
Note 1: Set the FMR03 bit to 1 after setting the FMR01 bit to “1”.
Note 2: Before the clock source for CPU clock can be changed to
main clock or sub clock, the clock to which to be changed
must be stable.
Note 3: Insert a tps wait time in a program. The flash memory
cannot be accessed during this wait time.
Figure 4.2.7. Processing Before and After Low Power Sissipation Mode
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Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation Speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the
CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in
the PM1 register to “1” (with wait state).
(2) Instructions to Prevent from Using
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is referenced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table.
_______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
(4) How to Access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary
to ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only
_______
when NMI pin is “H” level.
(5) Writing in the User ROM Space
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
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(6) DMA Transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
(7) Writing Command and Data
Write the command code and data at even addresses.
(8) Wait Mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing
the WAIT instruction.
(9) Stop Mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program
BSET
0, CM1
; Stop mode
JMP.B
L1
L1:
Program after returning from stop mode
(10) Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
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4.3 Software Commands
Software commands are described below. The command code and data must be read and written in 16bit units, to and from even addresses in the user ROM area. When writing command code, the 8 highorder bits (D1t–D8) are ignored.
Table 4.3.1. Software Commands
First bus cycle
Command
Second bus cycle
Mode
Address
Data
(D0 to D7)
Mode
Address
Data
(D0 to D7)
Read array
Write
X
xxFF16
Read status register
Write
X
xx7016
Read
X
SRD
Clear status register
Write
X
xx5016
Program
Write
WA
xx4016
Write
WA
WD
Write
X
xx2016
Write
BA
xxD016
Write
X
xxA716
Write
X
xxD016
Lock bit program
Write
BA
xx7716
Write
BA
xxD016
Read lock bit status
Write
X
xx7116
Write
BA
xxD016
Block erase
Erase all unlocked
block(Note)
Note: It is only blocks 0 to 12 that can be erased by the Erase All Unlocked Block command.
Block A cannot be erased. Use the Block Erase command to erase block A.
SRD: Status register data (D7 to D0)
WA: Write address (Make sure the address value specified in the the first bus cycle is the same even address
as the write address specified in the second bus cycle.)
WD: Write data (16 bits)
BA: Uppermost block address (even address, however)
X: Any even address in the user ROM area
x: High-order 8 bits of command code (ignored)
Read Array Command (FF16)
This command reads the flash memory.
Writing ‘xxFF16’ in the first bus cycle places the microcomputer in read array mode. Enter the read
address in the next or subsequent bus cycles, and the content of the specified address can be read in
16-bit units.
Because the microcomputer remains in read array mode until another command is written, the contents of multiple addresses can be read in succession.
Read Status Register Command (7016)
This command reads the status register.
Write ‘xx7016’ in the first bus cycle, and the status register can be read in the second bus cycle. (Refer
to “Status Register.”) When reading the status register too, specify an even address in the user ROM
area.
Do not execute this command in EW1 mode.
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Clear Status Register Command
This command clears the status register to “0”.
Write ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to
SR5 in the status register will be cleared to “0”.
Program Command
This command writes data to the flash memory in 1 word (2 byte) units.
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in
the first bus cycle is the same even address as the write address specified in the second bus cycle.
Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is
“0” during auto programming and set to “1” when auto programming is completed.
Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto
programming can be known. (Refer to “Full Status Check.”)
Each block can be protected against programming by a lock bit. (Refer to “Data Protect Function.”)
Be careful not to write over the already programmed addresses.
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto programming starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to
“0” at the same time auto programming starts, and set back to “1” when auto programming finishes. In
this case, the microcomputer remains in read status register mode until a read command is written
next. The result of auto programming can be known by reading the status register after auto programming has finished.
Start
Write the command code ‘xx4016’
to the write address
Write data to the write address
FMR00=1?
NO
YES
Full status check
Program
completed
Note: Write the command code and data at even number.
Figure 4.3.1. Program Command
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M306H3MC-XXXFP/FCFP
Block Erase
Write ‘xx2016’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished.
The FMR00 bit is “0” during auto erasing and set to “1” when auto erasiing is completed.
Check the FMR0 register’s FMR07 bit after auto erasing has finished, and the result of auto erasing
can be known. (Refer to “Full Status Check.”)
Figure 4.3.2 shows an example of a block erase flowchart.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”)
Writing over already programmed addresses is inhibited.
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at
the same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the
microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status
command is written next.
Start
Write the command code ‘xx2016’
Write ‘xxD016’ to the uppermost
block address
FMR00=1?
NO
YES
Full status check
Block erase completed
Note: Write the command code and data at even number.
Figure 4.3.2. Block Erase Command
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M306H3MC-XXXFP/FCFP
Erase All Unlocked Block
Write ‘xxA716’ in the first bus cycle and write ‘xxD016’ in the second bus cycle, and all blocks except
block A will be erased successively, one block at a time.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished. The result of the auto erase
operation can be known by inspecting the FMR0 register’s FMR07 bit.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”)
In EW1 mode, do not execute this command when the lock bit for any block = 1 (unlocked) in which the
rewrite control program is stored, or when the FMR0 register’s FMR02 bit = 1 (lock bit disabled).
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at
the same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the
microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status
command is written next.
Note that only blocks 0 to 12 can be erased by the Erase All Unlocked Block command. Block A
cannot be erased. Use the Block Erase command to erase block A.
Lock Bit Program Command
This command sets the lock bit for a specified block to “0” (locked).
Write ‘xx7716’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”.
Make sure the address value specified in the first bus cycle is the same uppermost block address that
is specified in the second bus cycle.
Figure 4.3.3 shows an example of a lock bit program flowchart. The lock bit status (lock bit data) can
be read using the Read Lock Bit Status command.
Check the FMR0 register’s FMR00 bit to see if writing has finished.
For details about the lock bit function, and on how to set the lock bit to “1”, refer to “Data Protect
Function.”
Start
Write command code ‘xx7716’ to
the uppermost block address
Write ‘xxD016’ to the uppermost
block address
FMR00=1?
NO
YES
Full status check
Lock bit program completed
Note: Write the command code and data at even number.
Figure 4.3.3. Lock Bit Program Command
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M306H3MC-XXXFP/FCFP
Read Lock Bit Status Command (7116)
This command reads the lock bit status of a specified block.
Write ‘xx7116’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit status of the specified block is stored in the
FMR1 register’s FMR16 bit. Read the FMR16 bit after the FMR0 register’s FMR00 bit is set to “1”
(ready).
Figure 4.3.4 shows an example of a read lock bit status flowchart.
Start
Write the command code ‘xx7116’
Write ‘xxD016’ to the uppermost
block address
FMR00=1?
NO
YES
FMR16=0?
NO
YES
Locked
Not locked
Note: Write the command code and data at even number.
Figure 4.3.4. Read Lock Bit Status Command
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M306H3MC-XXXFP/FCFP
Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is effective when the FMR02 bit =
0 (lock bit enabled). The lock bit allows each block to be individually protected (locked) against programming and erasure. This helps to prevent data from inadvertently written to or erased from the flash
memory. The following shows the relationship between the lock bit and the block status.
• When the lock bit = 0, the block is locked (protected against programming and erasure).
• When the lock bit = 1, the block is not locked (can be programmed or erased).
The lock bit is cleared to “0” (locked) by executing the Lock Bit Program command, and is set to “1”
(unlocked) by erasing the block. The lock bit cannot be set to “1” by a command.
The lock bit status can be read using the Read Lock Bit Status command
The lock bit function is disabled by setting the FMR02 bit to “1”, with all blocks placed in an unlocked state.
(The lock bit data itself does not change state.) Setting the FMR02 bit to “0” enables the lock bit function
(lock bit data retained).
If the Block Erase or Erase All Unlocked Block command is executed while the FMR02 bit = 1, the target
block or all blocks are erased irrespective of how the lock bit is set. The lock bit for each block is set to “1”
after completion of erasure.
For details about the commands, refer to “Software Commands.”
Status Register
The status register indicates the operating status of the flash memory and whether an erase or programming operation terminated normally or in error. The status of the status register can be known by reading
the FMR0 register’s FMR00, FMR06, and FMR07 bits.
Table 4.3.2 shows the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given even address in the user ROM area is read after writing the Read Status Register
command
(2) When a given even address in the user ROM area is read after executing the Program, Block Erase,
Erase All Unlocked Block, or Lock Bit Program command but before executing the Read Array
command.
Sequencer Status (SR7 and FMR00 Bits )
The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto
programming, auto erase, and lock bit write, and is set to “1” (ready) at the same time the operation
finishes.
Erase Status (SR5 and FMR07 Bits)
Refer to “Full Status Check.”
Program Status (SR4 and FMR06 Bits)
Refer to “Full Status Check.”
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M306H3MC-XXXFP/FCFP
Table 4.3.2. Status Register
Status
register
bit
SR7 (D7)
FMR0
register
bit
FMR00
Sequencer status
Reserved
SR6 (D6)
"0"
"1"
Value
after
reset
Busy
Ready
1
-
-
Contents
Status name
SR5 (D5)
FMR07
Erase status
Terminated normally
Terminated in error
0
SR4 (D4)
FMR06
Program status
Terminated normally
Terminated in error
0
SR3 (D3)
Reserved
-
-
SR2 (D2)
Reserved
-
-
SR1 (D1)
Reserved
-
-
SR0 (D0)
Reserved
-
-
• D0 to D7: Indicates the data bus which is read out when the Read Status Register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are cleared to “0” by executing the Clear Status Register
command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program, Block Erase, Erase All Unlocked Block,
and Lock Bit Program commands are not accepted.
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M306H3MC-XXXFP/FCFP
Full Status Check
When an error occurs, the FMR0 register’s FMR06 to FMR07 bits are set to “1”, indicating occurrence
of each specific error. Therefore, execution results can be verified by checking these status bits (full
status check). Table 4.3.3 lists errors and FMR0 register status. Figure 4.3.5 shows a full status check
flowchart and the action to be taken when each error occurs.
Table 4.3.3. Errors and FMR0 Register Status
FRM00 register
(status register)
status
FMR07
FMR06
(SR5)
(SR4)
1
1
1
0
0
1
Error
Error occurance condition
Command
• When any command is not written correctly
sequence error • When invalid data was written other than those that can be written in the second bus cycle of the Lock Bit Program, Block Erase,
or Erase All Unlocked Block command (i.e., other than ‘xxD016’ or
‘xxFF16’) (Note 1)
Erase error
• When the Block Erase command was executed on locked blocks
(Note 2)
• When the Block Erase or Erase All Unlocked Block command
was executed on unlocked blocks but the blocks were not automatically erased correctly
Program error • When the Block Erase command was executed on locked blocks
(Note 2)
• When the Program command was executed on unlocked blocks
but the blocks were not automatically programmed correctly.
• When the Lock Bit Program command was executed but not programmed correctly
Note 1: If "xxFF16" is written by the 2nd bus cycle of these commands, it will become lead array mode and
the command code written by the 1st bus cycle will become invalid simultaneously.
Note 2: When FMR02 bit is "1" (lock bit is invalid), an error is not generated on these conditions.
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M306H3MC-XXXFP/FCFP
Full status check
FMR06 =1
and
FMR07=1?
YES
Command
sequence error
(1) Execute the Clear Status Register command to
clear these status flags to “0”.
(2) Reexecute the command after checking that it is
entered correctly.
NO
FMR07=
0?
NO
Erase error
YES
FMR06=
0?
NO
YES
Full status check completed
Program error
(1) Execute the Clear Status Register command to
clear the erase status flag to “0”.
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
the FMR0 register’s FMR02 bit to “1”.
(3) Reexecute the Block Erase or Erase All Unlocked
Block command.
Note 1: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
[During programming]
(1) Execute the Clear Status Register command to
clear the erase status flag to “0”.
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
the FMR0 register’s FMR02 bit to “1”.
(3) Reexecute the Program command.
Note 2: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
[During lock bit programming]
(1) Execute the Clear Status Register command to
clear the erase status flag to “0”.
(2) Set the FMR0 register’s FMR02 bit to “1”.
(3) Execute the Block Erase command to erase the
block in error.
(4) Reexecute the Lock Bit command.
Note 3: If the error still occurs, the block in error
cannot be used.
Note 4: If FMR06 or FMR07 = 1, any of the Program, Block Erase, Erase All Unlocked
Block, Lock Bit Program, or Read Lock Bit Status command is not accepted.
Execute the Clear Status Register command before executing those commands.
Figure 4.3.5. Full Status Check and Handling Procedure for Each Error
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M306H3MC-XXXFP/FCFP
Standard Serial I/O Mode
In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is
mounted on-board by using a serial programmer suitable for M306H3FCFP. For more information about
serial programmers, contact the manufacturer of your serial programmer. For details on how to use, refer
to the user’s manual included with your serial programmer.
Table 4.3.4 lists pin functions (flash memory standard serial input/output mode). Figures 4.3.7 show pin
connections for serial input/output mode.
ID Code Check Function
This function determines whether the ID codes sent from the serial programmer and those written in the
flash memory match. (Refer to the desctiption of the functions to inhibit rewriting flash memory version.)
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M306H3MC-XXXFP/FCFP
Table 4.3.4. Pin Functions (Flash Memory Standard Serial I/O Mode)
Pin
Name
Description
I/O
Apply the voltage guaranteed for Program and Erase to Vcc pin and 0
V to Vss pin.
VCC,VSS
Power input
CNVSS
CNVSS
I
Connect to Vcc pin.
RESET
Reset input
I
Reset input pin. While RESET pin is "L" level, input a 20 cycle or
longer clock to XIN pin.
M1
Mode select
I
Connect to Vss pin.
START
Oscillation selection input
I
Connect to Vcc pin.
XIN
Clock input
I
XOUT
Clock output
O
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to X IN pin
and open XOUT pin.
BYTE
BYTE
I
Connect this pin to Vcc or Vss.
AV CC, AV SS
Analog power supply input
VREF
Reference voltage input
I
Enter the reference voltage for AD from this pin.
P00 to P07
Input port P0
I
Input "H" or "L" level signal or open.
P10 to P17
Input port P1
I
Input "H" or "L" level signal or open.
P20 to P27
Input port P2
I
Input "H" or "L" level signal or open.
P30 to P37
Input port P3
I
Input "H" or "L" level signal or open.
P40 to P47
Input port P4
I
Input "H" or "L" level signal or open.
P51 to P54,
P56, P57
Input port P5
I
Input "H" or "L" level signal or open.
P50
CE input
I
Input "H" level signal.
P55
EPM input
I
Input "L" level signal.
P60 to P63
Input port P6
I
Input "H" or "L" level signal or open.
Connect AVss to Vss and AVcc to Vcc, respectively.
P64/RTS1
BUSY output
O
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation
check signal output pin.
P65/CLK1
SCLK input
I
Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input "L".
P66/RXD1
RxD input
I
Serial data input pin
P67/TXD1
TxD output
O
Serial data output pin (Note 1)
P70 to P77
Input port P7
I
Input "H" or "L" level signal or open.
P80 to P84, P86,
P87
Input port P8
I
Input "H" or "L" level signal or open.
P85/NM1
NMI input
I
Connect this pin to Vcc.
P90 to P97
Input port P9
I
Input "H" or "L" level signal or open.
P100 to P107
Input port P10
I
Input "H" or "L" level signal or open.
P11
Output port P11
O
Open
VDD2, Vss2
Power input
Connect VDD2 pin to VCC and connect VSS2 pin to VSS.
VDD3, Vss3
Power input
Connect VDD3 pin to VCC and connect VSS3 pin to VSS.
LP2 to LP4
Filter output
O
Open
FSCIN
Fsc input pin for
synchronized signal generating
I
Open
CVIN1, SYNCIN Compound video input
I
Input "H" or "L" level signal or open.
SVREF
I
A slice potential input pin in slicing a synchronized signal.
Synchronous slice level input
___________
Note 1: When using standard serial input/output mode 1, the TxD pin must be held high while the RESET
pin is pulled low. Therefore, connect this pin to VCC via a resistor. Because this pin is directed for
data output after reset, adjust the pull-up resistance value in the system so that data transfers will
not be affected.
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P40
P41
P42
P35
P37
P34
P36
VCC
VCC
P31
P32
P33
VSS
P30
P24
P25
P26
P27
P22
P23
P17/INT5
P21
P20
P16/INT4
P13
P14
P15/INT3
P11
P12
P10
VSS
M306H3MC-XXXFP/FCFP
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
P07
P06
P05
88
58
89
57
P43
P44
90
56
P45
P04
P03
91
55
P46
92
54
P02
P01
93
53
P47
P50
94
52
P00
95
51
P51
P52
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
96
50
P53
97
49
P54
98
48
P55
P104/AN4/KI0
99
47
P103/AN3
P102/AN2
P101/AN1
AV SS
100
46
P56
P57/CLKOUT
P60/CTS0/RTS0
P100/AN0
VREF
AV CC
43
P61/CLK0
P62/RXD0
104
42
P63/TXD0
105
41
106
40
P64/CTS1/RTS1/CLKS1
P65/CLK1
107
39
P66/RXD1
108
38
109
37
SVREF
TEST2
110
36
P67/TXD1
P11/SLICEON
M1
111
35
VDD3
CVIN1
VSS3
112
34
113
33
114
32
LP3
115
31
116
30
LP2
VSS2
RESET
CE
VSS
The mode setting method
Signal line name
Value
CNVss
Vcc
Vss
M1
Vss→Vcc
Vcc
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P72/CLK2/TA1 OUT
P71/RXD2/SCL/TA0 IN/TB5IN
P70/TXD2/SDA/TA0 OUT
P73/CTS2/RTS2/TA1 IN
P75/TA2 IN
P74/TA2 OUT
P81/TA4 IN
P77/TA3 IN
P76/TA3 OUT
P80/TA4 OUT
P82/INT0
P85/NMI
P84/INT2
Note 1. Connect an oscillation circuit.
Figure 4.3.6. Pin Connections for Serial I/O Mode
Rev.1.00
P83/INT1
VCC
(Note 1)
XIN
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Vcc
8
XOUT
Vss
7
RESET
6
VSS
5
RESET
4
CNVss
3
44
P87/XCIN
P86/XCOUT
2
VCC
1
P90/TB0IN/CLK3
BYTE
FSCIN
P96/ANEX1/SOUT4
P92/TB2IN/SOUT3
P91/TB1IN/SIN3
SYNCIN
P93/DA0/TB3IN/JSTIN
P97/ADTRG/SIN4
START
103
P95/ANEX0/CLK4
VCC
45
M306H3FCFP
102
P94/DA1/TB4IN/RMTIN
VSS
101
TEST1
VDD2
LP4
CE
BUSY
SCLK
RXD
TXD
VSS
VCC
VSS
M306H3MC-XXXFP/FCFP
Example of Circuit Application in the Standard Serial I/O Mode
Figure 4.3.7 and 4.3.8 show example of circuit application in standard serial I/O mode 1 and mode 2,
respectively. Refer to the user's manual for serial writer to handle pins controlled by a serial writer.
Microcomputer
P65/CLK1
SCLK input
P50(CE)
P67/TxD1
TxD input
M1
P64/RTS1
BUSY output
P66/RxD1
RxD output
Reset input
CNVss
RESET
User reset
singnal
P85/NMI
START
BYTE
(1) Control pins and external circuitry will vary according to programmer.
For more information, see the programmer manual.
(2) In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.
(3) If in standard serial input/output mode 1 there is a possibility that the user reset
signal will go low during serial input/output mode, break the connection between
the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 4.3.7. Circuit Application in Standard Serial I/O Mode 1
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M306H3MC-XXXFP/FCFP
Microcomputer
P65/CLK1
P50(CE)
TxD output
P67/TxD1
M1
Monitor output
P64/RST1
RxD input
P66/RxD1
CNVss
P85/NMI
START
BYTE
(1) In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.
Figure 4.3.8. Circuit Application in Standard Serial I/o Mode 2
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M306H3MC-XXXFP/FCFP
Parallel I/O Mode
In parallel input/output mode, the user ROM and boot ROM areas can be rewritten by using a parallel
programmer suitable for the M16C/62P group. For more information about parallel programmers, contact
the manufacturer of your parallel programmer. For details on how to use, refer to the user’s manual included with your parallel programmer.
User ROM and Boot ROM Areas
In the boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area
contains a standard serial input/output mode based rewrite control program which was written in it when
shipped from the factory. Therefore, when using a serial programmer, be careful not to rewrite the boot
ROM area.
When in parallel output mode, the boot ROM area is located at addresses 0FF00016 to 0FFFFF16. When
rewriting the boot ROM area, make sure that only this address range is rewritten. (Do not access other
than the addresses 0FF00016 to 0FFFFF16.)
ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to the
description of the functions to inhibit rewriting flash memory version.)
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M306H3MC-XXXFP/FCFP
5. PACKAGE OUTLINE
MMP
116P6A-A
EIAJ Package Code
LQFP116-P-2020-0.65
Plastic 116pin 20✕20mm body LQFP
Weight(g)
1.78
Lead Material
Cu Alloy
MD
HD
D
ME
b2
e
JEDEC Code
–
l2
116
88
Recommended Mount Pad
1
87
Symbol
E
HE
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
59
29
30
58
A
L1
F
b
x
M
L
Lp
Detail F
Rev.1.00
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c
y
A1
A2
A3
e
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
1.7
–
–
0.125
0.2
0.05
1.4
–
–
0.17
0.22
0.27
0.105
0.125
0.175
19.9
20.0
20.1
19.9
20.0
20.1
0.65
–
–
21.8
22.0
22.2
21.8
22.0
22.2
0.35
0.5
0.65
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.13
0.1
–
–
0°
8°
–
0.225
–
–
0.95
–
–
–
20.4
–
–
20.4
–
M306H3MC-XXXFP/FCFP
6. USEGE NOTES
Precautions for External Bus
1. In the mask ROM version, connect the CNVSS pin to the VCC when use microprocessor mode or
memory expansion mode.
In the flash memory version, connect the CNVSS pin and the M1 pin to the VCC.
2. In the mask ROM version, contents of internal ROM cannot be read out when reseting the CNVSS pin
with "H" input. In the flash memory version, contents of internal ROM cannot be read out when reseting
the CNVSS pin and the M1 pin with "H" input.
Precautions for Power Control
____________
1. When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is
stabilized.
2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of
CM1 register to “1”. When shifting to wait mode or stop mode, an instruction queue reads ahead to the
next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to “1” (all
clocks stopped). The next instruction may be executed before entering wait mode or stop mode, depending on a combination of instruction and an execution timing.
3. Wait until the td(M-L) elapses or main clock oscillation stabilization time, whichever is longer, before
switching the clock source for CPU clock to the main clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the
sub clock.
4. Suggestions to reduce power consumption
(a) Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A
current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When
entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
(b) A-D converter
When A-D conversion is not performed, set the VCUT bit of ADiCON1 register to “0” (no VREF connection). When A-D conversion is performed, start the A-D conversion at least 1 µs or longer after setting
the VCUT bit to “1” (VREF connection).
(c) Stopping peripheral functions
Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode.
However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,
this measure is not conducive to reducing the power consumption of the chip. If low speed mode or
low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not peripheral
function clock stopped when in wait mode), before changing wait mode.
(d) Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
(e) External clock
When using an external clock input for the CPU clock, set the CM0 register CM05 bit to “1” (stop).
Setting the CM05 bit to “1” disables the XOUT pin from functioning, which helps to reduce the amount
of current drawn in the chip. (When using an external clock input, note that the clock remains fed into
the chip regardless of how the CM05 bit is set.)
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Precautions for Protect
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to
“0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction
after setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to “1” and the next instruction.
Precautions for Interrupts
Reading address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the
CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is
cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or
an unexpected interrupt request is generated.
Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to
‘000016’ after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP,
ISP), the program may go out of control.
_______
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the
_______
first and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
_______
The NMI Interrupt
_______
_______
1. The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a
resistor (pull-up).
_______
2. The input level of the NMI pin can be read by accessing the P8 register’s P8_5 bit. Note that the
_______
P8_5 bit can only be read when determining the pin level in NMI interrupt routine.
_______
3. Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on
_______
the NMI pin is low the CM1 register’s CM10 bit is fixed to “0”.
_______
_______
4. Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the
chip does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
_______
5. The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock
cycles + 300 ns or more.
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Changing the Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate
factor for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt
not requested).
“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change
of any peripheral function involves changing the generate factor, polarity or timing of an interrupt, be
sure to clear the IR bit for that interrupt to “0” (interrupt not requested) after making such changes.
Refer to the description of each peripheral function for details about the interrupts from peripheral
functions.
Figure 6.1 shows the procedure for changing the interrupt generate factor.
Changing the interrupt source
Disable interrupts (Note 2, Note 3)
Change the interrupt generate factor (including a mode change of peripheral function)
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (Note 3)
Enable interrupts (Note 2, Note 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
Note 1: The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
Note 2: Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable interrupts
can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding
ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed.
Note 3: Refer to Section “Rewrite the Interrupt Control Register” for details about the
instructions to use and the notes to be taken for instruction execution.
Figure 6.1. Procedure for Changing the Interrupt Generate Factor
______
INT Interrupt
1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the
signal input to pins INT0 through INT5 regardless of the CPU operation clock.
2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.
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Rewrite the Interrupt Control Register
(1) The interrupt control register for any interrupt should be modified in places where no requests for
that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with
the instruction to be used.
Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not requested). Therefore, be sure to use the MOV instruction to clear the IR bit.
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below
as you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the
sample program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before
the interrupt control register is rewrited, owing to the effects of the internal bus and the instruction
queue buffer.
Example 1: Using the NOP instruction to keep the program waiting until the interrupt control
register is modified
INT_SWITCH1:
FCLR
I
AND.B
#00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Set the TA0IC register to “0016”.
;
; Enable interrupts.
The number of NOP instruction is as follows.
PM20=1(1 wait) : 2, PM20=0(2 wait) : 3, when using HOLD function : 4.
Example 2: Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR
AND.B
MOV.W
FSET
I
#00h, 0055h
MEM, R0
I
; Disable interrupts.
; Set the TA0IC register to “0016”.
; Dummy read.
; Enable interrupts.
Example 3: Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC
FCLR
AND.B
POPC
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I
#00h, 0055h
FLG
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; Disable interrupts.
; Set the TA0IC register to “0016”.
; Enable interrupts.
M306H3MC-XXXFP/FCFP
Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
Precautions for DMAC
Write to DMAE Bit in DMiCON Register
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously(*1).
Step 2: Make sure that the DMAi is in an initial state(*2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
Notes:
*1. The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set
to “0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should
be written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit
immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to
the DMAS bit in order to maintain a DMA request which is generated during execution.
*2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to
a value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial
state. (If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register
is “1”.) If the read value is a value in the middle of transfer, the DMAi is not in an initial state.
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Precautions for Timers
Timer A
(a) Timer A (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the counter is read at the same time it is reloaded, the value “FFFF16” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.
(b) Timer A (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
2. While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, “FFFF16” can be read in underflow, while reloading, and “000016” in overflow.
When setting TAi register to a value during a counter stop, the setting value can be read before a
counter starts counting. Also, if the counter is read before it starts counting after a value is set in the
TAi register while not counting, the set value is read.
(c) Timer A (One-shot Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.
2. When setting TAiS bit to “0” (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit of TAiIC register is set to “1” (interrupt request).
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3. Output in one-shot timer mode synchronizes with a count source internally generated. When an
external trigger has been selected, one-cycle delay of a count source as maximum occurs between
a trigger input to TAiIN pin and output in one-shot timer mode.
4. The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operation mode from timer mode to one-shot timer mode.
• Change an operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have
been made.
5. When a trigger occurs, while counting, a counter reloads the reload register to continue counting
after generating a re-trigger and counting down once. To generate a trigger while counting, generate a second trigger between occurring the previous trigger and operating longer than one cycle of
a timer count source.
(d) Timer A (Pulse Width Modulation Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after
reset or not.
2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
listed changes have been made.
3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.
Timer B
(a) Timer B (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to
“1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
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2. A value of a counter, while counting, can be read in TBi register at any time. “FFFF16” is read while
reloading. Setting value is read between setting values in TBi register at count stop and starting a
counter.
(b) Timer B (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to
“1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
2. The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this
register is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the
TBi register is read after setting a value in it while not counting but before the counter starts counting, the read value is the one that has been set in the register.
(c) Timer B (Pulse Period/pulse Width Measurement Mode)
1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5)
register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register
while the TBiS bit = “1” (count starts), be sure to write the same value as previously written to the
TM0D0, TM0D1, MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit.
2. The IR bit of TBiIC register (i=0 to 5) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the MR3 bit of TBiMR register within the interrupt routine.
3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
timer B has overflowed.
4. To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).
5. Use the IR bit of TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
6. When a count is started and the first effective edge is input, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
7. A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and timer
Bi interrupt request may be generated between a count start and an effective edge input.
8. For pulse width measurement, pulse widths are successively measured. Use program to check
whether the measurement result is an “H” level width or an “L” level width.
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Precautions for Serial I/O (Clock-synchronous Serial I/O)
Transmission/reception
_______
________
With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes
to “L” when the data-receivable status becomes ready,
which informs the transmission side that the
________
reception has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if
________
________
the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and
_______
reception data with consistent timing. With the internal clock, the RTS function has no effect.
Transmission
When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit
= “0” (transmit data output at the falling edge and the receive data taken in at the rising edge of the
transfer clock), the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit
data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the
external clock is in the low state.
• The TE bit of UiC1 register= “1” (transmission enabled)
• The
TI bit of UiC1 register = “0” (data present
in UiTB register)
_______
_______
• If CTS function is selected, input on the CTSi pin = “L”
Reception
1. In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix
settings for transmission even when using the device only for reception. Dummy data is output to
the outside from the TxDi pin when receiving data.
2. When an internal clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 (transmission
enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated.
When an external clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 and write dummy
data to the UiTB register, and the shift clock will be generated when the external clock is fed to the
CLKi input pin.
3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi
receive register while the UiC1 register (i = 0 to 2)’s RE bit = “1” (data present in the UiRB register),
an overrun error occurs and the UiRB register OER bit is set to “1” (overrun error occurred). In this
case, because the content of the UiRB register is indeterminate, a corrective measure must be
taken by programs on the transmit and receive sides so that the valid data before the overrun error
occurred will be retransmitted. Note that when an overrun error occurred, the SiRIC register IR bit
does not change state.
4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every
time reception is made.
5. When an external clock is selected, the conditions must be met while if the CKPOL bit = “0”, the
external clock is in the high state; if the CKPOL bit = “1”, the external clock is in the low state.
• The RE bit of UiC1 register= “1” (reception enabled)
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register= “0” (data present in the UiTB register)
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Precautions for Serial I/O (UART Mode)
Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission
complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be
sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
Precautions for A-D Converter
1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A-D conversion is stopped (before
a trigger occurs).
2. When the VCUT bit of ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref connected), start A-D conversion after passing 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi(i=0 to 7)) each and the AVSS pin.
Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 6.2 is an example connection
of each pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input
mode). Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit for
___________
the ADTRG pin is set to “0” (input mode).
5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key
input interrupt request is generated when the A-D input voltage goes low.)
6. The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency
to 250kHZ or more. With the sample and hold function, limit the φAD frequency to 1MHZ or more.
7. When changing an A-D operation mode, select analog input pin again in the CH2 to CH0 bits of
ADCON0 register and the SCAN1 to SCAN0 bits of ADCON1 register.
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M306H3MC-XXXFP/FCFP
Microcomputer
VCC
VCC
VCC (15pin) AVCC
C4
VSS
VREF
C1
C2
AVSS
VCC
C3
VCC (69pin)
C5
ANi
VSS
ANi: ANi (i=0 to 7)
Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
Figure 6.2. Use of capacitors to reduce noise
8. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A-D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for
CPU clock.
• When operating in one-shot or single-sweep mode
Check to see that A-D conversion is completed before reading the target ADi register. (Check the
ADIC register’s IR bit to see if A-D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A-D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit to
“0” (A-D conversion halted), the conversion result of the A-D converter is indeterminate. The contents
of ADi registers irrelevant to A-D conversion may also become indeterminate. If while A-D conversion
is underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.
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Precautions for Programmable I/O Ports
1. Setting the SM32 bit in the S3C register to “1” causes the P92 pin to go to a high-impedance state.
Similarly, setting the SM42 bit in the S4C register to “1” causes the P96 pin to go to a high-impedance
state.
2. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither
“high” nor “low”), the input level may be determined differently depending on which side—the programmable input/output port or the peripheral function—is currently selected.
Electric Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin,
noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout
pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation
tests conducted in the flush memory version.
Precautions for Flash Memory Version
Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite
ID codes are stored in addresses 0FFFDF 16 , 0FFFE3 16, 0FFFEB 16 , 0FFFEF 16, 0FFFF3 16,
0FFFF716, and 0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be
read or written in standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the
flash memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses
(H) of fixed vectors.
Precautions for Stop mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program BSET
0, CM1
; Stop mode
JMP.B
L1
L1:
Program after returning from stop mode
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M306H3MC-XXXFP/FCFP
Precautions for Wait mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode diabled) before executing the
WAIT instruction.
Precautions for Low power dissipation mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
Writing command and data
Write the command code and data at even addresses.
Precautions for Program Command
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in
the first bus cycle is the same even address as the write address specified in the second bus cycle.
Precautions for Lock Bit Program Command
Write ‘xx7716’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”.
Make sure the address value specified in the first bus cycle is the same uppermost block address that
is specified in the second bus cycle.
Operation speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using
the CM0 register’s CM06 bit and CM1 register’s CM17–6 bits. Also, set the PM1 register’s PM17 bit to
1 (with wait state).
Instructions inhibited against use
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
_______
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. The jump addresses for those interrupt
service routines should be set in the fixed vector table.
_______
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
Rev.1.00
2004.03.23
page 312 of 320
M306H3MC-XXXFP/FCFP
• The address match interrupt cannot be used because the flash memory’s internal data is referenced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
_______
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when
this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed
vector table.
_______
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
How to access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary
to ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only
_______
when NMI pin is “H” level.
Writing in the user ROM area
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
Regarding Programming/Erasure Times and Execution Time
As the number of programming/erasure times increases, so does the execution time for software
commands (Program, Block Erase, Erase All Unlock Blocks, and Lock Bit Program). Especially when
the number of programming/erasure times exceeds 1,000, the software command execution time is
noticeably extended. Therefore, the software command wait time that is set must be greater than the
maximum rated value of electrical characteristics.
_______
The software commands are aborted by hardware reset 1, hardware reset 2, NMI interrupt, and
watchdog timer interrupt. If a software command is aborted by such reset or interrupt, the block that
was in process must be erased before reexecuting the aborted command.
Rev.1.00
2004.03.23
page 313 of 320
M306H3MC-XXXFP/FCFP
Other Notes
Timing of power supplying
The power need to supply to VCC, VDD2, VDD3 and AVCC at a time. While operating, must set same
voltage.
Power supply noise and latch-up
In order to avoid power supply noise and latch-up, connect a bypass capacitor (more than 0.1µF)
directly between the VCC pin and VSS pin, VDD2 pin and VSS2 pin, VDD3 pin and VSS3 pin, AVCC pin
and AVSS pin using a heavy wire.
And, connect a capacitor (more than 0.1µF) to the TEST1 pin (35 pin).
When oscillation circuit stop for data slicer
Expansion register XTAL_VCO, PDC_VCO_ON,VPS_VCO_ON is set at “L”, when the data slicer is
not used, and the oscillation is stopped. When starting oscillation again, set data at the folowing order.
(a) Set expansion register XTAL_VCO = “H.”
(b) Set expansion register PDC_VCO_ON, VPS_VCO_ON = “H.”
(c) 60 ms or more is a waiting state (stability period of internal oscillation circuit + data slice prepara
tion).
✽ To operate slice RAM, set expansion register XTAL_VCO = “H.”
Access the memories after wating for 20 ms certainly when resuming synchronous oscillation
from the off state.
When operation start from stand-by mode (clock is stopped)
Set up an extended register as follows in standby mode.
(a) Set extended register XTAL_VCO, PDC_VCO_ON, and VPS_VCO_ON as “L.”
(b) Set extended register STBY0 and STBY1 as “H.” Set the other extended register as an initial state
(at reset).
When you return to an oscillation state from a clock oscillation stop, set up as the notes of the oscillation circuit stop for data slicers.
Rev.1.00
2004.03.23
page 314 of 320
M306H3MC-XXXFP/FCFP
Notes on operating with a low supply voltage (VCC = 2.60 V to 5.25 V, f(XCIN) = 32 KHz)
When in single-chip mode, this product can operate with a low supply voltage only during low power
dissipation mode. Before operating with a low supply voltage, always be sure to set the relevant
register bits to select low power dissipation mode (BCLK : f(XCIN), main clock XIN : stop, subclock XCIN
: oscillating). Then reduce the power supply voltage VCC to 3.0 V.
Also, when returning to normal operation, raise the power supply voltage to 5.0V while in low power
consumption mode before entering normal operation mode.
When moving from any operation mode to another, make sure a state transition occurs according to
the state transition diagram (Figure 2.5.9) in Section 2.5.3, “Power control.”
The status of the power supply voltage VCC during operation mode transition is shown in Figure 6.3
below.
5V
VCC
3V
Power control
operation modes
Normal operation mode
Low power dissipation mode
Normal operation mode
Note 1: Normal operation mode refers to the high-speed, medium-speed, and low-speed modes.
Note 2: When operating with a low supply voltage, be aware that only the CPU, ROM, RAM,
input/output ports, timers (timers A and B), and the interrupt control circuit can be used.
All other internal resources (e.g., data slicer, DMAC and A/D ) cannot be used.
Figure 6.3 Status of the power supply voltage VCC during operation mode transition
Serial I/O (RxDi input setup time)
For the RXDi input setup time, refer to the rated values shown below, as well as Electrical Characteristics
Table 3.23, “Serial I/O.”
Table6.1. Serial I/O (VCC=5V)
Symbol
tsu(D-C)
Parameter
RxDi input setup time
Note: Refer to “Table 3.23. Serial I/O of the Electrical Characteristics.
Rev.1.00
2004.03.23
page 315 of 320
Standard
Min.
Max.
70
Unit
ns
M306H3MC-XXXFP/FCFP
7. Differences Between M306H3MC-XXXFP/FCFP and M306H2MC-XXXFP/FCFP
Differences Between M306H3MC-XXXFP/FCFP and M306H2MC-XXXFP/FCFP:
Differences in Mask ROM Version and Flash Memory Version (Note 1)
Item
M306H2MC-XXXFP/FCFP
M306H3MC-XXXFP/FCFP
Supply voltage
4.75 to 5.25V (f(XIN)=10MHz)
2.60 to 5.25V (f(XCIN)=32kHz)
4.75V to 5.25V (f(XIN)=10MHz)
2.80V to 5.25V (f(XIN)=32kHz)
Clock Generating
Circuit
When placed in low power mode, a divide-by-8
value is used foe these clocks. The XIN drive
capability is set to HIGH.
When placed in low power mode, the divide-by-n
value for the main clock does not change.
Nor does the XIN drive capability change.
External device
connect area
0400016 to 07FFF16 (PM13=0)
0800016 to 0FFFF16 (PM10=0)
1000016 to 26FFF16
2800016 to 7FFFF16
8000016 to CFFFF16 (PM13=0)
D0000 16 to FFFFF16 (Microprocessor mode)
0400016 to 07FFF16
0800016 to 27FFF 16
30000 16 to FFFFF16 (Microprocessor mode)
(M306H2FCFP doesn't have microprocessor
mode)
Upper address in
P40 to P43 (A16 to A19), P34 to P37
memory expansion (A12 to A15) : Switchable between address
mode and
bus and I/O port
microprocessor
mode
P4 0 to P43 (A 16 to A19)
: Switchable between address bus and I/O port
A12 to A15 : No switchable
Software wait to
external area
Variable (0 to 3 waits)
Variable (0 to 1 waits)
Protect
Can be set for PM0, PM1, PM2, CM0, CM1,
PD9, S3C, S4C, PCLKR registers
Can be set for PM0, PM1, CM0, CM1, PD9,
S3C, S4C registers
Watchdog timer
Watchdog timer interrupt or watchdog timer
reset is selected Count source protective
mode is available
Watchdog timer interrupt
Address match
interrupt
4
2
Timers A, B count
source
Selectable: f1, f2, f8, f32, fC32
Selectable: f1, f8, f32, fC32
(UART, clock synchronous, I2C bus, IE bus)
Serial I/O
(UART0 to UART2) ✕ 3
No count source protective mode
(UART, clock synchronous,) x 2
(UART, clock synchronous, IIC bus, IE bus)
✕1
UART0 to UART2, Select from f1SIO, f2SIO, f8SIO, f32SIO
SI/O3, SI/O4
count source
Select from f1, f8, f32
Serial I/O
RTS timing
Assert low when reception is completed
Assert low when receive buffer is read
Have
Serial I/O
CTS/RTS separate
function
None
UART2 data
transmit timing
After data was written, transfer starts at the 2nd
BRG overflow timing
(same as UART0 and UART1)
After data was written, transfer starts at the
1st BRG overflow timing
(Output starts one cycle of BRG overflow
earlier than UART0 and UART1)
Serial I/O
sleep function
None
Have
Note 1: About the details and the electric characteristics, refer to data sheet.
Rev.1.00
2004.03.23
page 316 of 320
M306H3MC-XXXFP/FCFP
Differences Between M306H3MC-XXXFP/FCFP and M306H2MC-XXXFP/FCFP:
Differences in Mask ROM Version and Flash Memory Version (Note 1)
Item
M306H2MC-XXXFP/FCFP
M306H3MC-XXXFP/FCFP
Serial I/O
I2C mode
Start condition, stop condition:
Auto-generationable
Start condition, stop condition:
Not auto-generationable
Serial I/O
I2C mode
SDA delay
Only digital delay is selected as SDA delay
SDA digital delay count source: BRG
Analog or digital delay is selected as SDA
delay
SDA digital delay count source: 1/ f(XIN)
SI/O3, SI/O4
clock polarity
Selectable
Fixed
A-D converter
operation clock
Selectable: fAD, fAD divided by 2, 3, 4, 6, 12
Selectable: fAD, fAD/2, fAD/4
Low power
dissipation starting
function
Selectable of middle speed mode (the main clock
divided by 8) and low power dissipation mode
(sub clock) by the external pin.
Only middle speed mode (the main clock
divided by 8) at reset release
Sauce clock for
data slicer
Use main clock
Supply from the FSCIN pin
The register for data
slice system setup
Three lines
Two lines
Horizontal synchronized
signal calculation
Have
None
Horizontal synchronized
interrupt
It is possible to generate interruption with the
specified horizonal line.
None
Filter pin for
JUST CLOCK
P93 : programmable I/O port, Timer B3 input or
the input for JUST CLOCK can be changed
P93 : programmable I/O port or Timer B3 input
can be changed
Remote control
function
By inputting the pulse of remote control into P94,
distinction of a header pattern is possible.
None
CRC operation
circuit for EPG-J
Have.
82-bit CRC error detection and the error
correction by majority logic are possible.
None
Note 1: About the details and the electric characteristics, refer to data sheet.
Rev.1.00
2004.03.23
page 317 of 320
M306H3MC-XXXFP/FCFP
Differences in Flash Memory Version (Note 1)
Item
M306H2FCFP
M306H3FCFP
User ROM blocks
7 blocks: 4 Kbytes x 2, 8 Kbytes x 3,
32 Kbytes x1, 64 Kbytes x 1
32 Kbytes x 4
CPU rewrite mode
Have (EW1 mode)
None (EW1 mode)
Protect by block unit Have
(by lock bit)
None
Boot ROM area
0DE00016 - 0DFFFF16
(8K byte)
0FF00016 - 0FFFFF16
(4K byte)
Note 1: About the details and the electric characteristics, refer to data sheet.
Rev.1.00
2004.03.23
page 318 of 320
M306H3MC-XXXFP/FCFP
Differences Between M306H3MC-XXXFP/FCFP and M306H2MC-XXXFP/FCFP:
Pin Connection (Note 1)
Item
M306H3FCFP
M306H3MC-XXXFP
M306H2MC-XXXFP
M306H2FCFP
35-pin
TEST 1 pin
• Pin for test
• It connects with GND through a
capacitor
36-pin
M1 pin
• Pin for test
• “H” or “L” is
inputted.
108-pin
START pin
• The pin for oscillation selection
input.
• Oscillation circuit is chosen
“H” ••• XIN-XOUT
“L” ••• XCIN-XCOUT
VDD1
• Digital system power supply input pin
• 4.75 to 5.25 are impressed
111-pin
TEST 2 pin
• Pin for test
• “L” is inputted
VSS1
• GND
M2 pin
• Pin for test
• “L” is inputted
M1 pin
M1 pin
• Mode selection input pin • Pin for test
• “H” is inputted when use • “L” is inputted
microprocesser mode or
memory expansion mode.
• “L” is inputted when use
standard serial I/O mode
(single-chip mode)
Note 1: About the details and the electric characteristics, refer to data sheet.
Rev.1.00
2004.03.23
page 319 of 320
M2 pin
• The power supply input pin for flash
rewriting.
• Usually, 0V are impressed, 4.75V to
5.25V are applied at flash memory
rewriting.
M1 pin
• Chip mode setting input pin.
• Usually, “L” is inputted
M306H3MC-XXXFP/FCFP
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
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contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
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Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
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as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
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Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Rev.1.00
2004.03.23
page 320 of 320
REVISION DESCRIPTION LIST
Rev.
Revision Description
No.
Rev.
date
0.20
First Edition of PDF File
0202
0.21
P2
P3
P4
P5
P7
P8
P9
0829
Table of contents is changed.
F1.3.1 is changed.
T1.4.1 is changed.
L1 and T1.5.1 are changed.
T1.5.2 is changed.
T1.5.3 is changed.
2.OPERATION OF FUNCTIONAL is added in L1.
M306H3FCFP is added in L3, L6 and L10. L2, L3, L5, L6, L9 and L10 are changed.
F2.1.1 is changed.
P10 L1, L2 are changed.
P12 L1 to L4 are changed. L5, L6 are delated. Hardware Reset 2 is delated.
P13 L1, L9 are changed. Oscillation Stop Detection Reset is delated.
P14 F2.3.2 is changed.
P15 T2.3.1 is changed.
P16 Table of SFR register is changed.
P17 Table of SFR register is changed.
P18 Table of SFR register is changed.
P19 Table of SFR register is changed.
P20 Table of SFR register is changed.
P21 Table of SFR register is changed.
P22 L1 is changed. L9 is added. T2.4.2 is changed. L16, L17 are changed.
P23 F2.4.1 is changed.
P24 F2.4.2 is changed.
– F1.6.3 Memory Map in Single Chip Mode is delated.
P25 to P35 2.4.1 Bus and 2.4.2 Bus Control are added.
P36 L2 is changed. L5 and L6 are delated. T2.5.1 is changed.
P37 F2.5.1 is changed.
P38 F2.5.2 is changed.
P39 F2.5.3 is changed.
P40 F2.5.4 is changed.
– F1.9.6 PLC0 Register is delated.
P41 L13 and L14 are added. L16 is changed. L19 is changed.
P42 L10 is changed. L14 and L15 are added.
– (4) PLL Clock is delated.
P43 F2.5.7 is changed.
P44 L6 to L8 is changed. L10 and L11 are delated. L13, L16, L17, L21 and L24 are changed.
P45 L5 and L12 are changed. L14 to L19, L23 to L27, L33 to L34 and L38 to L40 are delated.
(1/5)
Rev.
No.
0.21
Revision Description
P46 T1.9.3 delated. L3 to L5 are changed. L12 to L13 are delated.
P48 L4 to L6 are changed. L18 to L21 and L45 to L46 are delated.
P50 L3 to L4 are delated. F2.5.8 is changed.
P51 F2.5.9 is changed.
– T1.9.7 Allowed Transition and Setting is delated.
P52 L8 to L9 are delated.
– Oscillation Stop and Re-oscillation Detect Function is delated.
– How to Use Oscillation Stop and Re-oscillation Detect Function is delated.
P53 L8 and L9 are changed. L8 is delated. F2.6.1 is changed.
P86 F2.10.1 is changed.
P87 F2.10.2 is changed.
P158 L2 and L4 are changed. T2.12.1 is changed.
P159 F2.12.1 is changed.
P160 F2.12.2 is changed.
P161 F2.12.3 is changed.
P162 T2.12.2 is changed.
P163 F2.12.4 is changed.
P164 F2.12.3 is changed.
P165 F2.12.5 is changed.
P166 T2.12.4 is changed.
P167 F2.12.6 is changed.
P168 T2.12.5 is changed.
P169 F2.12.7 is changed.
P170 T2.12.6 is changed.
P171 F2.12.8 is changed.
P172 (a) Resolution Select Function is delated. L3 and L14 are changed.
L19 to L20 are delated.
P173 L8 is delated. F2.12.10 is changed.
P174 L8 is changed. L11 is delated. F2.12.11 is changed.
P199 T2.14.4 is changed.
P242 L3, L10, L11, L16 and L24 are changed. L14 to L15 are delated.
P243 F2.15.1 is changed.
P244 F2.15.2 is changed.
P246 F2.15.4 is changed.
P248 F2.15.7 is changed.
P249 F2.15.8 is changed.
–
F1.25.9 PC14 Register and PUR3 Register is delated.
P252 T2.15.1 and T2.15.2 are changed.
P254 to P275 3.Electrical Characteristics is changed.
P276 T4.1.1 and T4.1.2 are changed.
P277 L3 to L5 and L8 to L9 are delated. F4.2.1 is changed.
(2/5)
Rev.
date
0829
Rev.
Revision Description
No.
0.21
P278
P279
P280
P283
P284
P285
P296
P298
P299
P300
–
–
P301
P302
–
L2 is changed.
F4.2.2 is changed.
F4.2.1 is changed.
F4.2.4 is changed.
F4.2.5 is changed.
F4.2.6 is changed.
Notes are added in T4.3.3.
L6 to L7 are changed.
T4.3.4 is changed.
F4.3.6 is changed.
F1.27.14 Pin Connections for Serial I/O Mode (2) is delated.
F1.27.15 Pin Connections for Serial I/O Mode (3) is delated.
F4.3.7 is changed.
F4.3.8 is changed.
5.7 Electrical Characteristics is delated.
1.00
All page Type name is changed.
P3
F1.3.1 is changed.
P5
F1.4.1 is changed.
P6
F1.5.1 is changed.
P8
T1.5.2 is changed.
P9
T1.5.3 is changed.
P28 (3) Chip Select Signal L5 to L6 are delated.
P35 (10) Software Wait L3 to L4 are delated. L6 is changed.
P36 Note 3 is delated.
P40 F2.5.1 is changed.
P46 F2.5.7 is changed.
P54 F2.5.9 is changed.
P56 L11 is changed.
P61 T2.7.2 is changed.
P65 F2.7.4 is changed.
P71 F2.7.10 is changed.
P91 F2.10.6 is changed.
P98 F2.10.10 is changed.
P100 F2.10.11 is changed.
P101 F2.10.13 is changed.
P109 F2.11.1 is changed.
P132 F2.11.21 is changed.
P135 T2.11.12 is changed.
P159 F2.12.1 is changed.
P174 F2.12.11 is changed.
P177 F2.14.1 is changed.
(3/5)
Rev.
date
0829
0308
Rev.
Revision Description
No.
1.00
P178
P179
P180
P181
P182
P183
P185
P186
P192
P194
P195
P196
P197
P198
P199
P200
P201
P202
P204
P205
P222
P226
P235
P237
P243
P244
P249
P251
P252
P253
P254
P261
P277
P278
P279
P281
P285
P287
P307
P310
P315
P317
L2 and L4 are changed. T2.14.1 is changed.
T2.14.2 is changed
F2.14.2 is changed
F2.14.3 is changed
L2 to L4 are changed. T2.14.3 and F2.14.5 are changed.
L6 is changed. F2.14.6 is changed.
F2.14.8 is changed.
Figure of register (1) is changed.
Figure of register (7) is changed.
Figure of register (10) is changed.
Figure of register (11) is changed.
Figure of register (12) is changed.
Figure of register (13) is changed.
Figure of register (14) is changed.
T2.14.4 is changed.
L7 is changed. F2.14.9 is changed.
Figure of register (1) is changed.
Figure of register (2) is changed.
Figure of register (5) is changed.
Figure of register (6) is changed.
Figure of register (29) is changed.
Figure of register (38) is changed.
F2.14.22 is changed.
L15 and L23 are changed.
Title of F2.15.7 is changed.
Title of F2.15.8 is changed.
T3.1 is changed.
T3.4, T3.5 and T3.6 are changed.
T3.7 is changed.
T3.8 is changed.
T3.9 is changed.
F3.2 is changed.
L22 is changed.
F4.2.4 is changed.
F4.2.5 is changed.
F4.2.7 is changed.
L1 and L5 are changed.
L16 is changed.
(c) Timer B 8. is changed.
L13 is changed.
L21 is changed.
L2 to L3 in table are changed.
(4/5)
Rev.
date
0308
Rev.
Revision Description
No.
1.00
P1
P3
P36
P179
P181
P183
P186
P226
P254
P278
P310
L2 is changed.
F1.3.1 is changed.
T2.4.10 is changed.
T2.14.2 is changed.
F2.14.3 is changed.
F2.14.6 is changed.
Bit composition of a CRC register (1) is changed.
Bit composition of an expansion register (38) is changed.
T3.9 is changed.
F4.2.4 is changed.
F6.2 is changed.
(5/5)
Rev.
date
0308