NLU1G08 Single 2-Input AND Gate The NLU1G08 MiniGatet is an advanced high−speed CMOS 2−input AND gate in ultra−small footprint. The NLU1G08 input and output structures provide protection when voltages up to 7.0 V are applied, regardless of the supply voltage. www.onsemi.com Features High Speed: tPD = 3.5 ns (Typ) @ VCC = 5.0 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C Power Down Protection Provided on inputs Balanced Propagation Delays Overvoltage Tolerant (OVT) Input and Output Pins Ultra−Small Packages These are Pb−Free Devices 1 IN A 6 GND 3 1 NC 4 & IN B UDFN6 1.0 x 1.0 CASE 517BX UDFN6 1.45 x 1.0 CASE 517AQ M M 1 2 M OUT Y = Device Marking = Date Code ORDERING INFORMATION Figure 1. Pinout (Top View) IN A 2M 1 VCC 5 2 UDFN6 1.2 x 1.0 CASE 517AA D IN B MARKING DIAGRAMS K • • • • • • • See detailed ordering and shipping information on page 4 of this data sheet. OUT Y Figure 2. Logic Symbol PIN ASSIGNMENT 1 IN B 2 IN A 3 GND 4 OUT Y 5 NC 6 VCC FUNCTION TABLE Input Output A B Y L L H H L H L H L L L H © Semiconductor Components Industries, LLC, 2016 August, 2016 − Rev. 6 1 Publication Order Number: NLU1G08/D NLU1G08 MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage −0.5 to +7.0 V VIN DC Input Voltage −0.5 to +7.0 V DC Output Voltage −0.5 to +7.0 V VIN < GND −20 mA VOUT < GND ±20 mA VOUT Parameter IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Source/Sink Current ±12.5 mA ICC DC Supply Current Per Supply Pin ±25 mA IGND DC Ground Current per Ground Pin ±25 mA TSTG Storage Temperature Range −65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C TJ Junction Temperature Under Bias 150 °C MSL Moisture Sensitivity FR Flammability Rating ILATCHUP Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Latchup Performance Above VCC and Below GND at 125°C (Note 2) mA ±500 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow. 2. Tested to EIA / JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 1.65 5.5 V VCC Positive DC Supply Voltage VIN Digital Input Voltage 0 5.5 V Output Voltage 0 5.5 V −55 +125 °C 0 0 100 20 ns/V VOUT TA Operating Free−Air Temperature Dt/DV Input Transition Rise or Fall Rate VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V www.onsemi.com 2 NLU1G08 DC ELECTRICAL CHARACTERISTICS Symbol VIH VIL VOH VOL Parameter VCC (V) Conditions Low−Level Input Voltage Low−Level Input Voltage High−Level Output Voltage Low−Level Output Voltage TA = +855C TA = 25 5C Min Typ Max Min 1.65 0.75 x VCC 0.75 x VCC 2.3 to 5.5 0.70 x VCC 0.70 x VCC Max TA = −555C to +1255C Min Max V 1.65 0.25 x VCC 0.25 x VCC 0.25 x VCC 2.3 to 5.5 0.30 x VCC 0.30 x VCC 0.30 x VCC VIN = VIH or VIL IOH = −50 mA 2.0 3.0 4.5 1.9 2.9 4.4 VIN = VIH or VIL IOH = −4 mA IOH = −8 mA 3.0 4.5 2.58 3.94 VIN = VIH or VIL IOL = 50 mA 2.0 3.0 4.5 VIN = VIH or VIL IOL = 4 mA IOL = 8 mA 2.0 3.0 4.5 0 0 0 Unit 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.80 2.34 3.66 V V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Input Leakage Current 0 v VIN v 5.5 V 0 to 5.5 ±0.1 ±1.0 ±1.0 mA ICC Quiescent Supply Current VIN = 5.5 V or GND 5.5 1.0 10 40 mA AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 nS) Symbol Parameter tPLH, tPHL Propagation Delay, Input A or B to Output Y CIN Input Capacitance CPD Power Dissipation Capacitance (Note 3) VCC (V) Test Condition 3.0 to 3.6 4.5 to 5.5 TA = +855C TA = 25 5C Min Typ Max CL = 15 pF 4.1 8.8 CL = 50 pF 5.9 CL = 15 pF CL = 50 pF 5.0 Max Unit 10.5 12.5 ns 12.3 14 16.5 3.5 5.9 7.0 9.0 4.2 7.9 9.0 11 5.5 10 10 10 11 Min Max TA = −555C to +1255C Min pF pF 3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without load. Average operating current can be obtained by the equation ICC(OPR) = CPD • VCC • fin + ICC. CPD is used to determine the no−load dynamic power consumption: PD = CPD • VCC2 • fin + ICC • VCC. www.onsemi.com 3 NLU1G08 VCC Input A or B 50% VCC 50% CL* GND tPLH tPHL VOH Output Y OUTPUT INPUT 50% VCC *Includes all probe and jig capacitance. A 1−MHz square input wave is recommended for propagation delay tests. VOL Figure 3. Switching Waveforms Figure 4. Test Circuit ORDERING INFORMATION Package Shipping† NLU1G08MUTCG UDFN6, 1.2 x 1.0, 0.4P (Pb−Free) 3000 / Tape & Reel NLU1G08AMUTCG UDFN6, 1.45 x 1.0, 0.5P (Pb−Free) 3000 / Tape & Reel NLU1G08CMUTCG UDFN6, 1.0 x 1.0, 0.35P (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 4 NLU1G08 PACKAGE DIMENSIONS UDFN6, 1.2x1.0, 0.4P CASE 517AA ISSUE D EDGE OF PACKAGE PIN ONE REFERENCE 2X 0.10 C L1 ÉÉ ÉÉ E DETAIL A Bottom View (Optional) TOP VIEW 2X EXPOSED Cu 0.10 C (A3) 0.10 C A1 A 10X 0.08 C ÉÉÉ ÉÉÉ DETAIL B Side View (Optional) 5X A3 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 1.20 BSC 1.00 BSC 0.40 BSC 0.30 0.40 0.00 0.15 0.40 0.50 MOUNTING FOOTPRINT* 6X 6X 0.42 C A1 DIM A A1 A3 b D E e L L1 L2 MOLD CMPD SEATING PLANE SIDE VIEW 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B D 0.22 L 3 L2 6X b 0.10 C A B 0.05 C 6 0.40 PITCH 4 e NOTE 3 1.07 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BOTTOM VIEW www.onsemi.com 5 NLU1G08 PACKAGE DIMENSIONS UDFN6 1.45x1.0, 0.5P CASE 517AQ ISSUE O A B D L L L1 PIN ONE REFERENCE 0.10 C ÉÉÉ ÉÉÉ DETAIL A E OPTIONAL CONSTRUCTIONS DETAIL B OPTIONAL CONSTRUCTIONS A 0.05 C A1 SIDE VIEW MOLD CMPD DETAIL B 0.05 C 6X DIM A A1 A2 b D E e L L1 ÉÉ ÉÉ EXPOSED Cu TOP VIEW 0.10 C A2 6X C 6X SEATING PLANE 0.30 PACKAGE OUTLINE L 1.24 3 DETAIL A 6X 0.53 4 BOTTOM VIEW MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.07 REF 0.20 0.30 1.45 BSC 1.00 BSC 0.50 BSC 0.30 0.40 −−− 0.15 MOUNTING FOOTPRINT e 1 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 6X 0.50 PITCH DIMENSIONS: MILLIMETERS b 0.10 C A B 0.05 C 1 NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6 NLU1G08 PACKAGE DIMENSIONS UDFN6 1.0x1.0, 0.35P CASE 517BX ISSUE O PIN ONE REFERENCE 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. PACKAGE DIMENSIONS EXCLUSIVE OF BURRS AND MOLD FLASH. A B D ÉÉÉ ÉÉÉ ÉÉÉ E 0.10 C 2X 0.10 C DIM A A1 A3 b D E e L L1 TOP VIEW A3 0.05 C A MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.12 0.22 1.00 BSC 1.00 BSC 0.35 BSC 0.25 0.35 0.30 0.40 0.05 C SIDE VIEW A1 C RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE 5X e 5X 0.48 L 6X 0.22 3 1 L1 1.18 6 4 6X BOTTOM VIEW b 0.10 M C A B 0.05 M C 0.53 1 PKG OUTLINE NOTE 3 0.35 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MiniGate is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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