Rohm BD8963EFJ Low noise high-efficiency switching regulator with built-in power mosfet Datasheet

Single-chip Type with Built-in FET Switching Regulators
Low Noise
High-efficiency Switching Regulator
with Built-in Power MOSFET
BD8963EFJ
No.10027EAT43
●Description
ROHM’s high efficiency step-down switching regulator BD8963EFJ is a power supply designed to produce a low voltage
including 1 volts from 5.5/3.3 volts power supply line. Offers high efficiency with synchronous rectifier. Employs a current
mode control system to provide faster transient response to sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET)
3) Incorporates soft-start function.
4) Incorporates thermal protection and ULVO functions.
5) Incorporates short-current protection circuit with time delay function.
6) Incorporates shutdown function
7) Employs small surface mount package : HTSOP-J8
●Applications
Power supply for LSI including DSP, Micro computer and ASIC
●Absolute maximum ratings
Symbol
Ratings
VCC Voltage
VCC
-0.3 ~ +7 *1
V
EN Voltage
VEN
-0.3 ~ +7
V
VSW,VCOMP
-0.3 ~ +7
V
Parameter
SW,COMP Voltage
Unit
*2
Power Dissipation 1
Pd1
0.5
W
Power Dissipation 2
Pd2
3.76*3
W
Operating temperature range
Topr
-25 ~ +85
℃
Storage temperature range
Tstg
-55 ~ +150
℃
Tjmax
+150
℃
Maximum junction temperature
*1
*2
*3
Pd should not be exceeded.
Reduced by 4.0mW for increase in Ta of 1℃ above 25℃.
Reduced by 30.0mW for increase in Ta of 1℃ above 25℃.
(when mounted on a board 70.0mm × 70.0mm × 1.6mm Glass-epoxy PCB)
●Operating conditions (Ta=-25 ~ +85℃)
Parameter
Symbol
Ratings
Min.
Typ.
Max.
Unit
Power Supply Voltage
VCC
2.7 *5
5.0
5.5
V
EN Voltage
VEN
0
-
Vcc
V
*4
Output voltage range
SW average output current
*4
*5
VOUT
1.0
-
2.5
V
Isw
-
-
3.0*5
A
In case set output voltage 1.6V or more, VccMin. = Vout +2.25V
Pd should not be exceeded.
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1/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Electrical characteristics
◎BD8963EFJ(Unless otherwise specified , Ta=25℃ VCC=5V, EN=VCC, R1=20kΩ, R2=7.5kΩ)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
Standby Current
ISTB
-
5
20
µA
Bias Current
ICC
-
350
600
µA
Conditions
EN=GND
EN Low Voltage
VENL
-
GND
0.3
V
Stand-by Mode
EN High Voltage
VENH
2.0
VCC
-
V
Active Mode
VEN=5V
EN Current
IEN
-
1.25
10
µA
Oscillation Frequency
FOSC
0.8
1
1.2
MHz
Pch FET ON Resistance
RONP
-
145
290
mΩ
VCC=5V
Nch FET ON Resistance
RONN
-
80
160
mΩ
VCC=5V
ADJ Reference Voltage
VADJ
0.788
0.800
0.812
V
COMP SINK Current
ICOSI
10
25
-
µA
VADJ=1.0V
COMP Source Current
ICOSO
10
25
-
µA
VADJ=0.6V
UVLO Threshold Voltage
VUVLO1
2.400
2.500
2.600
V
Vcc=5V→0V
UVLO Hysteresis Voltage
VUVLO2
2.425
2.550
2.700
V
Vcc=0V→5V
TSS
0.5
1
2
ms
TLATCH
1
2
4
ms
VSCP
-
VOUT×0.5
VOUT×0.7
V
Soft Start Time
Timer Latch Time
Output Short circuit Threshold Voltage
●Physical dimension
VOUT=1.0V→0V
●Block diagram・Application circuit
V CC
4.9±0.1
EN 3
Max5.25(include.BURR)
(3.2)
7
6
0.65±0.15
(2.4)
6.0±0.2
3.9±0.1
Lot No.
2
3
4
Current
Comp
+
Gm Amp
SLOPE
+
+0.05
0.17 -0.03
0.545
R Q
4
OSC
V CC
Input
Current
Sense/
Protect
S
5
+
V CC
CLK
Output
6
Driver
Logic
SW
UVLO
Soft
Start
S
TSD
2
GND
0.08±0.05
SCP
0.85±0.05
1.0Max.
VREF
5
BD8963
1
+6
-4
1.05±0.2
8
4
1.27
+0.05
0.42 -0.04
0.08
M
8
HTSOP-J8
●Pin No. & function table
Pin No.
Pin name
COMP
2
GND
COMP
(unit:mm)
Fig.2 BD8963EFJ Block Diagram
Fig.1 BD8963EFJ TOP View
1
1
ADJ
0.08 S
PIN function
GmAmp output pin/Connected phase compensation capacitor
Ground
3
EN
Enable pin(Active High, Open Active)
4
VCC
VCC power supply input pin
5
SW
Pch/Nch FET drain output pin
6
SW
Pch/Nch FET drain output pin
7
N.C
Non Connect
8
ADJ
Output voltage detect pin
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2/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Characteristics data【BD8963EFJ】
1.0
1.0
VCC=5.0V
Ta=25℃
Io=0A
0.5
【VOUT=1.1V】
0.5
Ta=25℃
0.0
0.0
0
1
2
3
4
INPUT VOLTAGE:VCC[V]
VCC=5.0V
Io=0A
1
2
3
EN VOLTAGE:VEN[V]
4
1.11
1.10
1.09
1.08
1.15
70
60
50
40
30
10
1.05
【VOUT=1.1V】
VCC=5.0V
Ta=25℃
0
75
1.05
1.00
0.95
0.90
0.85
100
1000
OUTPUT CURRENT:IOUT[mA]
10000
-25
450
VCC=5.0V
PMOS
0.10
NMOS
0.05
CIRCUIT CURRENT:I CC [μA]
EN VOLTAGE:VEN[V]
0.15
1.4
1.2
1.0
0.8
0.6
0.4
0.2
75
Fig.9 Ta-RONN, RONP
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75
VCC=5.0V
400
350
300
250
200
150
100
50
0.0
0.00
25
50
TEMPERATURE:Ta[℃]
Fig.8 Ta-FOSC
1.6
25
50
TEMPERATURE:Ta[℃]
0
500
1.8
VCC=5.0V
ON RESISTANCE:RON[Ω]
1.10
2.0
0
VCC=5.0V
Fig.7 Efficiency
0.20
10
0.80
10
Fig. 6 Ta-VOUT
-25
2
4
6
8
OUTPUT CURRENT:IOUT[A]
Fig.5 IOUT-VOUT
1.20
1.06
25
50
TEMPERATURE:Ta[℃]
VCC=5.0V
Ta=25℃
0
90
20
0
【VOUT=1.1V】
0.5
100
1.07
-25
1
5
80
EFFICIENCY:η[%]
OUTPUT VOLTAGE:VOUT[V]
【VOUT=1.1V】
1.12
1.5
Fig.4 VEN-Vout
1.15
1.13
【VOUT=2.5V】
VCC=5V
Ta=25℃
2
0
0
5
Fig.3 Vcc-Vout
1.14
OUTPUT VOLTAGE:VOUT[V]
1.5
1.5
FREQUENCY:FOSC[MHz]
2.0
【VOUT=2.5V】
Ta=25℃
2.5
【VOUT=1.1V】
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
2.5
3
2.0
3.0
-25
0
25
50
TEMPERATURE:Ta[℃]
Fig.10 Ta-VEN
3/17
75
0
-25
0
25
50
TEMPERATURE:Ta[℃]
75
Fig.11 Ta-ICC
2010.06 - Rev.A
BD8963EFJ
Technical Note
1.2
FREQUENCY:FOSC[MHz]
【VOUT=1.1V】
EN
Ta=25℃
SW
[VOUT=1.1V】
1.1
1
VOUT
VOUT
0.9
VCC=5.0V
Ta=25℃
Io=0A
VCC=5.0V
Ta=25℃
0.8
2.7
3.1
3.5
3.9
4.3
4.7
INPUT VOLTAGE:VCC[V]
5.1
5.5
Fig.12 Vcc-FOSC
VOUT
Fig.13 Soft start waveform
【VOUT=1.1V】
Fig.14
SW waveform Io=10mA
【VOUT=1.1V】
VOUT
IOUT
IOUT
VCC=5.0V
Ta=25℃
Fig. 15 Transient response
Io=0.5A→1.5A(10µs)
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VCC=5.0V
Ta=25℃
Fig. 16 Transient response
Io=1.5A→0.5A(10µs)
4/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Information on advantages
Advantage 1 : Offers fast transient response with current mode control system.
Conventional product (Load response IO= 0.5A→1.5A)
BD8963EFJ (Load response IO= 0.5A→1.5A)
VOUT
VOUT
36mV
75mV
IOUT
IOUT
Voltage drop due to sudden change in load was reduced by about 50%.
Fig.17 Comparison of transient response
Advantage 2 : Offers high efficiency with synchronous rectifier
Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor.
ON resistance of P-channel MOS FET : 145mΩ(Typ.)
ON resistance of N-channel MOS FET : 80mΩ(Typ.)
100
90
EFFICIENCY:η[%]
80
70
60
50
40
30
【VOUT=1.1V】
VCC=5.0V
Ta=25℃
20
10
0
10
100
1000
OUTPUT CURRENT:IOUT[mA]
10000
Fig.18 Efficiency
Advantage 3 :・Supplied in smaller package due to small-sized power MOS FET incorporated.
・Output capacitor Co required for current mode control: 10μF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 1.5μH inductor
Reduces a mounting area required.
VCC
15mm
Cin
RCOMP
DC/DC
Convertor
Controller
RCOMP
L
VOUT
CIN
L
10mm
CCOMP
Co
CO
CCOMP
Fig.19 Example application
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5/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Operation
BD8963EFJ is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing
current mode PWM control system.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,
and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a
N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp)
receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback
control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the
P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control
repeat this operation.
SENSE
Current
Comp
RESET
VOUT
Level
Shift
R Q
FB
SET
Gm Amp.
COMP
S
IL
Driver
Logic
VOUT
SW
Load
OSC
Fig.20 Diagram of current mode PWM control
PVCC
Current
Comp
SENSE
Current
Comp
FB
SET
GND
SET
RESET
GND
RESET
SW
GND
SW
IL
IL(AVE)
VOUT
VOUT(AVE)
VOUT
Fig.21 PWM switching timing chart
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6/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Description of operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 5µF (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of
50mV (Typ.) is provided to prevent output chattering.
Hysteresis 50mV
VCC
EN
VOUT
Tss
Tss
Tss
Soft start
Standby mode
Standby
mode
Operating mode
Operating mode
UVLO
UVLO
Standby
mode
Operating mode
Standby mode
EN
UVLO
Fig.22 Soft start, Shutdown, UVLO timing chart
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking
UVLO.
EN
Output OFF
latch
Output Short circuit
Threshold Voltage
VOUT
IL Limit
IL
t1<TLATCH
Standby
mode
t2=TLATCH
Operating mode
Standby
mode
Timer latch
EN
Operating mode
EN
Fig.23 Short-current protection circuit with time delay timing chart
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7/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
η=
VOUT×IOUT
Vin×Iin
×100[%]=
POUT
Pin
×100[%]=
POUT
POUT+PDα
×100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
1) ON resistance dissipation of inductor and FET：PD(I2R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
1)PD(I2R)=IOUT2×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output
current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET)
2
3)PD(SW)= Vin ×CRSS×IOUT×f
IDRIVE
(CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.)
2
4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
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8/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
4
① IC only
θj-a=249.5℃/W
②1 layers（copper foil area:0mm×0mm）
θj-a=153.2℃/W
③2 layers（copper foil area:15mm×15mm）
θj-a=113.6℃/W
④2 layers（copper foil area:70mm×70mm）
θj-a=59.2℃/W
⑤4 layers（copper foil area:70mm×70mm）
θj-a=33.3℃/W
(when mounted on a board 70mm×70mm×1.6mm
Glass-epoxy PCB with termal Via)
⑤3.76W
Power dissipation:Pd [W]
3
P=IOUT2×RON
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RCOIL：DC resistance of coil
RONP：ON resistance of P-channel MOS FET
RONN：ON resistance of N-channel MOS FET
IOUT：Output current
④2.11W
2
③1.10W
1
②0.82W
①0.50W
0
0
25
50
75
85
100
125
150
Ambient temperature:Ta [℃]
Fig.24 Thermal derating curve
(HTSOP-J8)
Ex.)VCC=5V, VOUT=1.1V, RONP=0.145Ω, RONN=0.08Ω
IOUT=3A, for example,
D=VOUT/VCC=1.1/5=0.22
RON=0.22×0.145+(1-0.22)×0.08
=0.0319+0.0624
=0.0943[Ω]
P=32×0.0943=0.8487[W]
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater.
With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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9/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Selection of components externally connected
1. Selection of inductor (L)
The inductance significantly depends on output ripple current.
As seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
IL
ΔIL
VCC
ΔIL=
IL
(VCC-VOUT)×VOUT
L×VCC×f
[A]・・・(1)
Appropriate ripple current at output should be 20% more or less of the
maximum output current.
VOUT
L
ΔIL=0.2×IOUTmax. [A]・・・(2)
Co
(VCC-VOUT)×VOUT
[H]・・・(3)
ΔIL×VCC×f
(ΔIL: Output ripple current, and f: Switching frequency)
L=
Fig.25 Output ripple current
*Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases
efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its
current rating.
If VCC=5V, VOUT=1.1V, f=1MHz, ΔIL=0.2×3A=0.6A, for example,(BD8963EFJ)
L=
(5-1.1)×1.1
0.6×5×1M
=1.43µ → 1.5[µH]
*Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better
efficiency.
2. Selection of output capacitor (CO)
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
VCC
Output ripple voltage is determined by the equation (4)：
VOUT
L
ΔVOUT=ΔIL×ESR [V]・・・(4)
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
ESR
Co
*Rating of the capacitor should be determined allowing sufficient margin against
output voltage. A 10μF to 100μF ceramic capacitor is recommended.
Less ESR allows reduction in output ripple voltage.
Fig.26 Output capacitor
3. Selection of input capacitor (Cin)
VCC
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage. The
ripple current IRMS is given by the equation (5):
Cin
VOUT
L
Co
IRMS=IOUT×
√VOUT(VCC-VOUT)
VCC
< Worst case > IRMS(max.)
When Vcc is twice the VOUT, IRMS=
Fig.27 Input capacitor
[A]・・・(5)
IOUT
2
If VCC=5V, VOUT=1.1V, and IOUTmax.= 3A, (BD8963EFJ)
IRMS=3×
√1.1×(5-1.1)
5
=1.24[ARMS]
A low ESR 10µF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
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10/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
4. Determination of RCOMP, CCOMP that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.)
1
2π×RO×CO
1
fz(ESR)=
2π×ESR×CO
fp=
A
fp(Max.)
Gain
[dB]
0
fz(ESR)
IOUTMin.
Phase
[deg]
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
IOUTMax.
0
-90
fp(Min.)=
1
[Hz]←with lighter load
2π×ROMax.×CO
fp(Max.)=
1
2π×ROMin.×CO
Fig.28 Open loop gain characteristics
A
fz(Amp.)
[Hz] ←with heavier load
Zero at power amplifier
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This is
because when the capacitance is doubled, the capacitor ESR
reduces to half.)
Gain
[dB]
0
0
Phase
[deg]
-90
fz(Amp.)=
1
2π×RCOMP×CCOMP
Fig.29 Error amp phase compensation characteristics
Cin
VCC
EN
VOUT
VCC
L
SW
COMP
VOUT
ESR
ADJ
GND
RO
CO
RCOMP
CCOMP
Fig.30 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.)
1
2π×RCOMP×CCOMP
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=
1
2π×ROMax.×CO
11/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
5. Determination of output voltage
The output voltage VOUT is determined by the equation (6):
VOUT=(R2/R1+1)×VADJ・・・(6) VADJ: Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
5
L
Output
6
SW
Co
R2
8
Adjustable output voltage range : 1.0V ~ 2.5V
ADJ
R1
Fig.31 Determination of output voltage
Use 1 kΩ ~ 100 kΩ resistor for R1. If a resistor of the resistance higher than 100 kΩ is used, check the assembled set
carefully for ripple voltage etc.
4.7
INPUT VOLTAGE : VCC[V]
The lower limit of input voltage depends on the output voltage.
Basically, it is recommended to use in the condition :
VCCmin = VOUT+2.25V.
Fig.32. shows the necessary output current value at the lower limit of
input voltage. (DCR of inductor : 0.05Ω)
This data is the characteristic value, so it’ doesn’t guarantee the
operation range,
Vo=2.5V
4.2
3.7
Vo=2.0V
3.2
Vo=1.5V
Vo=1.8V
2.7
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT : IOUT[A]
Fig.32 minimum input voltage in each output voltage
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12/17
2010.06 - Rev.A
BD8963EFJ
●BD8963EFJ
Technical Note
Cautions on PC Board layout
①
Vout
VCC
L1
① 5
SW
VCC
SW
EN
N.C
GND
6
②,④
7
R2
COMP
ADJ
①,③
3
C3
2
①,③
②,④
1
R3
C2
①,③
8
4
⑥
R1
C1
⑤
Fig.33 Layout diagram
①To avoid conduction loss, please keep Black thick line as short and thick as possible.
②Don't close to switching current loop.
③Close to IC pin as possible.
④Keep PCB trace as short as possible.
⑤Use single point ground structure to connect with Pin2.
⑥Close to C2 as possible.
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13/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
Top Silkscreen Overlay
Top Layer
Middle Layer
Bottom Layer
Bottom Silkscreen Overlay
Fig.34 Reference PCB Layout Pattern
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© 2010 ROHM Co., Ltd. All rights reserved.
14/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Recommended components Lists on above application
Symbol
Part
Value
Manufacturer
L
Coil
1.5µH
TDK
CIN
Ceramic capacitor
CO
Ceramic capacitor
CCOMP
Ceramic capacitor
RCOMP
Resistance
Series
VLC6045T-1R5N
Vcc-VOUT>3V
10µF
Kyocera
CM316X5R106M10A
Vcc-VOUT<3V
22µF
Kyocera
CM32X5R226M10A
Kyocera
CM316X5R106M10A
10µF
VOUT=1.0V
330pF
Murata
GRM18 Series
VOUT=1.1V
330pF
Murata
GRM18 Series
VOUT=1.2V
330pF
Murata
GRM18 Series
VOUT=1.5V
390pF
Murata
GRM18 Series
VOUT=1.8V
390pF
Murata
GRM18 Series
VOUT=2.5V
390pF
Murata
GRM18 Series
VOUT=1.0V
2kΩ
Rohm
MCR03 Series
VOUT=1.1V
2kΩ
Rohm
MCR03 Series
VOUT=1.2V
2.4kΩ
Rohm
MCR03 Series
VOUT=1.5V
2.4kΩ
Rohm
MCR03 Series
VOUT=1.8V
3.6kΩ
Rohm
MCR03 Series
VOUT=2.5V
5.6kΩ
Rohm
MCR03 Series
* The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit
characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to
accommodate variations between external devices and this IC when employing the depicted circuit with other circuit
constants modified. Both static and transient characteristics should be considered in establishing these margins.
●I/O equivalence circuit
【BD8963EFJ】
・SW pin
・EN pin
VCC
VCC
VCC
EN
SW
・COMP pin
・ADJ pin
VCC
ADJ
COMP
Fig.35 I/O equivalence circuit
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© 2010 ROHM Co., Ltd. All rights reserved.
15/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Notes for use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4. Operation in Strong electromagnetic field
Be noted that using the IC in the strong electromagnetic radiation can cause operation failures.
5. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
6. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
7. Input to IC terminals
+
This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the
N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 36.
○P-N junction works as a parasitic diode if the following relationship is satisfied;
GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Resistor
Transistor (NPN)
Pin A
Pin B
C
B
Pin B
E
Pin A
N
P+
N
P+
P
N
N
P substrate
Parasitic element
GND
P+
Parasitic
element
B
N
P+
P
N
C
E
P substrate
Parasitic element
GND
GND
GND
Parasitic
element
Other adjacent elements
Fig.36 Simplified structure of monorisic IC
8. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
9. Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Especially, in case output
voltage is set 1.6V or more, note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output
voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit
protection will be activated and output will be latched OFF. When using an inductor over 0.1Ω, be careful to ensure
adequate margins for variation between external devices and this IC, including transient as well as static characteristics.
Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within operation range.
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16/17
2010.06 - Rev.A
BD8963EFJ
Technical Note
●Ordering part number
B
D
8
Part No.
9
6
3
Part No.
8963
E
F
J
-
Package
EFJ : HTSOP-J8
E
2
Packaging and forming specification
E2: Embossed tape and reel
(63: Adjustable (1 ~ 2.5V))
HTSOP-J8
<Tape and Reel information>
+6°
4°
−4°
(2.4)
3.9±0.1
6.0±0.2
8 7 6 5
1
1.05±0.2
(3.2)
0.65±0.15
4.9±0.1
(MAX 5.25 include BURR)
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
2 3 4
1PIN MARK
+0.05
0.17 -0.03
1.0MAX
0.545
S
0.08±0.08
0.85±0.05
1.27
+0.05
0.42 -0.04
0.08
M
0.08 S
1pin
Reel
(Unit : mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
17/17
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.06 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
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obtain a license or permit under the Law.
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More detail product informations and catalogs are available, please contact us.
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R1010A