GS820H32AT/Q-150/138/133/117/100/66 64K x 32 2M Synchronous Burst SRAM TQFP, QFP Commercial Temp Industrial Temp Features Flow Through / Pipeline Reads • FT pin for user configurable flow through or pipelined operation. • Single Cycle Deselect (SCD) Operation. • High Output Drive current. • 3.3V +10%/-5% Core power supply • 2.5V or 3.3V I/O supply. • LBO pin for linear or interleaved burst mode. • Internal input resistors on mode pins allow floating mode pins. • Default to Interleaved Pipelined Mode. • Byte write (BW) and/or global write (GW) operation. • Common data inputs and data outputs. • Clock Control, registered, address, data, and control. • Internal Self-Timed Write cycle. • Automatic power-down for portable applications. • JEDEC standard 100-lead TQFP or QFP package. -150 Pipeline tCycle 6.6ns 3-1-1-1 tKQ 3.8ns IDD 270mA Flow tCycle 10.5ns Through tKQ 9ns 2-1-1-1 IDD 170mA 150Mhz - 66Mhz 9ns - 18ns 3.3V VDD 3.3V & 2.5V I/O -138 -133 -117 -100 -66 7.25ns 7.5ns 8.5ns 10ns 12.5ns 4ns 4ns 4.5 5ns 6ns 245mA 240mA 210mA 180mA 150mA 15ns 15ns 15ns 15ns 20ns 9.7ns 10ns 11ns 12ns 18ns 120mA 120mA 120mA 120mA 95mA The function of the Data Output register can be controlled by the user via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FPBGA). Holding the FT mode pin/bump low, places the RAM in Flow through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined Mode, activating the rising edge triggered Data Output Register. Pipelined Reads The GS820H32A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages Functional Description Applications The GS820H32A is a 2,097,152 bit high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS820H32A operates on a 3.3V power supply and all inputs/ outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit. Controls Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive edge triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Rev: 1.04 3/2000 1/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Rev: 1.04 3/2000 2/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC NC LBO A5 A4 VSS DQ C6 DQ C5 DQ C4 DQ C3 VSS VDDQ DQ C2 DQ C1 FT VDD NC VSS DQ D1 DQ D2 VDDQ VSS DQ D3 DQ D4 DQ D5 DQ D6 VSS VDDQ DQ D7 DQ D8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 64K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 NC DQ C8 DQ C7 VDDQ CK GW BW G ADSC ADSP ADV A8 A9 A6 A7 E1 E2 BD BC BB BA E3 VDD VSS GS820H32A 100 Pin TQFP and QFP Pinout © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 TQFP Pin Description Pin Location Symbol Type Description 37, 36 A0, A1 I Address field LSB’s and Address Counter preset Inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 A2-15 I Address Inputs 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79 2, 3, 6, 7, 8, 9, 12, 13 18, 19, 22, 23, 24, 25, 28, 29 DQ A1-DQA8 DQ B1-DQB8 DQC1-DQC8 DQD1-DQD8 I/O Data Input and Output pins. 16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30 NC 87 BW I Byte Write. Writes all enabled bytes. Active Low. 93, 94 B A, B B I Byte Write Enable for DQA, DQB Data I/O’s. Active Low. 95, 96 BC, BD I Byte Write Enable for DQC, DQD Data I/O’s. Active Low. 89 CK I Clock Input Signal. Active High. 88 GW I Global Write Enable. Writes all bytes. Active Low. 98, 92 E1, E3 I Chip Enable. Active Low. 97 E2 I Chip Enable. Active High. 86 G I Output Enable. Active Low. 83 ADV I Burst address counter advance enable. Active Low. 84, 85 ADSP, ADSC I Address Strobe (Processor, Cache Controller). Active Low. 64 ZZ I Sleep Mode control. Active High. 14 FT I Flow Through or Pipeline mode. Active Low. 31 LBO I Linear Burst Order mode. Active Low. 15, 41, 65, 91 VDD I Core power supply. 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS I I/O and Core Ground. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ I Output driver power supply. No Connect H Rev: 1.04 3/2000 3/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 GS820H32A Block Diagram Register A0-An D Q A0 A0 D0 Q0 A1 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 32 Q BB 32 4 Register D Q D Q D Q Register D Q Register Register BC BD Register D Q Register E1 E2 E3 D Q Register D Q FT G ZZ Rev: 1.04 3/2000 Power Down DQx1-DQx8 Control 4/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Mode Pin Functions Mode Name Pin Name State Burst Order Control LBO Output Register Control FT Power Down Control ZZ Function L Linear Burst H or NC Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There are pull up devices on LBO and FT pins and a pull down device on and ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Interleaved Burst Sequence Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 3rd address 10 11 4th address 11 00 A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 00 2nd address 01 00 11 10 00 01 3rd address 10 11 00 01 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte A H L L H H H 2, 3 Write byte B H L H L H H 2, 3 Write byte C H L H H L H 2, 3, 4 Write byte D H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Note: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. Rev: 1.04 3/2000 5/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Synchronous Truth Table Operation State Address Used Diagram Key5 E1 E2 ADSP ADSC ADV W3 DQ4 Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D Note: 1. X = Don’t Care, H = High, L = Low. 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.04 3/2000 6/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR W X CR R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.04 3/2000 7/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.04 3/2000 8/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins -0.5 to 4.6 V VDDQ Voltage in VDDQ Pins -0.5 to VDD V VCK Voltage on Clock Input Pin -0.5 to 6 V VI/O Voltage on I/O Pins -0.5 to VDDQ+0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins -0.5 to VDD+0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/- 20 mA Output Current on Any I/O Pin +/- 20 mA 1.5 W IOUT PD Package Power Dissipation TSTG Storage Temperature -55 to 125 oC TBIAS Temperature Under Bias -55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Notes Supply Voltage VDD 3.135 3.3 3.6 V I/O Supply Voltage VDDQ 2.375 2.5 VDD V 1 Input High Voltage VIH 1.7 --- VDD+0.3 V 2 Input Low Voltage VIL -0.3 --- 0.8 V 2 Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 3 Ambient Temperature (Industrial Range Versions) TA -40 25 85 °C 3 Note: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O) and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be -2V > Vi < V DD+2V with a pulse width not to exceed 20% tKC. Rev: 1.04 3/2000 9/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD+-2.0V VSS 50% 50% VDD VSS-2.0V 20% tKC VIL Capacitance (TA=25oC, f=1MHZ, VDD=3.3V) Parameter Symbol Test conditions Typ. Max. Unit Control Input Capacitance CI VDD=3.3V 3 4 pF Input Capacitance CIN VIN=0V 4 5 pF COUT VOUT=0V 6 7 pF Output Capacitance Note: This parameter is sample tested. Package Thermal Characteristics Rating Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Layer Board Symbol TQFP Max QFP Max Unit Notes single RΘJA 40 TBD °C/W 1,2,4 four RΘJA 24 TBD °C/W 1,2,4 RΘJC 9 TBD °C/W 3,4 Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87. 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1. 4. For x18 configuration, consult factory. Rev: 1.04 3/2000 10/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 AC Test Conditions Parameter Conditions Input high level 2.3V Input low level 0.2V Input slew rate 1V/ns Input reference level 1.25V Output reference level 1.25V Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ. 4. Device is deselected as defined by the Truth Table. Output Load 2 Output Load 1 DQ 2.5V 225Ω DQ 30pF* 50Ω 5pF* VT=1.25V 225Ω * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max IIL VIN = 0 to VDD -1uA 1uA ZZ Input Current IINZZ VDD ≥ VIN ≥ VIH 0V ≤ VIN ≤ VIH -1uA -1uA 1uA 300uA Mode Pin Input Current IINM VDD ≥ VIN ≥ VIL 0V ≤ VIN ≤ VIL -300uA -1uA 1uA 1uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD -1uA 1uA Output High Voltage VOH IOH = - 8mA, VDDQ=2.375V 1.7V Output High Voltage VOH IOH = -8mA, VDDQ=3.135V 2.4V Output Low Voltage VOL IOL = 8mA Input Leakage Current (except mode pins) Rev: 1.04 3/2000 0.4V 11/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Operating Currents -150 -138 -133 Parameter Test Conditions Symbol 0 to 70°C -40 to 85°C 0 to 70°C -40 to 85°C 0 to 70°C -40 to 85°C Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open IDD Pipeline 270mA 275mA 245mA 250mA 240mA 245mA IDD Flow-Thru 170mA 175mA 120mA 125mA 120mA 125mA Standby Current ZZ ≥ VDD - 0.2V ISB Flow-Thru 10mA 15mA 10mA 15mA 10mA 15mA Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL IDD Pipeline 90mA 95mA 80mA 85mA 80mA 85mA IDD Flow-Thru 45mA 50mA 40mA 45mA 40mA 45mA Operating Currents -117 -100 -66 Parameter Test Conditions Symbol 0 to 70°C -40 to 85°C 0 to 70°C -40 to 85°C 0 to 70°C -40 to 85°C Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open IDD Pipeline 210mA 215mA 180mA 185mA 150mA 155mA IDD Flow-Thru 120mA 125mA 120mA 125mA 95mA 100mA Standby Current ZZ ≥ VDD - 0.2V ISB Flow-Thru 10mA 15mA 10mA 15mA 10mA 15mA Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL IDD Pipeline 70mA 75mA 60mA 65mA 50mA 55mA IDD Flow-Thru 40mA 45mA 40mA 45mA 40mA 45mA Rev: 1.04 3/2000 12/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 AC Electrical Characteristics Pipeline FlowThru Parameter Symbol Clock Cycle Time -150 -138 -133 -117 -100 -66 Max Min Max Unit Min Max Min Max Min Max Min Max Min tKC 6.6 --- 7.25 --- 7.5 --- 8.5 --- 10 Clock to Output Valid tKQ --- 3.8 --- 4 --- 4 --- 4.5 Clock to Output Invalid tKQX 1.5 --- 2 --- 2 --- 2 --- 2 2 ns Clock to Output in Low-Z tLZ 1 1.5 --- 2 --- 2 --- 2 --- 2 2 ns Clock Cycle Time tKC 10.5 --- 15 --- 15 --- 15 --- 15 20 ns Clock to Output Valid tKQ --- 9.0 --- 9.7 --- 10 --- 11 Clock to Output Invalid tKQX 3 --- 3 --- 3 --- 3 --- 3 3 ns Clock to Output in Low-Z tLZ1 3 --- 3 --- 3 --- 3 --- 3 3 ns Clock HIGH Time tKH 1.8 --- 1.9 --- 1.9 --- 2 --- 3 4 ns Clock LOW Time tKL 1.8 --- 1.9 --- 1.9 --- 2 --- 3 4 ns Clock to Output in High-Z tHZ1 1.5 3.8 1.5 4 1.5 4 1.5 4 5 6 ns G to Output Valid tOE --- 3.8 --- 4 --- 4 --- 4 5 6 ns G to output in Low-Z tOLZ1 0 --- 0 --- 0 --- 0 --- G to output in High-Z tOHZ1 --- 4 --- 4 --- 4 --- 4 Setup time tS 1.7 --- 2 --- 2 --- 2 --- 2 2 ns Hold time tH 0.5 --- 0.5 --- 0.5 --- 0.5 --- 0.5 0.5 ns ZZ setup time tZZS2 5 --- 5 --- 5 --- 5 --- 5 5 ns ZZ hold time tZZH2 1 --- 1 --- 1 --- 1 --- 1 1 ns ZZ recovery tZZR 20 --- 20 --- 20 --- 20 --- 20 20 ns 12.5 5 6 12 0 ns 18 0 5 ns ns ns 6 ns Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.04 3/2000 13/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Write Cycle Timing Single Write Burst Write Deselected Write CK tS tH tKH tKL tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH A0-An ADV must be inactive for ADSP Write WR2 WR1 WR3 tS tH GW tS tH BW tS tH BA - BD WR1 WR1 WR2 tS tH WR3 WR3 E1 masks ADSP E1 tS tH Deselected with E2 E2 tS tH E2 and E3 only sampled with ADSP or ADSC E3 G tS tH DQA - DQD Rev: 1.04 3/2000 Hi-Z Write specified byte for 2A and all bytes for 2B, 2C& 2D D1A D2A D2B D2C D2D 14/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D3A © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Flow Through Read Cycle Timing Single Read Burst Read tKL CK tKH tS tH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0-An RD1 RD2 RD3 tS tH tS tH GW BW BA - BD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E 2 E2 tS tH E3 tOE tOHZ G tKQX tOLZ DQA-DQD Q1 A Hi-Z Q2A tKQX Q2B Q2C Q2D Q3A tLZ tHZ tKQ Rev: 1.04 3/2000 15/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Flow Through Read-Write Cycle Timing Single Write Single Read Burst Read CK tS tH tKC tKH tKL ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0-An RD1 WR1 RD2 tS tH GW tH tS BW tS tH BA - BD WR1 tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 E3 tOE tOHZ G tS tKQ DQA - DQD Hi-Z Q1A tH D1A Q2A Q2B Q2C Q2D Q2A Burst wrap around to it’s initial state Rev: 1.04 3/2000 16/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Pipelined SCD Read Cycle Timing Single Read Burst Read CK tKH tS tH tKL tKC ADSP ADSP is blocked by E1 inactive tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH An RD2 RD1 RD3 tS tH tS tH GW BW BWA - BWD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E 2 E2 tS tH E3 tOE G DQA - DQD tOHZ Hi-Z tKQX tKQX tOLZ Q1A Q2A Q2B Q2C Q2D Q3A tLZ tHZ tKQ Rev: 1.04 3/2000 17/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Pipelined SCD Read - Write Cycle Timing Single Write Single Read Burst Read tKL CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0-An WR1 RD1 RD2 tS tH GW tS tH BW tS tH BA - BWD WR1 tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 E3 tOE tOHZ G DQa - DQd Rev: 1.04 3/2000 Hi-Z tS tH tKQ Q1A D1A Q2A 18/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q2B Q2C Q2D © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 CK tS tH tKC tKH tKL ADSP ADSC tZZS ZZ ~ ~ ~ ~ ~ ~ ~~ ~ ~ Sleep Mode Timing Diagram tZZH tZZR Snooze Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 1.04 3/2000 19/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 GS 820H32A Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 VDDQ I Out (mA) I Out 0.0 VOut -20.0 VSS -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Down) VDDQ - V Out (Pull Up) 3.6V PD HD Rev: 1.04 3/2000 3.3V PD HD 3.1V PD HD 3.1V PU HD 3.3V PU HD 20/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 3.6V PU HD © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 TQFP and QFP Package Drawing θ L c Pin 1 L1 D D1 e b A1 A2 Y E1 E Symbol Description Min. TQFP Nom. A1 Standoff 0.05 0.10 0.15 0.25 0.35 0.45 A2 Body Thickness 1.35 1.40 1.45 2.55 2.72 2.90 b Lead Width 0.20 0.30 0.40 0.20 0.30 0.40 c Lead Thickness 0.09 0.20 0.10 0.15 0.20 D Terminal Dimension 21.9 22.0 22.1 22.95 23.2 23.45 D1 Package Body 19.9 20.0 20.1 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 17.0 17.2 17.4 E1 Package Body 13.9 14.0 14.1 13.9 14.0 14.1 e Lead Pitch L Foot Length L1 Lead Length Y Coplanarity θ Lead Angle Max Min. QFP Nom. Max 0.65 0.45 0.60 0.65 0.75 .60 1.00 0.80 1.60 0.10 0° 1.00 7° 0.10 0° 7° Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion Rev: 1.04 3/2000 21/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Speed2 T A (Mhz/ 3 ns) Org Part Number1 Type Package 64K x 32 GS820H32AT-150 Pipeline/Flow Through TQFP 150/9 C 64K x 32 GS820H32A2T-138 Pipeline/Flow Through TQFP 138/9.7 C 64K x 32 GS820H32AT-133 Pipeline/Flow Through TQFP 133/10 C 64K x 32 GS820H32AT-4 Pipeline/Flow Through TQFP 117/11 C 64K x 32 GS820H32AT-5 Pipeline/Flow Through TQFP 100/12 C 64K x 32 GS820H32AT-6 Pipeline/Flow Through TQFP 66/18 C 64K x 32 GS820H32AT-150I Pipeline/Flow Through TQFP 150/9 I 64K x 32 GS820H32AT-138I Pipeline/Flow Through TQFP 138/9.7 I 64K x 32 GS820H32AT-133I Pipeline/Flow Through TQFP 133/10 I 64K x 32 GS820H32AT-4I Pipeline/Flow Through TQFP 117/11 I 64K x 32 GS820H32AT-5I Pipeline/Flow Through TQFP 100/12 I 64K x 32 GS820H32AT-6I Pipeline/Flow Through TQFP 66/18 I 64K x 32 GS820H32AQ-150 Pipeline/Flow Through QFP 150/9 C 64K x 32 GS820H32AQ-138 Pipeline/Flow Through QFP 138/9.7 C 64K x 32 GS820H32AQ-133 Pipeline/Flow Through QFP 133/10 C 64K x 32 GS820H32AQ-4 Pipeline/Flow Through QFP 117/11 C 64K x 32 GS820H32AQ-5 Pipeline/Flow Through QFP 100/12 C 64K x 32 GS820H32AQ-6 Pipeline/Flow Through QFP 66/18 C 64K x 32 GS820H32AQ-150I Pipeline/Flow Through QFP 150/9 I 64K x 32 GS820H32AQ-138I Pipeline/Flow Through QFP 138/9.7 I 64K x 32 GS820H32AQ-133I Pipeline/Flow Through QFP 133/10 I 64K x 32 GS820H32AQ-4I Pipeline/Flow Through QFP 117/11 I 64K x 32 GS820H32AQ-5I Pipeline/Flow Through QFP 100/12 I 64K x 32 GS820H32AQ-6I Pipeline/Flow Through QFP 66/18 I Status Not Available Not Available Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS820H32AT-100IT. 2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline / Flow through mode selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings. Rev: 1.04 3/2000 22/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E GS820H32AT/Q-150/138/133/117/100/66 Revision History DS/DateRev. Code: Old; New GS82032 Rev 1.03 2/ 2000D;GS820321.04 3/2000E Rev: 1.04 3/2000 Types of Changes Format or Content Content Revisions • First Release of A version. Added “A” Version to 82032T/Q, 820E32TQ, and 820H32TQ 23/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2000, Giga Semiconductor, Inc. E