CML Semiconductor Products PRODUCT INFORMATION FX623 Call Progress Tone Decoder Publication D/623/3 July 1994 Provisional Issue Features Measures Call Progress Tone Frequencies [‘Busy’, ‘Dial’, ‘Fax-Tone’ etc.] Custom Tone Decoder [13 Call-Progress Frequencies Recognized] Telephone, PABX, Fax and Dial-Up Modem Applications Operates to a 3.579545MHz Telephone System Clock Low-Power Requirement (600µA at 3.3 Volts TYP) for Line-Powered Applications Operates Under Simple Logic or µProcessor System Control VDD SIGNAL IN DIGITAL FILTER MEASUREMENT AND DECODE V SS LIMITER CHIP SELECT XTAL/CLOCK XTAL/CLOCK OSCILLATOR DATA CHANGE Clocks Clocks XTAL DATA OUTPUTS HOLD PURS FX623 CONTROL CIRCUITRY TIMER OUTPUT LATCHES Q0 Q1 Q2 Q3 IRQ Fig.1 Functional Block Diagram Brief Description The FX623 is a low-power decoding microcircuit that measures the frequency of telephone system call progress tones. With progress signals input from the telephone line, this single-chip product is programmed to recognize up to thirteen of the World's most commonly used call-progress frequencies, analyze signal quality and present the measured result as a 4-bit parallel data word at the tri-state Data Output. Using the parallel information from the FX623, the host system suitably configured, can recognize such call progress information as: ‘Dial’, ‘Busy’, ‘Number Unobtainable’, ‘Ringing’ and Fax/Modem system signals. This information can then be employed in telephone applications (simple or complex) to control telephone operations. The data output will require a suitable software format to analyze the frequency information from the FX623. Requiring only a single 3.0[MIN] volt power supply, the FX623 may be line-powered and will operate under simple logic or system µProcessor control using the 'Data-Change, 'Hold' and 'Chip-Select' functions. The FX623, whose small size and low power consumption makes it ideal for remote applications, requires a 3.579545MHz telephone system clock or Xtal input, is available in a 16-pin plastic DIL package. Pin Number Function FX623P 1 2 3 4 Q3: Q2: Q1: Q0: 5 VDD: Positive supply rail. A minimum supply voltage of 3.0 volts is required. Levels and voltages within this decoder are dependent upon this supply. 6 Signal In: The composite audio input. Signals to this pin should be a.c. coupled. The d.c. bias of the limiter section is set internally; this pin should not be loaded with any other circuitry. 7 No internal connection. Leave open circuit. 8 Xtal: The output of the on-chip clock oscillator inverter. 9 No internal connection. Leave open circuit. 10 Xtal/Clock: The input to the clock oscillator inverter. A 3.579545MHz Xtal or externally derived clock should be connected here (see Figure 2). 11 VSS: Negative supply rail (GND). 12 Hold: An input to control the Output Latch condition; employed in combination with the Data Change output to facilitate, if required, Interrupt and/or handshake operations with a µProcessor. With Hold placed “Low”, with a tone input, the Data Change output will be held “High” at the next data change, and the current output code is locked in the Output Latches regardless of any changes to the input signal. The output code remains as held until this input is returned “High” (see Figure 3). Whilst this input is “High” the output data, Q0 - Q3, cycles normally with the input audio. This pin has an internal 1.0MΩ pullup resistor. 13 PURS: Power-Up ReSet. To reset internal circuitry at power-up; a logic “1” level is required at this pin for a duration of at least 2.5mS after the Xtal/Clock input and full VDD levels are applied. The component configuration shown in Figure 2 is recommended; for slow-rising power supplies the time constant of components should be increased accordingly. 14 IRQ: Interrupt Request. An output for µProcessor operation; normally “High” this output is latched “Low” when an internal data change occurs if the Chip Select input is “High”. This output is reset (“High”) the when Chip Select line is taken “Low”. To permit “wire-OR” connection with other peripherals, this output has a low-impedance when “Low” and a high-impedance when “High”. 15 CS: Chip Select- A controlling function. When held “High” the Data Outputs Q0, Q1, Q2 and Q3 and the Data Change output are disabled. When taken “Low” the Data Outputs Q0, Q1, Q2 and Q3 and the Data Change output are enabled; the Interrupt Request (IRQ) is reset (“High”) when CS is taken “Low”. See Figures 3 and 4. 16 Data Change: A positive-going pulse is generated at this output when the data changes (Tone or NOTONE). New tone-data is presented to the Q0, Q1, Q2 and Q3 Data Outputs if the Hold input is set “High”. This is a tri-state output. Data Outputs: A 4-bit parallel data word, forming a HEX character representing the decoded tone frequency. This word is output after a successful decode. Table 1 details the Hex character output codes for the relevant decoded tone frequencies. Upon power-up this output is set to ‘EH’, but no Data Change pulse generated. These are tri-state outputs. 2 Application Information VDD C5 VSS Q3 1 DATA OUTPUTS A HEX Code Output representing the decoded tone frequency See Table 1 Q2 Q1 Q0 VDD SIGNAL IN COMPOSITE SIGNAL IN 2 15 3 14 4 C2 DATA CHANGE 16 FX623P C1 CS IRQ P U R S 13 HOLD 5 12 6 11 7 10 8 9 VSS XTAL/CLOCK XTAL R1 X1 R2 C3 VSS Fig.2 Recommended External Components Hex Output Code Character Q3 Q2 Q1 Q0 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Band Edges (Hz) Nominal Lower Upper Centre Edge Edge Freq. 364 488 520 580 386 412 436 463 900 1273 1350 1750 2062 386 520 580 618 412 436 463 487 1008 1325 1455 1855 2140 C4 375 500 550 600 400 425 450 475 950 1300 1400 1800 2100 Component Value R1 1.0MΩ R2 1.0MΩ C1 47.0nF C2 4.7nF C3 33.0pF C4 33.0pF C5 1.0µF X1 Tolerances R = ±10% 3.579545MHz C = ±20% frequency not guaranteed frequency not guaranteed NOTONE Table 1 Tone Decode Frequencies Timing Information With CS Low - Figure 3. After initial power-up and the Hold input inactive (High), as frequencies are input, with the Data Change output as an active (High) indicator, the data is presented at the Data Outputs. If/when the Hold input is placed active (Low), the data at the Data Outputs is frozen and the Data Change output held High at its next active excursion until the Hold input is returned High. With the Hold input held High - Figure 4. As frequencies are input a correct decode will produce an active (Low) interrupt level. This interrupt (IRQ) is serviced and reset by an active (Low) CS input. Note the ‘valid data’ period at the Data Outputs. 3 Application Information Decoder Timing VDD t PURS PURS SIGNAL IN NOTONE NOTONE Tone 1 t DE Tone 2 Tone 3 Tone ’N’ t NT t RESP OUTPUTS Q0 to Q3 ’N’ t DC t PUL DATA CHANGE t HOLD HOLD Fig.3 Timing with the Chip Select Input Held “Low”; t NORM CS and IRQ are not used VDD t PURS PURS SIGNAL IN NOTONE Tone 1 OUTPUTS Q0 - Q3 E 1 F (INTERNAL) DATA CHANGE t RIRQ IRQ t IR CS t HIZ t ACS DATA OUT Q0 - Q3 TRI-STATE Fig.4 Timing with the HOLD Input Held “High”; VALID DATA (READ DATA) CS and IRQ are used 4 TRI-STATE VALID DATA (READ DATA) Specification Absolute Maximum Ratings Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage -0.3 to 7.0V Input voltage at any pin (ref VSS = 0V) -0.3 to (VDD + 0.3V) Sink/source current (supply pins) +/- 30mA (other pins) +/- 20mA 800mW Max. Total device dissipation @ TAMB 25°C Derating 10mW/°C Storage temperature range: FX623P -40°C to +85°C (plastic) Operating Limits ...... Min. Max. Unit 3.0 5.5 V at 25°C Supply Voltage (VDD) Operating Temperature ...... -40 +85 °C All device characteristics are measured under the following conditions unless otherwise specified: VDD = 3.3V, TOP = -40 to +85 °C. Audio Level 0dB ref: = 775mVrms. Xtal/Clock Frequency = 3.579545MHz Characteristics Static Values Supply Current Input Logic “1” Input Logic “0” Output Logic “1” Output Logic “0” Impedance CS and PURS Input Hold Input Signal Input IRQ Output (logic “1”) IRQ Output (logic “0”) Q0 - Q3 & Data-Change Outputs (logic “1”) Q0 - Q3 & Data-Change Outputs (logic “0”) Q0 - Q3 & Data-Change Outputs (high Z) Dynamic Values Signal Input Range Decode Bandedge Tolerance Xtal Inverter Voltage Gain Input Impedance Output Impedance Decoder Timing - Figures 3 and 4 Power Up Reset Time tPURS Data 'E' Time tDE tRESP NOTONE to Tone Response Time Tone to NOTONE Response Time tNT Data to Data-Change Pulse Time tDC Data-Change Pulse Width tPUL Hold to Data-Change Rise Time tHOLD HOLD to Data-Change Fall Time tNORM IRQ Tone Response Time tRIRQ IRQ Reset Time tIR Data Access Time tACS CS High to Output Tri-State Time tHIZ Notes 1. 2. 3. 4. 5. See Note 1 2, 5 3 4 4 Min. Typ. Max. Unit 0.7 0.8 - 0.6 - 1.0 0.3 0.2 mA %VDD %VDD %VDD %VDD 10.0 0.5 0.1 1.0 30.0 175 0.7 175 - 100 500 2.0 500 - MΩ MΩ MΩ kΩ Ω kΩ Ω MΩ 35.0 -1.0 - 1,166 1.0 mVrms % 20.0 10.0 - - 160 V/V MΩ kΩ 2.5 31.0 0.625 63.0 - 27.0 1.25 29.0 - 50.0 60.0 1.15 150 52.0 250 250 100 ms ms ms ms ms ms µs µs ms ns ns ns This pin has an on-chip 1.0MΩ pullup resistor. An a.c. coupled sine or squarewave. See Table 1, Tone Decode Frequencies. Delay between the change of input (Tone/NOTONE) and the change at the Q0 - Q3 outputs. The signal input maximum value is determined by the formula VDD/2.83. 5 Package Outlines Handling Precautions The FX623 is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. The FX623 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. FX623P 16-pin plastic DIL (P3) NOT TO SCALE Max. Body Length Max. Body Width 20.57mm 6.60mm Ordering Information FX623P 16-pin plastic DIL (P3) CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.