FEDD56V62160E-07 Issue Date: Nov. 18, 2013 MD56V62160E 4-Bank 1,048,576-Word 16-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MD56V62160E is a 4-Bank 1,048,576-word 16-bit Synchronous dynamic RAM fabricated in LAPIS Semiconductor’s silicon-gate CMOS technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES • Silicon gate, quadruple poly-silicon CMOS, 1-transistor memory cell • 4-Bank 1,048,576-word 16-bit configuration • Single 3.3 V power supply, 0.3 V tolerances • Input : LVTTL compatible • Output : LVTTL compatible • Refresh : 4096 cycles/64 ms • Programmable data transfer mode - CAS Latency (2, 3) - Burst Length (1, 2, 4, 8, Full Page) - Data scramble (sequential, interleave) • CBR auto-refresh, Self-refresh capability • Packages: 54-pin 400 mil plastic TSOP (TypeII) (P-TSOP(2)54-400-0.80-UK6) (Product: MD56V62160E-xxTA) xx indicates speed rank. PRODUCT FAMILY Family MD56V62160E-10 Max. Frequency 100 MHz Access Time (Max.) tAC2 tAC3 6 ns 6 ns 1/33 FEDD56V62160E-07 MD56V62160E PIN CONFIGURATION (TOP VIEW) VCC 1 54 VSS DQ1 2 53 DQ16 VCCQ 3 52 VSSQ DQ2 4 51 DQ15 DQ3 5 50 DQ14 VSSQ 6 49 VCCQ DQ4 7 48 DQ13 DQ5 8 47 DQ12 VCCQ 9 46 VSSQ DQ6 10 45 DQ11 DQ7 11 44 DQ10 VSSQ 12 43 VCCQ DQ8 13 42 DQ9 VCC 14 41 VSS LDQM 15 WE 16 40 NC 39 UDQM 38 CLK CAS 17 RAS 18 37 CKE CS 19 A13 20 36 NC A12 21 34 A9 A10 22 33 A8 A0 23 A1 24 32 A7 A2 25 30 A5 A3 26 29 A4 VCC 27 28 VSS 35 A11 31 A6 54-Pin Plastic TSOP(II) (K Type) Pin Name Function Pin Name Function CLK System Clock UDQM, LDQM Data Input/ Output Mask CS Chip Select DQi Data Input/ Output CKE Clock Enable VCC Power Supply (3.3 V) A0–A11 Address VSS Ground (0 V) A12, A13 Bank Select Address VCCQ Data Output Power Supply (3.3 V) RAS Row Address Strobe VSSQ Data Output Ground (0 V) CAS Column Address Strobe NC No Connection WE Write Enable Note : The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/33 FEDD56V62160E-07 MD56V62160E PIN DESCRIPTION CLK Fetches all inputs at the “H” edge. CS Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, UDQM and LDQM. CKE Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address : RA0 – RA11 Column Address : CA0 – CA7 A13, A12 (BA0, BA1) Slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. RAS CAS Functionality depends on the combination. For details, see the function truth table. WE UDQM, LDQM Masks the read data of two clocks later when UDQM and LDQM are set “H” at the “H” edge of the clock signal. Masks the write data of the same clock when UDQM and LDQM are set “H” at the “H” edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte. DQi Data inputs/outputs are multiplexed on the same pin. 3/33 FEDD56V62160E-07 MD56V62160E ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Value Unit VIN, VOUT –0.5 to VCC+ 0.5 V VCC Supply Voltage VCC , VCCQ –0.5 to 4.6 V Storage Temperature Tstg –55 to 150 °C Power Dissipation PD* 1000 mW Short Circuit Output Current IOS 50 mA Operating Temperature Topr 0 to 70 °C Voltage on Any Pin Relative to VSS *: Ta = 25C Recommended Operating Conditions (Voltages referenced to VSS = 0 V) Parameter Symbol Min. Typ. Max. Unit VCC, VCCQ 3.0 3.3 3.6 V Input High Voltage VIH 2.0 VCC + 0.3 V Input Low Voltage VIL 0.3 0.8 V Power Supply Voltage Pin Capacitance (Vbias = 1.4 V, Ta = 25°C, f = 1 MHz) Parameter Input Capacitance (CLK) Symbol Min. Max. Unit CCLK 2.5 4 pF CIN 2.5 5 pF COUT 4 6.5 pF Input Capacitance (RAS, CAS, WE, CS, CKE, UDQM, LDQM, A0 – A13) Input/Output Capacitance (DQ1 – DQ16) 4/33 FEDD56V62160E-07 MD56V62160E DC Characteristics MD56V62160 Condition Parameter E-10 Symbol Unit Bank CKE Others Min. Max. Note Output High Voltage VOH IOH = 2.0mA 2.4 V Output Low Voltage VOL IOL = 2.0mA 0.4 V Input Leakage Current ILI 10 10 A Output Leakage Current ILO 10 10 A 70 mA 1,2 115 mA 1,2 Both ICC2 Banks CKE VIH tCC = Min. Precharge 30 mA 3 Both ICC3S Banks Active CKE VIL tCC = Min. 3 mA 2 One Bank CKE VIH tCC = Min. Active 30 mA 3 CKE VIH tCC = Min. 90 mA 1,2 One Bank t = Min. CKE VIH CC Active tRC = Min. 115 mA 2 tCC = Min. 2 mA Both ICC7 Banks CKE VIL tCC = Min. Precharge 2 mA ICC1 Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (Clock Suspension) Average Power Supply Current Both ICC1D Banks Active ICC3 (Active Standby) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power Down) tCC = Min. One Bank CKE VIH tRC = Min. Active No Burst Both ICC4 Banks Active ICC5 CKE VIH Both ICC6 Banks CKE VIL Precharge tCC = Min. tRC = Min. tRRD = Min. No Burst Notes: 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles. DC 5/33 FEDD56V62160E-07 MD56V62160E Mode Set Address Keys CAS Latency Single Write A9 BRSW A6 A5 A4 0 Normal 0 0 1 Single Write 0 Burst Type Burst Length CL A3 BT A2 A1 A0 BT = 0 BT = 1 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 1 Interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Notes: A7, A8, A10, A11, A12 and A13 should stay “L” during mode set cycle. MD56V62160E supports two methods of Power on Sequence. POWER ON SEQUENCE 1 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. POWER ON SEQUENCE 2 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Enter the mode register setting command. 5. Apply a CBR auto-refresh eight or more times. 6/33 FEDD56V62160E-07 MD56V62160E AC Characteristics (1/2) Note1, 2 MD56V62160 E-10 Parameter Symbol Unit Min. Max. Note CL = 3 tCC3 10 ns CL = 2 tCC2 10 ns CL = 3 tAC3 6 ns 3, 4 CL = 2 tAC2 6 ns 3, 4 Clock High Pulse Time tCH 3 ns 4 Clock Low Pulse Time tCL 3 ns 4 Input Setup Time tSI 3 ns Input Hold Time tHI 1 ns Output Low Impedance Time from Clock tOLZ 1 ns Output High Impedance Time from Clock tOHZ 6 ns Output Hold from Clock tOH 3 ns Random Read or Write Cycle Time tRC 70 ns RAS Precharge Time tRP 20 ns RAS Pulse Width tRAS 50 100,000 ns RAS to CAS Delay Time tRCD 20 ns Write Recovery Time tWR 10 ns RAS to CAS Bank Active Delay Time tRRD 20 ns Refresh Time tREF 64 ms Power-down Exit setup Time tPDE tSI +1CLK ns CAS to CAS Delay Time (Min.) lCCD 1 Cycle Clock Disable Time from CKE lCKE 1 Cycle Data Output High Impedance Time from UDQM, LDQM lDOZ 2 Cycle Dada Input Mask Time from UDQM, LDQM lDOD 0 Cycle Clock Cycle Time Access Time from Clock 3 7/33 FEDD56V62160E-07 MD56V62160E AC Characteristics (2/2) Note1, 2 Parameter Symbol MD56V62160 E-10 Unit Data Input Mask Time from Write Command lDWD 0 Cycle Data Output High Impedance Time from Precharge Command lROH CL Cycle Active Command Input Time from Mode Register Set Command Input (Min.) lMRD 2 Cycle Write Command Input Time from Output lOWD 2 Cycle Note Notes: 1. AC measurements assume that tT = 1 ns. 2. The reference level for timing of input signals is 1.4 V. The input signal conditions are below. VIH = 2.4 V, VIL = 0.4 V 3. Output load. Z = 50 Output 50 pF (External Load) 4. The access time is defined at 1.4 V. 5. If tT is longer than 1 ns, then the reference level for timing of input signals is VIH and VIL. 8/33 FEDD56V62160E-07 MD56V62160E TIMING CHART Read & Write Cycle (Same Bank) @CAS Latency 2, Burst Length 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tRC CKE CS tRP RAS tRCD CAS ADDR Ra Ca0 Rb Cb0 A12, A13 A10 Ra Rb tOH DQ Qa0 Qa1 Qa2 Qa3 tAC Db0 Db1 Db2 Db3 tOH WE UDQM, LDQM Row Active Read Command Precharge Command Row Active Write Command Precharge Command 9/33 FEDD56V62160E-07 MD56V62160E Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency 2, Burst Length = 4 0 1 2 3 4 tCH 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCC tCL High CKE CS tHI tSI RAS ICCD tHI tSI CAS tSI tSI ADDR Ra tSI Ca tHI A12. A13 BS A10 Ra Cb Cc BS BS tHI BS BS tHI tOHZ tAC DQ Qa Db tOLZ tOH lOWD Qc tSI tHI WE tSI UDQM, LDQM Row Active Read Command Write Command Precharge Command Read Command 10/33 FEDD56V62160E-07 MD56V62160E *Notes: 1. When CS is set “High” at a clock transition from “Low” to “High”, all inputs except CLK, CKE, UDQM and LDQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A12 and A13. A11 A12 Active, read or write 0 0 Bank A 0 1 Bank B 1 0 Bank C 1 1 Bank D 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 A12 A13 Operation 0 0 0 After the end of burst, bank A holds the idle status. 1 0 0 After the end of burst, bank A is precharged automatically. 0 0 1 After the end of burst, bank B holds the idle status. 1 0 1 After the end of burst, bank B is precharged automatically. 0 1 0 After the end of burst, bank C holds the idle status. 1 1 0 After the end of burst, bank C is precharged automatically. 0 1 1 After the end of burst, bank D holds the idle status. 1 1 1 After the end of burst, bank D is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 A12 A13 0 0 0 Bank A is precharged. 0 0 1 Bank B is precharged. 0 1 0 Bank C is precharged. 0 1 1 Bank D is precharged. 1 X X All banks are precharged. Operation 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1CLK+ tOHZ ) after UDQM, LDQM entry. 11/33 FEDD56V62160E-07 MD56V62160E Page Read & Write Cycle (Same Bank) @CAS Latency 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS Bank A Active RAS CAS ICCD ADDR Cb0 Ca0 Cc0 Cd0 Dc0 Dc1 Dd0 A12, A13 A10 DQ Qa0 Qa1 Qb0 Qb1 lOWD tWR Note 2 WE Note 1 UDQM, LDQM Read Command Read Command Write Command Precharge Command Write Command *Notes: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 12/33 FEDD56V62160E-07 MD56V62160E Burst Read & Single Write Cycle (Same Bank) @CAS Latency 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS tRCD CAS ADDR Ra Ca0 Cb0 Cc0 A12, A13 BS BS BS BS A10 Ra tOH Note 1 Qa0 Qa1 Qa2 Qa3 DQ tAC Db0 Qc0 Qc1 Qc2 Qc3 tOH WE UDQM, LDQM Row Active Read Command Write Command Read Command Precharge Command *Note: 1. If you set A9 to high during mode register set cycle, the write burst length is set to 1. 13/33 FEDD56V62160E-07 MD56V62160E Read & Write Cycle with Auto Precharge @ Burst Length 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS tRRD CAS ADDR Ra Rb Ra Rb Ca Cb A12, A13 A10 WE CAS Latency=2 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 A-Bank Precharge Start UDQM, LDQM CAS Latency=3 Qa0 Qa1 Qa2 Qa3 DQ Db0 Db1 Db2 Db3 tWR A-Bank Precharge Start UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) A Bank Read with Auto Precharge B Bank Write with Auto Precharge B Bank Precharge Start Point 14/33 FEDD56V62160E-07 MD56V62160E Bank Interleave Random Row Read Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS tRC RAS tRRD CAS ADDR RAa CAa RBb CBb RAc CAc A12, A13 A10 RAa DQ RBb QAa0 QAa1 QAa2 QAa3 RAc QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 WE UDQM, LDQM Read Command Read Command Row Active Row Active (B-Bank) (A-Bank) (A-Bank) (B-Bank) Read Command Row Active Precharge Command (A-Bank) (A-Bank) Precharge Command (A-Bank) (B-Bank) 15/33 FEDD56V62160E-07 MD56V62160E Bank Interleave Random Row Write Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc A12, A13 RBb RAa A10 RAc DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DQ DAc0 DAc1 WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Precharge Command (A-Bank) Write Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Precharge Command (B-Bank) Row Active (A-Bank) Precharge Command (A-Bank) 16/33 FEDD56V62160E-07 MD56V62160E Bank Interleave Page Read Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE Note 1 CS RAS CAS ADDR RAa CAa RBb CBb CAc CBd CAe A12, A13 A10 RBb RAa DQ QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 IROH WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Read Command (A-Bank) Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Read Command (A-Bank) *Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/33 FEDD56V62160E-07 MD56V62160E Bank Interleave Page Write Cycle @CAS Latency = 2, Burst Length 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb CAc CBd A12, A13 A10 RAa RBb DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Write Command (B-Bank) Precharge Command (Both Bank) Write Command (A-Bank) 18/33 FEDD56V62160E-07 MD56V62160E Bank Interleave Random Row Read/Write Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc A12, A13 A10 RBb RAa DQ RAc QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 WE UDQM, LDQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Row Active (A-Bank) 19/33 FEDD56V62160E-07 MD56V62160E Bank Interleave Page Read/Write Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR CAa0 CBb0 CAc0 A12, A13 A10 QAa0 QAa1 QAa2 QAa3 DQ DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 WE UDQM, LDQM Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 20/33 FEDD56V62160E-07 MD56V62160E Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK Note 1 Note 1 CKE CS RAS CAS Ra ADDR Ca Cb Cc A12, A13 Ra A10 Qa0 Qa1 DQ Note 2 Qa2 Qb0 Qb1 tOHZ tOHZ Dc0 Dc2 Note 3 WE UDQM, LDQM Row Active CLOCK Suspension Read Command Read DQM *Note: 1. 2. 3. 4. 5. Read Command Read DQM Write DQM Write Command Write DQM CLOCK Suspension When Clock Suspension is asserted, the next clock cycle is ignored. When UDQM and LDQM are asserted, the read data after two clock cycles is masked. When UDQM and LDQM are asserted, the write data in the same clock cycle is masked. When LDQM is set High, the input/output data of DQ1 – DQ8 is masked. When UDQM is set High, the input/output data of DQ9 – DQ16 is masked. 21/33 FEDD56V62160E-07 MD56V62160E Read to Write Cycle (Same Bank) @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS Note 1 RAS tRCD CAS ADDR Ra Ca0 Cb0 A12, A13 A10 Ra DQ Da0 Db0 Db1 Db2 Db3 tWR WE UDQM, LDQM Precharge Command Row Active Read Command Write Command *Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. UDQM, LDQM must be high at least 3 clocks prior to the write command. 22/33 FEDD56V62160E-07 MD56V62160E Read Interruption by Precharge Command @Burst Length 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ra Ca A12, A13 A10 Ra WE CAS Latency=2 Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 DQ lROH UDQM, LDQM CAS Latency=3 Note 1 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 lROH UDQM, LDQM Row Active Read Command Precharge Command *Note: 1. If row precharge is asserted before a burst read ends, then the read data will not output after lROH equals CAS latency. 23/33 FEDD56V62160E-07 MD56V62160E Burst Stop Command @Burst Length = 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ca Cb A12, A13 A10 WE CAS Latency = 2 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 UDQM, LDQM CAS Latency = 3 DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 UDQM, LDQM Read Command Burst Stop Command Write Command Burst Stop Command 24/33 FEDD56V62160E-07 MD56V62160E Power Down Mode @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI Note 1 tPDE Note 2t tSI SI CKE tREF (min.) CS RAS CAS ADDR Ra Ca A12, A13 Ra A10 Qa0 Qa1 Qa2 DQ WE UDQM, LDQM Power-down Entry Row Active Power-down Clock Exit Suspension Entry Read Command Clock Suspension Exit Precharge Command *Note: 1. When both banks are in precharge state, and if CKE is set low, then the MD56V62160E enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (tSI + 1CLK). 25/33 FEDD56V62160E-07 MD56V62160E Self Refresh Cycle 0 1 2 CLK tRC CKE tSI CS RAS CAS ADDR Ra A12, A13 BS A10 Ra Hi-Z DQ WE UDQM, LDQM Self Refresh Entry Self Refresh Exit Row Active 26/33 FEDD56V62160E-07 MD56V62160E Mode Register Set Cycle 0 1 2 Auto Refresh Cycle 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 CLK High CKE High CS lMRD tRC RAS CAS ADDR Key Ra Hi - Z DQ Hi - Z WE UDQM, LDQM MRS New Command Auto Refresh Auto Refresh 27/33 FEDD56V62160E-07 MD56V62160E FUNCTION TRUTH TABLE (Table 1) (1/2) Current 1 State CS Idle H X X X X X NOP L H H H X X NOP L H H L BA X L H L X BA CA ILLEGAL 2 ILLEGAL 2 L L H H BA RA L L H L BA A10 L L L H X X L L L L L OP Code Row Active Read Write Read with Auto Precharge Write with Auto Precharge RAS CAS WE BA ADDR Action Row Active NOP 4 Auto-Refresh or Self-Refresh 5 Mode Register Write H X X X X X NOP L H H X X X NOP L H L H BA CA, A10 Read L H L L BA CA, A10 Write L L H H BA RA L L H L BA A10 L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L X X Term Burst --> Row Active L H L H BA CA, A10 L H L L BA CA, A10 L L H H BA RA L L H L BA A10 L L L X X X ILLEGAL H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L X X Term Burst --> Row Active L H L H BA CA, A10 L H L L BA CA, A10 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 Precharge Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 ILLEGAL 2 Term Burst, execute Row Precharge Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 L L L X X X Term Burst, execute Row Precharge 3 ILLEGAL H X X X X X NOP (Continue Burst to End and enter Row Precharge) L H H H X X L H H L BA X NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 L H L H BA CA, A10 L H L L X X L L H X BA RA, A10 ILLEGAL 2 ILLEGAL ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End and enter Row Precharge) L H H H X X L H H L BA X NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 28/33 FEDD56V62160E-07 MD56V62160E FUNCTION TRUTH TABLE (Table 1) (2/2) Current 1 State CS RAS CAS WE BA ADDR Write with Auto Precharge L H L L X X L L H X BA RA, A10 Precharge Write Recovery Row Active Refresh Mode Register Access Action ILLEGAL L L L X X X H X X X X X ILLEGAL 2 ILLEGAL NOP --> Idle after tRP L H H H X X NOP --> Idle after tRP L H H L BA X L H L X BA CA ILLEGAL 2 ILLEGAL 2 L L H H BA RA L L H L BA A10 ILLEGAL 2 NOP 4 L L L X X X H X X X X X ILLEGAL NOP L H H H X X NOP L H H L BA X L H L X BA CA ILLEGAL 2 ILLEGAL 2 L L H H BA RA L L H L BA A10 L L L X X X ILLEGAL 2 ILLEGAL 2 H X X X X X ILLEGAL NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L BA X L H L X BA CA ILLEGAL 2 ILLEGAL 2 L L H H BA RA L L H L BA A10 ILLEGAL 2 ILLEGAL 2 L L L X X X H X X X X X ILLEGAL NOP --> Idle after tRC L H H X X X NOP --> Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL ILLEGAL L L L X X X H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL ABBREVIATIONS RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge NOP = No OPeration command Notes : 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 29/33 FEDD56V62160E-07 MD56V62160E FUNCTION TRUTH TABLE for CKE (Table 2) CKEn CS RAS CAS WE ADDR H X X X X X X INVALID L H H X X X X Exit Self Refresh --> ABI L H L H H H X Exit Self Refresh --> ABI Current State (n) CKEn-1 Self Refresh 6 Power Down 6 All Banks Idle 7 (ABI) Any State Other than Listed Above Action L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL 6 L L X X X X X NOP (Continue power down mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL L L X X X X X NOP H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enable Clock of Next Cycle L L X X X X X Continue Clock Suspension *Notes : 6. If the minimum set-up time tPDE is satisfied when CKE transition from “L” to “H”, CKE operates asynchronously so that a command can be input in the same internal clock cycle. 7. Power-down and self-refresh can be entered only when all the banks are in an idle state. 30/33 FEDD56V62160E-07 MD56V62160E PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 31/33 FEDD56V62160E-07 MD56V62160E REVISION HISTORY Page Previous Current Edition Edition Document No. Date FEDD56V62160E-01 Feb. 4, 2002 – – First edition FEDD56V62160E-02 Feb. 22, 2002 8 8 Change tRAS and tRC Specification FEDD56V62160E-03 Mar. 18, 2002 1, 7, 8, 15, 24, 25 1, 7, 8, 15, 24, 25 FEDD56V62160E-04 Oct. 15, 2011 – – Company name and Logo changed. FEDD56V62160E-05 Feb. 13, 2012 4 32 – – Deleted BLOCK DIAGRAM Deleted PACKAGE DIMENSIONS FEDD56V62160E-06 May 29, 2012 1,5,7,8 1,5,7,8 FEDD56V62160E-07 Nov. 18, 2013 1 – 1 31 Description Delete “CAS latency =1” Deleted Speed rank 7 Added package code Added PACKAGE DIMENSIONS 32/33 FEDD56V62160E-07 MD56V62160E NOTES No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. 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The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Copyright 2002 - 2013 LAPIS Semiconductor Co., Ltd. 33/33