Cypress CY2XP24ZXIT Crystal to lvpecl clock generator one lvpecl output pair Datasheet

CY2XP24
Crystal to LVPECL Clock Generator
Features
Functional Description
■
One LVPECL Output Pair
■
Selectable output frequency: 156.25 MHz or 187.5 MHz
■
External crystal frequency: 25 MHz
■
Low root mean square (RMS) phase jitter at 156.25 MHz, using
25 MHz crystal (1.875 MHz to 20 MHz): 0.33 ps (typical)
■
Pb-free 8-Pin thin shrunk small outline package (TSSOP)
Package
■
Supply voltage: 3.3 V or 2.5 V
■
Commercial and industrial temperature ranges
The CY2XP24 is a PLL (phase locked loop) based high
performance clock generator. It is optimized to generate 10 Gb
Ethernet, Fibre Channel, and other high performance clock
frequencies. It produces an output frequency that is either 6.25
times or 7.5 times the crystal frequency. It uses Cypress’s low
noise VCO technology to achieve low phase jitter, that meets
both 10 Gb Ethernet, Fibre Channel, and SATA jitter
requirements. The CY2XP24 has a crystal oscillator interface
input and one LVPECL output pair.
Logic Block Diagram
XIN
CRYSTAL
OSCILLATOR
External
Crystal
PHASE
DETECTOR
VCO
/4
CLK
CLK#
XOUT
0 = /25
1 = /30
F_SEL
Cypress Semiconductor Corporation
Document #: 001-15705 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 7, 2011
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CY2XP24
Contents
Pinouts .............................................................................. 3
Frequency Table ............................................................... 4
Absolute Maximum Conditions ....................................... 4
Operating Conditions ....................................................... 4
DC Electrical Characteristics .......................................... 4
AC Electrical Characteristics ........................................... 5
Recommended Crystal Specifications ............................ 5
Parameter Measurements ................................................ 6
Application Information ................................................... 7
Power Supply Filtering Techniques ............................. 7
Document #: 001-15705 Rev. *G
Termination for LVPECL Output .................................. 7
Crystal Input Interface ................................................. 7
Ordering Information ........................................................ 8
Ordering Code Definition ............................................. 8
Acronyms ........................................................................ 10
Document Conventions ................................................. 10
Units of Measure ....................................................... 10
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support ....................... 12
Products .................................................................... 12
PSoC Solutions ......................................................... 12
Page 2 of 12
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CY2XP24
Pinouts
Figure 1. Pin Diagram - 8 Pin TSSOP
VDD
VSS
XOUT
XIN
1
2
3
4
8
7
6
5
VDD
CLK
CLK#
F_SEL
Table 1. Pin Definitions - 8 Pin TSSOP
Pin
1, 8
Name
VDD
Type
Power
Description
3.3 V or 2.5 V power supply. All supply current flows through pin 1
2
VSS
Power
Ground
3, 4
XOUT, XIN
XTAL output and input
Parallel resonant crystal interface
5
F_SEL
CMOS input
Frequency select. When HIGH, the output frequency is 7.5 times of the
crystal frequency. When LOW, the output frequency is 6.25 times of the
crystal frequency
6,7
CLK#, CLK
LVPECL output
Differential clock output
Document #: 001-15705 Rev. *G
Page 3 of 12
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CY2XP24
Frequency Table
Inputs
PLL Multiplier Value
Output Frequency (MHz)
1
7.5
187.5
0
6.25
156.25
Crystal Frequency (MHz)
F_SEL
25
25
Absolute Maximum Conditions
Parameter
Description
Condition
Min
–
Max
Unit
VDD
Supply voltage
–0.5
4.4
V
VIN[1]
Input voltage, DC
Relative to VSS
–0.5
VDD + 0.5
V
Non operating
–65
150
C
–
135
C
–
V
TS
Temperature, vtorage
TJ
Temperature, junction
ESDHBM
ESD protection (human body model)
JEDEC STD 22-A114-B
UL–94
Flammability rating
At 1/8 in.
V–0
JA[2]
Thermal resistance, junction to ambient
0 m/s airflow
100
1 m/s airflow
91
2.5 m/s airflow
87
2000
C / W
Operating Conditions
Parameter
VDD
TA
TPU
Description
Min
Max
Unit
3.3 V supply voltage
3.135
3.465
V
2.5 V supply voltage
2.375
2.625
V
0
70
C
Ambient temperature, industrial
-40
85
C
Power-up time for all VDD to reach minimum specified voltage (ensure power ramps
are monotonic)
0.05
500
ms
Min
Typ
Max
Unit
Power supply current with output VDD = 3.465 V, FOUT = 187.5 MHz,
unterminated
output unterminated
–
–
125
V
VDD = 2.625 V, FOUT = 187.5 MHz,
output unterminated
–
–
120
V
Power supply current with output VDD = 3.465 V, FOUT = 187.5 MHz,
terminated
output terminated
–
–
150
V
VDD = 2.625V, FOUT = 187.5 MHz,
output terminated
–
–
145
V
Ambient temperature, commercial
DC Electrical Characteristics
Parameter
IDD
IDDT
Description
Test Conditions
VOH
LVPECL output high voltage
VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD –1.15
VDD – 2.0 V
–
VDD –0.75
V
VOL
LVPECL output low voltage
VDD = 3.3 V or 2.5 V, RTERM = 50  to VDD –2.0
VDD – 2.0 V
–
VDD –1.625
V
VOD1
LVPECL Peak-to-peak output
voltage swing
VDD = 3.3 V or 2.5 V, RTERM = 50  to
VDD – 2.0 V
–
1000
mV
600
Note
1. The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
Document #: 001-15705 Rev. *G
Page 4 of 12
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CY2XP24
DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VOD2
LVPECL output voltage swing
(VOH - VOL)
VDD = 2.5 V, RTERM = 50  to
VDD – 1.5 V
500
–
1000
mV
VOCM
LVPECL output common mode
voltage (VOH + VOL)/2
VDD = 2.5 V, RTERM = 50  to
VDD – 1.5 V
1.2
–
–
V
VIH
Input high voltage
0.7 x VDD
–
VDD + 0.3
V
VIL
Input low voltage
–0.3
–
0.3 x VDD
V
IIH
Input high current
F_SEL = VDD
–
–
115
µA
IIL
Input low current
F_SEL = VSS
–50
–
–
µA
CIN
[3]
CINX[3]
Input capacitance, F_SEL
–
15
–
pF
Pin capacitance, XIN & XOUT
–
4.5
–
pF
AC Electrical Characteristics[4]
Parameter
Description
Conditions
Min
Typ
Max
Unit
FOUT
Output frequency
156.25
–
187.5
MHz
TR, TF[5]
Output rise/fall time
20 % to 80 % of full swing
–
0.5
1.0
ns
RMS phase jitter (random)
156.25 MHz, (1.875 – 20 MHz), 3.3 V
–
0.33
–
ps
156.25 MHz, (12 kHz – 20 MHz), 3.3 V
–
0.6
–
ps
TJitter()
[6]
TDC[7]
Duty cycle
Measured at zero crossing point
45
–
55
%
TLOCK
Startup time
Time for CLK to reach valid frequency
measured from the time
VDD = VDD(min.)
–
–
5
ms
TLFS
Re-lock time
Time for CLK to reach valid frequency
from F_SEL pin change
–
–
1
ms
Max
Unit
Recommended Crystal Specifications[7]
Parameter
Description
Min
Mode
Mode of oscillation
Fundamental
F
Frequency
25
25
MHz
ESR
Equivalent series resistance
–
50

C0
Shunt capacitance
–
7
pF
Notes
3. Not 100% tested, guaranteed by design and characterization.
4. Characterized using an 18 pF parallel resonant crystal.
5. Refer to Figure 7 on page 7.
6. Refer to Figure 4 on page 4.
7. Refer to Figure 7 on page 7.
Document #: 001-15705 Rev. *G
Page 5 of 12
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CY2XP24
Parameter Measurements
Figure 2. 3.3 V Output Load AC Test Circuit
2V
VDD
SCOPE
Z = 50
CLK
Z = 50
CLK#
50
LVPECL
VSS
50
-1.3V +/- 0.165V
Figure 3. 2.5 V Output Load AC Test Circuit
2V
VDD
SCOPE
Z = 50
CLK
Z = 50
CLK#
50
LVPECL
VSS
50
-0.5V +/- 0.125V
Figure 4. Output DC Parameters
VA
CLK
VOD
VOCM = (V A + VB)/2
CLK#
VB
Figure 5. Output Rise and Fall Time
CLK#
CLK
80%
80%
20%
20%
TF
TR
Figure 6. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f1
RMS Jitter =
Document #: 001-15705 Rev. *G
f2
Area Under the Masked Phase Noise Plot
Page 6 of 12
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CY2XP24
Figure 7. Output Duty Cycle
CLK
TDC =
CLK#
TPW
TPERIOD
TPW
TPERIOD
Application Information
Figure 9. LVPECL Output Termination
3.3V
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter
performance, use good power supply isolation practices.
Figure 8 illustrates a typical filtering scheme. Because all current
flows through pin 1, the resistance and inductance between this
pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
Figure 8. Power Supply Filtering
3.3V
F
0.01 µF
125
CLK
CLK#
IN
Z0 = 50
84
84
Crystal Input Interface
V DD
(Pin 8)
VDD
(Pin 1)
125
Z0 = 50
10µF
The CY2XP24 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are
determined using a 25 MHz 18 pF parallel resonant crystal and
are chosen to minimize the ppm error. Note that the optimal
values for C1 and C2 depend on the parasitic trace capacitance
and are therefore layout dependent.
Figure 10. Crystal Input Interface
XIN
Termination for LVPECL Output
The CY2XP24 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3 V
operation, this data sheet specifies output levels for termination
to VDD–2.0 V. This termination voltage can also be used for VDD
= 2.5 V operation, or it can be terminated to VDD-1.5 V. Note that
it is also possible to terminate with 50 ohms to ground (VSS), but
the high and low signal levels differ from the data sheet values.
Termination resistors are best located close to the destination
device. To avoid reflections, trace characteristic impedance (Z0)
should match the termination impedance. Figure 9 shows a
standard termination scheme.
Document #: 001-15705 Rev. *G
X1
18 pF Parallel
Crystal
C1
30 pF
Device
XOUT
C2
27 pF
Page 7 of 12
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CY2XP24
Ordering Information
Part Number
Package Type
Product Flow
CY2XP24ZXC
8-Pin TSSOP
Commercial, 0 C to 70 C
CY2XP24ZXCT
8-Pin TSSOP–Tape and Reel
Commercial, 0 C to 70 C
CY2XP24ZXI
8-Pin TSSOP
Industrial, -40 C to 85 C
CY2XP24ZXIT
8-Pin TSSOP–Tape and Reel
Industrial, -40 C to 85 C
Ordering Code Definition
CY xx xxxx Z X C/I T
T = Tape and Reel
Temperature Range: C = Commercial, I = Industrial
Pb-free
Package Type
Part Identifier
Family
Company ID: CY = Cypress
Document #: 001-15705 Rev. *G
Page 8 of 12
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CY2XP24
Package Drawing and Dimensions
Figure 11. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8
51-85093 *C
Document #: 001-15705 Rev. *G
Page 9 of 12
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CY2XP24
Acronyms
Acronym
Description
CLKOUT
Clock output
CMOS
Complementary metal oxide semiconductor
DPM
Die pick map
EPROM
Erasable programmable read only memory
LVDS
Low-voltage differential signaling
LVPECL
Low voltage positive emitter coupled logic
NTSC
National television system committee
OE
Output enable
PAL
Phase alternate line
PD
Power down
PLL
Phase locked loop
PPM
Parts per million
TTL
Transistor transistor logic
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
kHz
kilohertz
k
kilohms
MHz
megahertz
M
megaohms
µA
microamperes
µs
microseconds
µV
microvolts
µVrms
microvolts root-mean-square
mA
milliamperes
mm
millimeters
ms
milliseconds
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts

ohms
Document #: 001-15705 Rev. *G
Page 10 of 12
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Document History Page
Document Title: CY2XP24 Crystal to LVPECL Clock Generator
Document Number: 001-15705
Rev.
ECN No.
Submission
Date
**
1285703
See ECN
WWZ/KVM/ New data sheet
ARI
*A
1451704
See ECN
WWZ/AESA Added I-temp devices
*B
2669117
03/05/2009
KVM/AESA Changed crystal frequency and output frequencies
Updated phase jitter value
Rise & fall times changed from 350 ps to 500 ps (typ.)
Junction temperature changed from 125C to 135C
Changed IIL and IIH values
Entered value for IDD
Removed MSL spec
Changed Data Sheet Status to Final
*C
2700242
04/30/2009
KVM/PYRS Typos: changed VCC to VDD, changed ps to MHz
Changed footnote about external power dissipation
Reformatted AC and DC tables
Changed LVPECL parameters from VPP to VOD and VOCM
Added CINX spec
Added IDD for 2.5V
Added TLOCK timing
Revised text in Application Information section
Changed recommended crystal load capacitor values
*D
2718433
06/12/2009
WWZ/HMT No change. Submit to ECN for product launch.
*E
2767308
09/22/2009
KVM
Add phase jitter spec for 12 kHz - 20 MHz integration range
Add IDD spec for unterminated outputs
Change parameter name for IDD (terminated outputs) from IDD to IDDT
Remove IDD footnote about externally dissipated current
Add footnote reference to CIN and CINX:not 100% tested
Add max limit for TR, TF: 1.0 ns
Change TLOCK max from 10 ms to 5 ms
Split out parameter TLFS from TLOCK
*F
2896121
03/19/2010
KVM
Updated Package Diagram (Figure 11)
*G
3218841
03/07/2011
BASH
Updated as per template
Added Acronyms and Units of Measure table
Added Ordering Code Definition details
Updated package diagram 51-85093 from *B to *C
Document #: 001-15705 Rev. *G
Orig. of
Change
Description of Change
Page 11 of 12
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CY2XP24
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15705 Rev. *G
Revised April 7, 2011
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