ON MMDF2C02E Power mosfet Datasheet

MMDF2C02E
Power MOSFET
2.5 Amps, 25 Volts
Complementary SO−8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a low reverse recovery time. MiniMOSt
devices are designed for use in low voltage, high speed switching
applications where power efficiency is important. Typical applications
are dc−dc converters, and power management in portable and battery
powered products such as computers, printers, cellular and cordless
phones. They can also be used for low voltage motor controls in mass
storage products such as disk drives and tape drives. The avalanche
energy is specified to eliminate the guesswork in designs where
inductive loads are switched and offer additional safety margin against
unexpected voltage transients.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, with Soft Recovery
• Avalanche Energy Specified
• Mounting Information for SO−8 Package Provided
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
25
Vdc
Gate−to−Source Voltage
VGS
± 20
Vdc
ID
3.6
2.5
18
13
Adc
TJ and
Tstg
− 55
to 150
°C
Total Power Dissipation @ TA= 25°C (Note 2)
PD
2.0
Watts
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 20 V, VGS = 10 V, Peak IL = 9.0 A,
L = 6.0 mH, RG = 25 Ω)
N−Channel
(VDD = 20 V, VGS = 10 V, Peak IL = 7.0 A,
P−Channel
L = 10 mH, RG = 25 Ω)
EAS
Thermal Resistance − Junction to Ambient
(Note 2)
RθJA
62.5
°C/W
TL
260
°C
Drain Current − Continuous N−Channel
P−Channel
− Pulsed
N−Channel
P−Channel
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering,
0.0625″ from case. Time in Solder Bath is
10 seconds.
IDM
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2.5 AMPERES, 25 VOLTS
RDS(on) = 100 mW (N−Channel)
RDS(on) = 250 mW (P−Channel)
N−Channel
D
245
D
G
G
S
S
MARKING
DIAGRAM
8
1
8
SO−8
CASE 751
STYLE 14
F2C02
ALYW
1
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
mJ
245
P−Channel
N−Source
1
8
N−Drain
N−Gate
2
7
N−Drain
P−Source
3
6
P−Drain
P−Gate
4
5
P−Drain
Top View
ORDERING INFORMATION
1. Negative signs for P−Channel device omitted for clarity.
2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with
one die operating, 10 sec. max.
Device
MMDF2C02ER2
Package
Shipping †
SO−8
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 8
1
Publication Order Number:
MMDF2C02E/D
MMDF2C02E
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Note 3)
Characteristic
Symbol
Polarity
Min
Typ
Max
−
25
−
−
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Vdc
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
IDSS
(N)
(P)
−
−
−
−
1.0
1.0
mAdc
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
−
−
−
100
nAdc
−
1.0
2.0
3.0
(N)
(P)
−
−
−
−
0.100
0.250
(N)
(P)
−
−
−
−
0.200
0.400
(N)
(P)
2.0
2.0
−
−
−
−
(N)
(P)
1.0
1.0
2.6
2.8
−
−
Ciss
(N)
(P)
−
−
380
340
532
475
Coss
(N)
(P)
−
−
235
220
329
300
Crss
(N)
(P)
−
−
55
75
110
150
td(on)
(N)
(P)
−
−
10
20
30
40
tr
(N)
(P)
−
−
35
40
70
80
td(off)
(N)
(P)
−
−
19
53
38
106
tf
(N)
(P)
−
−
25
41
50
82
td(on)
(N)
(P)
−
−
7.0
13
21
26
tr
(N)
(P)
−
−
17
29
30
58
td(off)
(N)
(P)
−
−
27
30
48
60
tf
(N)
(P)
−
−
18
28
30
56
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
VGS(th)
Drain−to−Source On−Resistance
(VGS = 10 Vdc, ID = 2.2 Adc)
(VGS = 10 Vdc, ID = 2.0 Adc)
RDS(on)
Drain−to−Source On−Resistance
(VGS = 4.5 Vdc, ID = 1.0 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)
RDS(on)
On−State Drain Current
(VDS = 5.0 Vdc, VGS = 4.5 Vdc)
ID(on)
Forward Transconductance
(VDS = 3.0 Vdc, ID = 1.5 Adc)
(VDS = 3.0 Vdc, ID = 1.0 Adc)
gFS
Vdc
Ohm
Ohm
Adc
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 4.5 Vdc, RG = 9.1 Ω)
(VDD = 10 Vdc, ID = 1.0 Adc,
VGS = 5.0 Vdc, RG = 25 Ω)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc, RG = 6.0 Ω)
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc, RG = 6.0 Ω)
3. Negative signs for P−Channel device omitted for clarity.
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
5. Switching characteristics are independent of operating junction temperature.
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2
ns
MMDF2C02E
ELECTRICAL CHARACTERISTICS − continued (TA = 25°C unless otherwise noted) (Note 6)
Characteristic
Symbol
Polarity
Min
Typ
Max
Unit
QT
(N)
(P)
−
−
10.6
10
30
15
nC
Q1
(N)
(P)
−
−
1.3
1.0
−
−
Q2
(N)
(P)
−
−
2.9
3.5
−
−
Q3
(N)
(P)
−
−
2.7
3.0
−
−
VSD
(N)
(P)
−
−
1.0
1.5
1.4
2.0
Vdc
trr
(N)
(P)
−
−
34
32
66
64
ns
ta
(N)
(P)
−
−
17
19
−
−
tb
(N)
(P)
−
−
17
12
−
−
QRR
(N)
(P)
−
−
0.025
0.035
−
−
SWITCHING CHARACTERISTICS − continued (Note 8)
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
(VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C)
Forward Voltage (Note 7)
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time
see Figure 7
(IF = IS,
dIS/dt = 100 A/ms)
6. Negative signs for P−Channel device omitted for clarity.
7. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
8. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
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3
mC
MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
P−Channel
7
VGS = 10 V
3.7 V
6
4.5 V
4.3 V
4.1 V
3.5 V
5
4
VGS = 10
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
N−Channel
3.9 V
3.3 V
4
3.1 V
3
2.9 V
2
2.7 V
2.5 V
1
0
TJ = 25°C
0
0.5
1
1.25
1.75
0.25
0.75
1.5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
4.3 V
2
4.1 V
3.9 V
1
3.7 V
3.5 V
3.3 V
0
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
4
VDS ≥ 10 V
TJ = 25°C
5
100°C
3
25°C
2
1
0
1.5
0.4
0.8
1.2
1.6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
2
Figure 1. On−Region Characteristics
7
4
TJ = 25°C
4.7 V
3
Figure 1. On−Region Characteristics
6
5V
4.5 V
0
2
7V
VDS ≥ 10 V
3
100°C
2
25°C
TJ = −55°C
1
TJ = −55°C
2
2.5
3
3.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
2.5
4
Figure 2. Transfer Characteristics
3
3.5
4
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
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4
4.5
MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
P−Channel
0.6
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
N−Channel
ID = 3.5 A
TJ = 25°C
0.5
0.4
0.3
0.2
0.1
0
2
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
0.6
ID = 1 A
TJ = 25°C
0.5
0.4
0.3
0.2
0.1
0
3
4
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.15
TJ = 25°C
VGS = 4.5
0.1
10 V
0.05
0
1
2
3
5
4
6
7
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
2.0
VGS = 10 V
ID = 3.5 A
1.5
1.0
0.5
0
25
50
75
9
10
TJ = 25°C
0.5
0.4
VGS = 4.5
0.3
0.2
10 V
0.1
0
0.5
1
1.5
2
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
−25
8
0.6
ID, DRAIN CURRENT (AMPS)
0
−50
7
6
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 3. On−Resistance versus
Gate−to−Source Voltage
0
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
VGS = 10 V
ID = 2 A
1.5
1.0
0.5
0
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
Figure 5. On−Resistance Variation
with Temperature
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5
150
MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
P−Channel
10000
100
VGS = 0 V
1000
100°C
I DSS , LEAKAGE (nA)
I DSS , LEAKAGE (nA)
VGS = 0 V
TJ = 125°C
100
25°C
10
1
5
10
15
20
TJ = 125°C
10
100°C
1
25
0
4
8
12
16
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
versus Voltage
Figure 6. Drain−to−Source Leakage Current
versus Voltage
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
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6
MMDF2C02E
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
di/dt = 300 A/μs
I S , SOURCE CURRENT
Standard Cell Density
trr
High Cell Density
trr
tb
ta
t, TIME
Figure 7. Reverse Recovery Time (trr)
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7
MMDF2C02E
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 9). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
N−Channel
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
P−Channel
100
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
10 ms
1
100 μs
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
100
10 μs
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
100 μs
1
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
100
Figure 8. Maximum Rated Forward Biased
Safe Operating Area
280
280
I pk = 9 A
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Maximum Rated Forward Biased
Safe Operating Area
240
200
160
120
80
40
0
10 μs
10 ms
0.01
0.1
100
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
25
50
75
100
125
150
I pk = 7 A
240
200
160
120
80
40
0
25
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 9. Maximum Avalanche Energy versus
Starting Junction Temperature
Figure 9. Maximum Avalanche Energy versus
Starting Junction Temperature
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8
150
MMDF2C02E
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
10
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
Normalized to θja at 10s.
Chip
0.0175 Ω
0.0710 Ω
0.2706 Ω
0.0154 F
0.0854 F
0.3074 F
0.5776 Ω
0.7086 Ω
0.01
0.01
SINGLE PULSE
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
1.0E+01
Figure 10. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 11. Diode Reverse Recovery Waveform
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9
1.7891 F
107.55 F
1.0E+02
Ambient
1.0E+03
MMDF2C02E
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE AB
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
Y
M
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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