Microchip B82559A0142A013 High-speed synchronous buck controller Datasheet

MCP19035
High-Speed Synchronous Buck Controller
Features
General Description
• Input Voltage Range: from 4.5V to 30V
• Targeted for Low Voltage Power Trains with
Output Current up to 20A
• High-Speed Voltage Mode, Analog Pulse-Width
Modulation Control
• Power Good Output
• Internal Oscillator, Reference Voltage and
Overcurrent Limit threshold for Stand-Alone
Applications.
• Fixed Switching Frequency (fSW): 300 kHz
• Integrated Synchronous MOSFET Drivers
• Multiple Dead-Time Options
• Internal Blocking Device for Bootstrap Circuit
• Integrated Current Sense Capability for Short
Circuit Protection
• Internal Overtemperature Protection
• Under Voltage Lockout (UVLO)
• Integrated Linear Voltage Regulator
• 10-LD 3 X 3 mm DFN Package
The MCP19035 is an application-optimized, highspeed synchronous buck controller that operates from
input voltage sources up to 30V. This controller
implements a voltage-mode control architecture with a
fixed switching frequency of 300 kHz. The highswitching frequency facilitates the use of smaller
passive components, including the inductor and
input/output capacitors, allowing a compact, highperformance power supply solution. The MCP19035
implements an adaptive anti-cross conduction scheme
to prevent shoot-through in the external power
MOSFETs. Further more, the MCP19035 offers
multiple dead-time options, enabling an additional
degree of optimization, allowing a higher efficiency
power supply design.
Applications
•
•
•
•
•
Point of Loads
Set-Top Boxes
DSL Cable Modems
FPGA’s/DSP’s Power Supply
PC’s Graphic/Audio Cards
The MCP19035 controller is intended to be used for
applications providing up to 20A of output currents
across a wide input voltage range, up to 30V.
The SHDN input is used to turn the device on and off.
While turned off, the current consumption is minimized.
The MCP19035 offers a Power Good feature
(PWRGD), enabling fault detection and simplifying
sequencing.
Package Types
MCP19035
3x3 DFN*
SHDN 1
10 HDRV
FB 2
COMP 3
9 PHASE
EP
11
8 BOOT
VIN 4
7 LDRV
PWRGD 5
6 +VCC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
 2012 Microchip Technology Inc.
DS22326A-page 1
MCP19035
Typical Application
+VIN
CIN
ON
MCP19035
SHDN
OFF
BOOT
Q1
CBOOT
HDRV
VIN
L
PHASE
PWRGD
C2
COMP
LDRV
FB
+VCC
Q2
COUT
GND
C3
+VOUT
CVCC
R4
R1
C1
R3
R2
DS22326A-page 2
 2012 Microchip Technology Inc.
MCP19035
1.0
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational sections of this
specification is not intended. Exposure to maximum
rating conditions for extended periods may affect
device reliability.
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VIN - VGND ........................................................ -0.3V to +30V
VBOOT................................................................ -0.3V to +36V
VHDRV, HDRV Pin................. +VPHASE -0.3V to VBOOT+0.3V
VLDRV, LDRV Pin.....................+ (VGND-0.3V) to (VCC+0.3V)
Max. Voltage on Any Pin ...........+ (VGND-0.3V) to (VCC+0.3V)
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature ................................. +150°C
ESD protection on all pins (HBM) .................................... 1 kV
ESD protection on all pins (MM) .....................................200V
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 300 kHz, CIN = 1.0 µF, TA = +25°C (for typical
values), TA = -40°C to +125°C (for minimum and maximum).
Parameters
Symbol
Min
Typ
Max
Units
Conditions
Inputs
Input Voltage Range
VIN
4.5
—
30
V
UVLO (VIN Rising)
UVLOON
4
4.2
4.4
V
UVLO (VIN Falling)
UVLOOFF
3.4
3.6
3.8
V
UVLO Hysteresis
UVLOHYST
—
600
—
mV
I(VIN)
—
6
8
mA
IIN_SHDN
—
25
50
µA
SHDN = GND.
Internal Voltage Regulator is
also disabled
VCC
4.875
5
5.125
V
6V  VIN < 30V
Output Current
IVCC-OUT
50
—
Short-Circuit
Output Current
IVCC-OUT_SC
—
—
Load Regulation
—
0.1
Line Regulation
—
Dropout Voltage
—
PSRR
Input Quiescent Current
Shutdown Current
Linear Regulator
Output Voltage
Power Supply
Rejection Ratio
mA
6.5V  VIN < 30V, Note 2
100
mA
VIN = 6V, RLOAD < 0.1
—
%
0.05
—
%
Note 1
0.75
1.3
V
IVCC_OUT = 50 mA
—
70
—
dB
f  1000 Hz,
IVCC_OUT = 50 mA
CIN = 0 µF,
CVCC-OUT = 4.7 µF, Note 1
FSW
255
300
345
kHz
See Section 4.4, Internal
Oscillator
VRAMP
0.9
1
1.1
VPP
Note 1
VREF
585
600
615
mV
Note 1
Internal Oscillator
Switching
Frequency
Ramp Signal Amplitude
Reference Voltage
Reference Voltage
Generator
Note 1:
2:
3:
Ensured by design. Not production tested.
Limited by the maximum power dissipation of the case.
Possibility to be adjusted for high volumes.
 2012 Microchip Technology Inc.
DS22326A-page 3
MCP19035
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 300 kHz, CIN = 1.0 µF, TA = +25°C (for typical
values), TA = -40°C to +125°C (for minimum and maximum).
Parameters
Symbol
Min
Typ
Max
Units
Conditions
Gain Bandwidth Product
GBP
6.5
10
—
MHz
Note 1
Open Loop Gain
AOL
70
80
—
dB
Note 1
Error Amplifier
Input Offset Voltage
VOS
-5
0.1
5
mV
Note 1
Input Bias Current
(FB Pin)
IBIAS
—
—
5
nA
Note 1
Error Amplifier
Sink Current
ISINK
—
5
—
mA
Note 1
Error Amplifier
Source Current
ISOURCE
—
5
—
mA
Note 1
Maximum Duty Cycle
DCMAX
85
—
—
%
Note 1
Minimum ON time
tON(MIN)
130
—
240
ns
6V  VIN < 30V, Note 1
tSS
—
2.6
—
ms
Logic Low-to-High
Threshold
SHDNHI
0.75
—
—
V
4.5V  VIN < 30V
Logic High-to-Low
Threshold
SHDNLO
—
—
0.4
V
4.5V  VIN < 30V
Power Good
Threshold High
PGTH-H
—
92
96
% of VREF
Power Good
Threshold Low
PGTH-LOW
88
90
—
% of VREF
Power Good
Threshold Hysteresis
PGTH-HYS
—
2
—
% of VREF
Power Good Delay
tPG-DELAY
—
150
—
us
VFB = (PGTH-HI + 100 mV) to
(PGTH-LOW – 100 mV)
Power Good Active
Time-Out Period
tPG-TIME-OUT
—
120
—
ms
VFB = (PGTH-HI – 100 mV) to
(PGTH-HI + 100 mV)
RHI-SOURCE
—
2
3.5

VBOOT – VPHASE = 4.5V,
IHDRV = 100 mA, Note 1
RHI-SINK
—
2
3.5

VBOOT – VPHASE = 4.5V,
IHDRV = 100 mA, Note 1
RLO-SOURCE
—
2
3.5

VCC = 5V, Note 1
RLO-SINK
—
1
2.5

VCC = 5V, Note 1
PWM Section
Soft Start
Soft Start Time
Shutdown
Power Good
MOSFET Drivers
High-Side Driver Pull-up
Resistance
High-Side Driver PullDown Resistance
Low-Side Driver Pull-Up
Resistance
Low-Side Driver PullDown Resistance
HDRV Rise Time
tRH
—
15
35
ns
CLOAD = 1.0 nF, Note 1
HDRV Fall Time
tFH
—
15
35
ns
CLOAD = 1.0 nF, Note 1
LDRV Rise Time
tRL
—
10
25
ns
CLOAD = 1.0 nF, Note 1
Note 1:
2:
3:
Ensured by design. Not production tested.
Limited by the maximum power dissipation of the case.
Possibility to be adjusted for high volumes.
DS22326A-page 4
 2012 Microchip Technology Inc.
MCP19035
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 300 kHz, CIN = 1.0 µF, TA = +25°C (for typical
values), TA = -40°C to +125°C (for minimum and maximum).
Parameters
Symbol
Min
Typ
Max
Units
Conditions
LDRV Fall Time
tFL
—
10
25
ns
CLOAD = 1.0 nF, Note 1
Dead Time
tDT
20
—
—
ns
—
12
—
Two Dead-Time options, See
Section 5.2.2, Dead Time
Selection, Note 1
Short Circuit Protection
High-Side Over Current
Threshold Voltage
OCTH-HI
430
480
530
mV
Note 1, VCBOOT = 5V
Low-Side Over Current
Threshold Voltage
OCTH-LO
130
180
230
mV
Note 1, Note 3
Minimum Pulse Width
During Short Circuit
tSS-MIN
—
800
—
ns
Note 1
Off-Time Between
Restart Attempts (HickUp Time)
tSS-HT
30
60
—
ms
Note 1
Thermal Shutdown
TSHD
—
150
—
°C
Note 1
Thermal Shutdown
Hysteresis
TSHD_HYS
—
15
—
°C
Note 1
Thermal Shutdown
Note 1:
2:
3:
Ensured by design. Not production tested.
Limited by the maximum power dissipation of the case.
Possibility to be adjusted for high volumes.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VIN = 6.0V to 30V, FSW = 300 kHz
Parameters
Sym
Min
Typ
Max
Units
TA
-40
—
+125
°C
TJ-MAX
—
—
+150
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
JA
—
53.3
—
°C/W
Conditions
Temperature Ranges
Specified Temperature Range
Maximum Junction Temperature
Thermal Package Resistances
Thermal Resistance, 10L-3x3 DFN
 2012 Microchip Technology Inc.
Typical 4-Layer board with
interconnecting vias
DS22326A-page 5
MCP19035
NOTES:
DS22326A-page 6
 2012 Microchip Technology Inc.
MCP19035
2.0
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
7.0
5.05
ILOAD = 20 mA
LDO O
Output Voltage (V)
Input Quiescent Current (mA)
Note: Unless otherwise indicated, TA = +25°C, VIN = 12V, VOUT = 1.8V, fSW = 300 kHz, CVCC = 4.7 uF.
6.0
5.0
4.0
0
5
FIGURE 2-1:
Input Voltage.
10
15
20
25
Input Voltage (V)
30
4.99
4.97
0
FIGURE 2-4:
Input Voltage.
10
20
Input Voltage (V)
30
40
+VCC-OUT Regulation vs.
5.05
LDO Output Voltage (V)
10.0
Input Quiiescent Current (mA)
5.01
4.95
35
Input Quiescent Current vs.
5.03
8.0
6.0
4.0
2.0
0.0
5.03
5.01
4.99
4.97
4.95
-50
FIGURE 2-2:
Temperature.
0
50
100
Junction Temperature (°C)
150
Input Quiescent Current vs.
0
FIGURE 2-5:
Load Current.
20
40
Load Current (mA)
60
+VCC-OUT Regulation vs.
LDO Drropout Voltage (V)
Relative O
Oscillator Frequency
Variation (%)
V
1.5
4.0
2.0
0.0
-2.0
-4.0
-6.0
-8.0
-10.0
-50
0
50
100
Junction Temperature (°C)
FIGURE 2-3:
Relative Oscillator
Frequency Variation vs. Temperature.
 2012 Microchip Technology Inc.
150
ILOAD = 50 mA
1.25
1
0.75
05
0.5
0.25
0
-50
0
50
100
Junction Temperature (°C)
150
FIGURE 2-6:
LDO Regulator Dropout
Voltage vs. Temperature.
DS22326A-page 7
MCP19035
Note: Unless otherwise indicated, TA = +25°C, VIN = 12V, VOUT = 1.8V, fSW = 300 kHz, CVCC = 4.7 uF.
4.0
VOUT = 1.8 V
IOUT = 1 A
3.5
Softt Start Time (ms)
LDO PSRR (dB)
L
-10.0
-30.0
-50.0
-70.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-90.0
10
FIGURE 2-7:
Frequency.
1000
Frequency (Hz)
-50
100000
+VCC-OUT LDO PSRR vs.
FIGURE 2-10:
Temperature.
High-Side Overcurrent
Th
hreshold (mV)
Relativ
ve Reference Voltage
Variation (%)
150
Soft Start Time vs.
600
0.2
0.1
0
-0.1
VCBOOT = 5V
500
400
300
-0.2
-50
0
50
100
Junction Temperature (°C)
-50
150
FIGURE 2-8:
Relative Reference Voltage
Variation vs. Temperature.
0
50
100
Junction Temperature (°C)
150
FIGURE 2-11:
High-Side Overcurrent
Threshold vs. Temperature.
0
Low--Side Overcurrent
Threshold (mV)
5
Under Volatge Lockout
hresholds (V)
Th
0
50
100
Junction Temperature (°C)
VIN Rising
4
VIN Falling
3
-100
-200
2
-50
FIGURE 2-9:
Temperature.
DS22326A-page 8
0
50
100
Junction Temperature (°C)
UVLO Thresholds vs.
150
-50
0
50
100
Junction Temperature (°C)
150
FIGURE 2-12:
Low-Side Overcurrent
Threshold vs. Temperature.
 2012 Microchip Technology Inc.
MCP19035
Note: Unless otherwise indicated, TA = +25°C, VIN = 12V, VOUT = 1.8V, fSW = 300 kHz, CVCC = 4.7 uF.
50
Low-Side
e Driver NMOS RDSon
Relattive Variation (%)
High-Sid
de Driver PMOS RDSon
Relattive Variation (%)
50
40
30
20
10
0
-10
-20
20
-30
-40
40
30
20
10
0
-10
-20
-30
-40
-50
-50
0
50
100
Junction Temperature (°C)
-50
150
FIGURE 2-13:
HDRV P-Ch RDSon Relative
Variation vs. Temperature.
-50
150
Power G
Good Active Timeout
(ms)
High-Side
e Driver NMOS RDSon
Relattive Variation (%)
150
FIGURE 2-16:
LDRV N-Ch RDSon Relative
Variation vs. Temperature
50
40
30
20
10
0
-10
-20
-30
-40
140
130
120
110
100
-50
-50
0
50
100
Junction Temperature (°C)
-50
150
FIGURE 2-14:
HDRV N-Ch RDSon Relative
Variation vs. Temperature.
FIGURE 2-17:
vs. Temperature.
0
50
100
Junction Temperature (°C)
150
PG Active Time Out Period
100
50
40
Powe Good Thresholds
(% of R
Reference Voltage)
Low-Side
e Driver PMOS RDSon
Releattive Variation (%)
0
50
100
Junction Temperature (°C)
30
20
10
0
-10
-20
-30
PWRGD = High
90
PWRGD = Low
-40
-50
80
-50
0
50
100
Junction Temperature (°C)
150
FIGURE 2-15:
LDRV P-Ch RDSon Relative
Variation vs. Temperature.
 2012 Microchip Technology Inc.
-50
FIGURE 2-18:
Temperature.
0
50
100
Junction Temperature (°C)
150
PG Thresholds Voltage vs.
DS22326A-page 9
MCP19035
NOTES:
DS22326A-page 10
 2012 Microchip Technology Inc.
MCP19035
3.0
PIN DESCRIPTION
Description of the pins are listed in Table 3-1.
TABLE 3-1:
3.1
PIN DESCRIPTION TABLE
MCP19035
3 x 3 DFN
Symbol
1
SHDN
2
FB
3
COMP
Description
Device shutdown input pin
Feedback voltage input pin
Internal error amplifier output pin
4
VIN
Input voltage pin
5
PWRGD
Power good pin
6
+VCC
+5.0V output voltage pin
7
LDRV
Lower gate drive output pin
8
BOOT
Floating bootstrap supply pin
9
PHASE
Switching node pin
10
HDRV
Upper gate drive output pin
11
EP
Exposed Thermal Pad, must be connected to GND
Shutdown Input Pin (SHDN)
This pin enables or disables the MCP19035 device.
When logic “High” is applied to this pin, the device is
enabled. A logic “Low” will disable the device. When
the device is disabled, both the LDRV and HDRV pins
are held low. The internal LDO regulator is also disabled when the SHDN pin is pulled low. Do not let this
pin float. If not used, connect to VIN using a 100 k
resistor.
3.5
Power Good Pin (PWRGD)
The power good pin is an open drain output. This pin is
pulled low when the output is 92% less than the typical
value. Connect this pin to +VCC pin through a pull-up
resistor. The recommended value for the pull-up resistor is 100 kΩ.
3.6
LDO Output Voltage Pin (+VCC)
This is the internal error amplifier’s negative input, and
is used to sense the output voltage. The positive input
to the amplifier is connected to the internal reference
voltage.
This pin is the output of the internal voltage regulator
(LDO). The internal circuitry of the controller is powered
from this pin (+5.0V). External low noise loads can be
powered from this pin, but the sum of the external load
current and the internal circuitry current should not
exceed 50 mA. A 4.7 μF ceramic capacitor must be
connected between this pin and GND.
3.3
3.7
3.2
Feedback Voltage Input Pin (FB)
Internal Error Amplifier Pin
(COMP)
This is the output of the internal error amplifier. The
compensation network is connected between this pin
and the FB pin.
This pin is the drive output for the low-side N-Channel
MOSFET (synchronous rectifier). The LDRV drive is
capable of sourcing 1A and sinking 1.5A.
3.8
3.4
Input Voltage Pin (VIN)
This pin is the input power for the controller. A bypass
capacitor must be connected between this pin and the
GND pin. The input of an internal voltage regulator
(LDO) is connected to this pin to generate the +5V VCC
used for internal circuitry bias.
 2012 Microchip Technology Inc.
Lower Gate Pin (LDRV)
Bootstrap Supply Pin (BOOT)
The BOOT pin is the floating bootstrap power supply
pin for the high-side MOSFET gate driver. A capacitor
connected between this pin and the PHASE pin provides the necessary charge to turn on the external
high-side MOSFET.
DS22326A-page 11
MCP19035
3.9
Switching Node Pin (PHASE)
This pin provides a return path for the high-side gate
driver. It also provides a path for the charging of the
BOOT capacitor, used while turning on the high-side
MOSFET. This pin also senses the switching transition
to eliminate cross conduction (shoot-through).
3.10
Upper Gate Drive Pin (HDRV)
This pin is the high-side N-channel MOSFET (control
transistor) gate drive output. The HDRV drive is
capable of sourcing and sinking 1A.
3.11
Exposed Thermal Pad (EP)
Analog ground and power ground are both connected
to this pin.
DS22326A-page 12
 2012 Microchip Technology Inc.
MCP19035
4.0
DETAILED DESCRIPTION
4.1
Device Overview
• Dead-Time optimization options of the MCP19035
assist in improving the power conversion efficiency, when used with high-speed, low Figure of
Merit MOSFETs.
• Overcurrent protection circuits in both high and
low-side switches, and a short circuit hiccuprecovery mode increase design flexibility and minimize power dissipation in the event of prolonged
output faults.
• The dedicated SHDN pin allows the converter to
be placed in a low quiescent current state.
• Internal fixed converter switching frequency and
soft-start reduce the external component count,
simplifying design and layout, as well as reducing
footprint and size.
• The 3 mm × 3 mm DFN package size also minimizes the overall converter footprint.
The MCP19035 family of devices are highperformance controllers providing all the necessary
functions to construct a high-performance DC/DC
converter, while keeping costs and design effort to a
minimum:
• Support for pre-biased outputs eliminates concerns about damaging sensitive loads during
startup.
• Strong gate drivers for the high side and rectifier
N-Channel MOSFETs decrease switching losses,
yielding increases in efficiency.
• Adaptive gate drive timing prevents shoot-through
and minimizes body diode conduction in the synchronous rectifier MOSFET, which also increases
the efficiency.
UVLO
Circuit
Over-Temperature
Detection Circuit
OT
VIN
Over-Current
Detection Circuit
VCC
VIN
Voltage
Regulator
BOOT
VCC
HD
SD
SHDN
SD
VCC
-
VCC
FB
Control
Logic
Oscillator
Shut-Down
Circuit
Comp
OT
Dead
Time
Generator
Cross
Conduction
Protection
PHASE
VCC
PWM
+
-
HDRV
LD
LDRV
EA
+
COMP
Soft Start
Circuit
VREF
Reference
Voltage
Generator
FB
SD
PWRGD
Power-Good
Circuit
GND
FIGURE 4-1:
Internal Block Diagram.
 2012 Microchip Technology Inc.
DS22326A-page 13
MCP19035
4.2
PWM Circuitry
The MCP19035 controller implements a fixed
frequency, voltage-mode control scheme. The internal
PWM generator is comprised of an oscillator, error
amplifier, high-speed comparator and a latch. The error
amplifier generates the control voltage by amplifying
the difference between voltage reference (600 mV,
internally generated) and the voltage of the FB pin
(feedback voltage). This control voltage is compared by
the high-speed comparator to an artificially generated
ramp signal; the result is a PWM signal. An SR latch
(Set-Reset flip-flop) is used to prevent the PWM
circuitry from turning the external switch on until the
beginning of the next clock cycle.
An external Compensation Network (Type-II or
Type-III) must be used to stabilize the control system.
4.3
Internal Reference Voltage VREF
An integrated, precision voltage reference is provided
by the MCP19035. An external resistor divider is used
to program the converter’s output voltage. The nominal
value of this internal reference voltage is 600 mV.
4.4
Internal Oscillator
The internal oscillator of the MCP19035 device
provides a 300 kHz fixed switching frequency.
4.5
Under Voltage Lockout Circuit
(UVLO)
An integrated Under Voltage Lockout Circuit (UVLO)
prevents the converter from starting until the input voltage is high enough for normal operation. The converter
will typically start at 4.2V and operate down to 3.6V.
Hysteresis is added to prevent starting and stopping
during startup, as a result of loading the input voltage
source.
4.6
A 100 kΩ pull-up resistor is recommended between the
SHDN pin and VIN pin. Note that the SHDN input is a
high-impedance pin. Noise generated by the circuits
located near this pin may inadvertently shut down the
controller. To improve the noise immunity of this input
pin, we recommend placing a small capacitor between
GND and SHDN, or decrease the value of the pull-up
resistor. The Shutdown input pin should not be left
floating.
4.7
Power Good Output (PWRGD)
This open drain output provides an indication that the
output voltage is 92% (typical) of its regulated value.
This output is also low for other existing conditions that
signal the possibility that the output of the power supply
is out of regulation. The conditions are:
• Feedback pin (FB) voltage differs more than ±8%
from its nominal value (600 mV)
• Soft-start period is active
• Undervoltage condition detected
• Overcurrent condition detected, on either the High
Side or Low Side
• Die temperature is above the thermal shutdown
threshold (+150°C)
The active high power good signal has a fixed time
delay of approximately 120 ms (tPG-TIMEOUT). There is
typically 150 μs delay (tPG-DELAY) on the power good
signal high-to-low transition.
PGTH-HI
VFB
PGTH-LOW
tPG-TIMEOUT
tPG-DELAY
Shutdown Input
The Shutdown input pin (SHDN) is used to enable and
disable the controller. When the SHDN pin is pulled
low, the MCP19035 is placed in Shutdown mode.
During Shutdown, most of the internal circuits
(including the LDO) are disabled, to minimize current
consumption.
DS22326A-page 14
PGV-LOW
PG
FIGURE 4-2:
Power Good Signal.
 2012 Microchip Technology Inc.
MCP19035
4.8
Internal Voltage Regulator (LDO)
The MCP19035 controller offers an internal 5V Low
Dropout Voltage Regulator. This regulator provides the
bias voltage for all internal circuits. A ceramic capacitor
(4.7 μF minimum) must be connected between the
output of this LDO (VCC pin) and ground (GND pin) for
stable operation.
An external low noise load may be powered from this
regulator, but the total current consumed from the LDO
output (internal circuitry of MCP19035 + external load)
should not exceed 50 mA. The internal circuitry of the
MCP19035 consume approximately 5 mA. The total
amount of current available to power the external load
can be estimated from Equation 4-1:
4.9
Internal MOSFET Drivers
Internal MOSFET drivers are capable of driving
external, “Logic Level” (+5V) MOSFETs.
The Low Side Driver (LDRV) is referenced to the GND
pin and is capable of sourcing 1A and sinking 1.5A.
The High Side Driver (HDRV) is floating and capable of
sourcing and sinking 1A. This driver is powered from an
external bootstrap capacitor.
The drivers have non-overlapping timing that is
governed by an adaptive delay circuit to minimize body
diode conduction in the synchronous rectifier.
For the optimized Dead Time version of the
MCP19035, the adaptive delay circuit is disabled and
the Dead Time has a fixed value.
EQUATION 4-1:
IExternal Load = 50 mA - fSW x (QG(High Side) + QG(Low Side)) - 5 mA
Where:
IExternal Load = Current Available for powering the
External Load
fSW = Switching Frequency (300 kHz)
QG(High Side) = Total Gate Charge of the High-Side
MOSFET at 4.5V VGS
QG(Low Side) = Total Gate Charge of the Low-Side
MOSFET at 4.5V VGS
This LDO dissipates power within the MCP19035. To
avoid tripping the Overtemperature Protection Circuit,
the designer must ensure that the maximum die
temperature is below +125°C under worst case
conditions (i.e. high input voltage). For further
information regarding the maximum dissipated power
for LDOs, see Microchip’s AN761 and AN792
application notes.
The LDO is protected against overload and short-circuit
conditions. Consistent performance of the internal
MOS drivers is ensured by monitoring the LDO output
voltage; if the voltage is lower than 3.3V typical, the
chip will enter in Shut-Down mode to prevent damage
to the external MOSFETs.
4.10
Overcurrent Protection
Overcurrent protection is accomplished by monitoring
the voltage across the external MOSFETs when they
are ON (conducting).
For the high-side overcurrent protection, when the
sensed voltage drop across the high-side MOSFET is
greater than the high-side overcurrent threshold
voltage, the high-side MOSFET is immediately turned
off and the high-side overcurrent counter is
incremented by one. On the next cycle, if the high-side
overcurrent threshold voltage is not exceeded, the
high-side overcurrent counter is decreased by one
count. If the high-side overcurrent counter reaches a
count of 7, a fault condition exists and the MCP19035
turns off both external MOSFETs.
After a 60 ms delay, the MCP19035 will attempt to
restart. If during the next cycle, a high-side overcurrent
threshold voltage is measured across the high-side
MOSFET, a fault is again declared and both external
MOSFETs are turned off for another 60 ms. However, if
after the attempted restart a high-side overcurrent
threshold voltage is not measured across the high-side
MOSFET, the high-side overcurrent counter is
decreased by one and the MCP19035 continues to
operate until the high-side overcurrent counter reaches
a count of 7.
The low-side overcurrent protection behaves much the
same way as the high-side overcurrent protection. The
difference is that the low-side MOSFET is not
immediately turned off when a low-side overcurrent
threshold voltage is measured. It remains on until the
next cycle begins.
 2012 Microchip Technology Inc.
DS22326A-page 15
MCP19035
For the low-side overcurrent protection, when the
sensed voltage drop across the low-side MOSFET is
greater than the low-side overcurrent threshold voltage
specified, a low-side overcurrent counter is
incremented by one count. On the next cycle, if the lowside over current threshold voltage is not exceeded, the
low-side overcurrent counter is decreased by one. If
the low-side overcurrent counter reaches a count of 7,
a fault condition exists and the MCP19035 turns off
both external MOSFETs. After a 60 ms delay, the
MCP19035 device will attempt to restart. If during the
next cycle, a low-side overcurrent threshold voltage is
measured across the low-side MOSFET, a fault is
again declared and both external MOSFETs are turned
off for another 60 ms. However, if after the attempted
restart a low-side overcurrent threshold voltage is not
measured across the low-side MOSFET, the low-side
overcurrent counter is decreased by one and the
MCP19035 continues to operate until the low-side
overcurrent counter reaches a count of 7.
The voltage threshold for high-side overcurrent
protection circuit is fixed, 480 mV typical. The high-side
voltage threshold will also depend on the value of the
voltage across the bootstrap circuit capacitor, and will
decrease when this voltage decreases. This will ensure
that the high-side protection will avoid a failure of the
MOSFET when the bootstrap voltage is low and the
switching losses are high. This threshold will provide a
cycle-by-cycle protection in case of short circuit, but it
should not be used to provide a precise current limit for
the converter. An estimation of the current that flows in
the high-side MOSFET during short circuit can be
found using Equation 4-2. Note that, due to the leading
edge blanking time, this current also depends on the
inductor's ripple current. To avoid false triggering of the
high side over current protection circuit during
transients, it is highly recommended to choose a
MOSFET that will provide a threshold at least four
times higher than the maximum output current of the
converter.
EQUATION 4-2:
PEAK CURRENT FOR
HIGH-SIDE MOSFET
V OC HS
I HS MOS = ----------------R DSON
Where:
IHS MOS = Current that passes through the
High-Side MOSFET
VOC HS = Threshold Voltage for High-Side
Overcurrent Protection Circuit
(480 mV)
RDSON = ON Resistance of the High-Side
MOSFET
The voltage threshold for the low-side overcurrent
protection circuit is fixed, 180 mV typical. Different
values for this threshold (from 100 mV to 300 mV) are
available on request. An estimation of the current that
flows on the low-side MOSFET during short circuit is
realized using Equation 4-3. Note that, due to the
leading edge blanking time, this current also depends
on the inductor's ripple current. To avoid false triggering
of the low-side over current protection circuit during
transients, it is highly recommended to choose a
MOSFET that will provide a threshold at least two times
higher than the maximum output current of the
converter.
EQUATION 4-3:
V OC LS
I LS MOS = ----------------R DSON
Where:
ILS MOS = Current that passes through the
Low-Side MOSFET
VOC LS = Threshold Voltage for Low-Side
Overcurrent Protection Circuit
(180 mV)
RDSON = ON Resistance of the Low-Side
MOSFET
To avoid a false trigger of the overcurrent circuit, a
leading edge blanking circuit is present on both the
high and low-side measurements. Due to this blanking
time, the accuracy of the overcurrent circuit may be
impacted if the converter operates at higher duty cycles
(more than 85%), or if the inductor's current ripple is
very high (i.e. the inductor is saturated by the excessive
current).
DS22326A-page 16
 2012 Microchip Technology Inc.
MCP19035
4.11
Soft Start
To control the output voltage during start-up, the
MCP19035 uses a soft-start circuit that allows the
output voltage of the system to monotonically increase.
The soft start circuitry allows the output voltage to rise
up to the desired regulation limit, typically within
2.6 ms. The soft start circuit is enabled each time the
MCP19035 starts. This includes initial start-up, start-up
from toggling the SHDN pin, start-up after thermal
shutdown, or start-up after an overcurrent condition.
SHDN
VOUT
Soft Start Time
(TSS = 2.6 ms)
FIGURE 4-3:
4.12
Soft Start-up Diagram.
Pre-Bias Load Start-up
A special start-up sequence will prevent any current to
be sourced from the output in case of a pre-biased
load. This is accomplished by monitoring the FB pin
and internal reference voltages. If the positive input to
the Error Amplifier (internal reference voltage) is
greater than the feedback voltage (voltage present at
FB pin), the controller will drive the low-side MOSFET
(synchronous rectifier) with a reduced duty cycle. This
sequence ensures a smooth output voltage transition
without sinking any current from the pre-biased
external load.
 2012 Microchip Technology Inc.
DS22326A-page 17
MCP19035
NOTES:
DS22326A-page 18
 2012 Microchip Technology Inc.
MCP19035
5.0
APPLICATION INFORMATION
5.1
Typical Applications
The MCP19035 synchronous buck controller operates
over an input voltage range, up to a maximum of 30V.
The output current capability depends only on the
external MOSFET’s selection and can also be very
high, typically up to 20A.
Typical applications include POL modules for powering
DSPs, FPGAs and ASICs, and, in general, any stepdown voltage conversion (from maximum 30V input
voltage) for medium-to-high output current loads.
5.2
Design Procedure
To simplify this design process, an Excel®-based
design tool is available to support typical applications.
This tool is available on the MCP19035 product web
site. Refer to AN1452 – “Using the MCP19035
Synchronous Buck Converter Design Tool” for further
details.
5.2.1
SWITCHING FREQUENCY AND THE
MAXIMUM CONVERSION RATIO
The MCP19035 controller provides a 300 kHz, fixed
switching frequency. This switching frequency offers a
good compromise between higher efficiency and the
size of the power train components.
Due to the minimum "On Time" for the high-side
MOSFET driver (170 ns typical), the maximum
conversion ratio must be limited to 15:1.
5.2.2
5.2.3
INDUCTOR SELECTION
The output inductor is responsible for smoothing the
square wave created by the switching action and for
controlling the output current ripple (∆IOUT). There is a
trade off between efficiency and load transient
response time when the value of the inductor is
chosen. The smaller the inductance, the quicker the
converter can respond to transients in the load current.
However, a smaller inductor requires a higher switching
frequency to maintain the same level of output current
ripple. Remember that increasing the switching
frequency will also increase the switching losses in the
MOSFETs.
A good compromise for the inductor current ripple is
30% of the output current. The value of the inductor is
calculated in Equation 5-1:
EQUATION 5-1:
INDUCTOR VALUE
V OUT
1
1
  ----------------------L = V
–V
 ----------  ----------------------------------------- IN MAX
OUT V
0.3  I
f
OUTMAX
INMAX SW
The peak current in the inductor is determined in
Equation 5-2:
EQUATION 5-2:
INDUCTOR PEAK
CURRENT
0.3  I
I
L PEAK
= I
OUT MAX
+ -----------------------------------------OUT MAX
2
EQUATION 5-3:
INDUCTOR RMS
CURRENT
DEAD TIME SELECTION
Dead Time will affect the maximum obtainable
efficiency of the converter. Selecting the Dead Time
depends on the external MOSFETs’ parameters. Lower
Figure of Merit (FOM) transistors will permit the use of
shorter Dead Times. This may increase the converter
efficiency by up to 2%.
Low Figure of Merit transistors allow the user to select
a low value for Dead Time (typical 12 ns) without
causing a shoot-through phenomenon. For low-FOM
transistors, the MCP19035 version with fixed 12 ns
Dead Time is recommended.
For typical medium Figure of Merit transistors, the
MCP19035 version with the adaptive Dead-Time
generator is recommended.
 2012 Microchip Technology Inc.
IL
=
RMS
2 I Ripple
I OUT + -------------------3
2
Additional care must be taken when selecting an inductor:
• Choose an inductor that has a saturation current
larger than the calculated peak current. The
tolerance of the inductor must also be considered
(typically 20%).
• To minimize the conduction losses, choose an
inductor with the lowest possible DC resistance.
The maximum DC resistance specified in the data
sheet will ensure the worst-case component specification.
• There are many magnetic materials available for
inductor core: ferrite, iron powder and composite
materials. The ferrite offers the lowest core
losses, but the saturation characteristic is “hard”
(i.e. the inductance drops rapidly after the current
reaches the saturation level). The losses of iron
powder or composite material cores are higher
than ferrite, but the saturation characteristic is
“soft”, making it more suitable for voltage mode
control converter, including the MCP19035.
DS22326A-page 19
MCP19035
5.2.4
INPUT CAPACITOR SELECTION
5.2.5
The input capacitor is responsible for providing a low
impedance voltage source for the step-down converter.
This capacitor must be able to sustain high ripple
current, a consequence of the discontinuous input
current of the buck converter. A low equivalent series
resistance capacitor (ESR), preferably ceramic, is
recommended. For wide temperature range
applications, a multi-layer X7R dielectric is
recommended, while for applications with limited
temperature range, a multi-layer X5R dielectric is
acceptable. A higher ESR will produce a higher voltage
ripple and higher power losses. The capacitor voltage
rating must be higher than the maximum operating
input voltage of the converter.
The minimum
Equation 5-4:
capacitance
is
determined
The output capacitor is responsible for smoothing the
output voltage. It also plays an important role in the
stability of the control system. The voltage ripple across
the output capacitor is the sum of ripple voltages due to
the Equivalent Series Resistance (ESR) and the
voltage sag due to the load current that must be
supplied by the capacitor as the inductor is discharged.
A low ESR capacitor, preferably ceramic, is
recommended. For wide temperature range
applications, a multi-layer X7R dielectric is
recommended, while for applications with limited
temperature range, a multi-layer X5R dielectric is
acceptable.
The output voltage ripple is estimated in Equation 5-6:
in
EQUATION 5-6:
EQUATION 5-4:
C IN_MIN
OUTPUT CAPACITOR SELECTION
MINIMUM CAPACITANCE
FOR INPUT CAPACITOR
I OUT  D   1 – D 
= ----------------------------------------------------------------------------------f SW   V Ripple – D  I OUT  ESR 
Where:
CIN_MIN = Minimum Capacitance of the Input
Capacitor (in Farad)
IOUT = Output Current (A)
OUTPUT VOLTAGE
RIPPLE
1
VRipple = I Ripple   ESR + --------------------------------------

8  C OUT  f SW
Where:
IRipple = Inductor Current Ripple (A)
VRipple = Output Voltage Ripple (V)
COUT = Output Capacitor (F)
ESR = Equivalent Series Resistance of the
Output Capacitor (Ohm)
D = Duty Cycle (for worst case this is 0.5)
fSW = Switching Frequency (Hz)
VRipple = Input Voltage Ripple (usually between
0.1V and 0.5V)
ESR = Equivalent Series Resistance of the
Capacitor (in Ohm)
The maximum ripple current in the input capacitor
occurs when the duty cycle is 50%. This must be
considered worst case for calculating the input
capacitor.
Minimum capacitance value is calculated according to
the demand of the load transient response. During a
transient load current, the excessive energy stored by
the inductor must be absorbed by the output capacitor
until the control loop sets the proper duty cycle.
Equation 5-7 calculates the minimum value for the
output capacitor value:
EQUATION 5-7:
OUTPUT CAPACITOR
MINIMUM VALUE
2
The RMS current in the input capacitor is estimated
with Equation 5-5:
C OUT
2
L  I OH – I OL
= ----------------------------------2
2
Vf – V OUT
Where:
EQUATION 5-5:
IRMS  C
IN 
RMS CURRENT IN THE
INPUT CAPACITOR
I Ripple
 VOUT  I OUT
=  IOUT + ---------------- D –  --------------------------------
12
VIN
The input capacitor must be rated to sustain this RMS
current without considerable losses.
DS22326A-page 20
IOH = Final Value of the Output Current
IOL = Initial Value of the Output Current
VOUT = Initial Output Voltage
Vf = Final Output Voltage
For applications that require low output voltage
overshoot during a step load, the value of the output
capacitor can become very large. In this case, it is
recommended to mix ceramic capacitors with
aluminum or polymer electrolytic capacitors to reach
the recommended value.
 2012 Microchip Technology Inc.
MCP19035
5.2.6
MOSFETS SELECTION
Choosing the right MOSFET is a critical part of the
design for a switching regulator. Their performance will
directly impact the efficiency and reliability of the
regulator.
The MCP19035 synchronous buck controller offers an
integrated, logic-level MOSFET driver, and is capable
of supplying 5V to drive the MOSFET gates. As a
result, logic-level MOSFETs must be used. Suitable
MOSFETs should meet the requirement of voltage and
current rating.
A key parameter for evaluating the MOS transistor
performance is the Figure of Merit. For a given
MOSFET, this is defined as the product between the
Total Gate Charge (QG) and RDS(ON) (see Equation 58).
EQUATION 5-8:
FIGURE OF MERIT
FOM = Q G  Tot   RDS ON 
A lower FOM value means a higher-performance MOS
transistor.
For the High-side MOSFET, power losses consist of
both switching and conduction losses. Conduction
losses are high when the duty cycle of the converter is
high. The conduction loss of the high-side MOSFET
can be estimated by multiplying the RDS(ON) with the
RMS value of the current that passes through the transistor (see Equation 5-9).
EQUATION 5-9:
I RMS
RMS VALUE FOR
HIGH-SIDE CURRENT
High-Side
=
2

2 I Ripple
D   I OUT + ----------------
12 

Where:
D = Duty Cycle
IRipple = Current Ripple in the Inductor
(typically 30% of the maximum output
current) (A)
The conduction losses for high-side MOS transistor are
estimated in Equation 5-10:
P COND
High-Side
CONDUCTION LOSSES
FOR HIGH-SIDE MOSFET
= I RMS
2
High-Side 
EQUATION 5-11:
P SW
High-Side
SWITCHING LOSSES FOR
HIGH-SIDE MOSFET
VIN  IOUT
=  ---------------------------   t s  HL  + t s  LH    fSW


2
Where:
VIN = Input Voltage (V)
IOUT = Output Current (A)
fSW = Switching Frequency (Hz)
ts(HL) = MOSFET Switching Time
(High-to-Low transition) (s)
ts(LH) = MOSFET Switching Time
(Low-to-High transition) (s)
The ts(HL) and ts(LH) times can be estimated using the
following equations:
EQUATION 5-12:
Q G  Total 
t s  HL  = --------------------I DRV Sink
Q G  Total 
t s  LH  = ---------------------I DRV Source
Where:
QG(Total) = High-side MOSFET Total Gate
Charge
IDRVSink = Sink Peak Current for High-Side
Driver (typical 1A)
IDRVSource = Source Peak Current for High-Side
Driver (typical 1A)
The total power losses for high-side MOSFET can be
calculated with Equation 5-13:
IOUT = Output Current (A)
EQUATION 5-10:
The switching losses are more difficult to calculate,
since they depend on many parameters. Equation 5-11
shows an estimation of these losses:
R DS  on HS  max 
EQUATION 5-13:
P Loss
High-Side
TOTAL POWER LOSSES
FOR HIGH-SIDE MOSFET
= P COND
High-Side
+ P SW
High-Side
For applications that operate with low duty cycle (lower
than 30%) or high input voltage, the power losses for
the high-side transistor are mainly switching losses.
For these applications, it is recommended to choose a
MOSFET that offers a low Total Gate Charge.
For applications that operate with duty cycles higher
than 50%, the power losses for the high-side transistor
are mainly conduction losses. For these applications,
choose a MOSFET that has a low RDS(on).
 2012 Microchip Technology Inc.
DS22326A-page 21
MCP19035
The low-side MOSFET (synchronous rectifier) is “softcommutated” by the energy stored in the inductor , thus
reducing the switching losses. For the low-side transistor, the power losses mainly consist of conduction
losses, body diode conduction losses and body diode
reverse recovery losses.
The body diode recovery time losses will be calculated
using Equation 5-17:
Similarly to the high-side, the RMS current that pass
through the low-side MOSFET is calculated using
Equation 5-14:
PRR = ---------------------------------------2
EQUATION 5-17:
BODY DIODE REVERSE
RECOVERY LOSSES
Q RR  V IN  f SW
Where:
QRR = Reverse Recovery Charge of the Body Diode (C)
EQUATION 5-14:
I RMS
Low-Side
RMS CURRENT FOR
LOW-SIDE MOSFET
2

2 I Ripple
 1 – D    I OUT + ----------------
12 

=
Where:
D = Duty Cycle
IRipple = Current Ripple in the Inductor
(typically 30% of the maximum output
current) (A)
The conduction losses for low-side MOS transistor are
estimated in Equation 5-15:
P COND
Low-Side
CONDUCTION LOSSES
FOR LOW-SIDE
TRANSISTOR
= IRMS
 R DS  on LS  max 
2
Low-Side
The body diode conduction loss is calculated in
Equation 5-16:
EQUATION 5-16:
PLOSS
BD
EQUATION 5-18:
PLoss
IOUT = Output Current (A)
EQUATION 5-15:
The total power loss for the low-side MOSFET can now
be estimated by summing the power losses in
Equation 5-18:
BODY DIODE
CONDUCTION LOSSES
Low-Side
+ PLOSS
BD
+ PRR
The body diode conduction and reverse recovery
losses can be greatly minimized by reducing the Dead
Times necessary to prevent the shoot-through. This
can be achieved by choosing transistors that have a
very low Figure of Merit (FOM) MOSFET for both sides.
5.2.7
BOOTSTRAP CAPACITOR
SELECTION
The selection of the bootstrap capacitor is based upon
the total gate charge of the high-side power MOSFET
and the allowable droop in gate drive voltage while the
high-side power MOSFET is conducting (see
Equation 5-19).
EQUATION 5-19:
BOOTSTRAP CAPACITOR
QG  Total 
C BOOT = ----------------------- V DROOP
Where:
VF = Forward Voltage of the Body Diode (V)
= P COND
The conduction losses are the dominant part of the total
losses for the low-side transistor; choose a MOSFET
with a low RDS(on).
= I OUT  V F  t BD  f SW
tBD = Total Conduction Time for Body Diode (s)
Low-Side
TOTAL POWER LOSS FOR
LOW-SIDE MOSFET (SR)
Where:
QG(Total) = High-side MOSFET Total Gate Charge (C)
∆VDROOP = Allowable Gate Drive Voltage Droop (V)
It is recommended that the voltage droop does not
exceed 50 mV. A low ESR, ceramic capacitor, rated at
least 16 VDC, is recommended.
DS22326A-page 22
 2012 Microchip Technology Inc.
MCP19035
5.2.8
FEEDBACK LOOP COMPENSATION
Since the MCP19035 implements a Voltage-Mode
PWM control, a Type-III compensation network is
recommended. Correct placing of poles and zeros
require analysis of the Bode plots for the buck
converter power train.
The frequencies for pole and zero are determined
using Equation 5-20:
EQUATION 5-20:
POLE AND ZERO
FREQUENCIES
1
fLC = ------------------------------------2 L  C
OUT
1
f
= ----------------------------------------------ESR
2   ESR  C
OUT
Magnitude
(dB)
AMOD
0 dB
-40 dB/decade
EQUATION 5-21:
PWM MODULATOR GAIN
V IN
A MOD = 20  log --------------------- = 20  log V IN
V RAMP
-20 db/decade
fLC
fESR
Frequency
(log scale)
The Type-III compensation network is represented in
Figure 5-2:
Phase
(deg)
C3
0°
C2
R4
C1
R3
-
-90°
COMP
EA
VIN
R1
+
R2
-180°
VREF
Frequency
(log scale)
FIGURE 5-1:
Bode Plots for Buck
Converter Power Train (Representation Using
Asymptotes).
The power train of a buck converter that uses voltage
mode control is a second order system. At the LC
resonance frequency, a double pole occurs; this pole
will “push” the gain down with a slope of -40db/decade.
This double pole also introduces a phase lag of -180°.
The compensation network must counteract the effects
of this double pole in order to achieve the stability of the
system.
Where:
1
1  
 s + -------------------  s + --------------------------------------

 R 1  R 3   C 1
R1 + R3
R 4  C 2 
G  s  = ---------------------------------  --------------------------------------------------------------------------------------------------R1  R 3  C1
 C2 + C3  

1
s   s + ---------------------------------   s + --------------------

R 3  C 1


R

4 C 2 C 3
FIGURE 5-2:
Network.
Type-III Compensation
The Equivalent Series Resistance (ESR) of the output
capacitor introduces a zero that “pushes” the gain and
phase up again. This zero helps the stability of the
system if it occurs before the phase reaches the critical
point of -180°. However, due to the performance criteria
(output voltage ripple, efficiency), the application
requires the use of low ESR capacitors. For capacitors
that have very low ESR (ceramic capacitors), this zero
occurs at high frequency, where the phase reaches the
critical point.
 2012 Microchip Technology Inc.
DS22326A-page 23
MCP19035
The Type-III compensation network provides two zeros
and three poles (including origin pole), pushing the
cross-over frequency as high as possible, and boosts
the phase margin of the system to greater than 45°. A
higher bandwidth yields a faster load transient
response. The faster transient response results in a
smaller output voltage overshoot.
Magnitude
(dB)
AOL
APOLE
AZERO
0 dB
Frequency
(log scale)
The procedure for placing the poles and zeros to
achieve the optimum phase margin are presented
below:
1.
Phase
(deg)
2.
90°
0°
3.
EQUATION 5-25:
-90°
fZ1
fZ2
fP1
fP2
Frequency
(log scale)
FIGURE 5-3:
Bode Plots for Type III
Compensation Network (Representation Using
Asymptotes).
Assuming C3 « C2 and R3 « R1, the pole and zero
frequencies can be calculated using Equation 5-22:
EQUATION 5-22:
POLE AND ZERO
FREQUENCIES OF THE
COMPENSATION
NETWORK
1
1
fZ1 = --------------------------------------------------  -------------------------------2    R 1 + R3   C 1 2   R 1  C1
1
f Z2 = -------------------------------2   R4  C2
1
1
f P1 = ---------------------------------------------------  -------------------------------C

C


R
2
2
3
4  C3
2   R4   --------------------
 C 2 + C 3
fP2
Determine the frequency of the double pole
(LC pole) and ESR zero using Equation 5-20.
Choose resistor R1 (usually between 10 kΩ and
100 kΩ). This value is a compromise between
high values for additional capacitors (higher
cost) and possible noise induced problems.
Resistor R2 is calculated using Equation 5-25:
0.6  R1
VREF  R1
R2 = --------------------------------- = --------------------------V OUT – V REF
V OUT – 0.6
4.
Choose the crossover frequency of the
compensated system. This frequency is
recommended to be between 1/10th and 1/5th of
the switching frequency (fSW). A higher
crossover frequency will improve the transient
response, but will decrease the phase margin.
For most of the applications, the crossover
frequency is set around 1/10th of switching
frequency. This is a reasonable compromise
between simplifying the design of the
compensation loop and achieving a fast
transient response. Since the frequency of the
ESR zero is much higher than LC resonant
frequency, the gain of the power train can be
typically approximated at the crossover
frequency, using Equation 5-26:
EQUATION 5-26:
1
= -------------------------------2   R3  C 1
EQUATION 5-23:
ZERO GAIN
R4
AZERO = 20  log -----R1
EQUATION 5-24:
FEEDBACK RESISTOR
DIVIDER
A PT
CO
POWER TRAIN GAIN AT
CROSSOVER
FREQUENCY
f CO
= AMOD – 40  log  --------
 f LC 
The compensated error amplifier must have a
gain equal to APTco at crossover frequency
(fCO). Typically, this crossover frequency occurs
between FZ2 and FP1 (see Figure 5-3).
POLE GAIN
R4   R 1 + R3 
A POLE = 20  log -----------------------------------R1  R 3
DS22326A-page 24
 2012 Microchip Technology Inc.
MCP19035
5.
The first zero of the compensation network must
be placed at the fLC frequency. The capacitor C1
is calculated using Equation 5-27:
EQUATION 5-27:
CAPACITOR C1
L  COUT
C 1 = ---------------------------R1
6.
The value of the resistor R4 is estimated using
Equation 5-28:
EQUATION 5-28:
The compensation circuit can be simulated with any
available simulator. The values of the components can
be adjusted to meet the initial design parameters
(crossover frequency and phase margin). It is also necessary to ensure that the gain of the compensation circuit does not exceed the gain of the error amplifier. Due
to the interactions between poles and zeros, it is highly
recommended to use the design tool provided by
Microchip Technology Inc. to design and analyze the
compensation network.
RESISTOR R4
f CO
1
R4 = --------  --------  R 1
f LC VIN
Where:
fCO = cross-over frequency for the compensated
system (usually 1/10th of fSW)
7.
The second zero of the compensation network
must be placed at half of the fLC frequency. The
value of the capacitor C2 is calculated in
Equation 5-29:
EQUATION 5-29:
CAPACITOR C2
L  COUT
C 2 = 2  ---------------------------R4
8.
The first pole of the compensation network must
be placed at fSW. The value of C3 is calculated in
Equation 5-30:
EQUATION 5-30:
CAPACITOR C3
1
C 3 = -----------------------------------------2    R 4  f SW
9.
The second pole of the compensation network
must be placed at half of the fSW .The value for
resistor R3 is calculated in Equation 5-31:
EQUATION 5-31:
RESISTOR R3
1
R 3 = --------------------------------  C 1  f SW
 2012 Microchip Technology Inc.
DS22326A-page 25
MCP19035
5.3
Operation with Low Input Voltages
If the application requires an input voltage below 5.5V,
it is recommended to use the alternative schematic
depicted in Figure 5-4.
+VIN
CIN
RIN
ON
MCP19035
SHDN
OFF
BOOT
Q1
CBOOT
HDRV
VIN
L
PHASE
PWRGD
C2
COMP
LDRV
FB
+VCC
+VOUT
COUT
CVCC
GND
C3
Q2
R4
R1
C1
R3
R2
FIGURE 5-4:
Typical Application for Low VIN.
This connection avoids the voltage drop on the internal
voltage regulator, ensuring the correct driving of the
MOSFETs at low input voltage.
Additional care must be exercised when this alternative
schematic is used to minimize the input voltage
ripple/noise. The internal circuitry of the MCP19035
may be affected by the ripple/noise present on the VCC
pin. The RIN resistor together with CVCC capacitor form
a low-pass filter for the bias voltage (VCC voltage). The
recommended value range for this resistor is between
2.2 and 10.
DS22326A-page 26
 2012 Microchip Technology Inc.
MCP19035
6.0
DESIGN EXAMPLE
This example illustrates the step-by-step design procedure for a 12V to 1.8V synchronous buck converter
using the MCP19035 controller. To minimize the design
effort, Microchip provides a design tool that is used to
calculate the component values. See AN1452 - “Using
the MCP19035 Synchronous Buck Converter Design
Tool” for further details (DS01452).
The electrical parameters are detailed in Table 6-1.
TABLE 6-1:
DESIGN EXAMPLE ELECTRICAL SPECIFICATION
Parameter
Test Conditions
Min
Nominal
Max
Unit
8
12
14
V
0  IOUT  15A
—
1.8
—
V
Line Regulation
8.0V  VIN  14V
—
—
0.5
%
Load Regulation
Input Voltage (VIN)
Output Voltage (VOUT)
0A  IOUT  15A
—
—
0.5
%
Output ripple (VOUT_RIPPLE)
IOUT = 15A
—
—
30
mV
Input ripple (VIN_RIPPLE)
IOUT = 15A
—
—
0.3
V
Output overshoot
Step from 3.75A to 11.25A
—
—
100
mV
Output undershoot
Step from 11.25A to 3.75A
—
—
100
mV
0
—
15
A
90
—
—
%
Output current (IOUT)
VIN = 12V, IOUT = 10A
Efficiency
6.0.1
INDUCTOR SELECTION
The inductor must be sized for a typical ripple current
that is around 30% of maximum output current. The
inductor value calculated with Equation 5-1 is 1.16 µH.
To compensate against component tolerance, choose
the next higher standard value 1.5 µH (typically 20% for
high current inductors).
The peak current in the inductor can be calculated with
Equation 5-2, its value being 17.25A. The inductor
must sustain, without saturating, this peak current. To
maintain low-conduction losses, the DC resistance of
the inductor must be as low as possible. Table 6-2
shows some suitable inductors for this application.
TABLE 6-2:
SUITABLE INDUCTORS FROM VARIOUS VENDORS
Vendor
Part Number
Inductance
(µH)
DCR
(m)
ISAT
(A)
Coilcraft®
XAL1010-152MEB
1.5
1.76
36.6
Wurth Elektronik®
7443320150
1.5
2.1
27
TDK -
EPC®
Bourns®
B82559A0142A013
1.4
1.5
22
SRP1270-1R5M
1.5
2.1
48
 2012 Microchip Technology Inc.
DS22326A-page 27
MCP19035
6.0.2
INPUT CAPACITOR SELECTION
The converter operates with a maximum duty cycle of
22.5%. A ceramic capacitor (X7R dielectric) with a
10 m ESR (typical) will be used. The minimum
capacitance for input capacitor, calculated in
Equation 5-4, is 32.7 µF. Use two standard 22 µF
capacitors (X7R) rated at 25VDC in parallel.
6.0.3
OUTPUT CAPACITOR SELECTION
Based on a step load from 25% to 75% of the maximum
output current, the minimum value for the output capacitor can be determined with Equation 5-7. The minimum value is 456 µF. Choose the next higher standard
value (500 µF). The ESR of the output capacitor will
strongly affect the output voltage ripple. Use five
100 µF standard ceramic capacitors (X7R or X5R
dielectric) rated at 6.3VDC in parallel. The estimated
final value of the ESR is lower than 5 m. The output
voltage ripple is now estimated with Equation 5-6.
6.0.4
MOSFETS SELECTION
Before the MOSFET selection, the total losses of the
converter should be estimated. For this application, the
input power can be estimated using Equation 6-1:
EQUATION 6-1:
INPUT POWER
U OUT  IOUTmax
PIN = -----------------------------------------Eff
The total power losses are estimated in Equation 6-2:
EQUATION 6-2:
TOTAL CONVERTER
LOSSES
P LOSS = P IN – POUT
To achieve the efficiency goal (90%), the total power
losses must be lower than 2W at 10A output current.
Table 6-3 shows how these losses are distributed over
the converter components. The power losses distribution varies with the design parameters. As a rule of
thumb, for designs that have higher conversion ratio
(low duty cycles), the losses for the high-side MOSFET
are mainly switching losses. For the low side, most of
the losses will be the conduction losses.
TABLE 6-3:
ESTIMATION OF THE POWER
LOSSES DISTRIBUTION
Component
Losses (%)
High-Side MOSFET
36
Low-Side MOSFET
40
Inductor
10
Input Capacitor
2
Output Capacitor
1
PWM Controller
10
Traces DC Resistance
1
An important part of the total power losses (over 75%)
are dissipated by the MOSFETs.
For the high-side MOSFET, the total amount of losses
(conduction and switching losses) should not exceed
0.72W. This design has a higher conversion ratio
(greater than 7:1), thus most of the losses of the highside MOSFET will be switching losses. As a rule of
thumb, the switching losses will be considered to be
70% of the total losses.
The conduction losses for the high-side MOSFET are
estimated in Equation 5-10. High-side MOSFET
conduction losses are high at low input voltages. The
maximum RDS(on) for the high-side MOSFET is:
EQUATION 6-3:
MAXIMUM
HIGH-SIDE RDS(ON)
PLOSS High – Side
R DS  on  = -----------------------------------------  0.3
I RMS High – Side2
For this design, where IRMS High-Side = 3.9A at 12V
input voltage and 10A output current, the high-side
MOSFET should have a RDS(On) lower than 14 mΩ.
For the high-side MOSFET, most of the losses are
switching losses (70%). The maximum total gate
charge for the high-side MOSFET is:
EQUATION 6-4:
MAXIMUM TOTAL
GATE CHARGE FOR
THE HIGH-SIDE MOSFET
P LOSS High – Side
Q G  Total  = -------------------------------------------------------  0.7
V IN  Max   I OUT  f SW
The maximum Total Gate Charge (QG(Total)) at 4.5V
VGS should be lower than 12 nC (calculated for 10A
output current).
DS22326A-page 28
 2012 Microchip Technology Inc.
MCP19035
For the low-side MOSFET, losses are mainly
conduction losses. As a rule of thumb, the conduction
losses are considered to be 85% of the total losses. For
this design, the maximum power losses (estimated at
12V input voltage and 10A output current) for low-side
should be lower than 0.9W. Estimate the maximum
RDS(On) for the low-side MOSFET using Equation 6-5:
EQUATION 6-5:
MAXIMUM RD(ON) OF
LOW-SIDE MOSFET
P LOSS Low – Side
RDS  on  = ----------------------------------------  0.85
IRMS Low – Side2
In this design, IRMS Low-Side = 9.3A at 12V input
voltage, 10A output current and the maximum RDS(On)
for low-side MOSFET = 7.8 m.
For this design, the Microchip's MCP87050 and
MCP87022 high-performance MOSFETs can be used.
Calculate the total losses introduced by these transistors using the provided equations. For the high-side
MOSFET (MCP87050), the total loss is 0.66W. The
low-side MOSFET (MCP87022) will dissipate a 0.3W
loss.
The peak current for the low-side MOSFET is:
EQUATION 6-7:
MAXIMUM PEAK
CURRENT FOR A
LOW-SIDE MOSFET
I MAX
LS
0.18
= -----------------------R DS  on LS
For this design, the maximum peak current that flows
into the low-side MOSFET is 81A.
6.0.8
FEEDBACK LOOP COMPENSATION
For this design, the crossover frequency is 30 kHz,
while the resonant frequency of LC tank is 5.88 kHz.
With these parameters, and following the design
procedure described in Section 5.2, Design
Procedure, the value for compensation network
components can be calculated.
TABLE 6-4:
COMPENSATION NETWORK
COMPONENTS
Component
Value
Standard Value
R1
20 k
20 k
BOOTSTRAP CAPACITOR
SELECTION
R2
10 k
10 k
R3
0.774 k
0.75 k
From Equation 5-19, the value of the Bootstrap
Capacitor should be higher than 276 nF. Choose the
standard value 330 nF ceramic capacitor (X7R) rated
at 16 VDC.
R4
8.6 k
8.2 k
C1
1.37 nF
1.2 nF
C2
6.36 nF
6.8 nF
C3
61 pF
68 pF
6.0.5
6.0.6
DEAD TIME (DT) SELECTION
The MOSFET used in this design has a low Figure of
Merit parameter. The overall efficiency of the converter
can be improved by choosing the MCP19035 with
optimized Dead Time.
The components used for the compensation network
must be of good quality and tolerance. The
recommended dielectric for capacitors is C0G and the
tolerance 5%. The recommended tolerance for
resistors is 1%.
6.0.7
6.0.9
OVERCURRENT PROTECTION
THRESHOLDS
The MCP19035 controller provides two fixed threshold
for high and low-side overcurrent protection circuits.
These thresholds are 480 mV (typical) for high-side
and 180 mV (typical) for the low-side. The peak current
for the high-side is:
EQUATION 6-6:
I MAX
MAXIMUM PEAK
CURRENT FOR A
HIGH-SIDE MOSFET
HS
0.48
= ------------------------RDS  on HS
For this design, the maximum peak current that flows
into the high-side MOSFET is 87A.
 2012 Microchip Technology Inc.
LAYOUT RECOMMENDATIONS
Good printed circuit board layout techniques are
important to any switching circuitry, and switching
power supplies are no different. Here are the guidelines
for the PCB layout:
• The exposed pad of MCP19035 DFN case is the
only connection to the internal device ground.
Connect this pad directly to the board ground
plane.
• Place at least four vias in the exposed pad land to
help remove heat from the device.
• Use separate grounds for power and signal paths.
Keep high current paths away from sensitive
components and nodes (ex. feedback and
compensation network components).
• Four layer PCBs are highly recommended to
obtain optimum results regarding noise/EMI. Use
an internal layer as ground plane.
• For double layer boards, a single ground plane
DS22326A-page 29
MCP19035
(usually the bottom) is recommended.
• Use short, wide traces for the MOSFET’s gate
drive connection (LDRV and HDRV signals).
• Place the main MOSFET (control/high-side MOSFET) as close as possible to the input capacitors.
• Minimize the connections between MOSFETs, the
inductor and the MCP19035 case (PHASE node).
Place this node over a ground plane to minimize
the radiated noise.
• Place the compensation network components
near the MCP19035 case and connect these
components to a low noise ground (signal
ground).
• Locate the VIN decoupling capacitor close to the
MCP19035 case.
• Locate the Bootstrap Circuit capacitor close to the
MCP19035 case.
• Minimize the area of high frequency current loops.
Figure 6-1 helps the PCB designer to identify the main
high frequency current paths for the Synchronous Buck
Converter.
CIN
Q1
MCP19035
IIN
HDRV
IHDRV
L1
PHASE
Q2
IRR
LDRV
ISR
COUT
RL
ILDRV
GND
Where:
IIN = Input Converter current
ISR = Current through the Synchronous Rectifier (SR) MOSFET
IHDRV and ILDRV = MOSFET drivers’ currents
IRR = Current produced by the Reverse Recovery of the SR MOSFET body diode
FIGURE 6-1:
High Frequency Current Paths.
All these currents contain high-frequency components
and can produce EMI. Minimizing the area of these
loops will reduce the radiated noise.
The Reverse Recovery of the SR MOSFET Body Diode
current is an important source of noise and EMI. This
current, although very short (less than 10 ns), can
easily reach a few hundred amps, especially when
using low ESR capacitors for input bypass and very fast
MOSFETs for switching transistors. If this current
passes through a path that has a high inductance, it will
produce an intense voltage ringing.
DS22326A-page 30
For noise sensitive applications (for example, RF
applications) the excessive voltage ringing in the
PHASE node produced by Reverse Recovery of SR
MOSFET Body Diode can be reduced by placing a lowvalue resistor in series with the bootstrap capacitor.
This resistor will slow down the high-side MOSFET
during low-to-high transition, reducing the slew rate of
the SW node signal. The recommended value for this
resistor is between 2.2Ω and 10Ω, and should be
determined by lab measurements. The penalty of
including this resistor is an efficiency reduction. It
should, however, be no more than 0.5%.
 2012 Microchip Technology Inc.
MCP19035
Figures 6-2 and 6-3 show the difference between
PHASE node voltage with and without this resistor.
FIGURE 6-2:
SW (PHASE) Node With Boot Capacitor Series Resistor.
FIGURE 6-3:
SW (PHASE) Node Without Boot Capacitor Series Resistor.
 2012 Microchip Technology Inc.
DS22326A-page 31
SCHEMATIC AND BILL OF MATERIALS
MCP19035
VIN
J1
1 2
DS22326A-page 32
6.0.10
C10
22uF
PGND
C11
22uF
PGND
R5
1M
Q1
U1
MCP87050
R4
8.2k
C2
C3
3
6.8nF
C12
1uF
HDRV
PHASE
FB
COMP
BOOT
VIN
LDVR
4
5
68pF
SHDN
C4
8
0.33uF
7
PWRGD
MCP19035
L1
9
VCC
1.5uH
Q2
MCP87022
6
11
R6
C13
4.7uF
100k
PGND
PGND
PGND
PGND
R1
 2012 Microchip Technology Inc.
20k
R2
10k
R3
C1
750
1.2nF
SGND
FIGURE 6-4:
Schematic Diagram.
C5
C6
C7
C8
C9
100uF 100uF 100uF 100uF 100uF
VOUT
J2
1 2
2
10
GND
1
SGND
PGND
MCP19035
TABLE 6-5:
Qty Reference
BILL OF MATERIALS
Value
Manufacturer
Manufacturer Part
Number
Description
1
C1
1.2 nF
KEMET®
Electronic Corp.
C0603C122J1GACTU
Cap. Ceramic 1200 PF 100V 5% NP0
0603
1
C2
6.8 nF
KEMET
Electronic Corp.
C0603C682J5GACTU
Cap. Ceramic 6800 PF 50V 5% NP0
0603
1
C3
68 pF
KEMET
Electronic Corp.
C0603C680J1GACTU
Cap. Ceramic 68 PF 100V 5% NP0 0603
1
C4
0.33 µF MURATA
Electronics®
5
C5, C6,
100 µF
C7, C8, C9
TDK® Corporation
C3225X5R0J107M
2
C10, C11
MURATA
Electronics
GRM32ER71E226KE15L Cap. Ceramic 22 µF 25V 10% X7R 1210
1
C12
1 µF
TDK Corporation
CGA4J3X7R1V105K
Cap. Ceramic 1 µF 35V 10% X7R 0805
1
C13
4.7 µF
TDK Corporation
C2012X5R1E475K
Cap. Ceramic 4.7 µF 25V X5R 0805
2
J1, J2
On-Shore
Technology Inc.
ED120/2DS
Terminal Block 5.08 MM Vert. 2 POS
1
L1
Wurth
Electronik Group
7443320150
Inductor Power 1.5 µH 19.5A SMD
1
Q1
Microchip
Technology Inc.
MCP87050T-U/MF
High-Speed N-Channel Power MOSFET,
5x6 mm PDFN
1
Q2
Microchip
Technology Inc.
MCP87022T-U/MF
High-Speed N-Channel Power MOSFET,
5x6 mm PDFN
1
R1
20 kΩ
Panasonic® - ECG ERJ-3EKF2002V
Res. 20k Ohm 1/10W 1% 0603 SMD
1
R2
10 kΩ
Panasonic - ECG
ERJ-3GEYJ103V
Res. 10k Ohm 1/10W 5% 0603 SMD
1
R3
750Ω
Vishay®/Dale
Intertechnology
CRCW0603750RFKEA
Res. 750 OHM 1/10W 1% 0603 SMD
1
R4
8.2 kΩ
Panasonic - ECG
ERJ-3EKF8201V
Res. 8.2k Ohm 1/10W 1% 0603 SMD
1
R5
1 MΩ
Panasonic - ECG
ERJ-3EKF1004V
Res. 1M Ohm 1/10W 1% 0603 SMD
1
R6
100 kΩ Panasonic - ECG
1
U1
22 µF
1.5 µH
Microchip
Technology Inc.
 2012 Microchip Technology Inc.
GRM188R71C334KA01D Cap. Ceramic 0.33 µf 16V 10% X7R
0603
Cap. Ceramic 100 µF 6.3V 20% X5R
1210
ERJ-3EKF1003V
Res. 100k Ohm 1/10W 1% 0603 SMD
MCP19035-AAABE/MF
High Speed Synchronous
Buck Controller
DS22326A-page 33
MCP19035
NOTES:
DS22326A-page 34
 2012 Microchip Technology Inc.
MCP19035
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
10-Lead DFN (3x3x0.9 mm)
Example:
Part Number
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Code
MCP19035-AAAAE/MF
BAFG
MCP19035T-AAAAE/MF
BAFG
MCP19035-AAABE/MF
BAFP
MCP19035T-AAABE/MF
BAFP
BAFG
1209
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2012 Microchip Technology Inc.
DS22326A-page 35
MCP19035
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22326A-page 36
 2012 Microchip Technology Inc.
MCP19035
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2012 Microchip Technology Inc.
DS22326A-page 37
MCP19035
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22326A-page 38
 2012 Microchip Technology Inc.
MCP19035
APPENDIX A:
REVISION HISTORY
Revision A (November 2012)
• Original Release of this Document.
 2012 Microchip Technology Inc.
DS22326A-page 39
MCP19035
NOTES:
DS22326A-page 40
 2012 Microchip Technology Inc.
MCP19035
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -X
X
X
X
X
/XX
Device Switching Reference LDRV OC Dead Temperature Package
Frequency Voltage
Range
Threshold Time
Device:
MCP19035:
MCP19035T:
High-Speed Synchronous Buck Controller
High-Speed Synchronous Buck Controller
(Tape and Reel)
Switching
Frequency:
A =300 kHz
Reference Voltage:
A =600 mV
LDRV OC
Threshold:
A =200 mV
Dead Time:
A =20 ns
B =12 ns
Temperature Range:
E
= -40C to +125C
Package:
MF
=
Examples:
a)
b)
c)
d)
 2012 Microchip Technology Inc.
(Extended)
MCP19035-AAAAE/MF: 300 kHz Switching Freq.,
600 mV VREF, 200 mV
LDRV OC Threshold,
20 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Pkg.
MCP19035T-AAAAE/MF: Tape and Reel,
300 kHz Switching Freq.,
600 mV VREF, 200 mV
LDRV OC Threshold,
20 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Pkg.
MCP19035T-AAABE/MF: Tape and Reel,
300 kHz Switching Freq.,
600 mV VREF, 200 mV
LDRV OC Threshold,
12 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Pkg.
MCP19035T-AAABE/MF: Tape and Reel,
300 kHz Switching Freq.,
600 mV VREF, 200 mV
LDRV OC Threshold,
12 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Pkg.
Plastic Dual Flat, No Lead Package - 3x3x0.9
mm, 10-Lead
DS22326A-page 41
MCP19035
NOTES:
DS22326A-page 42
 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-663-7
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22326A-page 43
Worldwide Sales and Service
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Technical Support:
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DS22326A-page 44
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10/26/12
 2012 Microchip Technology Inc.