PHILIPS ISP1106W Advanced universal serial bus transceiver Datasheet

ISP1105/1106/1107
Advanced Universal Serial Bus transceivers
Rev. 06 — 30 November 2001
Product data
1. General description
The ISP1105/1106/1107 range of Universal Serial Bus (USB) transceivers are fully
compliant with the Universal Serial Bus Specification Rev. 1.1. They are ideal for
portable electronics devices such as mobile phones, digital still cameras, Personal
Digital Assistants (PDA) and Information Appliances (IA).
They allow USB Application Specific ICs (ASICs) and Programmable Logic Devices
(PLDs) with power supply voltages from 1.65 V to 3.6 V to interface with the physical
layer of the Universal Serial Bus. They have an integrated 5 V to 3.3 V voltage
regulator for direct powering via the USB supply VBUS.
The ISP1105/1106/1107 range can be used as a USB device transceiver or a USB
host transceiver. They can transmit and receive serial data at both full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s) data rates.
ISP1105 allows single/differential input modes selectable by a MODE input and it is
available in HBCC16 package. ISP1106 allows only differential input mode and is
available in both TSSOP16 and HBCC16 packages. ISP1107 allows only
single-ended input mode and is available in both TSSOP16 and HBCC16 packages.
2. Features
■
■
■
■
■
■
■
■
■
■
■
■
Complies with Universal Serial Bus Specification Rev. 1.1
Integrated bypassable 5 V to 3.3 V voltage regulator for powering via USB VBUS
VBUS disconnection indication through VP and VM
Used as a USB device transceiver or a USB host transceiver
Supports full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) serial data rates
Stable RCV output during SE0 condition
Two single-ended receivers with hysteresis
Low-power operation
Supports an I/O voltage range from 1.65 V to 3.6 V
4 kV on-chip ESD protection
Full industrial operating temperature range −40 to +85 °C
Available in small TSSOP16 (except ISP1105) and HBCC16 packages.
ISP1105/1106/1107
Philips Semiconductors
Advanced USB transceivers
3. Applications
■ Portable electronic devices, such as:
◆ Mobile phone
◆ Digital still camera
◆ Personal Digital Assistant (PDA)
◆ Information Appliance (IA).
4. Ordering information
Table 1:
Ordering information
Type number
ISP1105W[1]
Package
Name
Description
Version
HBCC16
plastic, heatsink bottom chip carrier; 16 terminals; body 3 × 3 × 0.65 mm
SOT639-2
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
ISP1106W
ISP1107W
ISP1106DH
ISP1107DH
[1]
The ground terminal of ISP1105W is connected to the exposed diepad (heatsink).
4.1 Ordering options
Table 2:
Selection guide
Product
Package(s)
Description
ISP1105
HBCC16
Supports both single-ended and differential input modes[1]
ISP1106
TSSOP16 or HBCC16
Supports only the differential input mode[2]
ISP1107
TSSOP16 or HBCC16
Supports only the single-ended input mode[3]
[1]
[2]
[3]
Refer to Table 5 and Table 6.
Refer to Table 6.
Refer to Table 5.
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
9397 750 08872
Product data
Rev. 06 — 30 November 2001
2 of 24
ISP1105/1106/1107
Philips Semiconductors
Advanced USB transceivers
5. Functional diagram
3.3 V
V CC(I/O)
VOLTAGE
REGULATOR
VCC(5.0)
Vreg(3.3)
Vpu(3.3)
SOFTCON
1.5 kΩ(2)
OE
SPEED
D+
VMO/FSE0(3)
D−
VPO/VO(3)
MODE(4)
SUSPND
RCV
33 Ω(1) (1%)
33 Ω(1) (1%)
LEVEL
SHIFTER
ISP1105
ISP1106
ISP1107
VP
VM
MBL301
GND
(1) Use a 39 Ω resistor (1%) for a USB v2.0 compliant output impedance range.
(2) Connect to D− for low-speed operation.
(3) Pin function depends on device type see Section 7.2.
(4) Only for ISP1105.
Fig 1. Functional diagram (combined ISP1105, ISP1106 and ISP1107).
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
9397 750 08872
Product data
Rev. 06 — 30 November 2001
3 of 24
ISP1105/1106/1107
Philips Semiconductors
Advanced USB transceivers
6. Pinning information
D−
SUSPND
5
10
D+
VM
4
ISP1105W
1
16
15
14
VPO/VO
12
VMO/FSE0
13
Vreg(3.3)
VP
3
RCV
2
OE
1
7
8
ISP1106W
9
D−
10
D+
11
VPO/VO*
12
VMO/FSE0 *
13
Vreg(3.3)
ISP1107W*
Bottom view
MBL303
6
16
15
14
VCC(5.0)
OE
(exposed diepad)
VCC(5.0)
2
GND
Vpu(3.3)
RCV
Bottom view
11
3
SOFTCON
VP
SPEED
9
VCC(I/O)
8
Vpu(3.3)
7
GND
4
6
SOFTCON
VM
SPEED
5
VCC(I/O)
SUSPND
MODE
6.1 Pinning
MBL304
The asterisk (*) denotes that the signal names VO and
FSE0 apply to the ISP1107W.
Fig 2. Pinning diagram HBCC16 (ISP1105).
Fig 3. Pinning diagram HBCC16 (ISP1106 and
ISP1107).
Vpu(3.3) 1
16 VCC(5.0)
SOFTCON 2
15 Vreg(3.3)
14 VMO/FSE0*
OE 3
RCV 4
ISP1106DH
13 VPO/VO*
VP 5
ISP1107DH* 12 D+
VM 6
11 D−
SUSPND 7
10 SPEED
GND 8
9
V CC(I/O)
MBL302
The asterisk (*) denotes that the signal names VO and FSE0 apply to the ISP1107DH.
Fig 4. Pinning diagram TSSOP16 (ISP1106 and ISP1107).
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
9397 750 08872
Product data
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Philips Semiconductors
Advanced USB transceivers
6.2 Pin description
Table 3:
Pin description
Symbol[1]
Pin
Type
Description
ISP1105
HBCC16
ISP1106/7 ISP1106/7
HBCC16
TSSOP16
OE
1
1
3
I
input for output enable (CMOS level with respect to VCC(I/O),
active LOW); enables the transceiver to transmit data on
the USB bus
RCV
2
2
4
O
differential data receiver output (CMOS level with respect to
VCC(I/O)); driven LOW when input SUSPND is HIGH; the
output state of RCV is preserved and stable during an SE0
condition
VP
3
3
5
O
single-ended D+ receiver output (CMOS level with respect
to VCC(I/O)); for external detection of single-ended zero
(SE0), error conditions, speed of connected device; driven
HIGH when no supply voltage is connected to VCC(5.0) and
Vreg(3.3)
VM
4
4
6
O
single-ended D− receiver output (CMOS level with respect
to VCC(I/O)); for external detection of single-ended zero
(SE0), error conditions, speed of connected device; driven
HIGH when no supply voltage is connected to VCC(5.0) and
Vreg(3.3)
SUSPND
5
5
7
I
suspend input (CMOS level with respect to VCC(I/O)); a
HIGH level enables low-power state while the USB bus is
inactive and drives output RCV to a LOW level
MODE
6
I
mode input (CMOS level with respect to VCC(I/O)); a HIGH
level enables the differential input mode (VPO, VMO)
whereas a LOW level enables a single-ended input mode
(VO, FSE0). see Table 5 and Table 6
GND
-[2]
6
8
-
ground supply
VCC(I/O)
7
7
9
-
supply voltage for digital I/O pins (1.65 to 3.6 V). When
VCC(I/O) is not connected, the (D+, D−) pins are in
three-state. This supply pin is totally independent of
VCC(5.0) and Vreg(3.3) and must never exceed the Vreg(3.3)
voltage.
SPEED
8
8
10
I
speed selection input (CMOS level with respect to VCC(I/O));
adjusts the slew rate of differential data outputs D+ and D−
according to the transmission speed:
LOW: low-speed (1.5 Mbit/s)
HIGH: full-speed (12 Mbit/s)
D−
9
9
11
AI/O
negative USB data bus connection (analog, differential); for
low-speed mode connect to pin Vpu(3.3) via a 1.5 kΩ resistor
D+
10
10
12
AI/O
positive USB data bus connection (analog, differential); for
full-speed mode connect to pin Vpu(3.3) via a 1.5 kΩ resistor
VPO/VO
11
11
13
I
driver data input (CMOS level with respect to VCC(I/O),
Schmitt trigger); see Table 5 and Table 6
VMO/FSE0
12
12
14
I
driver data input (CMOS level with respect to VCC(I/O),
Schmitt trigger); see Table 5 and Table 6
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
9397 750 08872
Product data
Rev. 06 — 30 November 2001
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ISP1105/1106/1107
Philips Semiconductors
Advanced USB transceivers
Table 3:
Pin description…continued
Symbol[1]
Vreg(3.3)
Pin
ISP1105
HBCC16
ISP1106/7 ISP1106/7
HBCC16
TSSOP16
13
13
15
Type
Description
-
Internal regulator option: regulated supply voltage output
(3.0 to 3.6 V) during 5 V operation; a decoupling capacitor
of at least 0.1 µF is required
Regulator bypass option: used as a supply voltage input
for 3.3 V operation. (3.3 V ±10%)
VCC(5.0)
14
14
16
-
Internal regulator option: supply voltage input
(4.0 to 5.5 V); can be connected directly to USB supply
VBUS
Regulator bypass option: connect to Vreg(3.3)
Vpu(3.3)
15
15
1
pull-up supply voltage (3.3 V ±10%); connect an external
1.5 kΩ resistor on D+ (full-speed) or D− (low-speed); pin
function is controlled by input SOFTCON:
-
SOFTCON = LOW — Vpu(3.3) floating (high impedance);
ensures zero pull-up current
SOFTCON = HIGH — Vpu(3.3) = 3.3 V; internally connected
to Vreg(3.3)
SOFTCON
[1]
[2]
16
16
2
I
software controlled USB connection input; a HIGH level
applies 3.3 V to pin Vpu(3.3), which is connected to an
external 1.5 kΩ pull-up resistor; this allows USB
connect/disconnect signalling to be controlled by software
Symbol names with an overscore (e.g. NAME) indicate active LOW signals.
Down bonded to the exposed diepad.
7. Functional description
7.1 Function selection
Table 4:
Function table
SUSPND
OE
(D+, D−)
RCV
VP/VM
Function
L
L
driving &
receiving
active
active
normal driving
(differential receiver active)
L
H
receiving[1]
active
active
receiving
active
driving during ‘suspend’[3]
(differential receiver inactive)
active
low-power state
[1]
[2]
[3]
H
L
driving
inactive[2]
H
H
high-Z[1]
inactive[2]
Signal levels on (D+, D−) are determined by other USB devices and external pull-up/down resistors.
In ‘suspend’ mode (SUSPND = HIGH) the differential receiver is inactive and output RCV is always
LOW. Out-of-suspend (‘K’) signalling is detected via the single-ended receivers VP and VM.
During suspend, the slew-rate control circuit of low-speed operation is disabled. The (D+, D−) lines
are still driven to their intended states, without slew-rate control. This is permitted because driving
during suspend is used to signal remote wake-up by driving a ‘K’ signal (one transition from idle to
‘K’ state) for a period of 1 to 15 ms.
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
9397 750 08872
Product data
Rev. 06 — 30 November 2001
6 of 24
ISP1105/1106/1107
Philips Semiconductors
Advanced USB transceivers
7.2 Operating functions
Table 5:
Driving function using single-ended input data interface (OE = L) [for
ISP1107 and ISP1105 (MODE = L)]
FSE0
VO
Data
L
L
differential logic 0
L
H
differential logic 1
H
L
SE0
H
H
SE0
Driving function using differential input data interface (OE = L) [for ISP1106
and ISP1105 (MODE = H)]
Table 6:
VMO
VPO
Data
L
L
SE0
L
H
differential logic 1
H
L
differential logic 0
H
H
illegal state
Table 7:
[1]
[2]
Receiving function (OE = H)
(D+, D−)
RCV
VP[1]
VM[1]
differential logic 0
L
L
H
differential logic 1
H
H
L
SE0
RCV*[2]
L
L
VP = VM = H indicates the sharing mode (VCC(5.0)/Vreg(3.3) is disconnected).
RCV* denotes the signal level on output RCV just before SE0 state occurs. This level is stable during
the SE0 period.
7.3 Power supply configurations
The ISP1105/1106/1107 can be used with different power supply configurations,
which can be changed dynamically. An overview is given in Table 9.
Normal mode — Both VCC(I/O) and VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected.
For 5 V operation, VCC(5.0) is connected to a 5 V source (4.0 to 5.5 V). The internal
voltage regulator then produces 3.3 V for the USB connections. For 3.3 V operation,
both VCC(5.0) and Vreg(3.3) are connected to a 3.3 V source (3.0 to 3.6 V). VCC(I/O) is
independently connected to a voltage source (1.65 V to 3.6 V), depending on the
supply voltage of the external circuit.
Disable mode — VCC(I/O) is not connected, VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are
connected. In this mode, the internal circuits of the ISP1105/1106/1107 ensure that
the (D+, D−) pins are in three-state and the power consumption drops to the
low-power (suspended) state level. Some hysteresis is built into the detection of
VCC(I/O) lost.
Sharing mode — VCC(I/O) is connected, (VCC(5.0) and Vreg(3.3)) are not connected. In
this mode, the (D+, D−) pins are made three-state and the ISP1105/1106/1107 allows
external signals of up to 3.6 V to share the (D+, D−) lines. The internal circuits of the
ISP1105/1106/1107 ensure that virtually no current (maximum 10 µA) is drawn via
the (D+, D−) lines. The power consumption through pin VCC(I/O) drops to the
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
9397 750 08872
Product data
Rev. 06 — 30 November 2001
7 of 24
ISP1105/1106/1107
Philips Semiconductors
Advanced USB transceivers
low-power (suspended) state level. Both the VP and VM pins are driven HIGH to
indicate this mode. Pin RCV is made LOW. Some hysteresis is built into the detection
of Vreg(3.3) lost.
Table 8:
Pin states in Disable or Sharing mode
Pins
VCC(5.0)/Vreg(3.3)
Disable mode state
Sharing mode state
5 V input / 3.3 V output
3.3 V input / 3.3 V input
not present
VCC(I/O)
not present
1.65 V to 3.6 V input
Vpu(3.3)
high impedance (off)
high impedance (off)
(D+, D−)
high impedance
high impedance
(VP, VM)
invalid[1]
H
RCV
invalid[1]
L
high impedance
high impedance
Inputs (VO/VPO, FSE0/VMO,
SPEED, MODE[2], SUSPND, OE,
SOFTCON)
[1]
[2]
High impedance or driven LOW.
ISP1105 only.
Table 9:
Power supply configuration overview
VCC(5.0) or
Vreg(3.3)
VCC(I/O)
Configuration
Special characteristics
connected
connected
Normal mode
-
connected
not connected
Disable mode
(D+, D−) and Vpu(3.3) high
impedance; VP, VM, RCV:
invalid[1]
not connected
connected
Sharing mode
(D+, D−) and Vpu(3.3) high
impedance;
VP, VM driven HIGH;
RCV driven LOW
[1]
High impedance or driven LOW.
7.4 Power supply input options
The ISP1105/1106/1107 range has two power supply input options:
Internal regulator — VCC(5.0) is connected to 4.0 to 5.5 V. The internal regulator is
used to supply the internal circuitry with 3.3 V (nominal). The Vreg(3.3) pin becomes a
3.3 V output reference.
Regulator bypass — VCC(5.0) and Vreg(3.3) are connected to the same supply. The
internal regulator is bypassed and the internal circuitry is supplied directly from the
Vreg(3.3) power supply. The voltage range is 3.0 to 3.6 V to comply with the USB
specification.
The supply voltage range for each input option is specified in Table 10.
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
9397 750 08872
Product data
Rev. 06 — 30 November 2001
8 of 24
ISP1105/1106/1107
Philips Semiconductors
Advanced USB transceivers
Table 10:
Power supply input options
Input option
VCC(5.0)
Vreg(3.3)
VCC(I/O)
Internal
regulator
supply input for internal voltage reference
regulator
output
(4.0 to 5.5 V)
(3.3 V, 300 µA)
supply input for digital
I/O pins
(1.65 V to 3.6 V)
Regulator
bypass
connected to Vreg(3.3)
with maximum voltage
drop of 0.3 V
(2.7 to 3.6 V)
supply input for digital
I/O pins
(1.65 V to 3.6 V)
supply input
(3.0 V to 3.6 V)
8. Limiting values
Table 11: Absolute maximum ratings
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
VCC(5.0)
supply voltage
−0.5
+6.0
V
VCC(I/O)
I/O supply voltage
−0.5
+4.6
V
Vreg(3.3)
regulated supply voltage
−0.5
+4.6
V
VI
DC input voltage
−0.5
VCC(I/O) + 0.5
V
Ilatchup
latch-up current
-
100
mA
-
±4000
V
-
±2000
V
−40
+125
°C
electrostatic discharge
Vesd
Conditions
VI = −1.8 to 5.4 V
ILI < 1 µA
voltage[1]
pins D+, D−, VCC(5.0),
Vreg(3.3), GND
other pins
Tstg
[1]
storage temperature
Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor (Human Body Model). Refer to EIA/JEDEC Standard specification
EIA/JESD22-A114-A.
Table 12:
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC(5.0)
supply voltage (Internal
regulator option)
5 V operation
4.0
5.0
5.5
V
Vreg(3.3)
supply voltage (Regulator
bypass option)
3.3 V operation
3.0
3.3
3.6
V
VCC(I/O)
I/O supply voltage
1.65
-
3.6
V
VI
input voltage
0
-
VCC(I/O)
V
VI(AI/O)
input voltage on analog I/O
pins (D+/D−)
0
-
3.6
V
Tamb
operating ambient temperature
−40
-
+85
°C
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9397 750 08872
Product data
Rev. 06 — 30 November 2001
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ISP1105/1106/1107
Philips Semiconductors
Advanced USB transceivers
9. Static characteristics
Table 13: Static characteristics: supply pins
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
[1]
Min
Typ
Max
Unit
3.0[2]
3.3
3.6
V
Vreg(3.3)
regulated supply voltage
output
Internal regulator option;
Iload ≤ 300 µA
ICC
operating supply current
full-speed transmitting and receiving
at 12 Mbit/s; CL = 50 pF on D+/D−
-
4
8[3]
mA
ICC(I/O)
operating I/O supply current
full-speed transmitting and receiving
at 12 Mbit/s
-
1
2[3]
mA
ICC(idle)
supply current during
full-speed idle and SE0
full-speed idle: VD+ > 2.7 V,
VD− < 0.3 V; SE0: VD+ < 0.3 V,
VD− < 0.3 V
-
-
500
µA
ICC(I/O)(static)
static I/O supply current
full-speed idle, SE0 or suspend
ICC(susp)
ICC(dis)
suspend supply current
SUSPND = HIGH
disable mode supply current VCC(I/O) not connected
[4]
-
-
20
µA
[4]
-
-
20
µA
[4]
-
-
20
µA
ICC(I/O)(sharing) sharing mode I/O supply
current
VCC(5.0) or Vreg(3.3) not connected
-
-
20
µA
IDx(sharing)
sharing mode load current
on pins D+ and D−
VCC(5.0) or Vreg(3.3) not connected;
SOFTCON = LOW; VDx = 3.6 V
-
-
10
µA
Vth(reg3.3)
regulated supply voltage
detection threshold
1.65 V ≤ VCC(I/O) ≤ Vreg(3.3);
2.7 V ≤ Vreg(3.3) ≤ 3.6 V
supply lost
-
-
0.8
V
supply present
2.4[5]
-
-
V
-
0.45
-
V
supply lost
-
-
0.5
V
supply present
1.4
-
-
V
-
0.45
-
V
Vhys(reg3.3)
regulated supply voltage
detection hysteresis
VCC(I/O) = 1.8 V
Vth(I/Osup)
I/O supply voltage detection
threshold
Vreg(3.3) = 2.7 to 3.6 V
Vhys(I/Osup)
[1]
[2]
[3]
[4]
[5]
I/O supply voltage detection
hysteresis
Vreg(3.3) = 3.3 V
Iload includes the pull-up resistor current via pin Vpu(3.3).
In ‘suspend’ mode, the minimum voltage is 2.7 V.
Characterized only, not tested in production.
Excluding any load current and Vpu(3.3)/Vsw source current to the 1.5 kΩ and 15 kΩ pull-up and pull-down resistors (200 µA typ.).
When VCC(I/O) < 2.7 V, the minimum value for Vth(reg3.3)(present) is 2.0 V.
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
9397 750 08872
Product data
Rev. 06 — 30 November 2001
10 of 24
ISP1105/1106/1107
Philips Semiconductors
Advanced USB transceivers
Table 14: Static characteristics: digital pins
VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC(I/O) = 1.65 to 3.6 V
Input levels
VIL
LOW-level input voltage
-
-
0.3VCC(I/O)
V
VIH
HIGH-level input voltage
0.6VCC(I/O)
-
-
V
Output levels
VOL
LOW-level output voltage
VOH
HIGH-level output voltage
IOL = 100 µA
-
-
0.15
V
IOL = 2 mA
-
-
0.4
V
IOH = 100 µA
VCC(I/O) − 0.15 -
-
V
IOH = 2 mA
VCC(I/O) − 0.4
-
-
V
-
-
±1
µA
Leakage current
ILI
input leakage current
Example 1: VCC(I/O) = 1.8 V ± 0.15 V
Input levels
VIL
LOW-level input voltage
-
-
0.5
V
VIH
HIGH-level input voltage
1.2
-
-
V
IOL = 100 µA
-
-
0.15
V
Output levels
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
IOL = 2 mA
-
-
0.4
V
IOH = 100 µA
1.5
-
-
V
IOH = 2 mA
1.25
-
-
V
Example 2: VCC(I/O) = 2.5 V ± 0.2 V
Input levels
VIL
LOW-level input voltage
-
-
0.7
V
VIH
HIGH-level input voltage
1.7
-
-
V
Output levels
VOL
LOW-level output voltage
VOH
HIGH-level output voltage
IOL = 100 µA
-
-
0.15
V
IOL = 2 mA
-
-
0.4
V
IOH = 100 µA
2.15
-
-
V
IOH = 2 mA
1.9
-
-
V
Example 3: VCC(I/O) = 3.3 V ± 0.3 V
Input levels
VIL
LOW-level input voltage
-
-
0.9
V
VIH
HIGH-level input voltage
2.15
-
-
V
IOL = 100 µA
-
-
0.15
V
IOL = 2 mA
-
-
0.4
V
IOH = 100 µA
2.85
-
-
V
IOH = 2 mA
2.6
-
-
V
pin to GND
-
-
10
pF
Output levels
VOL
LOW-level output voltage
VOH
HIGH-level output voltage
Capacitance
CIN
input capacitance
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Table 15: Static characteristics: analog I/O pins (D+, D−)
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VGND = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input levels
Differential receiver
VDI
differential input sensitivity
|VI(D+) − VI(D−)|
0.2
-
-
V
VCM
differential common mode
voltage
includes VDI range
0.8
-
2.5
V
Single-ended receiver
VIL
LOW-level input voltage
-
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
-
V
Vhys
hysteresis voltage
0.4
-
0.7
V
RL = 1.5 kΩ to +3.6 V
-
-
0.3
V
RL = 15 kΩ to GND
2.8[1]
-
3.6
V
-
-
±1
µA
-
-
20
pF
Output levels
LOW-level output voltage
VOL
VOH
HIGH-level output voltage
Leakage current
OFF-state leakage current
ILZ
Capacitance
transceiver capacitance
pin to GND
ZDRV
driver output impedance
steady-state drive
[2]
34
39
44
Ω
ZDRV2
driver output impedance for
USB 2.0
steady-state drive
[3]
40.5
45
49.5
Ω
ZINP
input impedance
10
-
-
MΩ
RSW
internal switch resistance at
pin Vpu(3.3)
-
-
10
Ω
termination voltage for
upstream port pull-up (RPU)
3.0[5]
-
3.6
V
CIN
Resistance
Termination
VTERM[4]
[1]
[2]
[3]
[4]
[5]
VOH(min) = Vreg(3.3) − 0.2 V.
Includes external resistors of 33 Ω ±1% on both D+ and D−.
Includes external resistors of 39 Ω ±1% on both D+ and D−. This range complies with Universal Serial Bus Specification Rev. 2.0.
This voltage is available at pins Vreg(3.3) and Vpu(3.3).
In ‘suspend’ mode the minimum voltage is 2.7 V.
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10. Dynamic characteristics
Table 16: Dynamic characteristics: analog I/O pins (D+, D−)[1]
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
Full-speed mode (SPEED = HIGH)
tFR
rise time
CL = 50 to 125 pF;
10 to 90% of |VOH − VOL|;
see Figure 5
4
-
20
ns
tFF
fall time
CL = 50 to 125 pF;
90 to 10% of |VOH − VOL|;
see Figure 5
4
-
20
ns
FRFM
differential rise/fall time
matching (tFR/tFF)
excluding the first transition
from Idle state
90
-
111.1
%
VCRS
output signal crossover
voltage
excluding the first transition
from Idle state; see Figure 8
1.3
-
2.0
V
[2]
Low-speed mode (SPEED = LOW)
tLR
rise time
CL = 50 to 600 pF;
10 to 90% of |VOH − VOL|;
see Figure 5
75
-
300
ns
tLF
fall time
CL = 50 to 600 pF;
90 to 10% of |VOH − VOL|;
see Figure 5
75
-
300
ns
LRFM
differential rise/fall time
matching (tLR/tLF)
excluding the first transition
from Idle state
80
-
125
%
VCRS
output signal crossover
voltage
excluding the first transition
from idle state; see Figure 8
1.3
-
2.0
V
[2]
Driver timing
Full-speed mode (SPEED = HIGH)
tPLH(drv)
driver propagation delay
LOW-to-HIGH; see Figure 8
-
-
18
ns
tPHL(drv)
(VO/VPO, FSE0/VMO to
D+,D−)
HIGH-to-LOW; see Figure 8
-
-
18
ns
tPHZ
driver disable delay
HIGH-to-OFF; see Figure 6
-
-
15
ns
tPLZ
(OE to D+,D−)
LOW-to-OFF; see Figure 6
-
-
15
ns
tPZH
driver enable delay
OFF-to-HIGH; see Figure 6
-
-
15
ns
tPZL
(OE to D+,D−)
OFF-to-LOW; see Figure 6
-
-
15
ns
Low-speed mode (SPEED = LOW)
Not specified: low-speed delay timings are dominated by the slow rise/fall times tLR and tLF.
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Table 16: Dynamic characteristics: analog I/O pins (D+, D−)[1]…continued
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Receiver timings (full-speed and low-speed mode)
Differential receiver
tPLH(rcv)
propagation delay
LOW-to-HIGH; see Figure 7
-
-
15
ns
tPHL(rcv)
(D+,D− to RCV)
HIGH-to-LOW; see Figure 7
-
-
15
ns
Single-ended receiver
tPLH(se)
propagation delay
LOW-to-HIGH; see Figure 7
-
-
18
ns
tPHL(se)
(D+,D− to VP, VM)
HIGH-to-LOW; see Figure 7
-
-
18
ns
[1]
[2]
Test circuit: see Figure 11.
Characterized only, not tested. Limits guaranteed by design.
1.65 V
logic input
t FR, t LR
VOH
0V
t FF, t LF
90%
10%
VOH
10%
MGS963
Fig 5. Rise and fall times.
VOH −0.3 V
VCRS
VOL +0.3 V
VOL
MGS966
Fig 6. Timing of OE to D+, D−.
2.0 V
differential
data lines
t PHZ
t PLZ
t PZH
t PZL
90%
differential
data lines
VOL
0.9 V
0.9 V
1.65 V
VCRS
VCRS
logic input
0.8 V
t PLH(rcv)
t PLH(se)
0V
t PHL(rcv)
t PHL(se)
t PLH(drv)
VOH
logic output
t PHL(drv)
VOH
0.9 V
VOL
Fig 7. Timing of D+, D− to RCV, VP, VM.
differential
data lines
0.9 V
MGS965
VCRS
VCRS
VOL
MGS964
Fig 8. Timing of VO/VPO, FSE0/VMO to D+, D−.
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0.9 V
0.9 V
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11. Test information
test point
33 Ω(1)
500 Ω
D.U.T.
50 pF
V
MBL142
V = 0 V for tPZH, tPHZ
V = Vreg(/3.3) for tPZL, tPLZ
(1) Complies with USB 1.1. For USB 2.0 a resistor of 39 Ω must be used.
Fig 9. Load for enable and disable times.
test point
D.U.T.
25 pF
MGS968
Fig 10. Load for VM, VP and RCV.
Vpu(3.3)
1.5 kΩ (1)
D.U.T.
test point
D+/D−
33 Ω(2)
CL
15 kΩ
MGS967
Load capacitance:
CL = 50 pF or 125 pF (full-speed mode, minimum or maximum timing)
CL = 50 pF or 600 pF (low-speed mode, minimum or maximum timing)
(1) Full-speed mode: connected to D+, low-speed mode: connected to D−.
(2) Complies with USB 1.1. For USB 2.0 a resistor of 39 Ω must be used.
Fig 11. Load for D+, D−.
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12. Package outline
HBCC16: plastic thermal enhanced bottom chip carrier; 16 terminals; body 3 x 3 x 0.65 mm
b
D
B
SOT639-2
v M C A B
w M C
A
f
terminal 1
index area
v M C A B
w M C
b1
E
b2
b2
v M C A B
w M C
v M C A B
w M C
detail X
e1
C
Dh
e
y
y1 C
5
9
e
e4
Eh e2
1/2 e4
1
13
16
A1
X
1/2 e3
A2
e3
A
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
b1
b2
D
Dh
E
Eh
e
e1
e2
e3
e4
f
v
w
y
y1
mm
0.8
0.10
0.05
0.7
0.6
0.33
0.27
0.33
0.27
0.38
0.32
3.1
2.9
1.45
1.35
3.1
2.9
1.45
1.35
0.5
2.5
2.5
2.45
2.45
0.23
0.17
0.08
0.1
0.05
0.2
OUTLINE
VERSION
REFERENCES
IEC
SOT639-2
JEDEC
JEITA
MO-217
EUROPEAN
PROJECTION
ISSUE DATE
01-11-13
Fig 12. HBCC16 package outline.
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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
0o
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
SOT403-1
JEDEC
EIAJ
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
95-04-04
99-12-27
Fig 13. TSSOP16 package outline.
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13. Packaging
The ISP1105/1106/1107W (HBCC16 package) is delivered on a Type A carrier tape,
see Figure 14. The tape dimensions are given in Table 17.
The reel diameter is 330 mm. The reel is made of polystyrene (PS) and is not
designed for use in a baking process.
The cumulative tolerance of 10 successive sprocket holes is ±0.02 mm. The camber
must not exceed 1 mm in 100 mm.
4
idth
W
A0
K0
B0
P1
Type A
direction of feed
4
W
A0
K0
B0
elongated
sprocked hole
P1
Type B
direction of feed
MLC338
Fig 14. Carrier tape dimensions.
Table 17:
Type A carrier tape dimensions for ISP1105/1106/1107W
Dimension
Value
Unit
A0
3.3
mm
B0
3.3
mm
K0
1.1
mm
P1
8.0
mm
W
12.0 ±0.3
mm
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14. Soldering
14.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface
temperature of the packages should preferable be kept below 220 °C for thick/large
packages, and below 235 °C small/thin packages.
14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
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During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the
need for removal of corrosive residues in most applications.
14.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
14.5 Package related soldering information
Table 18:
Suitability of surface mount IC packages for wave and reflow soldering
methods
Package
Soldering method
BGA, HBGA, LFBGA, SQFP, TFBGA
Reflow[1]
not suitable
suitable
suitable[2]
HBCC, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, SMS
not
PLCC[3], SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
[1]
[2]
[3]
[4]
[5]
suitable
suitable
not
recommended[3][4]
suitable
not
recommended[5]
suitable
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
These packages are not suitable for wave soldering as a solder joint between the printed-circuit board
and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top
version).
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger
than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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15. Additional soldering information
15.1 (H)BCC packages: footprint
The surface material of the terminals on the resin protrusion consists of a 4-layer
metal structure (Au, Pd, Ni and Pd). The Au + Pd layer (0.1 µm min.) ensures
solderability, the Ni layer (5 µm min.) prevents diffusion, and the Pd layer on top
(0.5 µm min.) ensures effective wire bonding.
Terminal
PCB land
Solder resist mask
Stencil mask
All dimensions in mm
Normal
0.05
b1
Solder land
0.05
b1
b
Solder resist
b
Solder stencil
0.05
0.05
Corner
0.05
b2
b2
0.05
For exact dimensions
see package outline
drawing (SOT639-2)
b2
b2
0.05
0.05
Cavity
0.05
0.3 (8×)
Stencil print thickness:
0.1 to 0.12 mm
Eh
0.1
(4×)
Eh
004aaa123
Dh
Dh
0.05
Cavity: exposed diepad, either functioning as heatsink or as ground connection; only for HBCC packages.
Fig 15. (H)BCC footprint and solder resist mask dimensions.
15.2 (H)BCC packages: reflow soldering profile
The conditions for reflow soldering of (H)BCC packages are as follows:
• Preheating time: minimum 90 s at T = 145 to 155 °C
• Soldering time: minimum 90 s (BCC) or minimum 100 s (HBCC) at T > 183 °C
• Peak temperature:
– Ambient temperature: Tamb(max) = 260 °C
– Device surface temperature: Tcase(max) = 255 °C.
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16. Revision history
Table 19:
Revision history
Rev Date
06
20011130
CPCN
Description
-
Product data; sixth version. Supersedes ISP1105_1106_1107-05 of 3 Sept 2001 (9397
750 08643). Modifications:
•
Changed the HBCC16 package version from SOT639-1 to SOT639-2 in:
– Table 1 “Ordering information” on page 2.
– Section 12 “Package outline” on page 16.
– Figure 15 “(H)BCC footprint and solder resist mask dimensions.” on page 21.
•
05
20010903
-
Product data; fifth version. Supersedes ISP1105_1106_1107-04 of 2 Aug 2001 (9397
750 08643). Modifications:
•
04
20010802
-
Section 7.4 “Power supply input options”: Removed the last sentence “The internal
regulator is not used in single-ended mode and is shutdown.” from the Internal regulator
definition.
Replaced front-page logo with new USB basic-speed logo.
Preliminary data; fourth version. Supersedes ISP1105_1106_1107-03 of 4 July 2001
(9397 750 08515). Modifications:
•
•
Section 1 “General description”: removed backward compatibility with PDIUSBP11A.
Section 2 “Features”:
– Removed backward compatibility with PDIUSBP11A.
– Added ‘on-chip’ for the ESD protection.
– Changed the I/O voltage range from ‘1.8 V, 2.5 V or 3.3 V’ into ‘1.65 V to 3.6 V’.
•
•
Section 6.2 “Pin description”: changed the description for pin VCC(I/O).
Section 7.3 “Power supply configurations”: changed VCC(I/O) range from ‘1.8 V, 2.5 V or
3.3 V’ into ‘1.65 to 3.6 V’ in the description of Normal mode, in Table 8 and in Table 10.
•
Table 13 “Static characteristics: supply pins”: removed table note for ICC referencing the
USB On-The-Go specification.
•
Table 14 “Static characteristics: digital pins”: changed the commonly supported types of
VCC(I/O) into examples.
•
•
Section 15.1 “(H)BCC packages: footprint”: added paragraph on terminal composition.
Section 15.2 “(H)BCC packages: reflow soldering profile”: changed peak temperature
from 220 °C ±5 °C to 260 °C (ambient) and 255 °C (device surface).
03
20010704
-
Preliminary data; third version. Supersedes ISP1107-02 of 5 February 2001
(9397 750 07879). Modification:
02
20010205
-
Objective specification; second version. Supersedes ISP1107-01 of 23 February 2000
(9397 750 06899). ISP1107 stand-alone datasheet only.
01
20000223
-
Objective specification; initial version. ISP1107 stand-alone datasheet only.
•
ISP1107, ISP1106 and ISP1105 combined into one datasheet.
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17. Data sheet status
Data sheet status[1]
Product status[2]
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
18. Definitions
19. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected].
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
9397 750 08872
Rev. 06 — 30 November 2001
23 of 24
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
14.5
15
15.1
15.2
16
17
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Function selection. . . . . . . . . . . . . . . . . . . . . . . 6
Operating functions. . . . . . . . . . . . . . . . . . . . . . 7
Power supply configurations . . . . . . . . . . . . . . . 7
Power supply input options . . . . . . . . . . . . . . . . 8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Static characteristics. . . . . . . . . . . . . . . . . . . . 10
Dynamic characteristics . . . . . . . . . . . . . . . . . 13
Test information . . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 20
Package related soldering information . . . . . . 20
Additional soldering information . . . . . . . . . . 21
(H)BCC packages: footprint . . . . . . . . . . . . . . 21
(H)BCC packages: reflow soldering profile. . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
© Koninklijke Philips Electronics N.V. 2001.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 30 November 2001
Document order number: 9397 750 08872
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