EMC EM73361AAQ 4-bit micro-controller for lcd product Datasheet

EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
GENERAL DESCRIPTION
EM73361A is an advanced single chip CMOS 4-bit micro-controller. It contains 3K-byte ROM, 52-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function.
EM73361A also contains 3 interrupt sources, 1 input port, 4 bidirection I/O ports, built-in watch-dog-timer
counter, tone generator and LCD driver (27x3 to 13x3).
Except low-power consumption and high speed, EM73361A also have a sleep mode operation for power saving.
FEATURES
• Operation voltage
• Clock source
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
: 2.2V to 3.6V(clock frequency : 32K Hz).
: Single clock system for crystal, connect a external resistor or external clock
source available by mask option.
Instruction set
: 109 powerful instructions.
Instruction cycle time
: 122µs for 32K Hz.
ROM capacity
: 3072 X 8 bits.
RAM capacity
: 52 X 4 bits.
Input port
: 1 port (P0)(Pull-up and pull-down resistor with wakeup function available by
mask option).
Bidirection port
: 4 ports (P4, P5, P6, P7) are available by mask option. (each I/O pin is push-pull
and open-drain available by mask option) P4.0 is high current pin (P4.0 and
TONE available by mask option). P4.2~P4.3, P5, P6 and P7 are shared with
SEG26-SEG13 by mask option.
12-bit timer/counter
: Two 12-bit timer/counters are programmable for timer mode.
Low voltage reset (LVR) : Reset at 1.5V, and reset release at 1.8V.
Tone generator
: There is a built-in tone generator.
Built-in time base counter : 22 stages.
Subroutine nesting
: Up to 13 levels.
Interrupt
: External . . . . . 2 External interrupt (INT0, INT1).
Internal . . . . . . 2 Timer overflow interrupts.
1 Time base interrupt.
LCD driver
: 27 X 3 to 13 X 3 dots available by mask option. Capacitor divider and resistor
divider are available by mask option.1/3, 1/2 and static three kinds of duty (1/2
bias) selectable. The programming method of LCD driver is I/O mapping.
Built-in watch-dog-timer : The WDT is enabled or disabled by mask option.
Power saving function
: Sleep mode and Hold mode.
Package type
: EM73361AAH
Chip form 46 pins.
EM73361AAQ
QFP
100 pins.
APPLICATIONS
EM73361A is suitable for application in family appliance, consumer products, hand held games and the toy
controller.
* This specification are subject to be changed without notice.
10.8.2001
1
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
NC
NC
NC
P7.0/SEG16
P6.3/SEG17
P6.2/SEG18
P6.1/SEG19
P6.0/SEG20
P5.3/SEG21
P5.2/SEG22
P5.1/SEG23
P5.0/SEG24
P4.3/SEG25
P4.2/SEG26
COM2
TEST
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PIN CONFIGURATIONS
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
EM73361AAQ
QFP 100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
NC
NC
NC
NC
NC
P4.1/WDT
P4.0/TONE
TONE
P0.3/WAKEUP3
P0.2(INT0)/WAKEUP2
P0.1/WAKEUP1
P0.0(INT1)/WAKEUP0
RESET
VDD
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SEG2
SEG1
SEG0
COM1
COM0
VEE
VB
VA
XIN
XOUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
NC
NC
NC
P7.1/SEG15
P7.2/SEG14
P7.3/SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
NC
NC
NC
* This specification are subject to be changed without notice.
10.8.2001
2
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
FUNCTION BLOCK DIAGRAM
RESET
Reset
Control
XIN XOUT
Clock
Generator
Frequency
doubler
P0.0(INT1)/WAKEUP0
P0.1/WAKEUP1
P0.2(INT0)/WAKEUP2
P0.3/WAKEUP3
Sleep Mode
Control
Timing
Generator
VA
VB
VEE
COM0~COM2
SEG0~SEG12
System Control
Data pointer
ROM
Time
Base
12-bit
timer
counter
(TA,TB)
Stack pointer
LCD
driver
ACC
P4,P5,P6,P7/SEG(26..13)
Data Bus
Interrupt
Control
Instruction Decoder
Instruction Register
Stack
ALU
RAM
Flag
Z
C
S
HR
PC
Tone generator
TONE
G
LR
I/O Control
P4.0/TONE
P4.1/WDT
WDT
PIN DESCRIPTIONS
Symbol
V DD
V SS
RESET
XIN
XOUT
P0.0(INT1)/WAKEUP0,
P0.2(INT0)/WAKEUP2
P0.1/WAKEUP1,
P0.3/WAKEUP3
Pin-type
Function
Power supply (+)
Power supply (-)
RESET-A
System reset input signal, low active
mask option : none
pull-up
OSC-A/OSC-F Crystal/external resistor or external clock source connecting pin
OSC-A/OSC-F Crystal/external resistor connecting pin
INPUT-J
2-bit input port with external interrupt sources input and Sleep/Hold
releasing function
mask option : wakeup enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, none
wakeup disable, pull-down
INPUT-H
2-bit input port with Sleep/Hold releasing function
mask option : wakeup enable, pull-up
wakeup enable, none
* This specification are subject to be changed without notice.
10.8.2001
3
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Symbol
Pin-type
P4.0/TONE
I/O-O
P4.1/WDT
I/O-D
P4(2..3)/SEG(26..25)
P5(0..3)/SEG(24..21)
P6(0..3)/SEG(20..17)
P7(0..3)/SEG(16..13)
TONE
VA, VB, VEE
COM0~COM2
SEG0~SEG12
TEST
I/O-P
Function
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
1-bit bidirection I/O pin or inverse tone generator output
mask option : TONE enable, push-pull, high current PMOS
TONE disable, open-drain
TONE disable, push-pull, high current PMOS
TONE disable, push-pull, low current PMOS
1-bit bidirection I/O pin with watch-dog-timer output
mask option : open-drain
push-pull
4-bit bidirection I/O ports are shared with LCD segment pins
mask option : segment enable, open-drain
segment disable, push-pull
segment disable, open-drain
Built-in tone generator output
Connect the capacitors for LCD bias voltage
LCD common output pins
LCD segment output pins
Tie Vss as package type, no connecting as COB type
FUNCTION DESCRIPTIONS
PROGRAM ROM ( 3K X 8 bits )
3 K x 8 bits program ROM contains user's program and some fixed data .
The basic structure of program ROM can be divided into 4 parts.
1. Address 000h: Reset start address.
2. Address 002h - 00Ch: 4 kinds of interrupt service routine entry addresses .
3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h ,07Eh, 086h .
4. Address 000h - 7FFh : LCALL subroutine entry address
5. Address 000h - BFFh : Except used as above function, the other region can be used as user's program region.
address
000h
002h
004h
006h
008h
00Ah
00Ch
00Eh
086h
3072 x 8 bits
Reset start address
INT0 ; External interrupt service toutine entry address
TRGA; Timer/counter A interrupt service routine entry address
TRGB; Timer/counter B interrupt service routine entry address
TBI; Time base interrupt service routine entry address
INT1; External interrupt service routine entry address
SCALL, subroutine call entry address
..
.
BFFh
* This specification are subject to be changed without notice.
10.8.2001
4
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by table-look-up instruction.
Table-look-up instruction is depended on the Data Pointer ( DP ) to indicate to ROM address, then to get the
ROM code data.
LDAX
Acc ← ROM[DP]L
LDAXI
Acc ← ROM[DP]H,DP+1
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data.
First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the
lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".
PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.
LDIA #07h;
STADPL
STADPM
STADPH
:
LDL #00h;
LDH #03h;
LDAX
STAMI
LDAXI
STAM
;
ORG 777h
DATA 56h;
:
; [DP]L ← 07h
; [DP]M ← 07h
; [DP]H ← 07h, Load DP=777h
; ACC ← 6h
; RAM[30] ← 6h
; ACC ← 5h
; RAM[31] ← 5h
DATA RAM ( 52-nibble )
There is total 52 - nibble data RAM from address 00 to 33h
Data RAM includes 3 parts: zero page region, stacks and data area.
Increment
Address
Level 0
Level 1
Level 2
Level 3
10h - 1Fh
Level 4
Level 5
Level 6
Level 7
20h - 2Fh
Level 8
Level 9
Level 10
Level 11
30h - 33h
Level 12
Stack
Increment
00h - 0Fh
Zero-page
ZERO- PAGE:
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero -page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0
STACK:
There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User
can assign any level be the starting stack by giving the level number to stack pointer (SP).
* This specification are subject to be changed without notice.
10.8.2001 5
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.
DATA AREA:
Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.
ADDRESSING MODE
(1) Indirect addressing mode:
Indirect addressing mode indicates the RAM address by specified HL register.
For example: LDAM ; Acc ← RAM[HL]
STAM ; RAM[HL] ← Acc
(2) Direct addressing mode:
Direct addressing mode indicates the RAM address by immediate data.
For example: LDA x ; Acc← RAM[x]
STA x ; RAM[x] ← Acc
(3) Zero-page addressing mode
For zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit
manupulated operation directly.
For example: STD #k,y ; RAM[y] ← #k
ADD #k,y; RAM[y] ← RAM[y] + #k
PROGRAM COUNTER (3K ROM)
Program counter ( PC ) is composed by a 12-bit counter, which indicates the next executed address for the
instruction of program ROM.
For a 3K - byte size ROM, PC can indicate address form 000h - BFFh, for BRANCH and CALL instrcutions,
PC is changed by instruction indicating.
(1) Branch instruction:
SBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC 11-6.a ( branch condition satisified )
PC Hold original PC value+1 a
a
a
a
a
a
SF=0; PC← PC +1( branch condition not satisified)
PC
Original PC value + 1
LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← a ( branch condition satisified)
PC a
a
a
a
a
a
a
a
a
a
a
* This specification are subject to be changed without notice.
a
10.8.2001
6
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SF=0 ; PC ← PC + 2 ( branch condition not satisified )
PC
Original PC value + 2
(2) Subroutine instruction:
SCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0
PC
0 0 0
0 a
a
a
a a
a
a
a
a
a
a
a
a
a
LCALL a
Object code: 0100 0aaa aaaa aaaa
Condition: PC ← a
PC 0
a
a
a
a
a
RET
Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1
PC
The return address stored in stack
RT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC
The return address stored in stack
(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC,The interrupt vectors are as following:
INT0 (External interrupt from P0.2)
PC 0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
TRGA (Timer A overflow interrupt)
PC 0
0
0
0
0
TRGB (Time B overflow interrupt)
PC 0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
TBI (Time base interrupt)
PC 0
0
0
* This specification are subject to be changed without notice.
10.8.2001
7
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INT1 (External interrupt from P0.0)
PC 0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
(4) Reset operation:
PC 0
(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
ACCUMULATOR
Accumulator is a 4-bit data register for temporary data . For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result .
FLAGS
There are four kinds of flag, CF ( Carry flag ), ZF ( Zero flag ), SF ( Status flag ) and GF ( General flag ),
these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation .
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction executed .
(1) Carry Flag ( CF )
The carry flag is affected by following operation:
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",
in another word, if the operation has no carry-out, CF will be "0".
b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF
will be "0", in another word, if no borrow-in, CF will be "1".
c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction
operation.
d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".
For TTSFC instruction, the content of CF sends into SF then set itself "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1",
otherwise, the ZF will be "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status .
* This specification are subject to be changed without notice.
10.8.2001
8
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
a. SF is initiated to "1" for reset condition .
b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,
branch condition will not be satisified by SF = 0 .
(4) General Flag ( GF )
GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS.
PROGRAM EXAMPLE:
Check following arithematic operation for CF, ZF, SF
CF
-
LDIA #00h;
LDIA #03h;
ADDA #05h;
ADDA #0Dh;
ADDA #0Eh;
ZF
1
0
0
0
0
SF
1
1
1
0
0
ALU
The arithematic operation of 4 - bit data is performed in ALU unit . There are 2 flags can be affected by
the result of ALU operation, ZF and SF . The operation of ALU can be affected by CF only .
ALU STRUCTURE
ALU supported user arithematic operation function, including : addition, subtraction and rotaion.
DATA BUS
ALU
ZF CF SF GF
ALU FUNCTION
(1) Addition:
For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.
The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1",
otherwise, not equal "0", ZF will be "0", When the addition operation has a carry-out. CF will be "1",
otherwise, CF will be "0".
EXAMPLE:
Operation
3+4=7
7+F=6
0+0=0
8+8=0
Carry
0
1
0
1
Zero
0
0
1
1
(2) Subtraction:
For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function . The
subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will
* This specification are subject to be changed without notice.
10.8.2001
9
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result
of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1".
EXAMPLE:
Operation
8-4=4
7-F= -8(1000)
9-9=0
Carry
1
0
1
Zero
0
0
1
(3) Rotation:
There are two kinds of rotation operation, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data
will be hold in CF.
MSB LSB
ACC
CF
RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the
shift out data will be hold in CF.
MSB LSB
ACC
CF
PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc .
TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTER
HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also
2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the
pin number ( Port4, Port6, Port7 ) .
HL REGISTER STRUCTURE
3
2
1
0
3
2
1
0
H REGISTER L REGISTER
HL REGISTER FUNCTION
(1) For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a
temporary register .
PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register.
LDL #05h;
LDH #0Dh;
(2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory.
* This specification are subject to be changed without notice.
10.8.2001
10
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h.
LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
(3) For instruction : SELP, CLPL, TFPL, L regieter be a pointer to indicate the bit of I/O port.
When LR = 0 - 1, indicate P4.0 - P4.1.
PROGRAM EXAMPLE: To set bit 1 of Port4 to "1"
LDL #01h;
SEPL ; P4.1 ← 1
STACK POINTER (SP)
Stack pointer is a 4-bit register which stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition
. When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if
returning from a subroutine, the SP will be increased one .
The data transfer between ACC and SP is by instruction of "LDASP" and "STASP".
DATA POINTER (DP)
Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data
specified by user (refer to data ROM).
CLOCK AND TIMING GENERATOR
The clock generator is supported by a single clock system, the clock source comes from crystal (resonator)
or RC oscillation, the working frequency range is 32 KHz to 100 KHz depending on the working voltage.
CLOCK AND TIMING GENERATOR STRUCTURE
The clock generator connects outside compoments ( crystal or resonator by XIN and XOUT pin for crystal
osc type, capacitor for RC osc type, these two type is decided by mask option) the clock generator generates
a basic system clock "fc".
When CPU sleeping, the clock generator will be stoped until the sleep condition released.
The system clock control generates 4 basic phase signals ( S1, S2, S3, S4 ) and system clock .
Mask option
sleep
XIN
XIN/CLK
clock generator
Mask option for choose Crystal or RC oscillation
fc
System clock
System clock control
XOUT
S1
* This specification are subject to be changed without notice.
S2
S3
S4
10.8.2001
11
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
XIN
XIN
XOUT
XOUT
Crystal connection
Resistor connection
CLOCK AND TIMING GENERATOR FUNCTION
The frequency of fc is the oscillation frequency for XIN, XOUT by crystal ( resonator) or by RC osc.
When CPU sleeps, the XOUT pin will be in "high" state .
The instruction cycle equal 4 basic clock fc.
1 instructure cycle = 4 / fc
TIMING GENERATOR AND TIME BASE
The timing generator produces the system clock from basic clock pulse which can be normal mode or slow
mode clock.
1 instruction cycle = 4 basic clock pulses
There are 22 stages time base .
Binary counter
Prescaler
fc
0 1 2 3
4
5 6 7
8 9 10 11 12 13 14 15 16 17 18 19 20 21
When working in the single clock mode, the timebase clock source is come from fc.
Time base provides basic frequency for following function:
1. TBI (time base interrupt) .
2. Timer/counter, internal clock source.
3. Warm-up time for sleep - mode releasing.
TIME BASE INTERRUPT (TBI )
The time base can be used to generate a fixed frequency interrupt . There are 8 kinds of frequencies can be
selected by setting "P25"
Single clock mode
P25 3 2 1 0
( initial value 0000 )
0 0 x x: Interrupt disable
0 1 0 0: Interrupt frequency XIN / 29 Hz
0 1 0 1: Interrupt frequency XIN / 210 Hz
0 1 1 0: Interrupt frequency XIN / 212 Hz
0 1 1 1: Interrupt frequency XIN / 213 Hz
1 1 0 0: Interrupt frequency XIN / 214 Hz
1 1 0 1: Interrupt frequency XIN / 215 Hz
1 1 1 0: Interrupt frequency XIN / 216 Hz
1 1 1 1: Interrupt frequency XIN / 217 Hz
1 0 x x: Reserved
* This specification are subject to be changed without notice.
10.8.2001
12
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TIMER / COUNTER ( TIMERA, TIMERB)
EM73361A only can support timer function for timerA and timerB independently.
For timerA, the counter data is saved in timer register TAH, TAM, TAL, which user can set counter initial
value and read the counter value by instruction "LDATAH(M,L), STATAH(M,L)" and timerB register is
TBH, TBM, TBL and W/R instruction "LDATBH (M,L), STATBH (M,L)".
The basic structure of timer/counter is composed by two same structure counter, these two counters can be
set initial value and send counter value to timer register, P28 and P29 are the command ports for timerA
and timer B, user can choose different internal clock rate by setting these two ports. When timer/counter
overflow, it will generate a TRGA(B) interrupt request to interrupt control unit.
INTERRUPT CONTROL
TRGB request
TRGA request
DATA BUS
12 BIT COUNTER
internal clock
12 BIT COUNTER
TIMER CONTROL
P28
TMSA
IPSA
TIMER CONTROL
TMSB
P29
internal clock
IPSB
TIMER/COUNTER CONTROL
Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/
counterB.
Port 28
3 2 1 0
TMSA IPSA
Initial state: 0000
Port 29
3 2 1 0
TMSB IPSB
Initial state: 0000
TIMER/COUNTER MODE SELECTION
TMSA (B)
Function description
00
Stop
01
Reserved
10
Timer mode
11
Reserved
INTERNAL PULSE-RATE SELECTION
IPSA(B)
00
Function description
XIN/2 5 Hz
01
XIN/2
10
XIN/2
11
XIN/215 Hz
* This specification are subject to be changed without notice.
7
11
Hz
Hz
10.8.2001
13
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TIMER/COUNTER FUNCTION
Each timer/counter can execute the timer function independly.
TIMER MODE
For timer mode ,timer/counter increase one at any rising edge of internal pulse . User can choose 4 kinds
of internal pulse rate by setting IPSB for timerB (IPSA for timerA).
When timer/counter counts overflow, TRGB (TRGA) will be generated to interrupt control unit.
Internal pulse
TimerB (TimerA )value
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock XlN=32K Hz
LDIA
#0100B;
EXAE; enable mask 2
EICIL 110111B; internupt latch ← 0, enable EI
LDIA
#04H;
STATAL;
LDIA
#0CH;
STATAM;
LDIA
#0FH;
STATAH;
LDIA
#1000B;
OUTA P28; enable timerA with internal pulse rate: XIN/25 Hz
NOTE:
The preset value of timer/counter register is calculated as following procedure.
Internal pulse rate: XIN/25 ; XIN = 32KHz
The time of timer counter count one = 25 /XIN = 32/32K=1ms
The number of internal pulse to get timer overflow = 60 ms/ 1ms = 60 = 03CH
The preset value of timer/counter register = 1000H - 03CH = 0FC4H
INTERRUPT FUNCTION
There are 3 internal interrupt sources and 2 external interrupt sources. Multiple interrupts are admitted
according the priority .
Type
External
Internal
Internal
Internal
Internal
External
Interrupt source
External interrupt (INT0)
Reserved
TimerA overflow interrupt (TRGA)
TimerB overflow interrupt (TRGB)
Time base interrupt(TBI)
External interrupt (INT1)
Priority
Interrupt
Latch
Interrupt
Enable condition
Program ROM
entry address
1
2
3
4
5
6
IL5
IL4
IL3
IL2
IL1
IL0
EI=1
EI=1, MASK3=1
EI=1, MASK2=1
EI=1, MASK1=1
002H
004H
006H
008H
00AH
00CH
* This specification are subject to be changed without notice.
EI=1,MASK0=1
10.8.2001
14
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INTERRUPT STRUCTURE
MASK0 MASK1 MASK1 MASK2 MASK3
TRGB TRGA Reserved
Reserved
INT1INT1 TBI
r0
r1
r2
r3
r4
Reset by system reset and program
instruction
IL0
IL1
IL2
IL3
IL4
INT0
r5
IL5
Priority checker
Reset by system reset and program
instruction
Set by program instruction
EI
Interrupt request
Entry address generator
Interrupt entry address
Interrupt controller:
IL0-IL5
: Interrupt latch . Hold all interrupt requests from all interrupt sources. ILr can not be
set by program, but can be reset by program or system reset, so IL only can decide
which interrupt source can be accepted.
MASK0-MASK3
: MASK register can promit or inhibit all interrupt sources.
EI
: Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when interrupt happened, EI is cleared to "0" automatically, after RTI instruction happened,
EI will be set to "1" again .
Priority checker: Check interrupt priority when multiple interrupts happened.
INTERRUPT FUNCTION
The procedure of interrupt operation:
1. Push PC and all flags to stack.
2. Set interrupt entry address into PC.
3. Set SF= 1.
4. Clear EI to inhibit other interrupts happened.
5. Clear the IL for which interrupt source has already be accepted.
6. To excute interrupt subroutine from the interrupt entry address.
7. CPU accept RTI, restore PC and flags from stack . Set EI to accept other interrupt requests.
PROGRAM EXAMPLE: To enable interrupt of "TRGA"
LDIA #1100B;
EXAE; set mask register "1100B"
EICIL 111111B ; enable interrupt F.F.
* This specification are subject to be changed without notice.
10.8.2001
15
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
POWER SAVING FUNCTION ( Sleep / Hold function )
During sleep and hold condition, CPU holds the system's internal status with a low power consumption, for
the sleep mode, the system clock will be stoped in the sleep condition and system need a warm up time for
the stability of system clock running after wakeup . In the other way, for the hold mode, the system clock
does not stop at all and it does not need a warm-up time any way.
The sleep and hold mode is controlled by Port 16 and released by P0(0..3)/WAKEUP0..3.
P16
3
2
WM SE
1
0
SWWT
initial value :0000
WM Set wake-up release mode
0
1
Wake-up in edge release mode
Reserved
SWWT Set wake-up warm-up time
00
01
10
11
217 /XIN
213 /XIN
215 /XIN
Hold mode
SE Enable sleep/hold
0 Reserved
1 Enable sleep / hold rnode
Sleep and hold condition:
1. Osc stop ( sleep only ) and CPU internal status held .
2. Internal time base clear to "0".
3. CPU internal memory ,flags, register, I/O held original states.
4. Program counter hold the executed address after sleep release.
Release condition:
1. Osc start to oscillating.(sleep only).
2. Warm-up time passing ( sleep only ).
3. According PC to execute the following program.
There is one kind of sleep/hold release mode .
1. Edge release mode:
Release sleep/hold condition by the falling edge of any one of P0(0..3)/WAKEUP0..3.
Note : There are 4 independent mask options for wakeup function in EM73360. So, the wakeup function
of P0(0..3)/WAKEUP0..3 are enabled or disabled inpendently.
LCD DRIVER
EM73361A can directly drive the liquid crystal display (LCD) and has 27 segment, 3 common output pins. There
are total 27 x 3 dots can be display. The VDD, VEE and VSS pins are the bias voltage inputs of the LCD driver.
The VA and VB are used to the voltage double for 3V system. The method of LCD programming is I/O
mapping.
CONTROL OF LCD DRIVER
The LCD driver control command register is P27. When LDC is 00, the LCD is disabled. When LDC is 01,
the LCD is blanking,
* This specification are subject to be changed without notice.
10.8.2001 16
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
the COM pins are inactive and the SEG pins continously output the display data. When LDC is 11, the LCD
driver enables, the power swich is turned on and it cannot be turned off forever except the CPU is reseted or
sleeping. Users must enable the LCD driver by self when the CPU is waked up.
Port27
3
2
LDC
LDC
0 0
0 1
1 0
1 1
1
0
Initial value : 0000
DUTY
LCD display control
LCD display disable & change duty
Blanking
Reserved
LCD display enable
DUTY
0
0
0
1
1
0
1
1
Driving method select
Reserved
1/3 duty (1/2 bias)
1/2 duty (1/2 bias)
Static
LCD driving methods
There are four kinds of driving methods can be selected by DUTY (P27.0~P27.1). The driving waveforms of
LCD driver are as below :
1/3 duty (1/2 bias)
C C
O O
M M
0 1
C
O
M
2
1/2duty (1/2 bias)
Static
COM0
COM1
SEG0
SEG1
COM2
SEG2
:
ON
OFF
SEG0
SEG0-COM0
ON
SEG0-COM1
OFF
Frame
Frame
Frame
LCD Frame frequency : According to the drive method to set the frame frequency.
Driving method
1/3 duty
1/2 duty
Static
Frame frequency (Hz)
43 x (3/3) = 43
43 x (3/2) = 64
43
The relation between LCD display data and driving method
Driving method
1/3 duty
1/2 duty
Static
bit3
-
bit2
COM2
-
bit1
COM1
COM1
-
bit0
COM0
COM0
COM0
LCD drive voltage
EM73361A provides 2 kinds of LCD bias methods, capacitor divider and resistor divider, when the LCD bias
method is capacitor divider,the VA is connected a capacitor to VB and the VEE is connected a capacitor
to VSS. The output of VEE is 1.5V for LCD bias voltage. When the LCD bias method is resistor divider, the
VA, VB and VEE are floating.
* This specification are subject to be changed without notice.
10.8.2001
17
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
• Capacitor divider
VA VEE
• Resistor divider
1.5V
VA VEE
0.1F
VDD
VB
VSS
VDD
3V
VB
VSS
3V
LCD DISPLAY OPERATION
The LCD programming method is I/O mapping and P10~P12 are must be used.
Address register of LCD display buffer
It is a 5-bit register to specify address for LCD display buffer.
Port11
3
Port10
2
1
0
3
A4
2
A3 A2
1
0
A1
A0
Initial value :0000 0000
Data register of LCD display buffer
P12 is a 3-bit data register to read or write LCD display buffer.
Port12
3
2
1
0
D2
D1
D0
Initial value : 0000
TONE GENERATOR
tone
EM73361A has a built-in tone generator. It is a binary down counter. When the CPU is reseted or sleeping, the
generator is disabled and the output (P4.0/TONE) is high.
P30.0
P23, P24
Tone
generator
XIN
fo
High
Output
control
TONE
TONE
Tone generator command register
Port30
3
*
2
*
1
*
0
SM
Initial value : 0000
SM Sound generator mode
0 Tone generator disable
1 Tone generator enable
* This specification are subject to be changed without notice.
10.8.2001
18
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Tone frequency register
The 8-bit tone frequency register is P24 and P23. The tone frequency will be changed when user output the
different data to P23. Thus, the data must be output to P24 before P23 when user want to change the 8-bit
tone frequency (TF).
Port24
3
Port23
2
1
0
3
Higher nibble register
2
1
0
Initial value : 1111 1111
Lower nibble register
** f1=XIN/(TF+1), TF=1~255, TF≠0
** Example : XIN=32K Hz, TF=00110001B.
⇒ fo=32K Hz/50=655.36 Hz
WATCH-DOG-TIMER (MASK OPTION)
Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a time up signal every
certain time . User can use the time up signal to give system a reset signal when system is fail. When CPU is reseted
or sleeping, the watch-dog-timer is disabled. Users must enable the watch-dog-timer by self when CPU is waked
up.
The basic structure of watch-dog-timer control is composed by a 4-stage binary counter and a control unit . the
WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the counter
will be cleared and counting . Otherwise, if there is a malfunction happened, the WDT control will send a WDT
signal ( low active ) to outside, user can use this signal to reset CPU . The WDT checking period is assign by
P21 ( WDT command port )
WDT counter
fc/213
0 1 2 3
counter clear request
WDT CONTROL
system reset
P21
WDT
command PORT
P4.1 OUTPUT DATA
F/F
R Q
S
P4.1
P4.1 OUTPUT
DATA LATCH
P21 is the control port of watchdog timer, and the watchdog timer timeup signal is output by P4.1/WDT, user can
use this timeup signal (active low) to reset CPU and initialize system.
Port 21
3
2
1
0
Initial value :0000
CWC
CWC
0
1
WDT
0
1
*
*
WDT
Clear watchdog timer counter
Clear counter then return to 1
Nothing
Set watchdog timer detect time
3 x 213/fc=3 x 213/32 KHz=0.75 sec
7 x 213/fc=7 x 213/32K Hz=1.75 sec
* This specification are subject to be changed without notice.
10.8.2001
19
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE
To enable WDT with 3 x 213/fc detection ftime.
LDIA #0000B
OUTA P21; set WDT detection time and clear WDT counter
RESETTING FUNCTION
When CPU in normal working condition and RESET pin holds in low level for three instruction cycles at least,
then CPU begins to initialize the whole internal states, and when RESET pin changes to high level, CPU begins
to work in normal condition.
The CPU internal state during reset condition is as following table :
Hardware condition in RESET state
Program counter
Status flag
Interrupt enable flip-flop ( EI )
MASK0 ,1, 2, 3
Interrupt latch ( IL )
P10, 11, 12, 16, 21, 25, 27, 28, 29, 30
P4, 5, 6, 7, 23, 24
XIN
Initial value
000h
01h
00h
00h
00h
00h
0Fh
Start oscillation
The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option.
The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
* This specification are subject to be changed without notice.
10.8.2001
20
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
EM73361A I/O PORT DESCRIPTION :
Port
0 E
1
2
3
4 E
Input function
Input port , wakeup function
---Input port
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Input port
Input port
Input port
---------
E
E
E
Output function
E
E
E
E
I
I
I
I
I
I
I
I
I
I
I
I
---Output port, P4.0/TONE,P4.1/WDT, P4(2..3)
/SEG(26..25)
P5(0..3)/SEG(24..21)
P6(0..3)/SEG(20..17)
P7(0..3)/SEG(16..13)
--Address register of LCD display buffer
Address register of LCD display buffer
Data register of LCD display buffer
---Sleep/Hold mode control register
----Watch-dog-timer control register
-Sound effect frequency register
Sound effect frequency register
Timebase control register
-LCD control register
Timer/counter A control register
Timer/counter B control register
Sound effect command register
--
* This specification are subject to be changed without notice.
Note
low nibble
high nibble
low nibble
high nibble
10.8.2001
21
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ABSOLUTE MAXIMUM RATINGS
Items
Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Sym.
V DD
V IN
VO
PD
T OPR
T STG
Ratings
Conditions
-0.5V to 6V
-0.5V to VDD+0.5V
-0.5V to VDD+0.5V
200mW
0oC to 50oC
-55oC to 125oC
TOPR=50oC
RECOMMENDED OPERATING CONDITIONS
Items
Supply Voltage
Input Voltage
Sym.
VDD
VIH
VIL
Ratings
2.2V to 3.6V
0.9xVDD to VDD
0V to 0.10xVDD
* This specification are subject to be changed without notice.
Conditions
Fc=32KHz
10.8.2001
22
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
DC ELECTRICAL CHARACTERISTICS (VDD=3.0±0.3V, VSS=0V, TOPR=25oC)
Min.
Typ. Max. Unit
Conditions
Parameters
Sym.
Supply current
Hysteresis voltage
I DD
Input current
V HYS+
V HYSI IH
Output voltage
I IL
V OH
Leakage current
Input resistor
LCD bias voltage
COM, SEG pins
output current
V OL
I LO
R IN
V EE
V 01
V 02
V 03
-
10
20
µA
-
30
60
µA
0.50VDD
0.20VDD
-30
2.4
50
5
0.1
20
-20
-320
-
85
8
1
0.75VDD
0.40VDD
30
1
-500
-
µA
µA
µA
V
V
µA
µA
µA
µA
V
2.0
-
-
V
30
70
0.3
1
110
1
/2VDD-0.1
VDD-0.1
VEE-0.1
-
1
/2VDD
VDD
VEE
VSS
V
µA
KΩ
1
/2VDD+0.1 V
V
VEE+0.1
V
VSS+0.1
V
%
Frequency stability
-
20
Frequency variation
-
20
-
%
-
1.5
1.8
-
V
V
LVR reset voltage
LVR reset release
voltage
V LVR
V RLVR
* This specification are subject to be changed without notice.
VDD=3.3V, Cap. divider, no load, no LVR,
Fc=32KHz
VDD=3.3V, Res. divider, no load, no LVR,
Fc=32KHz
VDD=3.3V, no load, with LVR, Fc=32KHz
VDD=3.3V, Hold mode, no LVR
VDD=3.3V, sleep mode, no LVR
RESET, P0
Port0, Pull-down, VIH=VDD
Port0, Pull-up, VIH=VSS
Port0, None
Push-pull , VDD=3.3V, VIL=0.4V, except P4.0, TONE
Push-pull, P4.0(high current PMOS), TONE,
VDD=2.7V,IOH=-1mA
Push-pull, P4.0(low current PMOS),
VDD=2.7V, IOH=-60µA
VDD=2.7V, IOL=1mA
Open-drain.VDD=3.3V, VO=3.3V
RESET
Voltage halfer
I01=-5µA, Cap. divider
I02=±5µA, Cap. divider
I03=5µA, Cap. divider
Fc=32KHz, RC osc, R=750KΩ,
[F(3.0V)-F(2.7V)]/F(3.0V)
Fc=32KHz, VDD=3.0V,RC osc, R=750KΩ,
[F(typical)-F(worse case)]/F(typical)
10.8.2001
23
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
RESET PIN TYPE
TYPE RESET-A
RESET
mask option
INPUT PIN TYPE
TYPE INPUT-H
TYPE INPUT-J
WAKEUP function
mask option
WAKEUP function
mask option
input data
special function
control input
: mask option
: mask option
OSCILLATION PIN TYPE
TYPE OSC-A
TYPE OSC-F
XIN
XIN
RC Osc.
(inverter)
Crystal
Osc.
XOUT
* This specification are subject to be changed without notice.
XOUT
10.8.2001
24
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
I/O PIN TYPE
TYPE I/O
TYPE I/O-D
path B
Input
data
path A
mask option
TYPE I/O
MUX
Output
data
latch
Output
data
special function
control output
TYPE I/O-N
TYPE I/O-O
path B
Input
data
path A
TYPE I/O
: mask option
Output
data
latch
Output
data
: mask option
Special function output
TYPE I/O-P
Input
data
path B
path A
TYPE I/O
Special function
output
Path A :
Path B :
Output
data
latch
Output
data
: mask option
For set and clear bit of port instructions, data goes through path A from output data latch to CPU.
For input and test instructions, data from output pin go through path B to CPU and the output data latch
will be set to high.
* This specification are subject to be changed without notice.
10.8.2001
25
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
APPLICATION CIRCUIT
VBAT
VBAT
0.1µF
VDD
3V
SEG0~
SEG12
COM0~
COM2
P0.0
P0.1
LCD PANNEL
VA
P0.2
0.1µF
VB
Capacitor
driver
VEE
Resistor driver
VEE
TONE
Buzzer
P4.0/TONE
RESET
0.1µF
X'tal osc type
XIN
RESET
20P
XOUT
32.768KHz
20P
VSS
RC osc type
EM73361A
XOUT
XIN
* This specification are subject to be changed without notice.
10.8.2001
26
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
P7.3
P7.2
P7.1
PAD DIAGRAM
46
45
44
43
42
41
40
39
38
37
36
35
34
SEG2
1
33
P7.0
SEG1
2
32
P6.3
SEG0
3
31
P6.2
COM1
4
30
P6.1
COM0
5
29
P6.0
6
28
P5.3
VEE
VB
7
27
P5.2
P5.1
8
26
VA
XIN
25
P5.0
9
24
P4.3
23
P4.2
22
COM2
21
TEST
(0,0)
X
EM73361A
P0.0
P0.1
16
17
18
19
20
P4.1
15
P4.0
14
TONE
13
P0.3
12
P0.2
11
RESET
ELAN
VDD
10
VSS
XOUT
Y
Chip Size : 1710 µm x 1910 µm
PadNo.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Symbol
SEG2
SEG1
SEG0
COM1
COM0
VEE
VB
VA
XIN
XOUT
VSS
VDD
RESET
P0.0
P0.1
P0.2
P0.3
X
-685.5
-685.5
-685.5
-685.5
-685.5
-685.5
-685.5
-685.5
-685.5
-685.5
-522.3
-409.3
-296.3
-185.9
-71.9
38.6
152.6
* This specification are subject to be changed without notice.
Y
583.8
473.3
362.9
252.4
141.9
31.5
-79.0
-189.4
-299.9
-639.3
-785.5
-785.5
-785.5
-785.5
-785.5
-785.5
-785.5
10.8.2001
27
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PadNo.
Symbol
X
Y
18
TONE
263.0
-785.5
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
P4.0
P4.1
TEST
COM2
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P7.0
P7.1
P7.2
P7.3
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
373.5
483.9
685.5
685.5
685.5
685.5
685.5
685.5
685.5
685.5
685.5
685.5
685.5
685.5
685.5
662.4
552.0
441.5
331.1
220.6
110.1
-0.3
-110.8
-221.2
-331.7
-442.2
-552.6
-663.1
-785.5
-785.5
-741.7
-631.3
-520.8
-410.4
-299.9
-189.4
-79.0
31.5
141.9
252.4
362.9
473.3
583.8
785.4
785.4
785.4
785.4
785.4
785.4
785.4
785.4
785.4
785.4
785.4
785.4
785.4
Note : For PCB llayout, IC substrate must be floated or connect to VSS.
* This specification are subject to be changed without notice.
10.8.2001
28
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INSTRUCTION TABLE
(1) Data Transfer
Mnemonic
LDA
x
LDAM
LDAX
LDAXI
LDH #k
LDHL x
LDIA #k
LDL #k
STA
x
STAM
STAMD
STAMI
STD
#k,y
STDMI #k
THA
TLA
Object code ( binary )
Operation description
Byte
0110 1010 xxxx xxxx
0101 1010
0110 0101
0110 0111
1001 kkkk
0100 1110 xxxx xx00
1101 kkkk
1000 kkkk
0110 1001 xxxx xxxx
0101 1001
0111 1101
0111 1111
0100 1000 kkkk yyyy
1010 kkkk
0111 0110
0111 0100
Acc←RAM[x]
Acc ←RAM[HL]
Acc←ROM[DP]L
Acc←ROM[DP]H,DP+1
HR←k
LR←RAM[x],HR←RAM[x+1]
Acc←k
LR←k
RAM[x]←Acc
RAM[HL]←Acc
RAM[HL]←Acc, LR-1
RAM[HL]←Acc, LR+1
RAM[y]←k
RAM[HL]←k, LR+1
Acc←HR
Acc←LR
2
1
1
1
1
2
1
1
2
1
1
1
2
1
1
1
Object code ( binary )
Operation description
Byte
Cycle
2
1
2
2
1
2
1
1
2
1
1
1
2
1
1
1
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C
Flag
Z
Z
Z
S
C'
C'
C
C
-
Flag
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
S
C'
C'
C'
C'
C'
C'
C'
C
C
C
C'
10.8.2001
29
S
1
1
1
1
1
1
1
1
1
1
C
C'
1
C'
1
1
(2) Rotate
Mnemonic
RLCA
RRCA
0101 0000
0101 0001
←CF←Acc←
→CF→Acc→
1
1
Cycle
1
1
(3)
3) Arithmetic operation
Mnemonic
Object code ( binary )
Operation description
Byte
ADCAM
ADD
#k,y
ADDA #k
ADDAM
ADDH #k
ADDL #k
ADDM #k
DECA
DECL
DECM
INCA
0111
0100
0110
0111
0110
0110
0110
0101
0111
0101
0101
Acc←Acc + RAM[HL] + CF
RAM[y]←RAM[y] +k
Acc←Acc+k
Acc←Acc + RAM[HL]
HR←HR+k
LR←LR+k
RAM[HL]←RAM[HL] +k
Acc←Acc-1
LR←LR-1
RAM[HL]←RAM[HL]-1
Acc←Acc + 1
1
2
2
1
2
2
2
1
1
1
1
0000
1001 kkkk yyyy
1110 0101 kkkk
0001
1110 1001 kkkk
1110 0001 kkkk
1110 1101 kkkk
1100
1100
1101
1110
* This specification are subject to be changed without notice.
Cycle
1
2
2
1
2
2
2
1
1
1
1
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INCL
INCM
SUBA #k
SBCAM
SUBM #k
0111 1110
0101 1111
0110 1110 0111 kkkk
0111 0010
0110 1110 1111 kkkk
LR←LR + 1
RAM[HL]←RAM[HL]+1
Acc←k-Acc
Acc←RAM[HLl - Acc - CF'
RAM[HL]←k - RAM[HL]
1
1
2
1
2
1
1
2
1
2
C
-
Z
Z
Z
Z
Z
C'
C'
C
C
C
(4) Logical operation
Object code ( binary )
Operation description
Byte
ANDA #k
ANDAM
ANDM #k
ORA
#k
ORAM
ORM #k
XORAM
0110
0111
0110
0110
0111
0110
0111
Acc←Acc&k
Acc←Acc & RAM[HL]
RAM[HL]←RAM[HL]&k
Acc←Acc k
Acc ←Acc RAM[HL]
RAM[HL]←RAM[HL] k
Acc←Acc^RAM[HL]
2
1
2
2
1
2
1
--
1110 0110 kkkk
1011
1110 1110 kkkk
1110 0100 kkkk
1000
1110 1100 kkkk
1001
----
Mnemonic
Cycle
2
1
2
2
1
2
1
Flag
C
Z
Z
Z
Z
Z
Z
Z
Z
S
Z'
Z'
Z'
Z'
Z'
Z'
Z'
(5) Exchange
Mnemonic
Object code ( binary )
Operation description
Byte
EXA x
EXAH
EXAL
EXAM
EXHL x
0110 1000 xxxx xxxx
0110 0110
0110 0100
0101 1000
0100 1100 xxxx xx00
Acc↔RAM[x]
Acc↔HR
Acc↔LR
Acc↔RAM[HL]
LR↔RAM[x],
HR↔RAM[x+1]
2
1
1
1
2
Cycle
Flag
C
Z
S
2
2
2
1
-
Z
Z
Z
Z
1
1
1
1
2
-
-
1
Flag
C
Z
S
(6) Branch
Mnemonic
Object code ( binary )
Operation description
Byte
Cycle
SBR a
00aa aaaa
1
1
-
-
1
LBR a
1100 aaaa aaaa aaaa
If SF=1 then PC←PC11-6.a5-0
else null
If SF= 1 then PC←a else null
2
2
-
-
1
Operation description
Byte
C
Flag
Z
S
C
C
C
C
-
Z
Z
Z
Z
Z
Z
Z'
Z'
Z'
C
Z'
C
(7) Compare
Mnemonic
CMP #k,y
CMPA x
CMPAM
CMPH #k
CMPIA #k
CMPL #k
Object code ( binary )
0100 1011 kkkk yyyy
0110 1011 xxxx xxxx
0111 0011
0110 1110 1011 kkkk
1011 kkkk
0110 1110 0011 kkkk
k-RAM[y]
RAM[x]-Acc
RAM[HL] - Acc
k - HR
k - Acc
k-LR
* This specification are subject to be changed without notice.
2
2
1
2
1
2
Cycle
2
2
1
2
1
2
10.8.2001
30
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
(8) Bit manipulation
Mnemonic
Object code ( binary )
Operation description
Byte
CLM
CLP
CLPL
CLR
SEM
SEP
SEPL
SET
TF
TFA
TFM
TFP
TFPL
TT
TTP
1111 00bb
0110 1101 11bb pppp
0110 0000
0110 1100 11bb yyyy
1111 01bb
0110 1101 01bb pppp
0110 0010
0110 1100 01bb yyyy
0110 1100 00bb yyyy
1111 10bb
1111 11bb
0110 1101 00bb pppp
0110 0001
0110 1100 10bb yyyy
0110 1101 10bb pppp
RAM[HL]b←0
PORT[p]b←0
PORT[LR3-2+4]LR1-0←0
RAM[y]b←0
RAM[HL]b←1
PORT[p]b←1
PORT[LR3-2+4]LRl-0←1
RAM[y]b←1
SF←RAM[y]b'
SF←Accb'
SF←RAM[HL]b'
SF←PORT[p]b'
SF←PORT[LR3-2+4]LR1-0'
SF←RAM[y]b
SF←PORT[p]b
1
2
1
2
1
2
1
2
2
1
1
2
1
2
2
Object code ( binary )
Operation description
Byte
b
p,b
y,b
b
p,b
y,b
y,b
b
b
p,b
y,b
p,b
Cycle
1
2
2
2
1
2
2
2
2
1
1
2
2
2
2
C
-
Flag
Z
-
S
1
1
1
1
1
1
1
1
*
*
*
*
*
*
*
Flag
Z
-
S
-
(9) Subroutine
Mnemonic
Cycle
2
2
1
2
-
-
-
0100 1111
STACK[SP]←PC,
SP←SP -1, PC←a
STACK[SP]←PC,
SP←SP - 1, PC←a,a = 8n + 6
(n =1∼15),0086h (n = 0)
SP←SP + 1, PC←STACK[SP]
C
-
1
2
-
-
-
Mnemonic
Object code ( binary )
Operation description
Byte
INA
INM
OUT
OUTA
OUTM
0110 1111 0100 pppp
0110 1111 1100 pppp
0100 1010 kkkk pppp
0110 1111 000p pppp
0110 1111 100p pppp
Acc←PORT[p]
RAM[HL]←PORT[p]
PORT[p]←k
PORT[p]←Acc
PORT[p]←RAM[HL]
2
2
2
2
2
LCALL a
0100 0aaa aaaa aaaa
SCALL a
1110 nnnn
RET
(10) Input/output
p
p
#k,p
p
p
Cycle
2
2
2
2
2
Flag
Z
Z
-
S
Z'
Z'
1
1
1
Flag
C
Z
-
S
1
1
10.8.2001
31
C
-
(11) Flag manipulation
Mnemonic
Object code ( binary )
Operation description
Byte
CGF
SGF
0101 0111
0101 0101
GF←0
GF←1
1
1
* This specification are subject to be changed without notice.
Cycle
1
1
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TFCFC
TGS
TTCFS
TZS
0101 0011
0101 0100
0101 0010
0101 1011
SF←CF', CF←0
SF←GF
SF←CF, CF←1
SF←ZF
1
1
1
1
1
1
1
1
0
1
-
-
*
*
*
*
(12) Interrupt control
Mnemonic
Object code ( binary )
Operation description
Byte
CIL
r
DICIL r
EICIL r
EXAE
RTI
0110 0011 11rr rrrr
0110 0011 10rr rrrr
0110 0011 01rr rrrr
0111 0101
0100 1101
IL←IL & r
EIF←0,IL←IL&r
EIF←1,IL←IL&r
MASK↔Acc
SP←SP+1,FLAG.PC
←STACK[SP],EIF ←1
2
2
2
1
1
Mnemonic
Object code ( binary )
Operation description
Byte
NOP
0101 0110
no operation
1
Cycle
2
2
2
1
2
Flag
C
Z
*
*
S
1
1
1
1
*
Flag
C
Z
-
S
-
Flag
C
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10.8.2001
32
(13) CPU control
Cycle
1
(14) Timer/Counter & Data pointer & Stack pointer control
Mnemonic
Object code ( binary )
Operation description
Byte
LDADPL
LDADPM
LDADPH
LDASP
LDATAL
LDATAM
LDATAH
LDATBL
LDATBM
LDATBH
STADPL
STADPM
STADPH
STASP
STATAL
STATAM
STATAH
STATBL
STATBM
STATBH
0110 1010 1111 1100
0110 1010 1111 1101
0110 1010 1111 1110
0110 1010 1111 1111
0110 1010 1111 0100
0110 1010 1111 0101
0110 1010 1111 0110
0110 1010 1111 1000
0110 1010 1111 1001
0110 1010 1111 1010
0110 1001 1111 1100
0110 1001 1111 1101
0110 1001 1111 1110
0110 1001 1111 1111
0110 1001 1111 0100
0110 1001 1111 0101
0110 1001 1111 0110
0110 1001 1111 1000
0110 1001 1111 1001
0110 1001 1111 1010
Acc←[DP]L
Acc←[DP]M
Acc←[DP]H
Acc←SP
Acc←[TA]L
Acc←[TA]M
Acc←[TA]H
Acc←[TB]L
Acc←[TB]M
Acc←[TB]H
[DP]L←Acc
[DP]M←Acc
[DP]H←Acc
SP←Acc
[TA]L←Acc
[TA]M←Acc
[TA]H←Acc
[ TB]L←Acc
[TB]M←Acc
[TB]H←Acc
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
* This specification are subject to be changed without notice.
Cycle
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
EM73361A
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
**** SYMBOL DESCRIPTION
Symbol
Description
Symbol
HR
PC
SP
ACC
CF
SF
EI
MASK
ΤΑ
RAM[HL]
ROM[DP]L
[DP]L
[DP]H
H register
Program counter
Stack pointer
Accumulator
Carry flag
Status flag
Enable interrupt register
Interrupt mask
Timer/counter A
Data memory (address : HL )
Low 4-bit of program memory
Low 4-bit of data pointer register
High 4-bit of data pointer register
LR
DP
STACK[SP]
FLAG
ZF
GF
IL
PORT[p]
ΤΒ
RAM[x]
ROM[DP]H
[DP]M
[TA]L([TB]L)
[TA]M([TB]M)
Middle 4-bit of timer/counter A
(timer/counter B) register
Transfer
Addition
Logic AND
Logic XOR
Concatenation
8-bit RAM address
4-bit or 5-bit port address
6-bit interrupt latch
Contents of bit assigned by bit
1 to 0 of LR
Bit 3 to 2 of LR
[TA]H([TB]H)
LR 1-0
LR3-2
↔
--
←
+
&
^
.
x
p
r
'
#k
y
b
PC11-6
a5-0
* This specification are subject to be changed without notice.
Description
L register
Data pointer
Stack specified by SP
All flags
Zero flag
General flag
Interrupt latch
Port ( address : p )
Timer/counter B
Data memory (address : x )
High 4-bit of program memory
Middle 4-bit of data pointer register
Low 4-bit of timer/counter A
(timer/counter B) register
High 4-bit of timer/counter A
(timer/counter B) register
Exchange
Substraction
Logic OR
Inverse operation
4-bit immediate data
4-bit zero-page address
Bit address
Bit 11 to 6 of program counter
Bit 5 to 0 of destination address for
branch instruction
10.8.2001
33
Similar pages