SHARC+ Dual Core DSP with ARM Cortex-A5 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 SYSTEM FEATURES Dual enhanced SHARC+ high performance floating-point cores Up to 450 MHz per SHARC+ core Up to 5 Mbits (640 kB) L1SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short-word, word, long-word addressed ARM Cortex-A5 core 450 MHz/720 DMIPS with Neon/VFPv4-D16/Jazelle 32 kB L1 instruction cache/32 kB L1 data cache 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant Low system power across automotive temperature range MEMORY Large on-chip L2 SRAM with ECC protection, up to 256 kB On-chip L2 ROM (512 kB) Two L3 interfaces optimized for low system power, providing 16-bit interface to DDR3, DDR2 or LPDDR1 SDRAM devices ADDITIONAL FEATURES Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Support for TrustZone® Accelerators High performance pipelined FFT/IFFT engine FIR, IIR, HAE, SINC offload engines PERIPHERALS SYSTEM CONTROL SRU SECURITY AND PROTECTION CORE 0 SYSTEM PROTECTION (SPU) CORE 1 SYSTEM MEMORY PROTECTION UNIT (SMPU) CORE 2 S FAULT MANAGEMENT S 4× PRECISION CLOCK GENERATORS ASRC 8× PAIRS 2x DAI FULL SPORT 2x PIN 0-7 BUFFER 2× S/PDIF Rx/Tx ARM® TrustZone® SECURITY 2 DUAL CRC WATCHDOGS OTP MEMORY THERMAL SENSOR L1 CACHE 32 kB L1 I-CACHE 32 kB L1 D-CACHE L2 CACHE 256 kB (PARITY) 3× I C L1 SRAM (PARITY) L1 SRAM (PARITY) 5M BITS (640 kB) SRAM/CACHE 5M BITS (640 kB) SRAM/CACHE 2× LINK PORTS 2× SPI + 1× QUAD SPI 3× UARTs 1× EPPI PROGRAM FLOW 3× ePWM SYS EVENT CONTROLLER (SEC) 8× TIMERS + 1× COUNTER TRIGGER ROUTING (TRU) SYSTEM CROSSBAR AND DMA SUBSYSTEM ADC CONTROL MODULE (ACM) G P I O CLOCK, RESET, AND POWER ASYNC MEMORY (16-BIT) CLOCK GENERATION (CGU) 2× CAN2.0 CLOCK DISTRIBUTION UNIT (CDU) REAL TIME CLOCK (RTC) RESET CONTROL (RCU) POWER MANAGEMENT (DPM) L3 MEMORY INTERFACES DDR3 DDR2 LPDDR1 DDR3 DDR2 LPDDR1 16 16 DEBUG UNIT ARM® CoreSightTM WATCHPOINTS (SWU) DATA SYSTEM L2 MEMORY SYSTEM ACCELERATION 2M BITS (256 kB) L2 SRAM (ECC) DSP FUNCTIONS (FFT/iFFT, FIR, IIR, HAE/SINC) 4M BITS (512 kB) 2 × 2M BITS ROM ENCRYPTION/DECRYPTION SD/SDIO/eMMC MLB 3-PIN 2× EMAC SINC FILTER 8x SHARC FLAGS 2× USB 2.0 HS MLB 6-PIN DATA PCIe2.0 (1 lane) HADC (8 CHAN, 12-BIT) Figure 1. Processor Block Diagram Rev. PrF Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data TABLE OF CONTENTS General Description ................................................. 3 GPIO Multiplexing for 529-Ball CSP_BGA ................... 54 ARM Cortex-A5 Processor ...................................... 5 ADSP-SC58x/ADSP-2158x Designer Quick Reference .... 58 SHARC Processor ................................................. 6 Specifications ........................................................ 80 SHARC+ Core Architecture .................................... 8 Operating Conditions ........................................... 80 System Infrastructure ........................................... 10 Electrical Characteristics ....................................... 83 System Memory Map ........................................... 11 Absolute Maximum Ratings ................................... 87 Security Features ................................................ 14 ESD Sensitivity ................................................... 87 Safety Features ................................................... 14 Package Information ............................................ 87 Processor Peripherals ........................................... 15 Timing Specifications ........................................... 88 System Acceleration ............................................ 20 Environmental Conditions .................................. 152 System Design .................................................... 20 System Debug .................................................... 23 ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments .................................................... 153 Development Tools ............................................. 23 Numerical by Ball Number ................................... 153 Additional Information ........................................ 24 Alphabetical by Pin Name .................................... 155 Related Signal Chains .......................................... 24 ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments .................................................... 158 Security Features Disclaimer .................................. 24 Numerical by Ball Number ................................... 158 ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions ...................................................... 25 Alphabetical by Pin Name .................................... 161 349-Ball CSP_BGA Signal Descriptions ....................... 30 Outline Dimensions .............................................. 165 GPIO Multiplexing for 349-Ball CSP_BGA .................. 39 Surface-Mount Design ........................................ 166 529-Ball CSP_BGA Signal Descriptions ....................... 42 Pre Release Products .......................................... 167 REVISION HISTORY 2/16—Revision PrE to Revision PrF Revised Processor Comparison ................................... 4 Revised Processor Comparison for Automotive ............... 4 Updated Dynamic Memory Controller (DMC) ............. 15 Updated Digital Audio Interface (DAI) ....................... 15 Updated Serial Ports (SPORT) .................................. 15 Updated Precision Clock Generators (PCG) ................. 16 Changed Max specification for fSPICLKPROG parameter in Clock Related Operating Conditions ........................... 81 Rev. PrF | Page 2 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 GENERAL DESCRIPTION The ADSP-SC58x/ADSP-2158x processors are members of the SHARC® family of products. The ADSP-SC58x processor is based on the SHARC+ dual-core and the ARM Cortex-A5 core. The ADSP-SC58x/ADSP-2158x SHARC processors are members of the SIMD SHARC family of DSPs that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with their large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and innovative digital audio interfaces (DAI). New enhancements to the SHARC+ core add cache enhancements, branch prediction, and other instruction set improvements—all while maintaining instruction set compatibility to previous SHARC products. Table 1. Common Product Features DAI (includes SRU) Full SPORTs S/PDIF Rx/Tx ASRCs Precision Clock Generators I2C (TWI) Quad Data Bit SPI Dual Data Bit SPI CAN2.0 UARTs Link Ports Enhanced PPI GP Timer1 GP Counter Enhanced PWMs2 Watchdog Timers ADC Control Module Static Memory Controller Hardware Accelerators High Performance FFT/IFFT FIR/IIR Harmonic Analysis Engine SINC Filter Security Crypto Engine Multi-channel 12-bit ADC By integrating a rich set of industry-leading system peripherals and memory (see Table 1, Table 2, and Table 3), the ARM/SHARC processor is the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package. These applications span a wide array of markets, from automotive and pro-audio to industrial-based applications that require high floating-point performance. Table 2 provides feature comparison information for features that vary across the standard processors. Table 3 provides feature comparison information for features that vary across the automotive processors. 1 2 Rev. PrF | Page 3 of 168 | ADSP-SC58x / ADSP-2158x 2 2×4 2×1 2×4 2×2 3 1 2 2 3 2 1 8 1 3 2 Yes Yes Yes Yes Yes Yes Yes 8-ch Eight timers are available in the 529-BGA package only. The 349-BGA package does not include Timer 6 and 7. Three ePWMs are available in the 529-BGA package only. The 349-BGA package does not include PWM 2. February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 2. Processor Comparison System Memory Processor Feature ARM Cortex-A5 (MHz max) ARM Core L1 Cache (I, D kB) ARM Core L2 Cache (kB) SHARC+ Core1 (MHz max) SHARC+ Core2 (MHz max) SHARC L1 SRAM/core (kB) L2 SRAM (shared) (kB) L2 ROM (shared) (kB) DDR3/DDR2/LPDDR1 Controller (16-bit) USB 2.0 HS + PHY (host/device/OTG) USB 2.0 HS + PHY (host/device) 10/100 Std EMAC 10/100/1000 Std/AVB EMAC + Timer IEEE-1588 SDIO/eMMC PCIe 2.0 (1 Lane) Real Time Clock (RTC) GPIO + DAI Pins Package Options: 19 mm × 19 mm ADSPSC582 450 32, 32 256 450 – 640 256 512 ADSPSC583 450 32, 32 256 450 450 384 256 512 ADSPSC584 450 32, 32 256 450 450 640 256 512 ADSPSC587 450 32, 32 256 450 450 640 256 512 ADSPSC589 450 32, 32 256 450 450 640 256 512 ADSP21583 – – – 450 450 384 256 512 ADSP21584 – – – 450 450 640 256 512 ADSP21587 – – – 450 450 640 256 512 1 1 1 2 2 1 1 2 1 – – 1 – – 1 – – 1 1 1 1 1 1 – – – – – – – – – 1 1 1 1 1 – – – – – – 80 + 28 349-BGA – – – 80 + 28 349-BGA – – – 80 + 28 349-BGA 1 – 1 102 + 40 529-BGA 1 1 1 102 + 40 529-BGA – – – 80 + 28 349-BGA – – – 80 + 28 349-BGA – – 1 102 + 40 529-BGA Table 3. Processor Comparison for Automotive System Memory Processor Feature ADSP-SC583W ADSP-SC584W ADSP-SC587W ADSP-SC589W ADSP-21583W ADSP-21584W ARM Cortex-A5 (MHz max) 450 450 450 450 – – ARM Core L1 Cache (I, D kB) 32, 32 32, 32 32, 32 32, 32 – – ARM Core L2 Cache (kB) 256 256 256 256 – – SHARC+ Core1 (MHz max) 450 450 450 450 450 450 SHARC+ Core2 (MHz max) 450 450 450 450 450 450 SHARC L1 SRAM/core (kB) 384 640 640 640 384 640 L2 SRAM (shared) (kB) 256 256 256 256 256 256 L2 ROM (shared) (kB) 512 512 512 512 512 512 DDR3/DDR2/LPDDR1 1 1 2 2 1 1 Controller (16-bit) USB 2.0 HS + PHY (host/device/OTG) 1 1 1 1 – – USB 2.0 HS + PHY (host/device) – – 1 1 – – 10/100 Std EMAC – – 1 1 – – 10/100/1000 Std/AVB EMAC + Timer 1 1 1 1 – – IEEE-1588 SDIO/eMMC – – 1 1 – – PCIe 2.0 (1 Lane) – – – 1 – – MLB 3-pin/6-pin 1 1 1 1 1 1 Real Time Clock (RTC) – – 1 1 – – GPIO + DAI Pins 80 + 28 80 + 28 102 + 40 102 + 40 80 + 28 80 + 28 Package Options: 19 mm × 19 mm 349-BGA 349-BGA 529-BGA 529-BGA 349-BGA 349-BGA Rev. PrF | Page 4 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data ARM CORTEX-A5 PROCESSOR • ARM v7 debug architecture The ARM Cortex-A5 processor (Figure 2) is a high performance processor with the following features: • Trace support through an embedded trace macrocell (ETM) interface • Extension: vector floating-point unit (IEEE754) with trapless execution • Instruction and Data L1 cache units (32/32K bytes) • In-order pipeline with dynamic branch prediction • Extension: media processing engine (MPE) with NEON technology • ARM, Thumb, and ThumbEE instruction set support • TrustZone security extensions • Extension: Jazelle hardware acceleration • Harvard level 1 memory system with a memory management unit (MMU) EMBEDDED TRACE MACROCELL (ETM) INTERFACE CoreSight INTERFACE CORTEX-A5 PROCESSOR TM DEBUG CP15 DATA PROCESSING UNIT (DPU) PREFETCH UNIT AND BRANCH PREDICTOR (PFU) DATA MICRO-TLB DATA STORE BUFFER (STB) NEON MEDIA PROCESSING ENGINE INSTRUCTION MICRO-TLB DATA CACHE UNIT (DCU) INSTRUCTION CACHE UNIT (ICU) MAIN TRANSMISSION LOOKINSIDE BUFFER (TLB) 32 KB 32 KB BUS INTERFACE UNIT (BIU) A5 BUS MASTER PORT GENERIC INTERRUPT CONTROLLER (PrimeCell® PL-390) L2 CACHE CONTROLLER (CoreLinkTM PL-310) DATA MASTER PORTS SHARC PROCESSORS 256 KB SYSTEM FABRIC TO OTHER CORES Figure 2. ARM Cortex A-5 Processor Block Diagram Rev. PrF | Page 5 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Generic Interrupt Controller, PL390 (ADSP-SC58x only) L2 Cache Controller, PL310 (ADSP-SC58x only) The generic interrupt controller (GIC) is a centralized resource for supporting and managing interrupts. The ADSP-SC58x processor has a uniprocessor implementation of the GIC. The GIC splits logically into GICPORT0 (distributor block) and GICPORT1 (CPU interface block). The L2 cache controller PL310 (Figure 2) works efficiently with ARM processors that implement system fabric. The cache controller directly interfaces on the data and instruction interface. The internal pipelining of the cache controller is optimized to enable the processors to operate at the same clock frequency. The cache controller supports: Generic Interrupt Controller Port0 (GICPORT0) • Two read/write 64-bit slave ports for interfacing with data and instruction interfaces or for data between ARM and SHARC cores The GICPORT0 (distributor) performs interrupt prioritization and distribution to the GICPORT1 (CPU interface) blocks that connect to the processors in the system. It centralizes all interrupt sources, determines the priority of each interrupt, and forwards the interrupt with the highest priority to the interface, for priority masking and preemption handling. • Two read/write 64-bit master ports for interfacing with the system fabric SHARC PROCESSOR Generic Interrupt Controller Port1 (GICPORT1) As shown in Figure 3, the SHARC processor integrates a SHARC+ SIMD core, L1 memory crossbar, I/D cache controller, L1 memory blocks, and the master/slave ports. The SHARC+ SIMD core is shown in Figure 4. GICPORT1 (CPU interface) block performs priority masking and preemption handling for a connected processor in the system. GICPORT1 supports 8 SGIs (software generated interrupts) and 254 SPIs (shared peripheral interrupts). B2 RAM B2 B1 RAM S P-CACHE B0 RAM B2 RAM SIMD Processor CCLK DOMAIN B0 (64) B3 RAM B1 (64) D-CACHE P-CACHE B2 (64) P-CACHE D-CACHE B3 (64) I-CACHE The SHARC processor supports a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories typically operate at the full processor speed with little or no latency. IO (32) IO (32) SLAVE PORT 1 IO (32) PM (64) DM (64) INTERNAL MEMORY INTERFACE (IMIF) I/D CACHE CONTROL SLAVE PORT 2 IO (32) SYSTEM FABRIC SYSCLK DOMAIN CORE MMR (32) DM (64) CMD (64) PM (64) SHARC+ SIMD CORE MASTER PORT DATA CMI (64) PS (64/48) MASTER PORT INSTRUCTION INTERRUPT SEC Figure 3. SHARC Processor Block Diagram Rev. PrF | Page 6 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 S+ DEBUG TRACE SIMD Core BTB BP CEC FLAGS CONFLICT CACHE PM DATA 48 DMD/PMD 64 11-STAGE PROGRAM SEQUENCER PM ADDRESS 24 DAG1 16 × 32 DAG2 16 × 32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 PM DATA 64 TO IMIF USTAT PX DM DATA 64 MULTIPLIER MRF 80-BIT MRB 80-BIT SHIFTER ALU PEX DATA REGISTER Rx 16 × 40-BIT DATA SWAP PEY DATA REGISTER Sx 16 × 40-BIT ASTATx ASTATy STYKx STYKy ALU SHIFTER MULTIPLIER MSB 80-BIT MSF 80-BIT Figure 4. SHARC+ SIMD Core Block Diagram L1 Memory The ADSP-SC58x/ADSP-2158x memory structure is shown in Figure 5 on Page 8. Each SHARC+ core has a tightly coupled Level 1 (L1) SRAM of up to 5 Mbits. Each SHARC+ core can access code and data in a single cycle from this memory space. The ARM Cortex-A5 core can also access these memory spaces with multi-cycle accesses. In the SHARC+ core private address space, both cores have their own L1 memory. SHARC+ core MMR address space is 0x 0000 0000-0x0003 FFFF in Normal Word (32-bit). Each block can be configured for different combinations of code and data storage. Of the 5M bits SRAM, up to 1024K bits can be configured for DM, PM, and instruction cache. Each memory block supports single cycle, independent accesses by the core processor and I/O processor. The memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor in a single cycle. The processor’s SRAM can be configured as a maximum of 160K words of 32-bit data, 320K words of 16-bit data, 106.7K words of 48-bit Rev. PrF | instructions (or 40-bit data), or combinations of different word sizes up to 5 M bits. All of the memory can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The system configuration is flexible, but a configuration is 512K bits DM, 128K bits PM, and 128K bits of cache, with the remaining L1 memory configured as SRAM is typical. Each addressable memory space outside the L1 memory can be accessed either directly or via cache. Page 7 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 The memory map in Table 4 on Page 11 gives the L1 memory address space. Preliminary Technical Data 0x FFFF FFFF DMC1 (1GB) 0x C000 0000 In addition, there are multiple L1 memory blocks offering a configurable mix of SRAM and cache. DMC0 (1GB) 0x 8000 0000 SPI2 FLASH (512MB) 0x 6000 0000 L1 Master and Slave Ports PCIe DATA (256MB) 0x 5000 0000 SMC BANK 3 (64MB) Each SHARC+ core has two master and two slave ports to/from the system fabric. One master port fetches instructions; the second master port drives data to the system world. Both slave ports allow conflict free core/DMA streams to the individual memory blocks. For slave port addresses, refer to the L1 memory address map. 0x 4C00 0000 SMC BANK 2 (64MB) 0x 4800 0000 SMC BANK 1 (64MB) 0x 4400 0000 SMC BANK 0 (64MB) 0x 4000 0000 SYSTEM MMR SPACE 0x 3000 0000 RESERVED L1 On-Chip Memory Bandwidth 0x 28FA 0000 The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming no block conflicts). The total bandwidth is realized using the DMD and PMD buses (2 × 64-bits, CCLK speed and 2 × 32-bit, SYSCLK speed). 0x 28A4 0000 SHARC2 LI MEMORY IN MULTIPROCESSOR SPACE RESERVED 0x 287A 0000 0x 2824 0000 SHARC1 LI MEMORY IN MULTIPROCESSOR SPACE UNIFIED ADDRESS SPACE RESERVED 0x 202B FFFF L2 ROM 2 (2Mb) 0x 2028 0000 RESERVED Instruction and Data Cache 0x 2020 7FFF The ADSP-SC58x/ADSP-2158x processors also include a traditional instruction cache (I-cache) and two data caches. (PM/DM caches). Together, these caches support one instruction access and two data accesses, over the DM and PM buses, per cycle. The cache controllers automatically manage the configured part of the L1 memory. The system can configure part of the L1 memory for automatic management by the cache controllers. The sizes of these caches are independently configurable from zero to a maximum of 128 kB each. The memory not managed by the cache controllers is directly addressable by the processors. The controllers ensure the data coherence between the two data caches. The caches provide user-controllable features such as locking (full as well as partial), range-bound invalidation, and flushing. 0x 2020 0000 RESERVED 0x 201B FFFF L2 ROM 1 (2Mb) 0x 2018 0000 RESERVED 0x 2010 7FFF 0x 2010 0000 RESERVED L2 SRAM (2Mb) 0x 2008 0000 RESERVED 0x 2000 7FFF 0x 2000 0000 L2 BOOT ROM 0 (0.25Mb) (ARM CORE 0) 0x 2000 0000 RESERVED 0x 0039 FFFF L1 BLOCK 3 SRAM (1Mb) 0x 0038 0000 RESERVED ARM ADDRESS SPACE RESERVED 0x 0031 FFFF L1 BLOCK 2 SRAM (1Mb) 0x 0030 0000 RESERVED 0x 002E FFFF L1 BLOCK 1 SRAM (1.5Mb) SHARC PRIVATE ADDRESS SPACE The output of the SEC controller is forwarded to the core event controller (CEC) to respond directly to all unmasked system based interrupts. It also supports nesting including various SEC interrupt channel arbitration options. For all SEC channels the processor automatically stacks the arithmetic status (ASTATx, and STATy) registers and mode (MODE1) registers in parallel with the interrupt servicing. The core memory mapped registers control L1 I/D cache, BTB, L2 cache, parity error, system control, debug and monitor functions. L2 BOOT ROM 1 (0.25Mb) (SHARC Cores) 0x 200B FFFF System Event Controller Input Core Memory-Mapped Registers (CMMR) L2 BOOT ROM 2 (0.25Mb) (SHARC Cores) 0x 002C 0000 0x 1000 1000 ARM L2 CONFIG REGS (4KB) RESERVED 0x 1000 0000 0x 0026 FFFF RESERVED L1 BLOCK 0 SRAM (1.5Mb) 0x 0000 7FFF 0x 0024 0000 ARM BOOT (32KB) 0x 0000 0000 RESERVED/CORE MMRs/ OTHER MEMORY ALIASES 0x 0000 0000 Figure 5. ADSP-SC58x/ADSP-2158x Memory Map ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-214xx and ADSP-2116x SIMD SHARC processors, as shown in Figure 4 and detailed in the following sections. SIMD Computational Engine SHARC+ CORE ARCHITECTURE The ADSP-SC58x/ADSP-2158x processors are code compatible at the assembly level with the ADSP-2148x, ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-SC58x/ADSP2158x processors share architectural features with the Rev. PrF | The SHARC+ core contains two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEx and PEy and each contains an ALU, multiplier, shifter, and register file. PEx is always active, and PEy is enabled by setting the PEYEN mode bit in the MODE1 register. SIMD mode allows the processors to execute the same instruction in both Page 8 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 processing elements, but each processing element operates on different data. This architecture is efficient at executing mathintensive DSP algorithms. In addition to all the features of its predecessors, the SHARC+ core also provides a new and simpler way to execute an instruction only on PEy. SIMD mode also affects the way data transfers between memory and the processing elements because to sustain computational operation in the processing elements requires twice the data bandwidth. Therefore, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values transfer with each memory or register file access. Independent, Parallel Computation Units Within each processing element is a set of pipelined computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units are arranged in parallel, maximizing computational throughput. These computational units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, IEEE 64-bit double-precision floating-point, and 32-bit fixed-point data formats. Multifunction instruction set supports parallel execution of ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements per core. All processing operations take one cycle to complete. For all floating-point operations, the processor takes two cycles to complete in case of data dependency. Double-precision floating-point data take two to six cycles to complete. The processor stalls for the appropriate number of cycles (interlocked pipeline plus data dependency check). Core Timer Each SHARC+ processor core also has its own dedicated timer. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generating periodic operating system interrupts. Data Register File Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the enhanced Harvard architecture of the processor, allow unconstrained data flow between computation units and internal memory. The registers in PEx are referred to as R0-R15 and in PEy as S0-S15. Context Switch Many of the registers of the processor have secondary registers that can activate during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result registers all have secondary registers. The primary registers are active at reset, while control bits in a mode control register activate the secondary registers. Rev. PrF | Universal Registers General-purpose tasks use these registers. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all peripheral registers (control/status). The data bus exchange register (PX) permits data to pass between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference. Data Address Generators With Zero-Overhead Hardware Circular Buffer Support For indirect addressing and implementing circular data buffers in hardware, the processor uses the two data address generators (DAGs). Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the processors contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible ISA Instruction Set The 48-bit instruction word accommodates various parallel operations for concise programming. For example, the processors can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. Additionally, the double precision floating-point instruction set is an addition to the SHARC+ core. Variable Instruction Set Architecture (VISA) In addition to supporting the standard 48-bit instructions (ISA) from previous SHARC processors, the SHARC+ core processors support new instructions of 16 and 32 bits for ADSP-214xx products. This feature, called Variable Instruction Set Architecture (VISA), drops redundant/unused bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32-bit instructions from both internal and external memories. VISA is not an operating mode, it is only address-dependent (refer to memory map ISA/VISA address spaces). Furthermore, it allows jumps between ISA and VISA instruction fetches. Single-Cycle Fetch of Instructional Four Operands The ADSP-SC58x/ADSP-2158x processors feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data. With its separate program and data memory buses and on-chip instruction conflict-cache, the processors can simultaneously fetch four operands (two over each data bus) and one instruction (from the conflict-cache), all in a single cycle. Page 9 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 • Storage for additional data for either ARM or SHARC+ cores to avoid external memory latencies and reduce external memory bandwidth Core Event Controller (CEC) The SHARC+ core IVT generates various core interrupts (arithmetic and circular buffer instruction flow exceptions) and SEC events (debug/monitor, software). The core only responds to interrupts which are unmasked (IMASK register). • Storage for incoming Ethernet traffic to improve performance • Storage for data coefficient tables cached by the SHARC+ core Instruction Conflict-Cache The processors include a 32-entry instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses cache. This cache allows full speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. The conflict cache serves for on-chip bus conflicts only. Preliminary Technical Data See System Memory Protection Unit (SMPU) for options in limiting access by specific cores and DMA masters. The ARM Cortex-A5 core has an L1 instruction and data cache, each of which is 32 kB in size. An L2 cache controller of 256 kB is also available. When enabling the caches, accesses to all other memory spaces (internal and external) go through the cache. Branch Target Buffer/Branch Predictor SHARC+ Core L1 Memory in Multiprocessor Space Implementation of a hardware-based branch predictor (BP) and branch target buffer (BTB) reduce branch delay. The program sequencer supports efficient branching using this branch target buffer (BTB) for conditional and unconditional instructions. The ARM Cortex-A5 core can access the L1 memory of the SHARC+ core. See Table 6 for the L1 memory address in multiprocessor space. The SHARC+ core can access the L1 memory of the other SHARC+ core in the multiprocessor space. Addressing Spaces One-Time-Programmable Memory (OTP) In addition to traditionally supported long-word, normal word, extended-precision word and short word addressing aliases, the processors support byte addressing for the data and instruction accesses. The enhanced ISA/VISA provides new instructions for accessing all sizes of data from byte space as well as for converting word addresses to byte and byte to word addresses. The processors feature 7K bits of one-time-programmable (OTP) memory which is memory-map accessible. This memory stores a unique chip identification and supports secure-boot and secure operation. Additional Features The enhanced ISA/VISA of the ADSP-SC58x/ADSP-2158x processors also provides memory barrier instruction (sync) for data synchronization, exclusive data accesses support for multi-core data sharing, and exclusive data accesses to enable multiprocessor programming. To enhance the reliability of application, L1 data RAMs support parity error detection logic for every byte. Additionally, the processors detect illegal opcodes. Core interrupts flag both the errors. Master ports of the core also detect for failed external accesses. I/O Memory Space The static memory controller (SMC) is programmed to control up to two blocks of external memories or memory-mapped devices, with flexible timing parameters. Each block occupies an 8K byte segment regardless of the size of the device used. Mapped I/Os also include PCIe data and SPI2 memory address space. See Table 7. SYSTEM INFRASTRUCTURE The following sections describe the system infrastructure of the ADSP-SC58x/ADSP-2158x processors. System L2 Memory A system level L2 memory of 2 Mbits (256 kB) is also available to both SHARC+ cores, the ARM Cortex-A5 core, and DMA channels. (See Table 5.) Memory accesses to this memory space are multi-cycle accesses by both the ARM and SHARC+ cores. The memory space is used for various cases including: • ARM-to-SHARC+ core data sharing and inter-core communications • Accelerator and peripheral source and destination memory to avoid having to access data in external memory • A location for DMA descriptors Rev. PrF | Page 10 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 SYSTEM MEMORY MAP Table 4. L1 Block 0, 1, 2, and 3 SHARC Addressing Memory Map (Private Address Space) Memory L1 Block 0 SRAM (1.5 Mb) L1 Block 1 SRAM (1.5 Mb) L1 Block 2 SRAM (1 Mb) L1 Block 3 SRAM (1 Mb) Long Word (64 Bits) 0x00048000– 0x0004DFFF 0x00058000– 0x0005DFFF 0x00060000– 0x00063FFF 0x00070000– 0x00073FFF Extended Precision/ ISA Code (48 Bits) 0x00090000– 0x00097FFF 0x000B0000– 0x000B7FFF 0x000C0000– 0x000C5554 0x000E0000– 0x000E5554 Normal Word (32 Bits) 0x00090000– 0x0009BFFF 0x000B0000– 0x000BBFFF 0x000C0000– 0x000C7FFF 0x000E0000– 0x000E7FFF Short Word/ VISA Code (16 Bits) 0x00120000– 0x00137FFF 0x00160000– 0x00177FFF 0x00180000– 0x0018FFFF 0x001C0000– 0x001CFFFF Byte Access (8 Bits) 0x00240000– 0x0026FFFF 0x002C0000– 0x002EFFFF 0x00300000– 0x0031FFFF 0x00380000– 0x0039FFFF Table 5. L2 Memory Addressing Map Memory L2 Boot-ROM01 L2 RAM (2 Mb) Boot ROM1 L2 ROM1 Boot ROM2 L2 ROM2 1 Byte Address Space ARM – Data Access and Instruction Fetch SHARC – Data Access ARM: 0x00000000–0x00007FFF SHARC/DMA: 0x20000000–0x20007FFF 0x20080000–0x200BFFFF 0x20100000–0x20107FFF 0x20180000–0x201BFFFF 0x20200000–0x20207FFF 0x20280000–0x202BFFFF Normal Word Address Space for Data Access SHARC Instruction Fetch VISA Address Space SHARC Instruction Fetch ISA Address Space SHARC 0x08000000–0x08001FFF 0x08020000–0x0802FFFF 0x08040000–0x08041FFF 0x08060000–0x0806FFFF 0x08080000–0x08081FFF 0x080A0000–0x080AFFFF 0x00B80000–0x00B83FFF 0x00BA0000–0x00BBFFFF 0x00B00000–0x00B03FFF 0x00B20000–0x00B3FFFF 0x00B40000–0x00B43FFF 0x00B60000–0x00B7FFFF 0x00580000–0x00581555 0x005A0000–0x005AAAAF 0x00500000–0x00501555 0x00520000–0x0052AAAF 0x00540000–0x00541555 0x00560000–0x0056AAAF From the ARM point of view, L2 Boot-ROM0 byte address space is 0x 0000 0000–0x 0000 7FFF. Table 6. SHARC L1 Memory in Multiprocessor Space L1 Memory of SHARC1 in Multiprocessor Space Address via Slave1 Port Address via Slave2 Port L1 Memory of SHARC2 in Multiprocessor Space Address via Slave1 Port Address via Slave2 Port Memory Block Block0 Block1 Block2 Block3 Block0 Block1 Block2 Block3 Block0 Block1 Block2 Block3 Block0 Block1 Block2 Block3 Rev. PrF | Byte Address Space for ARM and SHARC 0x28240000–0x28270000 0x282C0000–0x282F0000 0x28300000–0x28320000 0x28380000–0x283A0000 0x28640000–0x28670000 0x286C0000–0x286F0000 0x28700000–0x28720000 0x28780000–0x287A0000 0x28A40000–0x28A70000 0x28AC0000–0x28AF0000 0x28B00000–0x28B20000 0x28B80000–0x28BA0000 0x28E40000–0x28E70000 0x28EC0000–0x28EF0000 0x28F00000–0x28F20000 0x28F80000–0x28FA0000 Page 11 of 168 | February 2016 Normal Word Address Space for SHARC 0x0A090000–0x0A09C000 0x0A0B0000–0x0A0BC000 0x0A0C0000–0x0A0C8000 0x0A0E0000–0x0A0E8000 0x0A190000–0x0A19C000 0x0A1B0000–0x0A1BC000 0x0A1C0000–0x0A1C8000 0x0A1E0000–0x0A1E8000 0x0A290000–0x0A29C000 0x0A2B0000–0x0A2BC000 0x0A2C0000–0x0A2C8000 0x0A2E0000–0x0A2E8000 0x0A390000–0x0A39C000 0x0A3B0000–0x0A3BC000 0x0A3C0000–0x0A3C8000 0x0A3E0000–0x0A3E8000 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 7. Memory Map of Mapped I/Os SMC Bank 0 (64 MB) SMC Bank 1 (64 MB) SMC Bank 2 (64 MB) SMC Bank 3 (64 MB) PCIe Data (256 MB) SPI2 Memory (512 MB) Byte Address Space ARM – Data Access and Instruction Fetch SHARC – Data Access 0x40000000–0x43FFFFFF 0x44000000–0x47FFFFFF 0x48000000–0x4BFFFFFF 0x4C000000–0x4FFFFFFF 0x50000000–0x5FFFFFFF 0x60000000–0x7FFFFFFF SHARC Core Instruction Fetch Normal Word Address Space for Data Access SHARC 0x01000000–0x01FFFFFF Not Available Not Available Not Available 0x02000000–0x03FFFFFF 0x04000000–0x07FFFFFF VISA Space 0x00F00000–0x00F3FFFF Not Available Not Available Not Available 0x00F40000–0x00F7FFFF 0x00F80000–0x00FFFFFF ISA Space 0x00700000–0x0073FFFF Not Available Not Available Not Available 0x00740000–0x0077FFFF 0x00780000–0x007FFFFF Table 8. DMC Memory Map DMC0 – 1 GB DMC1 – 1 GB Byte Address Space ARM – Data Access and Instruction Fetch SHARC – Data Access 0x80000000–0xBFFFFFFF 0xC0000000–0xFFFFFFFF SHARC Core Instruction Fetch Normal Word Address Space for Data Access SHARC 0x10000000–0x17FFFFFF 0x18000000–0x1FFFFFFF System Crossbars (SCB) The system crossbars (SCB) are the fundamental building blocks of a switch-fabric style for (on-chip) system bus interconnection. The SCBs connect system bus masters to system bus slaves, providing concurrent data transfer between multiple bus masters and multiple bus slaves. A hierarchical model— built from multiple SCBs—provides a power and area efficient system interconnect, which satisfies the performance and flexibility requirements of a specific system. The SCBs provide the following features: • Highly efficient, pipelined bus transfer protocol for sustained throughput ISA Space 0x00400000–0x004FFFFF 0x00600000–0x006FFFFF All DMAs can transport data to and from all on-chip and offchip memories. Programs can use two types of DMA transfers, descriptor-based or register-based. Register-based DMA allows the processors to program DMA control registers directly to initiate a DMA transfer. On completion, the control registers automatically update with their original setup values for continuous transfer. Descriptor-based DMA transfers require a set of parameters stored within memory to initiate a DMA sequence. Descriptor-based DMA transfers allow multiple DMA sequences to be chained together. Program a DMA channel to set up and start another DMA transfer automatically after the current sequence completes. The DMA engine supports the following DMA operations: • Full-duplex bus operation for flexibility and reduced latency • A single linear buffer that stops on completion • A linear buffer with negative, positive or zero stride length • Concurrent bus transfer support to allow multiple bus masters to access bus slaves simultaneously • Protection model (privileged/secure) support for selective bus interconnect protection Direct Memory Access (DMA) The processors use direct memory access (DMA) to transfer data within memory spaces or between a memory space and a peripheral. The processors can specify data transfer operations and return to normal processing while the fully integrated DMA controller carries out the data transfers independent of processor activity. DMA transfers can occur between memory and a peripheral or between one memory and another memory. Each memory-tomemory DMA stream uses two channels, where one channel is the source channel, and the second is the destination channel. Rev. PrF VISA Space 0x00800000–0x00AFFFFF 0x00C00000–0x00EFFFFF | Page 12 of 168 | • A circular, auto-refreshing buffer that interrupts when each buffer becomes full • A similar buffer that interrupts on fractional buffers (for example, 1/2, 1/4) • 1D DMA: Uses a set of identical ping-pong buffers defined by a linked ring of two-word descriptor sets, each containing a link pointer and an address • 1D DMA: Uses a linked list of four word descriptor sets containing a link pointer, an address, a length, and a configuration • 2D DMA: Uses an array of one-word descriptor sets, specifying only the base DMA address • 2D DMA: Uses a linked list of multi-word descriptor sets, specifying everything February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The processors provide support for five different types of events: Memory DMA (MDMA) The processor supports various memory-to-memory DMA operations which include: • Emulation: An emulation event causes the processors to enter emulation mode, allowing command and control of the processors through the JTAG interface. • Standard bandwidth MDMA channels with CRC protection (32-bit bus width, run on SCLK0) • Enhanced bandwidth MDMA channel (32-bit bus width, runs on SYSCLK) • Reset: This event resets the processors. • Exceptions: Events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions triggered on the one side by the SHARC+ core, such as data alignment (SIMD/long word) or compute violations (fixed or floating point), and illegal instructions cause core exceptions. Conditions triggered on the other side by the SEC, such as ECC/parity/watchdog/system clock, cause system exceptions. • Maximum bandwidth MDMA channels (64-bit bus width, run on SYCLK, one channel may be assigned to the FFT accelerator) Extended Memory DMA Extended memory DMA supports various operating modes such as delay line (allows processor reads and writes to external delay line buffers and hence to external memory) with limited core interaction and scatter/gather DMA (writes to/from noncontiguous memory blocks). • Interrupts: Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. CRC Protection The CRC protection modules allow system software to calculate the signature of code or data or both in memory, the content of memory-mapped registers, or communication message objects periodically. Dedicated hardware circuitry compares the signature with pre calculated values and triggers appropriate fault events. System Event Controller (SEC) Both SHARC+ cores feature a system event controller. System event controller features include the following: • Comprehensive system event source management including interrupt enable, fault enable, priority, core mapping and source grouping For example, every 100 ms the system software initiates the signature calculation of the entire memory contents and compares these contents with expected, pre calculated values. If a mismatch occurs, a fault condition is generated (through the processor core or the trigger routing unit). • Distributed programming model where each system event source control and all status fields are independent of all others • Determinism where all system events have the same propagation delay and provide unique identification of a specific system event source The CRC is a hardware module based on a CRC32 engine that computes the CRC value of the 32-bit data words presented to it. The source channel of the memory-to-memory DMA (in memory scan mode) provides data. The data forwards optionally to the destination channel (memory transfer mode). The main features of the CRC peripheral are: • Slave Control Port which provides access to all SEC registers for configuration, status, and interrupt/fault service model • Global locking supports a register level protection model to prevent writes to “locked” registers • Memory scan mode • Memory transfer mode • Fault management including fault action configuration, time out, external indication, and system reset • Data verify mode • Data fill mode Trigger Routing Unit (TRU) • User-programmable CRC32 polynomial The TRU provides system-level sequence control without core intervention. The TRU maps trigger masters (generators of triggers) to trigger slaves (receivers of triggers). Slave endpoints can be configured to respond to triggers in various ways. Common applications enabled by the TRU include: • Bit/byte mirroring option (endianness) • Fault/error interrupt mechanisms • 1D and 2D fill block to initialize array with constants • 32-bit CRC signature of a block of a memory or MMR block • Automatically triggering the start of a DMA sequence after a sequence from another DMA channel completes Event Handling • Software triggering The processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that • Synchronization of concurrent activities Rev. PrF | Page 13 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data SECURITY FEATURES System Protection Unit (SPU) The following sections describe the security features of the ADSP-SC58x/ADSP-2158x processors. The system protection unit (SPU) guards against accidental or unwanted access to an MMR space of the peripheral by providing a write-protection mechanism. The user is able to choose and configure the protected peripherals as well as configure which ones of the four system MMR masters (core, memory DMA, and CoreSight debug) the peripherals are guarded against. ARM TrustZone The ADSP-SC58x processors provide TrustZone technology, which is tightly integrated into the Cortex-A5 processors. This technology enables a secure state which is also extended throughout the system through the AMBA AXI buses and interconnect fabric. Crypto Hardware Accelerators The ADSP-SC58x/ADSP-2158x processors support standardsbased hardware-accelerated encryption, decryption, authentication, and true random number generation. Support for the following hardware-accelerated cryptographic ciphers include: • AES in ECB, CBC, ICM and CTR modes with 128-bit, 192-bit, and 256-bit keys • DES in ECB and CBC mode with 56-bit key • 3DES in ECB and CBC mode with 3x 56-bit key • ARC4 in stateful, stateless mode, up to 128-bit key Support for the following hardware-accelerated hash functions include: The SPU is also part of the security infrastructure. Along with providing write-protection functionality, the SPU is employed to define which resources in the system are secure or non-secure and to block access to secure resources from non-secure masters. System Memory Protection Unit (SMPU) Synonymously, the system memory protection unit (SMPU) provides memory protection against read and/or write transactions to defined regions of memory. There are SMPU units in the ADSP-SC58x/ADSP-2158x processors for each memory space, except for SHARC L1 and SPI direct memory slave. The SMPU is also part of the security infrastructure. It allows the user to not only protect against arbitrary read and/or write transactions, but it also allows regions of memory to be defined as secure and prevent non-secure masters from accessing those memory regions. • SHA-1 SAFETY FEATURES • SHA-2 with 224-bit and 256-bit digest The ADSP-SC58x/ADSP-2158x processors have been designed to support functional safety applications. While the level of safety is mainly dominated by the system concept, the following primitives are provided by the devices to build a robust safety concept. • HMAC transforms for SHA-1 and SHA-2 • MD5 Public Key Accelerator is available to offload computationintensive public key cryptography operations. Multi-Parity-Bit-Protected SHARC+ Core L1 Memories Both a hardware-based non-deterministic random number generator and pseudo-random number generator are available. Secure boot is also available with 224-bit elliptic curve digital signatures ensuring integrity and authenticity of the boot stream. Optionally, ensuring confidentiality through AES-128 encryption is available. CAUTION This product includes security features that can be used to protect embedded nonvolatile memory contents and prevent execution of unauthorized code. When security is enabled on this device (either by the ordering party or the subsequent receiving parties), the ability of Analog Devices to conduct failure analysis on returned devices is limited. Contact Analog Devices for details on the failure analysis limitations for this device. Employ secure debug to allow only trusted users to access the system with debug tools. Rev. PrF | In the SHARC+ core L1 memory space, whether SRAM or cache, each word is protected by multiple parity bits to detect the single event upsets that occur in all RAMs. The cache tags are not protected by parity. ECC-Protected L2 Memories Error correcting codes (ECC) are used to correct single event upsets. The L2 memory is protected with a single error correctdouble error detect (SEC-DED) code. By default ECC is enabled, but it can be disabled on a per-bank basis. Single-bit errors are transparently corrected. Dual-bit errors can issue a system event or fault if enabled. ECC protection is fully transparent to the user, even if L2 memory is read or written by 8-bit or 16-bit entities. CRC-Protected Memories While parity bit and ECC protection mainly protect against random soft errors in L1 and L2 memory cells, the CRC engines can be used to protect against systematic errors (pointer errors) and static content (instruction code) of L1, L2 and even L3 memories (DDR2, LPDDR). The processors feature two CRC engines which are embedded in the memory-to-memory DMA controllers. CRC checksums can be calculated or compared on the fly Page 14 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 during memory transfers, or one or multiple memory regions can be continuously scrubbed by a single DMA work unit as per DMA descriptor chain instructions. The CRC engine also protects data loaded during the boot process. Signal Watchdogs The eight general-purpose timers feature modes to monitor offchip signals. The watchdog period mode monitors whether external signals toggle with a period within an expected range. The watchdog width mode monitors whether the pulse widths of external signals are within an expected range. Both modes help to detect undesired toggling (or lack thereof) of system-level signals. System Event Controller (SEC) Besides system events the SEC further supports fault management including fault action configuration as time out, internal indication by system interrupt or external indication via SYS_FAULT pin, and system reset. PROCESSOR PERIPHERALS The following sections describe the peripherals of the ADSPSC58x/ADSP-2158x processors. Serial Ports (SPORT) The processors feature 8 synchronous full serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices AD19xx/ADAU19xx family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. An individual full SPORT module consists of two independently configurable SPORT halves with identical functionality. Two bidirectional data lines—primary (0) and secondary (1) per SPORT half, configurable as either transmitters or receivers. Therefore, each SPORT half can be configured for two transmitter or two receiver channels, permitting two unidirectional streams into or out of the same full SPORT. This bidirectional functionality provides greater flexibility for serial communications. For full-duplex configuration, one half SPORT provides two transmit signals, while the other half SPORT provides the two receive signals. The frame sync and clock are shared. The maximum SCLK is 1024xFS (TX master, RX slave) and 512xFS (TX slave, RX master). Serial ports operate in six modes: • Standard DSP serial mode Dynamic Memory Controller (DMC) • Multichannel (TDM) mode The 16-bit DMC interfaces to: • I2S mode • LPDDR1 (JESD209A) max freq 200 MHz DDRCLK (64M bit – 2G bit) • Packed I2S mode • Left-justified mode • DDR2 (JESD79-2E) max freq 400 MHz DDRCLK (256M bit – 4Gbit) • Right-justified mode • DDR3 (JESD79-3E) max freq 450 MHz DDRCLK (512M bit – 8G bit) Asynchronous Sample Rate Converter (ASRC) See Table 8 for DMC memory map. Digital Audio Interface (DAI) The processor supports two DAI units which are mirrored. Each DAI provides the ability to connect various peripherals to any of the DAI pins (DAI_PIN20–PIN01). Programs make these connections using the signal routing unit (SRU), shown in Figure 1 on Page 1. The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI includes the peripherals described in the following sections. DAI pin buffers 20–19 can be used to change the polarity of the input signals. Signals of the peripherals belonging to different DAIs cannot be interconnected, with few exceptions. The DAI pin buffers may also be used as GPIO pins. DAI input signals allow the triggering of interrupts on the rising edge, the falling edge, or both edges. Rev. PrF | The asynchronous sample rate converter (ASRC) contains eight ASRC blocks, is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter, and provides up to 140 dB SNR. The ASRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the ASRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. S/PDIF-Compatible Digital Audio Receiver/Transmitter The Sony/Philips Digital Interface (S/PDIF) is a standard audio data transfer format that allows the transfer of digital audio signals from one device to another without having to convert them to an analog signal. There are two S/PDIF Tx/Rx blocks on the processor. The digital audio interface carries three types of information; audio data, non audio data (compressed data) and timing information. The S/PDIF interface supports one stereo channel or compressed audio streams. The S/PDIF transmitter and receiver is AES3-compliant. The S/PDIF receiver supports professional jitter standard. Page 15 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left-justified, I2S or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources, such as the SPORTs, external pins, and the precision clock generators (PCGs), and are controlled by the SRU control registers. Precision Clock Generators (PCG) The precision clock generators (PCG) consist of four units, units A/B located in DAI0 and units C/D located into DAI1. The PCG can generate a pair of signals (clock and frame sync) derived from a clock input signal (CLKIN1-0, SCLK0, DAI pin buffer). Each unit can also access the opposite DAI unit. All units are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Parallel Peripheral Interface (PPI) The processors provide a parallel peripheral interface (PPI) that supports data widths up to 24 bits. The PPI supports direct connection to TFT LCD panels, parallel analog-to-digital and digital-to-analog converters, video encoders and decoders, image sensor modules and other general-purpose peripherals. The following features are supported in the PPI module: • Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, 16 bits, 18 bits and 24 bits per clock • Various framed, non-framed, and general-purpose operating modes. Frame syncs can be generated internally or can be supplied by an external device. • ITU-656 status word error detection and correction for ITU-656 receive modes and ITU-656 preamble and status word decode • Optional packing and unpacking of data to/from 32 bits from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is enabled, endianness can be configured to change the order of packing/unpacking of bytes/words. • RGB888 can be converted to RGB666 or RGB565 for transmit modes. • Various de-interleaving/interleaving modes for receiving/transmitting 4:2:2 YCrCb data • Configurable LCD data enable (DEN) output available on Frame Sync 3 UART Ports The processors provide three full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, and none, even, or odd parity. Optionally, an Rev. PrF | Preliminary Technical Data additional address bit can be transferred to interrupt only addressed nodes in multi-drop bus (MDB) systems. A frame is terminated by a configurable number of stop bits. The UART ports support automatic hardware flow control through the clear-to-send (CTS) input and request-to-send (RTS) output with programmable assertion FIFO levels. To help support the Local Interconnect Network (LIN) protocols, a special command causes the transmitter to queue a break command of programmable bit length into the transmit buffer. Similarly, the number of stop bits can be extended by a programmable inter-frame space. Serial Peripheral Interface (SPI) Ports The processors have three industry-standard SPI-compatible ports that allow it to communicate with multiple SPI-compatible devices. The baseline SPI peripheral is a synchronous, four-wire interface consisting of two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other SPI-compatible devices. An additional two (optional) data pins are provided to support quad SPI operation. Enhanced modes of operation such as flow control, fast mode and dualI/O mode (DIOM) are also supported. In addition, a direct memory access (DMA) mode allows for transferring several words with minimal CPU interaction. With a range of configurable options, the SPI ports provide a glueless hardware interface with other SPI-compatible devices in master mode, slave mode, and multimaster environments. The SPI peripheral includes programmable baud rates, clock phase, and clock polarity. The peripheral can operate in a multimaster environment by interfacing with several other devices, acting as either a master device or a slave device. In a multimaster environment, the SPI peripheral uses open-drain outputs to avoid data bus contention. The flow control features enable slow slave devices to interface with fast master devices by providing an SPI Ready pin which flexibly controls the transfers. The SPI port’s baud rate and clock phase/polarities are programmable, and it has integrated DMA channels for both transmit and receive data streams. Link Ports (LP) Two 8-bit wide link ports can connect to the link ports of other DSPs or peripherals. Link ports are bidirectional ports having eight data lines, an acknowledge line, and a clock line. ADC Control Module (ACM) Interface The ADC control module (ACM) provides an interface that synchronizes the controls between the processors and an analog-to-digital converter (ADC). The analog-to-digital conversions are initiated by the processors, based on external or internal events. The ACM allows for flexible scheduling of sampling instants and provides precise sampling signals to the ADC. Page 16 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 The ACM synchronizes the ADC conversion process, generating the ADC controls, the ADC conversion start signal, and other signals. The actual data acquisition from the ADC is done by an internal DAI routing of ACM with SPORT0. • Frame status delivery to memory through DMA, including frame completion semaphores for efficient buffer queue management in software • TX DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations The processors interface directly to many ADCs without any glue logic required. • Convenient frame alignment modes 3-Phase Pulse Width Modulator (PWM) Units The pulse width modulator (PWM) module is a flexible and programmable waveform generator. With minimal CPU intervention the PWM peripheral is capable of generating complex waveforms for motor control, pulse coded modulation (PCM), digital-to-analog Conversion (DAC), power switching and power conversion. The PWM module has four PWM pairs capable of 3-phase PWM generation for source inverters for AC induction and DC brushless motors. The three 3-phase PWM generation units each feature: • 16-bit center-based PWM generation unit • 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value • Advanced power management • Magic packet detection and wakeup frame filtering • Support for 802.3Q tagged VLAN frames • Programmable MDC clock rate and preamble suppression Audio Video Bridging (AVB) Support (10/100/1000 EMAC Only) The 10/100/1000 EMAC supports the following audio video (AVB) features: • Programmable PWM pulse width • Single update mode with option for asymmetric duty • Separate channels or queues for AV data transfer in 100 Mbps and 1000 Mbps modes • Programmable dead time and switching frequency • IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for the additional transmit channels • Programmable dead time per channel • Twos-complement implementation which permits smooth transition to full ON and full OFF states • Configuring up to two additional channels (Channel 1 and Channel 2) on the transmit and receive paths for AV traffic. Channel 0 is available by default and carries the legacy besteffort Ethernet traffic on the transmit side. • Dedicated asynchronous PWM shutdown signal Ethernet MAC (EMAC) • Separate DMA, Tx FIFO, and Rx FIFO for AVB latency class The processor features two EMACs: 10/100 Std Ethernet and 10/100/1000 Std/AVB Ethernet with precision time protocol IEEE-1588. The processors can directly connect to a network by way of an embedded fast Ethernet media access controller (MAC) that supports 10-BaseT (10M bits/sec), 100-BaseT (100M bits/sec) and 1000-BaseT (1G bits/sec) operations. The 10/100 Ethernet MAC peripheral on the processors is fully compliant to the IEEE 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. Some standard features are: • Programmable control to route received VLAN tagged non-AV packets to channels or queues Precision Time Protocol IEEE 1588 Support The IEEE 1588 standard is a precision clock synchronization protocol for networked measurement and control systems. The processors include hardware support for IEEE 1588 with an integrated precision time protocol synchronization engine (PTP_TSYNC). This engine provides hardware assisted time stamping to improve the accuracy of clock synchronization between PTP nodes. The main features of the engine are: • Support and RMII/RGMII protocols for external PHYs • Support for both IEEE 1588-2002 and IEEE 1588-2008 protocol standards • Full duplex and half-duplex modes • Hardware assisted time stamping capable of up to 12.5 ns resolution • Media access management (in half-duplex operation) • Flow control • Station management: generation of MDC/MDIO frames for read-write access to PHY registers Some advanced features are: • Independent 32-bit descriptor-driven receive and transmit DMA channels | • Automatic detection of IPv4 and IPv6 packets, as well as PTP messages • Multiple input clock sources (SCLK0, RGMII, RMII, RMII clock, external clock) • Automatic checksum computation of IP header and IP payload fields of RX frames Rev. PrF • Lock adjustment Page 17 of 168 | • Programmable pulse per second (PPS) output • Auxiliary snapshot to time stamp external events February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Controller Area Network (CAN) There are two CAN modules. A CAN controller implements the CAN 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The CAN protocol is well suited for control applications due to its capability to communicate reliably over a network. This is because the protocol incorporates CRC checking, message error tracking, and fault node confinement. The CAN controller offers the following features: • 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit) • Dedicated acceptance masks for each mailbox • Additional data filtering on first two bytes • Support for both the standard (11-bit) and extended (29bit) identifier (ID) message formats • Support for remote frames • Active or passive network support • Interrupts, including: TX complete, RX complete, error and global An additional crystal is not required to supply the CAN clock, as the CAN clock is derived from a system clock through a programmable divider. Timers value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts down to zero from the programmed value. This protects the system from remaining in an unknown state where software that would normally reset the timer has stopped running due to an external noise condition or software error. General-Purpose Counters (CNT) A 32-bit counter is provided that can operate in general-purpose up/down count modes and can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. Count direction is either controlled by a levelsensitive input pin or by two edge detectors. A third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumbwheel devices. All three pins have a programmable debouncing circuit. Internal signals forwarded to a GP timer enable this timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmed count values are exceeded. PCI Express (PCIe) A PCI express interface is available on some product variants. This single, bidirectional lane can be configured to be either a root complex (RC) or end point (EP) system. The interface has the following features: The processors include several timers which are described in the following sections. • Compliance with the PCI Express Base Specification 3.0 • Support for transfers at either 2.5 Gbps (Gen 1.1) or 5.0 Gbps (Gen 2) in each direction General-Purpose Timers (TIMER) There is one GP timer unit, and it provides eight general-purpose programmable timers. Each timer has an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input on the TIMER_TMRx pins, an external TIMER_CLK input pin, or to the internal SCLK0. These timer units can be used in conjunction with the UARTs and the CAN controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The GP timers can generate interrupts to the processor core, providing periodic events for synchronization to either the system clock or to external signals. Timer events can also trigger other peripherals via the TRU (for instance, to signal a fault). Each timer may also be started and/or stopped by any TRU master without core intervention. Preliminary Technical Data • Support for 8b/10b encode and decode • Lane reversal and lane polarity inversion • Flow control of data in both the transmit and receive directions • Support for removal of corrupted packets for error detection and recovery • Maximum transaction payload of 256 bytes Housekeeping Analog-to-Digital Converter (HADC) The HADC provides a general-purpose, multi-channel successive approximation A-to-D converter. It supports the following set of features: • 12-bit ADC core (10-bit accuracy) with built in sample and hold • 8 single-ended input channels that can be extended to 15 channels by adding an external channel multiplexer • Throughput rates up to 1 MSPS Watchdog Timer (WDT) Two on-chip software watchdog timers can be used by the ARM and/or SHARC+ cores. A software watchdog can improve system availability by forcing the processors to a known state, via a general-purpose interrupt, or a fault, if the timer expires before being reset by software. The programmer initializes the count Rev. PrF | Page 18 of 168 | • Single external reference with analog inputs between 0 and 3.3 V • Selectable ADC clock frequency including the ability to program a pre-scaler February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 • Adaptable conversion type: allows single or continuous conversion with option of autoscan General-Purpose I/O (GPIO) • Auto sequencing capability with up to 15 autoconversions in a single session. Each conversion can be programmed to select any 1–15 input channels. Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: • GPIO direction control register: Specifies the direction of each individual GPIO pin as input or output. • 16 data registers (individually addressable) to store conversion values • GPIO control and status registers: A “write one to modify” mechanism allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. USB 2.0 On-the-Go Dual-Role Device Controller There are two USB modules + PHY. USB0 supports HS/FS/LS USB2.0 OTG and USB1 supports HS/FS USB2.0 only and can be programmed to be a host or device. Each USB 2.0 OTG dual-role device controller provides a lowcost connectivity solution for the growing adoption of this bus standard in industrial applications, as well as consumer mobile devices such as cell phones, digital still cameras, and MP3 players. The USB 2.0 controller allows these devices to transfer data using a point-to-point USB connection without the need for a PC host. The module can operate in a traditional USB peripheral-only mode as well as the host mode presented in the on-the-go (OTG) supplement to the USB 2.0 specification. The USB clock is provided through a dedicated external crystal or crystal oscillator. The USB on-the-go dual-role device controller includes a phase locked loop with programmable multipliers to generate the necessary internal clocking frequency for USB. Media Local Bus (MLB) The automotive model has a MLB slave interface which allows the processors to function as a media local bus device. It includes support for both 3-pin and 6-pin media local bus protocols. MLB 3-pin supports speeds up to 1024 × FS and 6-pin up to 4096 × FS (48 kHz). MLB also supports up to 63 logical channels, with up to 124 bytes of data per media local bus frame. The MLB interface supports MOST25/50/150 data rates and operates in slave mode only. 2-Wire Controller Interface (TWI) The processors include three 2-wire interface (TWI) modules for providing a simple exchange method of control data between multiple devices. The TWI module is compatible with the widely used I2C bus standard. The TWI module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock (TWI_SCL) and data (TWI_SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels. • GPIO interrupt mask registers: Allow each individual GPIO pin to function as an interrupt to the processors. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. • GPIO interrupt sensitivity registers: Specify whether individual pins are level- or edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the rising and falling edges of the signal are significant. Pin Interrupts Every port pin on the processors can request interrupts in either an edge-sensitive or a level-sensitive manner with programmable polarity. Interrupt functionality is decoupled from GPIO operation. Six system-level interrupt channels (PINT0–5) are reserved for this purpose. Each of these interrupt channels can manage up to 32 interrupt pins. The assignment from pin to interrupt is not performed on a pin-by-pin basis. Rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. Every pin interrupt channel features a special set of 32-bit memory-mapped registers that enable half-port assignment and interrupt management. This includes masking, identification, and clearing of requests. These registers also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. Most control registers feature multiple MMR address entries to write-one-to-set or write-one-to-clear them individually. Mobile Storage Interface (MSI) The mobile storage interface (MSI) controller acts as the host interface for multimedia cards (MMC), secure digital memory cards (SD), and secure digital input/output cards (SDIO). The MSI controller has the following features: Additionally, the TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. • Support for a single MMC, SD memory, SDIO card • Support for 1-bit and 4-bit SD modes • Support for 1-bit, 4-bit, and 8-bit MMC modes • Support for eMMC 4.3 embedded NAND flash devices • An 11-signal external interface with clock, command, optional interrupt, and up to 8 data lines • Integrated DMA controller • Card interface clock generation from CLKO9 from CDU • SDIO interrupt and read wait features Rev. PrF | Page 19 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data SYSTEM ACCELERATION Sinus Cardinalis (SINC) Filter The following sections describe the system acceleration blocks of the ADSP-SC58x/ADSP-2158x processors. The SINC module processes four bit streams using a pair of configurable SINC filters for each bitstream. The purpose of the primary SINC filter of each pair is to produce the filtered and decimated output for the pair. The output may be decimated to any integer rate between 8 and 256 times lower than the input rate. Greater decimation allows greater removal of noise and therefore greater ENOB. FFT Accelerator A high performance FFT/IFFT accelerator is available to greatly improve the overall floating-point computation power of the ADSP-SC58x/ADSP-2158x processors. In addition, the following features are available to improve the overall performance of the accelerator: • Support for the IEEE-754/854 single-precision floatingpoint data format • Automatic twiddle factor generation to reduce system bandwidth • Support for a vector complex multiply for windowing and frequency domain filtering • Ability to pipeline the data flow. This allows the accelerator to bring in a new data set while the current set is being processed and the previous set is being sent out to memory. This can provide a significant system-level performance improvement. • Ability to output the result as the magnitude squared of the complex samples • Dedicated, high-speed DMA controller with 64-bit buses that can read and write data from any memory space The FFT accelerator can be run concurrently with the other accelerators on these processors. Optional additional filtering outside the SINC module may be used to further increase ENOB. The primary SINC filter output is accessible through transfer to processor memory, or to another peripheral, via DMA. Each of the four channels is also provided with a low-latency secondary filter with programmable positive and negative overrange detection comparators. These limit detection events can be used to interrupt the core, generate a trigger, or signal a system fault. Digital Transmission Content Protection (DTCP) The ADSP-SC58x/ADSP-2158x processors support the AES128 data cipher engine. The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content scrambling system) is protected by this copy protection system. Contact Analog Devices for more information on DTCP. FIR Accelerator SYSTEM DESIGN The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. It can access all memory spaces and can run simultaneously with other accelerators. IIR Accelerator The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coefficients, a data memory for storing the intermediate data, and one MAC unit. A controller manages the accelerator. The IIR accelerator runs at the peripheral clock frequency. It can access all memory spaces and can run simultaneously with other accelerators. Harmonic Analysis Engine (HAE) The harmonic analysis engine (HAE) block receives 8 kHz input samples from two source signals whose frequencies are between 45 Hz and 65 Hz. The HAE will then process the input samples and produce output results. The output results consist of power quality measurements of the fundamental and up to 12 additional harmonics. Rev. PrF | The following sections provide an introduction to system design options and power supply issues. Clock Management The processors provide three operating modes, each with a different performance/power profile. Control of clocking to each of the processor peripherals also reduces power consumption. The processors do not support any low power operation modes. Control of clocking to each of the processor peripherals can reduce the power consumption. Reset Control Unit (RCU) Reset is the initial state of the whole processor or the core and is the result of a hardware- or software-triggered event. In this state, all control registers are set to their default values and functional units are idle. Exiting a full system reset starts with the core being ready to boot. The reset control unit (RCU) controls how all the functional units enter and exit reset. Differences in functional requirements and clocking constraints define how reset signals are generated. Programs must guarantee that none of the reset functions puts the system into an undefined state or causes resources to stall. This is particularly important when the core is reset (programs must ensure that there is no pending system activity involving the core when it is being reset). Page 20 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 From a system perspective reset is defined by both the reset target and the reset source as described below. Target defined: • System reset: All functional units except the RCU are set to their default states. • Hardware reset: All functional units are set to their default states without exception. History is lost. • Core-only reset: Affects the core only. The system software should guarantee that the core, while in reset state, is not accessed by any bus master. Source defined: • System reset: May be triggered by software (writing to the RCU_CTL register) or by another functional unit such as the dynamic power management (DPM) unit or any of the system event controllers (SEC), trigger routing unit (TRU), or emulator inputs. • Hardware reset: The SYS_HWRST input signal is asserted active (pulled down). • Core-only reset: Triggered by software. • Trigger request (peripheral). Real-Time Clock (RTC) The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the processor. Connect RTC pins RTC0_CLKIN and RTC0_XTAL with external components as shown in Figure 6. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. RTC0_CLKIN RTC0_XTAL R1 X1 C1 the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch interrupt is enabled and the counter underflows, an interrupt is generated. Clock Generation Unit (CGU) The ADSP-SC58x/ADSP-2158x processors support two independent PLLs. Each PLL is part of a clock generation unit (CGU). (Refer to Figure 8 on Page 82.) Each CGU can either be driven externally by the same clock source or each can be driven by separate sources. This provides flexibility in determining the internal clocking frequencies for each clock domain. Frequencies generated by each CGU are derived from a common multiplier with different divider values available for each output. The clock generation unit (CGU) generates all on-chip clocks and synchronization signals. Multiplication factors are programmed to define the PLLCLK frequency. Programmable values divide the PLLCLK frequency to generate the core clock (CCLK), the system clocks, the DDR1/2/3 clock (DCLK), and the output clock (OCLK). For more information on clocking, refer to the Clock Generation Unit (CGU) chapter of the hardware reference manual. Writing to the CGU control registers does not affect the behavior of the PLL immediately. Registers are first programmed with a new value, and the PLL logic executes the changes so that it transitions smoothly from the current conditions to the new conditions. System Crystal Oscillator and USB Crystal Oscillator The processor can be clocked by an external crystal, (Figure 7) a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the SYS_CLKIN pin of the processor. When an external clock is used, the SYS_XTAL pin must be left unconnected. Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. C2 For fundamental frequency operation, use the circuit shown in Figure 7. A parallel-resonant, fundamental frequency, microprocessor grade crystal is connected across the SYS_CLKIN and SYS_XTAL pins. The on-chip resistance between SYS_CLKIN and the SYS_XTAL pin is in the 500 kΩ range. Further parallel resistors are typically not recommended. NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. Figure 6. External Components for RTC The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and a 32,768-day counter. When the alarm interrupt is enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in Rev. PrF | The two capacitors and the series resistor shown in Figure 7 fine-tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 7 are typical values only. The capacitor values are dependent upon the load capacitance recommendations of the crystal manufacturer and the PCB physical layout. The resistor value depends on the drive Page 21 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Booting SHARC PROCESSOR The processors have several mechanisms for automatically loading internal and external memory after a reset. The boot mode is defined by the SYS_BMODE input pins dedicated for this purpose. There are two categories of boot modes. In master boot mode, the processor actively loads data from serial memories. In slave boot modes, the processors receive data from external host devices. TO PLL CIRCUITRY ȍ SYS_CLKIN SYS_XTAL Nȍ * FOR OVERTONE OPERATION ONLY: 18 pF* The boot modes are shown in Table 9. These modes are implemented by the SYS_BMODE bits of the reset configuration register and are sampled during power-on resets and softwareinitiated resets. In the ADSP-SC58x processors, the ARM Cortex-A5 (core 0) controls the boot process, including loading all internal and external memory. Likewise, in the ADSP-2158x processors, the SHARC+ (core 1) controls the boot function. The option for secure boot is available on all products. 18 pF* NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE OF 18pF SHOULD BE TREATED AS A MAXIMUM. Table 9. Boot Modes Figure 7. External Crystal Connection level specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over the required temperature range. A third-overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in Figure 7. A design procedure for third-overtone operation is discussed in detail in application note “Using Third Overtone Crystals with the ADSP-218x DSP” (EE-168). The same recommendations may be used for the USB crystal oscillator. Clock Distribution Unit (CDU) The two CGUs each provide outputs which feed a clock distribution unit (CDU). The clock outputs CLKO0-9 are connected to various targets. For more information, refer to the Clock Distribution Unit (CDU) chapter of the hardware reference manual. SYS_BMODE Setting 000 001 010 011 100 101 110 111 Boot Mode No boot SPI2 Master SPI2 Slave Reserved Reserved Reserved Link0 Slave UART0 Slave Thermal Monitoring Unit (TMU) The thermal monitoring unit provides on-chip temp measurement which is important in applications that require substantial power consumption. The TMU is integrated into the processor die and digital infrastructure using an MMR-based system access to measure the die temperature variations in real-time. TMU features include: Power-Up • On-chip temperature sensing XTAL oscillations (SYS_CLKIN) start when power is applied to the VDD_EXT pins. The rising edge of SYS_HWRST starts onchip PLL locking (PLL lock counter). The deassertion should apply only if all voltage supplies and SYS_CLKIN oscillations are valid (refer to Power-Up Reset Timing on Page 88). • Programmable over-temperature and under-temperature limits • Programmable conversion rate Clock Out/External Clock • Averaging feature available The SYS_CLKOUT output pin has programmable options to output divided-down versions of the on-chip clocks. By default, the SYS_CLKOUT pin drives a buffered version of the SYS_ CLKIN0 input. Refer to the Clock Distribution Unit (CDU) chapter in the hardware reference manual to change the default mapping of clocks. • Programmable clock source selection to run the sensor off an independent local clock Power Supplies The processors have separate power supply connections for: • Internal (VDD_INT) • External (VDD_EXT) • USB (VDD_USB) • HADC (VDD_HADC) Rev. PrF | Page 22 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 • RTC (VDD_RTC) System Watchpoint Unit (SWU) • DMC (VDD_DMC) The system watchpoint unit (SWU) is a single module which connects to a single system bus and provides for transaction monitoring. One SWU is attached to the bus going to each system slave. The SWU provides ports for all system bus address channel signals. Each SWU contains four match groups of registers with associated hardware. These four SWU match groups operate independently, but share common event (interrupt, trigger and others) outputs. • PCIe (VDD_PCIE, VDD_PCIE_TX and VDD_PCIE_RX) All the power supplies should meet the specifications provided in Operating Conditions on Page 80. All the external supply pins must be connected to the same power supply. Power Management As shown in Table 10, the processor supports four different power domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. There are no sequencing requirements for the various power domains, but all domains must be powered according to the appropriate Specifications table for processor operating conditions; even if the feature/peripheral is not used. Table 10. Power Domains Power Domain All internal logic DDR3/DDR2/LPDDR USB HADC RTC PCIe_TX PCIe_RX PCIe All other I/O (includes SYS, JTAG, and Ports pins) Debug Access Port (DAP) DAP (debug access port) provides IEEE-1149.1 JTAG interface support through its JTAG debug. The DAP provides an optional instrumentation trace for both the core and system. It provides a trace stream that conforms to MIPI System Trace Protocol version 2(STPv2). DEVELOPMENT TOOLS Analog Devices supports its processors with a complete line of software and hardware development tools, including an integrated development environment (CrossCore® Embedded Studio), evaluation products, emulators, and a wide variety of software add-ins. VDD Range VDD_INT VDD_DMC VDD_USB VDD_HADC VDD_RTC VDD_PCIE_TX VDD_PCIE_RX VDD_PCIE VDD_EXT Integrated Development Environments (IDEs) For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers the CrossCore Embedded Studio IDE. The power dissipated by a processor is largely a function of its clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation. CrossCore Embedded Studio is based on the Eclipse framework. Supporting most Analog Devices processor families, it is the IDE of choice for processors, including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information visit www.analog.com/cces. Target Board JTAG Emulator Connector EZ-KIT Lite Evaluation Board Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing. For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. Also available are various EZ-Extenders®, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information visit www.analog.com and search on “ezkit” or “ezextender”. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate Emulator Hardware User’s Guide. EZ-KIT Lite Evaluation Kits SYSTEM DEBUG The processors include various features that allow for easy system debug. These are described in the following sections. Rev. PrF | For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user’s PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the Page 23 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 EZ-KIT Lite system. It also supports in-circuit programming of the on-board Flash device to store user-specific boot code, enabling standalone operation. With the full version of CrossCore Embedded Studio installed (sold separately), engineers can develop software for supported EZ-KITs or any custom system utilizing supported Analog Devices processors. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio IDE once the add-in is installed. Preliminary Technical Data to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports connection of the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see “Analog Devices JTAG Emulation Technical Reference” (EE-68). This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSPSC58x/ADSP-2158x architecture and functionality. For detailed information on the core architecture and instruction set, refer to the programming reference manual. RELATED SIGNAL CHAINS Board Support Packages for Evaluation Hardware Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called Board Support Packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download area of the product web page. Middleware Packages Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information see the following web pages: A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The application signal chains page in the Circuits from the Lab® site (http:\\www.analog.com\circuits) provides: • www.analog.com/ucos2 • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • www.analog.com/ucos3 • Drill down links for components in each chain to selection guides and application information • www.analog.com/ucfs • www.analog.com/ucusbd • Reference designs applying best practice design techniques • www.analog.com/ucusbh SECURITY FEATURES DISCLAIMER • www.analog.com/lwip Algorithmic Modules To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are available for use with CrossCore Embedded Studio. For more information visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set Rev. PrF | To our knowledge, the Security Features, when used in accordance with the data sheet and hardware reference manual specifications, provide a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE SECURITY FEATURES CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY. Page 24 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ADSP-SC58x/ADSP-2158x DETAILED SIGNAL DESCRIPTIONS Table 11 provides a detailed description of each pin. Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions Signal Name ACM_A[n] ACM_CLK ACM_FS ACM_T[n] C1_FLG[n] C2_FLG[n] CAN_RX CAN_TX CNT_DG Direction Output Output Output Input InOut InOut Input Output Input CNT_UD Input CNT_ZM Input DAI_PIN[nn] InOut DMC_A[nn] DMC_BA[n] Output Output DMC_CAS Output DMC_CK DMC_CKE DMC_CK DMC_CS[n] DMC_DQ[nn] DMC_LDM Output Output Output Output InOut Output DMC_LDQS InOut DMC_LDQS DMC_ODT InOut Output DMC_RAS Output DMC_RESET DMC_RZQ DMC_UDM Output InOut Output Description ADC Control Signals. Function varies by mode Clock. SCLK derived clock for connecting to an ADC. Frame Sync. Typically used as an ADC chip select. External Trigger n. Input for external trigger events SHARC+ Core 1 Flag Pin. SHARC+ Core 2 Flag Pin. Receive. Typically an external CAN transceiver’s RX output. Transmit. Typically an external CAN transceiver’s TX input. Count Down and Gate. Depending on the mode of operation this input acts either as a count down signal or a gate signal. Count down: This input causes the GP counter to decrement. Gate: Stops the GP counter from incrementing or decrementing. Count Up and Direction. Depending on the mode of operation this input acts either as a count up signal or a direction signal. Count up: This input causes the GP counter to increment. Direction: Selects whether the GP counter is incrementing or decrementing. Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the pressing of a pushbutton. Pin n. The digital applications interfaces (DAI0 and DAI1) provide the ability to connect various peripherals to any of the DAI pins (DAI0_PINxx and DAI1_PINxx). Programs make these connections using the signal routing unit (SRU). Both DAI units are symmetric. The shared DAIx__PIN03 and DAIx_PIN04 pins allow routing between both DAI units. Address n. Address bus Bank Address n. Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR, EMR2, and/or EMR3) are loaded during the LOAD MODE REGISTER command. Column Address Strobe. Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the CAS input of dynamic memory. Clock. Outputs DCLK to external dynamic memory. Clock enable. Active high clock enables. Connects to the dynamic memory's CKE input. Clock (complement). Complement of DMC_CK. Chip Select n. Commands are recognized by the memory only when this signal is asserted. Data n. Bidirectional Data bus Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled on both edges of the data strobe by the dynamic memory. Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with Read Data. May be single-ended or differential depending on register settings. Data Strobe for Lower Byte (complement). Complement of LDQS. Not used in single-ended mode. On-die termination. Enables dynamic memory termination resistances when driven high (assuming the memory is properly configured). Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the RAS input of dynamic memory. Reset (DDR3 only). External calibration resistor connection. Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled on both edges of the data strobe by the dynamic memory. Rev. PrF | Page 25 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued) Signal Name DMC_UDQS Direction InOut DMC_UDQS DMC_VREF DMC_WE InOut Input Output ETH_CRS Input ETH_MDC ETH_MDIO ETH_PTPAUXIN[n] Output InOut Input ETH_PTPCLKIN[n] ETH_PTPPPS[n] Input Output ETH_REFCLK ETH_RXCLK_REFCLK ETH_RXCTL_CRS ETH_RXD[n] ETH_TXCLK ETH_TXCTL_TXEN ETH_TXD[n] ETH_TXEN HADC_EOC_DOUT Input InOut InOut Input Input InOut Output InOut Output HADC_MUX[n] Output HADC_VIN[n] HADC_VREFN Input Input HADC_VREFP Input JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST LP_ACK Input Input Output Input Input InOut LP_CLK InOut LP_D[n] MLB_CLKN MLB_CLKP MLB_DATN InOut Input Input InOut Description Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with Write Data. Input with Read Data. Not used in single-ended mode. Data Strobe for Upper Byte (complement). Complement of UDQS. Not used in single-ended mode. Voltage Reference. Externally driven to VDD_DMC/2. Write Enable. Defines the operation for external dynamic memory to perform in conjunction with other DMC command signals. Connect to the WEb input of dynamic memory. Carrier Sense/RMII Receive Data Valid. Multiplexed on alternate clock cycles. CRS: Asserted by the PHY when either the transmit or receive medium is not idle. Deasserted when both are idle. RXDV: Asserted by the PHY when the data on RXDn is valid. Management Channel Clock. Clocks the MDC input of the PHY. Management Channel Serial Data. Bidirectional data bus for PHY control. PTP Auxiliary Trigger Input. Assert this signal to take an auxiliary snapshot of the time and store it in the auxiliary time stamp FIFO. PTP Clock Input. Optional external PTP clock input PTP Pulse-Per-Second Output. When the Advanced Time Stamp feature is enable this signal is asserted based on the PPS mode selected. Otherwise, PTPPPS is asserted every time the seconds counter is incremented. Reference Clock. Externally supplied Ethernet clock RXCLK (GigE) or REFCLK (10/100). RXCTL (GigE) or CRS (10/100). Receive Data n. Receive data bus Reference Clock. Externally supplied Ethernet clock TXCTL (GigE) or TXEN (10/100). Transmit Data n. Transmit data bus Transmit Enable. When asserted indicates that the data on TXDn is valid. End of Conversion / Serial Data Out. Transitions high for one cycle of the HADC internal clock at the end of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate bit in HADC_CTL. Controls to external multiplexer. Allows additional input channels when connected to an external multiplexer. Analog Input at channel n. Analog voltage inputs for digital conversion. Ground Reference for ADC. Connect to an external voltage reference that meets data sheet specifications. External Reference for ADC. Connect to an external voltage reference that meets data sheet specifications. JTAG Clock. JTAG test access port clock. JTAG Serial Data In. JTAG test access port data input. JTAG Serial Data Out. JTAG test access port data output. JTAG Mode Select. JTAG test access port mode select. JTAG Reset. JTAG test access port reset. Acknowledge. Provides handshaking. When the link port is configured as a receiver, ACK is an output. When the link port is configured as a transmitter, ACK is an input. Clock. When the link port is configured as a receiver, CLK is an input. When the link port is configured as a transmitter, CLK is an output. Data n. Data bus. Input when receiving, output when transmitting. Differential Clock (–) Differential Clock (+) Differential Data (–) Rev. PrF | Page 26 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued) Signal Name MLB_DATP MLB_SIGN MLB_SIGP MLB_CLK MLB_DAT MLB_SIG MLB_CLKOUT MSI_CD MSI_CLK MSI_CMD MSI_D[n] MSI_INT Direction InOut InOut InOut Input InOut InOut Output Input Output InOut InOut Input PCIE_CLKM PCIE_CLKP PCIE_REF PCIE_RXM PCIE_RXP PCIE_TXM PCIE_TXP PPI_CLK PPI_D[nn] PPI_FS1 PPI_FS2 PPI_FS3 PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL PWM_DH PWM_DL PWM_SYNC InOut InOut InOut InOut InOut InOut InOut InOut InOut InOut InOut InOut Output Output Output Output Output Output Output Output Input PWM_TRIP[n] P_[nn] Input InOut RTC_CLKIN RTC_XTAL Input Output SINC_CLK0 SINC_CLK1 SINC_D0 SINC_D1 SINC_D2 SINC_D3 InOut InOut InOut InOut InOut InOut Description Differential Data (+) Differential Signal (–) Differential Signal (+) Single-Ended Clock Single-Ended Data Single-Ended Signal Single-Ended Clock Out Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket. Clock. The clock signal applied to the connected device from the MSI. Command. Used to send commands to and receive responses from the connected device. Data n. Bidirectional data bus. eSDIO Interrupt Input. Used only for eSDIO. Connects to an eSDIO card's interrupt output. An interrupt may be sampled even when the MSI clock to the card is switched off. CLK – CLK + Reference RX – RX + TX – TX + Clock. Input in external clock mode, output in internal clock mode. Data n. Bidirectional data bus. Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details. Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details. Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the EPPI HRM chapter for more details. Channel A High Side. High side drive signal Channel A Low Side. Low side drive signal Channel B High Side. High side drive signal Channel B Low Side. Low side drive signal Channel C High Side. High side drive signal Channel C Low Side. Low side drive signal Channel D High Side. High side drive signal Channel D Low Side. Low side drive signal PWMTMR Grouped. This input is for an externally generated sync signal. If the sync signal is internally generated no connection is necessary. Shutdown Input n. When asserted the selected PWM channel outputs are shut down immediately. Position n. General purpose input/output. See the GP Ports chapter of the HRM for programming information. Crystal input / external oscillator connection. Connect to an external clock source or crystal. Crystal output. Drives an external crystal. Must be left unconnected if an external clock is driving RTC_CLKIN. Clock 0 Clock 1 Data 0 Data 1 Data 2 Data 3 Rev. PrF | Page 27 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued) Signal Name SMC_ABE[n] Direction Output SMC_AMS[n] SMC_AOE SMC_ARDY Output Output Input SMC_ARE SMC_AWE SMC_A[nn] SMC_D[nn] SPI_CLK SPI_D2 SPI_D3 SPI_MISO Output Output Output InOut InOut InOut InOut InOut SPI_MOSI InOut SPI_RDY SPI_SEL[n] SPI_SS InOut Output Input SPT_ACLK InOut SPT_AD0 InOut SPT_AD1 InOut SPT_AFS InOut SPT_ATDV Output SPT_BCLK InOut SPT_BD0 InOut SPT_BD1 InOut SPT_BFS InOut SPT_BTDV Output SYS_BMODE[n] SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT Input Input Input Output Description Byte Enable n. Indicate whether the lower or upper byte of a memory is being accessed. When an asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1b = 0 and SMC_ABE0b = 1. When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1b = 1 and SMC_ABE0b = 0. Memory Select n. Typically connects to the chip select of a memory device. Output Enable Asserts at the beginning of the setup period of a read access. Asynchronous Ready. Flow control signal used by memory devices to indicate to the SMC when further transactions may proceed. Read Enable. Asserts at the beginning of a read access. Write Enable. Asserts for the duration of a write access period. Address n. Address bus Data n. Bidirectional data bus Clock. Input in slave mode, output in master mode. Data 2. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled. Data 3. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled. Master In, Slave Out. Used to transfer serial data. Operates in the same direction as SPI_MOSI in Dual and Quad modes. Open-drain when ODM mode is enabled. Master Out, Slave In. Used to transfer serial data. Operates in the same direction as SPI_MISO in Dual and Quad modes. Open-drain when ODM mode is enabled. Ready. Optional flow signal. Output in slave mode, input in master mode. Slave Select Output n. Used in Master mode to enable the desired slave. Slave Select Input. Slave mode: Acts as the slave select input. Master mode: Optionally serves as an error detection input for the SPI when there are multiple masters. Channel A Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated. Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in multi-channel transmit mode. It is asserted during enabled slots. Channel B Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated. Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in multi-channel transmit mode. It is asserted during enabled slots. Boot Mode Control n. Selects the boot mode of the processor. Clock/Crystal Input Clock/Crystal Input Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter of the HRM for more details. Rev. PrF | Page 28 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued) Signal Name SYS_FAULT Direction InOut SYS_FAULT InOut SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 TM_ACI[n] TM_ACLK[n] TM_CLK TM_TMR[n] TRACE_CLK TRACE_D[nn] TWI_SCL TWI_SDA UART_CTS UART_RTS UART_RX Input Output Output Output Input Input Input InOut Output Output InOut InOut Input Output Input UART_TX Output USB_CLKIN Input USB_DM USB_DP USB_ID InOut InOut Input USB_VBC Output USB_VBUS USB_XTAL InOut Output Description Active-High Fault Output. Indicates indicates internal faults or senses external faults depending on the operating mode. Active-Low Fault Output. Indicates indicates internal faults or senses external faults depending on the operating mode. Processor Hardware Reset Control. Resets the device when asserted. Reset Output. Indicates that the device is in the reset state. Crystal Output Crystal Output Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes. Alternate Clock n. Provides an additional time base for use by an individual timer. Clock. Provides an additional global time base for use by all the GP timers. Timer n. The main input/output signal for each timer. Trace Clock. Clock output/ Trace Data n. Unidirectional data bus. Serial Clock. Clock output when master, clock input when slave Serial Data. Receives or transmits data Clear to Send. Flow control signal. Request to Send. Flow control signal. Receive. Receive input. Typically connects to a transceiver that meets the electrical requirements of the device being communicated with. Transmit. Transmit output. Typically connects to a transceiver that meets the electrical requirements of the device being communicated with. Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet specifications for frequency/tolerance information. Data –. Bidirectional differential data line Data +. Bidirectional differential data line OTG ID. Senses whether the controller is a host or device. This signal is pulled low when an A-type plug is sensed (signifying that the USB controller is the A device), but the input is high when a B-type plug is sensed (signifying that the USB controller is the B device). VBUS Control. Controls an external voltage source to supply VBUS when in host mode. May be configured as open-drain. Polarity is configurable as well. Bus Voltage. Connects to bus voltage in host and device modes. Crystal. Drives an external crystal. Must be left unconnected if an external clock is driving USB_CLKIN. Rev. PrF | Page 29 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data 349-BALL CSP_BGA SIGNAL DESCRIPTIONS The processor’s pin definitions are shown in Table 12. The columns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions Signal Name ACM0_A0 ACM0_A1 ACM0_A2 ACM0_A3 ACM0_A4 ACM0_T0 C1_FLG0 C1_FLG1 C1_FLG2 C1_FLG3 C2_FLG0 C2_FLG1 C2_FLG2 C2_FLG3 CAN0_RX CAN0_TX CAN1_RX CAN1_TX CNT0_DG CNT0_UD CNT0_ZM DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN19 DAI0_PIN20 DAI1_PIN01 DAI1_PIN02 DAI1_PIN03 Description ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 External Trigger n SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin CAN0 Receive CAN0 Transmit CAN1 Receive CAN1 Transmit CNT0 Count Down and Gate CNT0 Count Up and Direction CNT0 Count Zero Marker DAI0 Pin 1 DAI0 Pin 2 DAI0 Pin 3 DAI0 Pin 4 DAI0 Pin 5 DAI0 Pin 6 DAI0 Pin 7 DAI0 Pin 8 DAI0 Pin 9 DAI0 Pin 10 DAI0 Pin 11 DAI0 Pin 12 DAI0 Pin 19 DAI0 Pin 20 DAI1 Pin 1 DAI1 Pin 2 DAI1 Pin 3 Rev. PrF | Page 30 of 168 | Port C C C D D C E E E E E E E E C C B B B B B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed February 2016 Pin Name PC_13 PC_14 PC_15 PD_00 PD_01 PC_12 PE_01 PE_03 PE_05 PE_07 PE_02 PE_04 PE_06 PE_08 PC_07 PC_08 PB_10 PB_09 PB_14 PB_12 PB_11 DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN19 DAI0_PIN20 DAI1_PIN01 DAI1_PIN02 DAI1_PIN03 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name DAI1_PIN04 DAI1_PIN05 DAI1_PIN06 DAI1_PIN07 DAI1_PIN08 DAI1_PIN09 DAI1_PIN10 DAI1_PIN11 DAI1_PIN12 DAI1_PIN19 DAI1_PIN20 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_A14 DMC0_A15 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 Description DAI1 Pin 4 DAI1 Pin 5 DAI1 Pin 6 DAI1 Pin 7 DAI1 Pin 8 DAI1 Pin 9 DAI1 Pin 10 DAI1 Pin 11 DAI1 Pin 12 DAI1 Pin 19 DAI1 Pin 20 DMC0 Address 0 DMC0 Address 1 DMC0 Address 2 DMC0 Address 3 DMC0 Address 4 DMC0 Address 5 DMC0 Address 6 DMC0 Address 7 DMC0 Address 8 DMC0 Address 9 DMC0 Address 10 DMC0 Address 11 DMC0 Address 12 DMC0 Address 13 DMC0 Address 14 DMC0 Address 15 DMC0 Bank Address 0 DMC0 Bank Address 1 DMC0 Bank Address 2 DMC0 Column Address Strobe DMC0 Clock DMC0 Clock enable DMC0 Clock (complement) DMC0 Chip Select 0 DMC0 Data 0 DMC0 Data 1 DMC0 Data 2 DMC0 Data 3 DMC0 Data 4 DMC0 Data 5 DMC0 Data 6 DMC0 Data 7 DMC0 Data 8 DMC0 Data 9 DMC0 Data 10 DMC0 Data 11 DMC0 Data 12 Rev. PrF | Page 31 of 168 | Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed February 2016 Pin Name DAI1_PIN04 DAI1_PIN05 DAI1_PIN06 DAI1_PIN07 DAI1_PIN08 DAI1_PIN09 DAI1_PIN10 DAI1_PIN11 DAI1_PIN12 DAI1_PIN19 DAI1_PIN20 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_A14 DMC0_A15 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_RESET DMC0_RZQ DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE ETH0_CRS ETH0_MDC ETH0_MDIO ETH0_PTPAUXIN0 ETH0_PTPAUXIN1 ETH0_PTPAUXIN2 ETH0_PTPAUXIN3 ETH0_PTPCLKIN0 ETH0_PTPPPS0 ETH0_PTPPPS1 ETH0_PTPPPS2 ETH0_PTPPPS3 ETH0_RXCLK_REFCLK ETH0_RXCTL_CRS ETH0_RXD0 ETH0_RXD1 ETH0_RXD2 ETH0_RXD3 ETH0_TXCLK ETH0_TXCTL_TXEN ETH0_TXD0 ETH0_TXD1 ETH0_TXD2 ETH0_TXD3 ETH0_TXEN HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VIN4 HADC0_VIN5 HADC0_VIN6 HADC0_VIN7 Description DMC0 Data 13 DMC0 Data 14 DMC0 Data 15 DMC0 Data Mask for Lower Byte DMC0 Data Strobe for Lower Byte DMC0 Data Strobe for Lower Byte (complement) DMC0 On-die termination DMC0 Row Address Strobe DMC0 Reset (DDR3 only) DMC0 External calibration resistor connection DMC0 Data Mask for Upper Byte DMC0 Data Strobe for Upper Byte DMC0 Data Strobe for Upper Byte (complement) DMC0 Voltage Reference DMC0 Write Enable ETH0 Carrier Sense/RMII Receive Data Valid ETH0 Management Channel Clock ETH0 Management Channel Serial Data ETH0 PTP Auxiliary Trigger Input 0 ETH0 PTP Auxiliary Trigger Input 1 ETH0 PTP Auxiliary Trigger Input 2 ETH0 PTP Auxiliary Trigger Input 3 ETH0 PTP Clock Input 0 ETH0 PTP Pulse-Per-Second Output 0 ETH0 PTP Pulse-Per-Second Output 1 ETH0 PTP Pulse-Per-Second Output 2 ETH0 PTP Pulse-Per-Second Output 3 ETH0 RXCLK (GigE) or REFCLK (10/100) ETH0 RXCTL (GigE) or CRS (10/100) ETH0 Receive Data 0 ETH0 Receive Data 1 ETH0 Receive Data 2 ETH0 Receive Data 3 ETH0 Transmit Clock ETH0 TXCTL (GigE) or TXEN (10/100) ETH0 Transmit Data 0 ETH0 Transmit Data 1 ETH0 Transmit Data 2 ETH0 Transmit Data 3 ETH0 Transmit Enable HADC0 Analog Input at channel 0 HADC0 Analog Input at channel 1 HADC0 Analog Input at channel 2 HADC0 Analog Input at channel 3 HADC0 Analog Input at channel 4 HADC0 Analog Input at channel 5 HADC0 Analog Input at channel 6 HADC0 Analog Input at channel 7 Rev. PrF | Page 32 of 168 | February 2016 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed A A A B B B B B B B A A A A A A A A A A A A A A A Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Pin Name DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_RESET DMC0_RZQ DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE PA_07 PA_02 PA_03 PB_03 PB_04 PB_05 PB_06 PB_02 PB_01 PB_00 PA_15 PA_14 PA_06 PA_07 PA_04 PA_05 PA_08 PA_09 PA_11 PA_10 PA_00 PA_01 PA_12 PA_13 PA_10 HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VIN4 HADC0_VIN5 HADC0_VIN6 HADC0_VIN7 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST LP0_ACK LP0_CLK LP0_D0 LP0_D1 LP0_D2 LP0_D3 LP0_D4 LP0_D5 LP0_D6 LP0_D7 LP1_ACK LP1_CLK LP1_D0 LP1_D1 LP1_D2 LP1_D3 LP1_D4 LP1_D5 LP1_D6 LP1_D7 MLB0_CLKN MLB0_CLKP MLB0_DATN MLB0_DATP MLB0_SIGN MLB0_SIGP MLB0_CLK MLB0_DAT MLB0_SIG MLB0_CLKOUT PA_00-15 PB_00-15 PC_00-15 PD_00-15 PE_00-15 PPI0_CLK PPI0_D00 PPI0_D01 PPI0_D02 PPI0_D03 PPI0_D04 Description HADC0 Ground Reference for ADC HADC0 External Reference for ADC TAPC JTAG Clock TAPC JTAG Serial Data In TAPC JTAG Serial Data Out TAPC JTAG Mode Select TAPC JTAG Reset LP0 Acknowledge LP0 Clock LP0 Data 0 LP0 Data 1 LP0 Data 2 LP0 Data 3 LP0 Data 4 LP0 Data 5 LP0 Data 6 LP0 Data 7 LP1 Acknowledge LP1 Clock LP1 Data 0 LP1 Data 1 LP1 Data 2 LP1 Data 3 LP1 Data 4 LP1 Data 5 LP1 Data 6 LP1 Data 7 MLB0 Differential Clock (–) MLB0 Differential Clock (+) MLB0 Differential Data (–) MLB0 Differential Data (+) MLB0 Differential Signal (–) MLB0 Differential Signal (+) MLB0 Single-Ended Clock MLB0 Single-Ended Data MLB0 Single-Ended Signal MLB0 Single-Ended Clock Out PORTA Position 00 through Position 15 PORTB Position 00 through Position 15 PORTC Position 00 through Position 15 PORTD Position 00 through Position 15 PORTE Position 00 through Position 15 EPPI0 Clock EPPI0 Data 0 EPPI0 Data 1 EPPI0 Data 2 EPPI0 Data 3 EPPI0 Data 4 Rev. PrF | Page 33 of 168 | Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed D D D D D D D D D D B C B B B B B B B B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed B B B D A B C D E E E E E E E February 2016 Pin Name HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST PD_11 PD_10 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PB_15 PC_00 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 MLB0_CLKN MLB0_CLKP MLB0_DATN MLB0_DATP MLB0_SIGN MLB0_SIGP PB_04 PB_06 PB_05 PD_14 PA_00-15 PB_00-15 PC_00-15 PD_00-15 PE_00-15 PE_03 PE_12 PE_11 PE_10 PE_09 PE_08 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name PPI0_D05 PPI0_D06 PPI0_D07 PPI0_D08 PPI0_D09 PPI0_D10 PPI0_D11 PPI0_D12 PPI0_D13 PPI0_D14 PPI0_D15 PPI0_D16 PPI0_D17 PPI0_D18 PPI0_D19 PPI0_D20 PPI0_D21 PPI0_D22 PPI0_D23 PPI0_FS1 PPI0_FS2 PPI0_FS3 PWM0_AH PWM0_AL PWM0_BH PWM0_BL PWM0_CH PWM0_CL PWM0_DH PWM0_DL PWM0_SYNC PWM0_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL PWM1_CH PWM1_CL PWM1_DH PWM1_DL PWM1_SYNC PWM1_TRIP0 PWM2_CH PWM2_CL PWM2_DH PWM2_DL PWM2_SYNC PWM2_TRIP0 Description EPPI0 Data 5 EPPI0 Data 6 EPPI0 Data 7 EPPI0 Data 8 EPPI0 Data 9 EPPI0 Data 10 EPPI0 Data 11 EPPI0 Data 12 EPPI0 Data 13 EPPI0 Data 14 EPPI0 Data 15 EPPI0 Data 16 EPPI0 Data 17 EPPI0 Data 18 EPPI0 Data 19 EPPI0 Data 20 EPPI0 Data 21 EPPI0 Data 22 EPPI0 Data 23 EPPI0 Frame Sync 1 (HSYNC) EPPI0 Frame Sync 2 (VSYNC) EPPI0 Frame Sync 3 (FIELD) PWM0 Channel A High Side PWM0 Channel A Low Side PWM0 Channel B High Side PWM0 Channel B Low Side PWM0 Channel C High Side PWM0 Channel C Low Side PWM0 Channel D High Side PWM0 Channel D Low Side PWM0 PWMTMR Grouped PWM0 Shutdown Input 0 PWM1 Channel A High Side PWM1 Channel A Low Side PWM1 Channel B High Side PWM1 Channel B Low Side PWM1 Channel C High Side PWM1 Channel C Low Side PWM1 Channel D High Side PWM1 Channel D Low Side PWM1 PWMTMR Grouped PWM1 Shutdown Input 0 PWM2 Channel C High Side PWM2 Channel C Low Side PWM2 Channel D High Side PWM2 Channel D Low Side PWM2 PWMTMR Grouped PWM2 Shutdown Input 0 Rev. PrF | Port E E E E E D D B B B B B B D D E E E D E E C B B B C B B B B E B D D D D D D D D D D D E E E E D Page 34 of 168 | February 2016 Pin Name PE_07 PE_06 PE_05 PE_04 PE_00 PD_15 PD_14 PB_04 PB_05 PB_00 PB_01 PB_02 PB_03 PD_13 PD_12 PE_13 PE_14 PE_15 PD_00 PE_02 PE_01 PC_15 PB_07 PB_08 PB_06 PC_00 PB_13 PB_14 PB_11 PB_12 PE_09 PB_15 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_02 PD_15 PE_00 PE_04 PE_10 PE_05 PD_14 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name GND VDD_EXT VDD_INT SINC0_CLK0 SINC0_D0 SINC0_D1 SINC0_D2 SINC0_D3 SMC0_A01 SMC0_A02 SMC0_A03 SMC0_A04 SMC0_A05 SMC0_A06 SMC0_A07 SMC0_A08 SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 SMC0_A13 SMC0_A14 SMC0_A15 SMC0_A16 SMC0_A17 SMC0_A18 SMC0_A19 SMC0_A20 SMC0_A21 SMC0_A22 SMC0_A23 SMC0_A24 SMC0_A25 SMC0_ABE0 SMC0_ABE1 SMC0_AMS0 SMC0_AMS1 SMC0_AMS2 SMC0_AMS3 SMC0_AOE SMC0_ARDY SMC0_ARE SMC0_AWE SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 Description Ground External Voltage Domain Internal Voltage Domain SINC0 Clock 0 SINC0 Data 0 SINC0 Data 1 SINC0 Data 2 SINC0 Data 3 SMC0 Address 1 SMC0 Address 2 SMC0 Address 3 SMC0 Address 4 SMC0 Address 5 SMC0 Address 6 SMC0 Address 7 SMC0 Address 8 SMC0 Address 9 SMC0 Address 10 SMC0 Address 11 SMC0 Address 12 SMC0 Address 13 SMC0 Address 14 SMC0 Address 15 SMC0 Address 16 SMC0 Address 17 SMC0 Address 18 SMC0 Address 19 SMC0 Address 20 SMC0 Address 21 SMC0 Address 22 SMC0 Address 23 SMC0 Address 24 SMC0 Address 25 SMC0 Byte Enable 0 SMC0 Byte Enable 1 SMC0 Memory Select 0 SMC0 Memory Select 1 SMC0 Memory Select 2 SMC0 Memory Select 3 SMC0 Output Enable SMC0 Asynchronous Ready SMC0 Read Enable SMC0 Write Enable SMC0 Data 0 SMC0 Data 1 SMC0 Data 2 SMC0 Data 3 SMC0 Data 4 Rev. PrF | Port Not Muxed Not Muxed Not Muxed B A A B B B B B B D D B B A A A A A A A A A A A A A A A A C E E C E C C D B C B E E E E E Page 35 of 168 | February 2016 Pin Name GND VDD_EXT VDD_INT PB_01 PA_14 PA_15 PB_00 PB_04 PB_05 PB_06 PB_03 PB_02 PD_13 PD_12 PB_01 PB_00 PA_15 PA_14 PA_09 PA_08 PA_13 PA_12 PA_11 PA_07 PA_06 PA_05 PA_04 PA_01 PA_00 PA_10 PA_03 PA_02 PC_12 PE_14 PE_15 PC_15 PE_13 PC_07 PC_08 PD_01 PB_04 PC_00 PB_15 PE_12 PE_11 PE_10 PE_09 PE_00 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name SMC0_D05 SMC0_D06 SMC0_D07 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_RDY SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI0_SEL4 SPI0_SEL5 SPI0_SEL6 SPI0_SEL7 SPI0_SS SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_RDY SPI1_SEL1 SPI1_SEL2 SPI1_SEL3 SPI1_SEL4 SPI1_SEL5 SPI1_SS SPI2_CLK SPI2_D2 SPI2_D3 SPI2_MISO SPI2_MOSI SPI2_RDY SPI2_SEL1 SPI2_SEL2 SPI2_SEL3 SPI2_SEL4 SPI2_SEL5 SPI2_SS SYS_BMODE0 SYS_BMODE1 SYS_BMODE2 Description SMC0 Data 5 SMC0 Data 6 SMC0 Data 7 SMC0 Data 8 SMC0 Data 9 SMC0 Data 10 SMC0 Data 11 SMC0 Data 12 SMC0 Data 13 SMC0 Data 14 SMC0 Data 15 SPI0 Clock SPI0 Master In, Slave Out SPI0 Master Out, Slave In SPI0 Ready SPI0 Slave Select Output 1 SPI0 Slave Select Output 2 SPI0 Slave Select Output 3 SPI0 Slave Select Output 4 SPI0 Slave Select Output 5 SPI0 Slave Select Output 6 SPI0 Slave Select Output 7 SPI0 Slave Select Input SPI1 Clock SPI1 Master In, Slave Out SPI1 Master Out, Slave In SPI1 Ready SPI1 Slave Select Output 1 SPI1 Slave Select Output 2 SPI1 Slave Select Output 3 SPI1 Slave Select Output 4 SPI1 Slave Select Output 5 SPI1 Slave Select Input SPI2 Clock SPI2 Data 2 SPI2 Data 3 SPI2 Master In, Slave Out SPI2 Master Out, Slave In SPI2 Ready SPI2 Slave Select Output 1 SPI2 Slave Select Output 2 SPI2 Slave Select Output 3 SPI2 Slave Select Output 4 SPI2 Slave Select Output 5 SPI2 Slave Select Input Boot Mode Control n Boot Mode Control n Boot Mode Control n Rev. PrF Port D D D B B B B B B B B C C C C C D C C E E E D E E E E C E E E E E C C C C C E C E E E E C Not Muxed Not Muxed Not Muxed | Page 36 of 168 | February 2016 Pin Name PD_15 PD_14 PD_00 PB_14 PB_13 PB_12 PB_11 PB_10 PB_09 PB_08 PB_07 PC_09 PC_10 PC_11 PC_12 PC_07 PD_01 PC_12 PC_00 PE_01 PE_02 PE_03 PD_01 PE_13 PE_14 PE_15 PE_08 PC_13 PE_07 PE_11 PE_12 PE_08 PE_11 PC_01 PC_04 PC_05 PC_02 PC_03 PE_12 PC_06 PE_03 PE_04 PE_05 PE_06 PC_06 SYS_BMODE0 SYS_BMODE1 SYS_BMODE2 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT SYS_FAULT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 TM0_ACI0 TM0_ACI1 TM0_ACI2 TM0_ACI3 TM0_ACI4 TM0_ACLK1 TM0_ACLK2 TM0_ACLK3 TM0_ACLK4 TM0_CLK TM0_TMR0 TM0_TMR1 TM0_TMR2 TM0_TMR3 TM0_TMR4 TM0_TMR5 TRACE0_CLK TRACE0_D00 TRACE0_D01 TRACE0_D02 TRACE0_D03 TRACE0_D04 TRACE0_D05 TRACE0_D06 TRACE0_D07 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA UART0_CTS UART0_RTS UART0_RX UART0_TX UART1_CTS UART1_RTS UART1_RX UART1_TX Description Clock/Crystal Input Clock/Crystal Input Processor Clock Output Active-High Fault Output Active-Low Fault Output Processor Hardware Reset Control Reset Output Crystal Output Crystal Output TIMER0 Alternate Capture Input 0 TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Clock 1 TIMER0 Alternate Clock 2 TIMER0 Alternate Clock 3 TIMER0 Alternate Clock 4 TIMER0 Clock TIMER0 Timer 0 TIMER0 Timer 1 TIMER0 Timer 2 TIMER0 Timer 3 TIMER0 Timer 4 TIMER0 Timer 5 TRACE0 Trace Clock TRACE0 Trace Data 0 TRACE0 Trace Data 1 TRACE0 Trace Data 2 TRACE0 Trace Data 3 TRACE0 Trace Data 4 TRACE0 Trace Data 5 TRACE0 Trace Data 6 TRACE0 Trace Data 7 TWI0 Serial Clock TWI0 Serial Data TWI1 Serial Clock TWI1 Serial Data TWI2 Serial Clock TWI2 Serial Data UART0 Clear to Send UART0 Request to Send UART0 Receive UART0 Transmit UART1 Clear to Send UART1 Request to Send UART1 Receive UART1 Transmit Rev. PrF | Page 37 of 168 | Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed C B D C B D D B B C E B B B B B D D D D D D D D D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed D C C C E E B B February 2016 Pin Name SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT SYS_FAULT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 PC_14 PB_03 PD_13 PC_07 PB_10 PD_08 PD_09 PB_00 PB_01 PC_11 PE_09 PB_15 PB_10 PB_07 PB_08 PB_14 PD_10 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA PD_00 PC_15 PC_14 PC_13 PE_01 PE_02 PB_03 PB_02 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued) Signal Name UART2_CTS UART2_RTS UART2_RX UART2_TX USB0_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB0_XTAL VDD_DMC VDD_HADC VDD_USB Description UART2 Clear to Send UART2 Request to Send UART2 Receive UART2 Transmit USB0 Clock/Crystal Input USB0 Data – USB0 Data + USB0 OTG ID USB0 VBUS Control USB0 Bus Voltage USB0 Crystal DMC VDD HADC VDD USB VDD Rev. PrF Port E E D D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed | Page 38 of 168 | February 2016 Pin Name PE_11 PE_10 PD_13 PD_12 USB_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB_XTAL VDD_DMC VDD_HADC VDD_USB Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 GPIO MULTIPLEXING FOR 349-BALL CSP_BGA Table 13 through Table 17 identify the pin functions that are multiplexed on the general-purpose I/O pins of the 349-ball CSP_BGA package. Table 13. Signal Multiplexing for Port A Signal Name PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Multiplexed Function 0 ETH0_TXD0 ETH0_TXD1 ETH0_MDC ETH0_MDIO ETH0_RXD0 ETH0_RXD1 ETH0_RXCLK_REFCLK ETH0_CRS ETH0_RXD2 ETH0_RXD3 ETH0_TXEN ETH0_TXCLK ETH0_TXD2 ETH0_TXD3 ETH0_PTPPPS3 ETH0_PTPPPS2 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3 SMC0_A21 SMC0_A20 SMC0_A24 SMC0_A23 SMC0_A19 SMC0_A18 SMC0_A17 SMC0_A16 SMC0_A12 SMC0_A11 SMC0_A22 SMC0_A15 SMC0_A14 SMC0_A13 SMC0_A10 SMC0_A09 Multiplexed Function Input Tap Multiplexed Function 2 PPI0_D14 PPI0_D15 PPI0_D16 PPI0_D17 PPI0_D12 PPI0_D13 PWM0_BH TM0_TMR3 TM0_TMR4 CAN1_TX CAN1_RX PWM0_DH PWM0_DL PWM0_CH PWM0_CL TM0_TMR1 Multiplexed Function 3 SMC0_A08 SMC0_A07 SMC0_A04 SMC0_A03 SMC0_ARDY SMC0_A01 SMC0_A02 SMC0_D15 SMC0_D14 SMC0_D13 SMC0_D12 SMC0_D11 SMC0_D10 SMC0_D09 SMC0_D08 SMC0_AWE Multiplexed Function Input Tap TM0_ACLK3 TM0_ACLK4 SINC0_D0 SINC0_D1 Table 14. Signal Multiplexing for Port B Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 Multiplexed Function 0 ETH0_PTPPPS1 ETH0_PTPPPS0 ETH0_PTPCLKIN0 ETH0_PTPAUXIN0 MLB0_CLK MLB0_SIG MLB0_DAT LP1_D0 LP1_D1 LP1_D2 LP1_D3 LP1_D4 LP1_D5 LP1_D6 LP1_D7 LP1_ACK Multiplexed Function 1 SINC0_D2 SINC0_CLK0 UART1_TX UART1_RX SINC0_D3 PWM0_AH PWM0_AL TM0_TMR2 TM0_TMR5 PWM0_TRIP0 Rev. PrF | Page 39 of 168 | February 2016 TM0_ACI1 ETH0_PTPAUXIN1 ETH0_PTPAUXIN2 ETH0_PTPAUXIN3 TM0_ACI4 CNT0_ZM CNT0_UD CNT0_DG ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 15. Signal Multiplexing for Port C Signal Name PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 PC_15 Multiplexed Function 0 LP1_CLK SPI2_CLK SPI2_MISO SPI2_MOSI SPI2_D2 SPI2_D3 SPI2_SEL1 CAN0_RX CAN0_TX SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_SEL3 UART0_TX UART0_RX UART0_RTS Multiplexed Function 1 PWM0_BL Multiplexed Function 2 SPI0_SEL4 SPI0_SEL1 Multiplexed Function 3 SMC0_ARE SMC0_AMS2 SMC0_AMS3 Multiplexed Function Input Tap SPI2_SS TM0_ACI3 TM0_CLK SPI0_RDY SPI1_SEL1 PPI0_FS3 ACM0_T0 ACM0_A0 ACM0_A1 ACM0_A2 SMC0_A25 Multiplexed Function 2 ACM0_A3 ACM0_A4 TRACE0_D00 TRACE0_D01 TRACE0_D02 TRACE0_D03 TRACE0_D04 TRACE0_D05 TRACE0_D06 TRACE0_D07 TRACE0_CLK Multiplexed Function 3 SMC0_D07 SMC0_AOE PPI0_D19 PPI0_D18 MLB0_CLKOUT SMC0_A06 SMC0_A05 SMC0_D06 SMC0_D05 TM0_ACI0 SMC0_AMS0 Table 16. Signal Multiplexing for Port D Signal Name PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 Multiplexed Function 0 UART0_CTS SPI0_SEL2 LP0_D0 LP0_D1 LP0_D2 LP0_D3 LP0_D4 LP0_D5 LP0_D6 LP0_D7 LP0_CLK LP0_ACK UART2_TX UART2_RX PPI0_D11 PPI0_D10 Multiplexed Function 1 PPI0_D23 PWM1_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL PWM1_CH PWM1_CL PWM1_DH PWM1_DL PWM1_SYNC PWM2_TRIP0 PWM2_CH Rev. PrF | Page 40 of 168 | February 2016 Multiplexed Function Input Tap SPI0_SS TM0_ACLK1 TM0_ACLK2 TM0_ACI2 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 17. Signal Multiplexing for Port E Signal Name PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 Multiplexed Function 0 PPI0_D09 PPI0_FS2 PPI0_FS1 PPI0_CLK PPI0_D08 PPI0_D07 PPI0_D06 PPI0_D05 PPI0_D04 PPI0_D03 PPI0_D02 PPI0_D01 PPI0_D00 SPI1_CLK SPI1_MISO SPI1_MOSI Multiplexed Function 1 PWM2_CL SPI0_SEL5 SPI0_SEL6 SPI0_SEL7 PWM2_DH PWM2_SYNC SPI1_SEL5 PWM0_SYNC PWM2_DL SPI1_SEL3 SPI1_SEL4 Rev. PrF | Multiplexed Function 2 UART1_CTS UART1_RTS SPI2_SEL2 SPI2_SEL3 SPI2_SEL4 SPI2_SEL5 SPI1_SEL2 SPI1_RDY TM0_TMR0 UART2_RTS UART2_CTS SPI2_RDY PPI0_D20 PPI0_D21 PPI0_D22 Page 41 of 168 | February 2016 Multiplexed Function 3 SMC0_D04 C1_FLG0 C2_FLG0 C1_FLG1 C2_FLG1 C1_FLG2 C2_FLG2 C1_FLG3 C2_FLG3 SMC0_D03 SMC0_D02 SMC0_D01 SMC0_D00 SMC0_AMS1 SMC0_ABE0 SMC0_ABE1 Multiplexed Function Input Tap SPI1_SS ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data 529-BALL CSP_BGA SIGNAL DESCRIPTIONS The processor’s pin definitions are shown Table 18. The columns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions Signal Name ACM0_A0 ACM0_A1 ACM0_A2 ACM0_A3 ACM0_A4 ACM0_T0 C1_FLG0 C1_FLG1 C1_FLG2 C1_FLG3 C2_FLG0 C2_FLG1 C2_FLG2 C2_FLG3 CAN0_RX CAN0_TX CAN1_RX CAN1_TX CNT0_DG CNT0_UD CNT0_ZM DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN13 DAI0_PIN14 DAI0_PIN15 DAI0_PIN16 DAI0_PIN17 Description ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 ADC Control Signals ACM0 External Trigger n SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 1 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin SHARC Core 2 Flag Pin CAN0 Receive CAN0 Transmit CAN1 Receive CAN1 Transmit CNT0 Count Down and Gate CNT0 Count Up and Direction CNT0 Count Zero Marker DAI0 Pin 1 DAI0 Pin 2 DAI0 Pin 3 DAI0 Pin 4 DAI0 Pin 5 DAI0 Pin 6 DAI0 Pin 7 DAI0 Pin 8 DAI0 Pin 9 DAI0 Pin 10 DAI0 Pin 11 DAI0 Pin 12 DAI0 Pin 13 DAI0 Pin 14 DAI0 Pin 15 DAI0 Pin 16 DAI0 Pin 17 Rev. PrF | Port C C C D D C E E E E E E E E C C B B B B B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Page 42 of 168 | February 2016 Pin Name PC_13 PC_14 PC_15 PD_00 PD_01 PC_12 PE_01 PE_03 PE_05 PE_07 PE_02 PE_04 PE_06 PE_08 PC_07 PC_08 PB_10 PB_09 PB_14 PB_12 PB_11 DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN13 DAI0_PIN14 DAI0_PIN15 DAI0_PIN16 DAI0_PIN17 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name DAI0_PIN18 DAI0_PIN19 DAI0_PIN20 DAI1_PIN01 DAI1_PIN02 DAI1_PIN03 DAI1_PIN04 DAI1_PIN05 DAI1_PIN06 DAI1_PIN07 DAI1_PIN08 DAI1_PIN09 DAI1_PIN10 DAI1_PIN11 DAI1_PIN12 DAI1_PIN13 DAI1_PIN14 DAI1_PIN15 DAI1_PIN16 DAI1_PIN17 DAI1_PIN18 DAI1_PIN19 DAI1_PIN20 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_A14 DMC0_A15 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 Description DAI0 Pin 18 DAI0 Pin 19 DAI0 Pin 20 DAI1 Pin 1 DAI1 Pin 2 DAI1 Pin 3 DAI1 Pin 4 DAI1 Pin 5 DAI1 Pin 6 DAI1 Pin 7 DAI1 Pin 8 DAI1 Pin 9 DAI1 Pin 10 DAI1 Pin 11 DAI1 Pin 12 DAI1 Pin 13 DAI1 Pin 14 DAI1 Pin 15 DAI1 Pin 16 DAI1 Pin 17 DAI1 Pin 18 DAI1 Pin 19 DAI1 Pin 20 DMC0 Address 0 DMC0 Address 1 DMC0 Address 2 DMC0 Address 3 DMC0 Address 4 DMC0 Address 5 DMC0 Address 6 DMC0 Address 7 DMC0 Address 8 DMC0 Address 9 DMC0 Address 10 DMC0 Address 11 DMC0 Address 12 DMC0 Address 13 DMC0 Address 14 DMC0 Address 15 DMC0 Bank Address 0 DMC0 Bank Address 1 DMC0 Bank Address 2 DMC0 Column Address Strobe DMC0 Clock DMC0 Clock enable DMC0 Clock (complement) DMC0 Chip Select 0 DMC0 Data 0 Rev. PrF | Page 43 of 168 | Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed February 2016 Pin Name DAI0_PIN18 DAI0_PIN19 DAI0_PIN20 DAI1_PIN01 DAI1_PIN02 DAI1_PIN03 DAI1_PIN04 DAI1_PIN05 DAI1_PIN06 DAI1_PIN07 DAI1_PIN08 DAI1_PIN09 DAI1_PIN10 DAI1_PIN11 DAI1_PIN12 DAI1_PIN13 DAI1_PIN14 DAI1_PIN15 DAI1_PIN16 DAI1_PIN17 DAI1_PIN18 DAI1_PIN19 DAI1_PIN20 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_A14 DMC0_A15 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_RESET DMC0_RZQ DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE DMC1_A00 DMC1_A01 DMC1_A02 DMC1_A03 DMC1_A04 DMC1_A05 DMC1_A06 DMC1_A07 DMC1_A08 DMC1_A09 DMC1_A10 DMC1_A11 DMC1_A12 DMC1_A13 DMC1_A14 DMC1_A15 DMC1_BA0 DMC1_BA1 DMC1_BA2 DMC1_CAS DMC1_CK Description DMC0 Data 1 DMC0 Data 2 DMC0 Data 3 DMC0 Data 4 DMC0 Data 5 DMC0 Data 6 DMC0 Data 7 DMC0 Data 8 DMC0 Data 9 DMC0 Data 10 DMC0 Data 11 DMC0 Data 12 DMC0 Data 13 DMC0 Data 14 DMC0 Data 15 DMC0 Data Mask for Lower Byte DMC0 Data Strobe for Lower Byte DMC0 Data Strobe for Lower Byte (complement) DMC0 On-die termination DMC0 Row Address Strobe DMC0 Reset (DDR3 only) DMC0 External calibration resistor connection DMC0 Data Mask for Upper Byte DMC0 Data Strobe for Upper Byte DMC0 Data Strobe for Upper Byte (complement) DMC0 Voltage Reference DMC0 Write Enable DMC1 Address 0 DMC1 Address 1 DMC1 Address 2 DMC1 Address 3 DMC1 Address 4 DMC1 Address 5 DMC1 Address 6 DMC1 Address 7 DMC1 Address 8 DMC1 Address 9 DMC1 Address 10 DMC1 Address 11 DMC1 Address 12 DMC1 Address 13 DMC1 Address 14 DMC1 Address 15 DMC1 Bank Address 0 DMC1 Bank Address 1 DMC1 Bank Address 2 DMC1 Column Address Strobe DMC1 Clock Rev. PrF | Page 44 of 168 | February 2016 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Pin Name DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_RESET DMC0_RZQ DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE DMC1_A00 DMC1_A01 DMC1_A02 DMC1_A03 DMC1_A04 DMC1_A05 DMC1_A06 DMC1_A07 DMC1_A08 DMC1_A09 DMC1_A10 DMC1_A11 DMC1_A12 DMC1_A13 DMC1_A14 DMC1_A15 DMC1_BA0 DMC1_BA1 DMC1_BA2 DMC1_CAS DMC1_CK Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name DMC1_CKE DMC1_CK DMC1_CS0 DMC1_DQ00 DMC1_DQ01 DMC1_DQ02 DMC1_DQ03 DMC1_DQ04 DMC1_DQ05 DMC1_DQ06 DMC1_DQ07 DMC1_DQ08 DMC1_DQ09 DMC1_DQ10 DMC1_DQ11 DMC1_DQ12 DMC1_DQ13 DMC1_DQ14 DMC1_DQ15 DMC1_LDM DMC1_LDQS DMC1_LDQS DMC1_ODT DMC1_RAS DMC1_RESET DMC1_RZQ DMC1_UDM DMC1_UDQS DMC1_UDQS DMC1_VREF DMC1_WE ETH0_CRS ETH0_MDC ETH0_MDIO ETH0_PTPAUXIN0 ETH0_PTPAUXIN1 ETH0_PTPAUXIN2 ETH0_PTPAUXIN3 ETH0_PTPCLKIN0 ETH0_PTPPPS0 ETH0_PTPPPS1 ETH0_PTPPPS2 ETH0_PTPPPS3 ETH0_RXCLK_REFCLK ETH0_RXCTL_CRS ETH0_RXD0 ETH0_RXD1 ETH0_RXD2 Description DMC1 Clock enable DMC1 Clock (complement) DMC1 Chip Select 0 DMC1 Data 0 DMC1 Data 1 DMC1 Data 2 DMC1 Data 3 DMC1 Data 4 DMC1 Data 5 DMC1 Data 6 DMC1 Data 7 DMC1 Data 8 DMC1 Data 9 DMC1 Data 10 DMC1 Data 11 DMC1 Data 12 DMC1 Data 13 DMC1 Data 14 DMC1 Data 15 DMC1 Data Mask for Lower Byte DMC1 Data Strobe for Lower Byte DMC1 Data Strobe for Lower Byte (complement) DMC1 On-die termination DMC1 Row Address Strobe DMC1 Reset (DDR3 only) DMC1 External calibration resistor connection DMC1 Data Mask for Upper Byte DMC1 Data Strobe for Upper Byte DMC1 Data Strobe for Upper Byte (complement) DMC1 Voltage Reference DMC1 Write Enable ETH0 Carrier Sense/RMII Receive Data Valid ETH0 Management Channel Clock ETH0 Management Channel Serial Data ETH0 PTP Auxiliary Trigger Input 0 ETH0 PTP Auxiliary Trigger Input 1 ETH0 PTP Auxiliary Trigger Input 2 ETH0 PTP Auxiliary Trigger Input 3 ETH0 PTP Clock Input 0 ETH0 PTP Pulse-Per-Second Output 0 ETH0 PTP Pulse-Per-Second Output 1 ETH0 PTP Pulse-Per-Second Output 2 ETH0 PTP Pulse-Per-Second Output 3 ETH0 RXCLK (GigE) or REFCLK (10/100) ETH0 RXCTL (GigE) or CRS (10/100) ETH0 Receive Data 0 ETH0 Receive Data 1 ETH0 Receive Data 2 Rev. PrF | Page 45 of 168 | February 2016 Port Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed A A A B B B B B B B A A A A A A A Pin Name DMC1_CKE DMC1_CK DMC1_CS0 DMC1_DQ00 DMC1_DQ01 DMC1_DQ02 DMC1_DQ03 DMC1_DQ04 DMC1_DQ05 DMC1_DQ06 DMC1_DQ07 DMC1_DQ08 DMC1_DQ09 DMC1_DQ10 DMC1_DQ11 DMC1_DQ12 DMC1_DQ13 DMC1_DQ14 DMC1_DQ15 DMC1_LDM DMC1_LDQS DMC1_LDQS DMC1_ODT DMC1_RAS DMC1_RESET DMC1_RZQ DMC1_UDM DMC1_UDQS DMC1_UDQS DMC1_VREF DMC1_WE PA_07 PA_02 PA_03 PB_03 PB_04 PB_05 PB_06 PB_02 PB_01 PB_00 PA_15 PA_14 PA_06 PA_07 PA_04 PA_05 PA_08 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name ETH0_RXD3 ETH0_TXCLK ETH0_TXCTL_TXEN ETH0_TXD0 ETH0_TXD1 ETH0_TXD2 ETH0_TXD3 ETH0_TXEN ETH1_CRS ETH1_MDC ETH1_MDIO ETH1_REFCLK ETH1_RXD0 ETH1_RXD1 ETH1_TXD0 ETH1_TXD1 ETH1_TXEN HADC0_EOC_DOUT HADC0_MUX0 HADC0_MUX1 HADC0_MUX2 HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VIN4 HADC0_VIN5 HADC0_VIN6 HADC0_VIN7 HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST LP0_ACK LP0_CLK LP0_D0 LP0_D1 LP0_D2 LP0_D3 LP0_D4 LP0_D5 LP0_D6 LP0_D7 LP1_ACK LP1_CLK Description ETH0 Receive Data 3 ETH0 Transmit Clock ETH0 TXCTL (GigE) or TXEN (10/100) ETH0 Transmit Data 0 ETH0 Transmit Data 1 ETH0 Transmit Data 2 ETH0 Transmit Data 3 ETH0 Transmit Enable ETH1 Carrier Sense/RMII Receive Data Valid ETH1 Management Channel Clock ETH1 Management Channel Serial Data ETH1 Reference Clock ETH1 Receive Data 0 ETH1 Receive Data 1 ETH1 Transmit Data 0 ETH1 Transmit Data 1 ETH1 Transmit Enable HADC0 End of Conversion / Serial Data Out HADC0 Controls to external multiplexer HADC0 Controls to external multiplexer HADC0 Controls to external multiplexer HADC0 Analog Input at channel 0 HADC0 Analog Input at channel 1 HADC0 Analog Input at channel 2 HADC0 Analog Input at channel 3 HADC0 Analog Input at channel 4 HADC0 Analog Input at channel 5 HADC0 Analog Input at channel 6 HADC0 Analog Input at channel 7 HADC0 Ground Reference for ADC HADC0 External Reference for ADC TAPC JTAG Clock TAPC JTAG Serial Data In TAPC JTAG Serial Data Out TAPC JTAG Mode Select TAPC JTAG Reset LP0 Acknowledge LP0 Clock LP0 Data 0 LP0 Data 1 LP0 Data 2 LP0 Data 3 LP0 Data 4 LP0 Data 5 LP0 Data 6 LP0 Data 7 LP1 Acknowledge LP1 Clock Rev. PrF | Page 46 of 168 | Port A A A A A A A A F F F G G G G G G F F F F Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed D D D D D D D D D D B C February 2016 Pin Name PA_09 PA_11 PA_10 PA_00 PA_01 PA_12 PA_13 PA_10 PF_13 PF_14 PF_15 PG_00 PG_04 PG_05 PG_02 PG_03 PG_01 PF_02 PF_05 PF_04 PF_03 HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VIN4 HADC0_VIN5 HADC0_VIN6 HADC0_VIN7 HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST PD_11 PD_10 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PB_15 PC_00 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name LP1_D0 LP1_D1 LP1_D2 LP1_D3 LP1_D4 LP1_D5 LP1_D6 LP1_D7 MLB0_CLKN MLB0_CLKP MLB0_DATN MLB0_DATP MLB0_SIGN MLB0_SIGP MLB0_CLK MLB0_DAT MLB0_SIG MLB0_CLKOUT MSI0_CD MSI0_CLK MSI0_CMD MSI0_D0 MSI0_D1 MSI0_D2 MSI0_D3 MSI0_D4 MSI0_D5 MSI0_D6 MSI0_D7 MSI0_INT PA_00-15 PB_00-15 PCIE0_CLKM PCIE0_CLKP PCIE0_REF PCIE0_RXM PCIE0_RXP PCIE0_TXM PCIE0_TXP PC_00-15 PD_00-15 PE_00-15 PF_00-15 PG_00-5 PPI0_CLK PPI0_D00 PPI0_D01 PPI0_D02 Description LP1 Data 0 LP1 Data 1 LP1 Data 2 LP1 Data 3 LP1 Data 4 LP1 Data 5 LP1 Data 6 LP1 Data 7 MLB0 Differential Clock (–) MLB0 Differential Clock (+) MLB0 Differential Data (–) MLB0 Differential Data (+) MLB0 Differential Signal (–) MLB0 Differential Signal (+) MLB0 Single-Ended Clock MLB0 Single-Ended Data MLB0 Single-Ended Signal MLB0 Single-Ended Clock Out MSI0 Card Detect MSI0 Clock MSI0 Command MSI0 Data 0 MSI0 Data 1 MSI0 Data 2 MSI0 Data 3 MSI0 Data 4 MSI0 Data 5 MSI0 Data 6 MSI0 Data 7 MSI0 eSDIO Interrupt Input PORTA Position 00 through Position 15 PORTB Position 00 through Position 15 PCIE0 CLK PCIE0 CLK + PCIE0 Reference PCIE0 RX PCIE0 RX + PCIE0 TX PCIE0 TX + PORTC Position 00 through Position 15 PORTD Position 00 through Position 15 PORTE Position 00 through Position 15 PORTF Position 00 through Position 15 PORTG Position 00 through Position 5 EPPI0 Clock EPPI0 Data 0 EPPI0 Data 1 EPPI0 Data 2 Rev. PrF | Page 47 of 168 | Port B B B B B B B B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed B B B D F F F F F F F F F F F F A B Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed C D E F G E E E E February 2016 Pin Name PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 MLB0_CLKN MLB0_CLKP MLB0_DATN MLB0_DATP MLB0_SIGN MLB0_SIGP PB_04 PB_06 PB_05 PD_14 PF_12 PF_11 PF_10 PF_02 PF_03 PF_04 PF_05 PF_06 PF_07 PF_08 PF_09 PF_13 PA_00-15 PB_00-15 PCIE0_CLKM PCIE0_CLKP PCIE0_REF PCIE0_RXM PCIE0_RXP PCIE0_TXM PCIE0_TXP PC_00-15 PD_00-15 PE_00-15 PF_00-15 PG_00-5 PE_03 PE_12 PE_11 PE_10 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name PPI0_D03 PPI0_D04 PPI0_D05 PPI0_D06 PPI0_D07 PPI0_D08 PPI0_D09 PPI0_D10 PPI0_D11 PPI0_D12 PPI0_D13 PPI0_D14 PPI0_D15 PPI0_D16 PPI0_D17 PPI0_D18 PPI0_D19 PPI0_D20 PPI0_D21 PPI0_D22 PPI0_D23 PPI0_FS1 PPI0_FS2 PPI0_FS3 PWM0_AH PWM0_AL PWM0_BH PWM0_BL PWM0_CH PWM0_CL PWM0_DH PWM0_DL PWM0_SYNC PWM0_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL PWM1_CH PWM1_CL PWM1_DH PWM1_DL PWM1_SYNC PWM1_TRIP0 PWM2_AH PWM2_AL PWM2_BH PWM2_BL Description EPPI0 Data 3 EPPI0 Data 4 EPPI0 Data 5 EPPI0 Data 6 EPPI0 Data 7 EPPI0 Data 8 EPPI0 Data 9 EPPI0 Data 10 EPPI0 Data 11 EPPI0 Data 12 EPPI0 Data 13 EPPI0 Data 14 EPPI0 Data 15 EPPI0 Data 16 EPPI0 Data 17 EPPI0 Data 18 EPPI0 Data 19 EPPI0 Data 20 EPPI0 Data 21 EPPI0 Data 22 EPPI0 Data 23 EPPI0 Frame Sync 1 (HSYNC) EPPI0 Frame Sync 2 (VSYNC) EPPI0 Frame Sync 3 (FIELD) PWM0 Channel A High Side PWM0 Channel A Low Side PWM0 Channel B High Side PWM0 Channel B Low Side PWM0 Channel C High Side PWM0 Channel C Low Side PWM0 Channel D High Side PWM0 Channel D Low Side PWM0 PWMTMR Grouped PWM0 Shutdown Input 0 PWM1 Channel A High Side PWM1 Channel A Low Side PWM1 Channel B High Side PWM1 Channel B Low Side PWM1 Channel C High Side PWM1 Channel C Low Side PWM1 Channel D High Side PWM1 Channel D Low Side PWM1 PWMTMR Grouped PWM1 Shutdown Input 0 PWM2 Channel A High Side PWM2 Channel A Low Side PWM2 Channel B High Side PWM2 Channel B Low Side Rev. PrF | Port E E E E E E E D D B B B B B B D D E E E D E E C B B B C B B B B E B D D D D D D D D D D F F F F Page 48 of 168 | February 2016 Pin Name PE_09 PE_08 PE_07 PE_06 PE_05 PE_04 PE_00 PD_15 PD_14 PB_04 PB_05 PB_00 PB_01 PB_02 PB_03 PD_13 PD_12 PE_13 PE_14 PE_15 PD_00 PE_02 PE_01 PC_15 PB_07 PB_08 PB_06 PC_00 PB_13 PB_14 PB_11 PB_12 PE_09 PB_15 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_02 PF_07 PF_06 PF_09 PF_08 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name PWM2_CH PWM2_CL PWM2_DH PWM2_DL PWM2_SYNC PWM2_TRIP0 GND VDD_EXT VDD_INT RTC0_CLKIN RTC0_XTAL SINC0_CLK0 SINC0_D0 SINC0_D1 SINC0_D2 SINC0_D3 SMC0_A01 SMC0_A02 SMC0_A03 SMC0_A04 SMC0_A05 SMC0_A06 SMC0_A07 SMC0_A08 SMC0_A09 SMC0_A10 SMC0_A11 SMC0_A12 SMC0_A13 SMC0_A14 SMC0_A15 SMC0_A16 SMC0_A17 SMC0_A18 SMC0_A19 SMC0_A20 SMC0_A21 SMC0_A22 SMC0_A23 SMC0_A24 SMC0_A25 SMC0_ABE0 SMC0_ABE1 SMC0_AMS0 SMC0_AMS1 SMC0_AMS2 SMC0_AMS3 SMC0_AOE Description PWM2 Channel C High Side PWM2 Channel C Low Side PWM2 Channel D High Side PWM2 Channel D Low Side PWM2 PWMTMR Grouped PWM2 Shutdown Input 0 Ground External Voltage Domain Internal Voltage Domain RTC0 Crystal input / external oscillator connection RTC0 Crystal output SINC0 Clock 0 SINC0 Data 0 SINC0 Data 1 SINC0 Data 2 SINC0 Data 3 SMC0 Address 1 SMC0 Address 2 SMC0 Address 3 SMC0 Address 4 SMC0 Address 5 SMC0 Address 6 SMC0 Address 7 SMC0 Address 8 SMC0 Address 9 SMC0 Address 10 SMC0 Address 11 SMC0 Address 12 SMC0 Address 13 SMC0 Address 14 SMC0 Address 15 SMC0 Address 16 SMC0 Address 17 SMC0 Address 18 SMC0 Address 19 SMC0 Address 20 SMC0 Address 21 SMC0 Address 22 SMC0 Address 23 SMC0 Address 24 SMC0 Address 25 SMC0 Byte Enable 0 SMC0 Byte Enable 1 SMC0 Memory Select 0 SMC0 Memory Select 1 SMC0 Memory Select 2 SMC0 Memory Select 3 SMC0 Output Enable Rev. PrF | Page 49 of 168 | February 2016 Port D E E E E D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed B A A B B B B B B D D B B A A A A A A A A A A A A A A A A C E E C E C C D Pin Name PD_15 PE_00 PE_04 PE_10 PE_05 PD_14 GND VDD_EXT VDD_INT RTC0_CLKIN RTC0_XTAL PB_01 PA_14 PA_15 PB_00 PB_04 PB_05 PB_06 PB_03 PB_02 PD_13 PD_12 PB_01 PB_00 PA_15 PA_14 PA_09 PA_08 PA_13 PA_12 PA_11 PA_07 PA_06 PA_05 PA_04 PA_01 PA_00 PA_10 PA_03 PA_02 PC_12 PE_14 PE_15 PC_15 PE_13 PC_07 PC_08 PD_01 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name SMC0_ARDY SMC0_ARE SMC0_AWE SMC0_D00 SMC0_D01 SMC0_D02 SMC0_D03 SMC0_D04 SMC0_D05 SMC0_D06 SMC0_D07 SMC0_D08 SMC0_D09 SMC0_D10 SMC0_D11 SMC0_D12 SMC0_D13 SMC0_D14 SMC0_D15 SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_RDY SPI0_SEL1 SPI0_SEL2 SPI0_SEL3 SPI0_SEL4 SPI0_SEL5 SPI0_SEL6 SPI0_SEL7 SPI0_SS SPI1_CLK SPI1_MISO SPI1_MOSI SPI1_RDY SPI1_SEL1 SPI1_SEL2 SPI1_SEL3 SPI1_SEL4 SPI1_SEL5 SPI1_SEL6 SPI1_SEL7 SPI1_SS SPI2_CLK SPI2_D2 SPI2_D3 SPI2_MISO SPI2_MOSI Description SMC0 Asynchronous Ready SMC0 Read Enable SMC0 Write Enable SMC0 Data 0 SMC0 Data 1 SMC0 Data 2 SMC0 Data 3 SMC0 Data 4 SMC0 Data 5 SMC0 Data 6 SMC0 Data 7 SMC0 Data 8 SMC0 Data 9 SMC0 Data 10 SMC0 Data 11 SMC0 Data 12 SMC0 Data 13 SMC0 Data 14 SMC0 Data 15 SPI0 Clock SPI0 Master In, Slave Out SPI0 Master Out, Slave In SPI0 Ready SPI0 Slave Select Output 1 SPI0 Slave Select Output 2 SPI0 Slave Select Output 3 SPI0 Slave Select Output 4 SPI0 Slave Select Output 5 SPI0 Slave Select Output 6 SPI0 Slave Select Output 7 SPI0 Slave Select Input SPI1 Clock SPI1 Master In, Slave Out SPI1 Master Out, Slave In SPI1 Ready SPI1 Slave Select Output 1 SPI1 Slave Select Output 2 SPI1 Slave Select Output 3 SPI1 Slave Select Output 4 SPI1 Slave Select Output 5 SPI1 Slave Select Output 6 SPI1 Slave Select Output 7 SPI1 Slave Select Input SPI2 Clock SPI2 Data 2 SPI2 Data 3 SPI2 Master In, Slave Out SPI2 Master Out, Slave In Rev. PrF Port B C B E E E E E D D D B B B B B B B B C C C C C D C C E E E D E E E E C E E E E F F E C C C C C | Page 50 of 168 | February 2016 Pin Name PB_04 PC_00 PB_15 PE_12 PE_11 PE_10 PE_09 PE_00 PD_15 PD_14 PD_00 PB_14 PB_13 PB_12 PB_11 PB_10 PB_09 PB_08 PB_07 PC_09 PC_10 PC_11 PC_12 PC_07 PD_01 PC_12 PC_00 PE_01 PE_02 PE_03 PD_01 PE_13 PE_14 PE_15 PE_08 PC_13 PE_07 PE_11 PE_12 PE_08 PF_00 PF_01 PE_11 PC_01 PC_04 PC_05 PC_02 PC_03 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name SPI2_RDY SPI2_SEL1 SPI2_SEL2 SPI2_SEL3 SPI2_SEL4 SPI2_SEL5 SPI2_SS SYS_BMODE0 SYS_BMODE1 SYS_BMODE2 SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT SYS_FAULT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 TM0_ACI0 TM0_ACI1 TM0_ACI2 TM0_ACI3 TM0_ACI4 TM0_ACLK1 TM0_ACLK2 TM0_ACLK3 TM0_ACLK4 TM0_CLK TM0_TMR0 TM0_TMR1 TM0_TMR2 TM0_TMR3 TM0_TMR4 TM0_TMR5 TM0_TMR6 TM0_TMR7 TRACE0_CLK TRACE0_CLK TRACE0_D00 TRACE0_D00 TRACE0_D01 TRACE0_D01 TRACE0_D02 TRACE0_D02 TRACE0_D03 TRACE0_D03 TRACE0_D04 Description SPI2 Ready SPI2 Slave Select Output 1 SPI2 Slave Select Output 2 SPI2 Slave Select Output 3 SPI2 Slave Select Output 4 SPI2 Slave Select Output 5 SPI2 Slave Select Input Boot Mode Control 0 Boot Mode Control 1 Boot Mode Control 2 Clock/Crystal Input Clock/Crystal Input Processor Clock Output Active-High Fault Output Active-Low Fault Output Processor Hardware Reset Control Reset Output Crystal Output Crystal Output TIMER0 Alternate Capture Input 0 TIMER0 Alternate Capture Input 1 TIMER0 Alternate Capture Input 2 TIMER0 Alternate Capture Input 3 TIMER0 Alternate Capture Input 4 TIMER0 Alternate Clock 1 TIMER0 Alternate Clock 2 TIMER0 Alternate Clock 3 TIMER0 Alternate Clock 4 TIMER0 Clock TIMER0 Timer 0 TIMER0 Timer 1 TIMER0 Timer 2 TIMER0 Timer 3 TIMER0 Timer 4 TIMER0 Timer 5 TIMER0 Timer 6 TIMER0 Timer 7 TRACE0 Trace Clock TRACE0 Trace Clock TRACE0 Trace Data TRACE0 Trace Data 0 TRACE0 Trace Data 1 TRACE0 Trace Data TRACE0 Trace Data TRACE0 Trace Data 2 TRACE0 Trace Data TRACE0 Trace Data 3 TRACE0 Trace Data Rev. PrF | Page 51 of 168 | Port E C E E E E C Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed C B D C B D D B B C E B B B B B F F G D F D D F F D G D G February 2016 Pin Name PE_12 PC_06 PE_03 PE_04 PE_05 PE_06 PC_06 SYS_BMODE0 SYS_BMODE1 SYS_BMODE2 SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT SYS_FAULT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 PC_14 PB_03 PD_13 PC_07 PB_10 PD_08 PD_09 PB_00 PB_01 PC_11 PE_09 PB_15 PB_10 PB_07 PB_08 PB_14 PF_00 PF_01 PG_00 PD_10 PF_13 PD_02 PD_03 PF_14 PF_15 PD_04 PG_01 PD_05 PG_02 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name TRACE0_D04 TRACE0_D05 TRACE0_D05 TRACE0_D06 TRACE0_D06 TRACE0_D07 TRACE0_D07 TRACE0_D08 TRACE0_D09 TRACE0_D10 TRACE0_D11 TRACE0_D12 TRACE0_D13 TRACE0_D14 TRACE0_D15 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA UART0_CTS UART0_RTS UART0_RX UART0_TX UART1_CTS UART1_RTS UART1_RX UART1_TX UART2_CTS UART2_RTS UART2_RX UART2_TX USB0_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB0_XTAL USB1_DM USB1_DP USB1_VBUS VDD_DMC VDD_HADC VDD_PCIE VDD_PCIE_RX Description TRACE0 Trace Data 4 TRACE0 Trace Data 5 TRACE0 Trace Data TRACE0 Trace Data TRACE0 Trace Data 6 TRACE0 Trace Data TRACE0 Trace Data 7 TRACE0 Trace Data 8 TRACE0 Trace Data 9 TRACE0 Trace Data 10 TRACE0 Trace Data 11 TRACE0 Trace Data 12 TRACE0 Trace Data 13 TRACE0 Trace Data 14 TRACE0 Trace Data 15 TWI0 Serial Clock TWI0 Serial Data TWI1 Serial Clock TWI1 Serial Data TWI2 Serial Clock TWI2 Serial Data UART0 Clear to Send UART0 Request to Send UART0 Receive UART0 Transmit UART1 Clear to Send UART1 Request to Send UART1 Receive UART1 Transmit UART2 Clear to Send UART2 Request to Send UART2 Receive UART2 Transmit USB0 Clock/Crystal Input USB0 Data – USB0 Data + USB0 OTG ID USB0 VBUS Control USB0 Bus Voltage USB0 Crystal USB1 Data USB1 Data + USB1 Bus Voltage DMC VDD HADC VDD PCIE Supply Voltage PCIE RX Supply Voltage Rev. PrF Port D D G G D G D F F F G G G G G Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed D C C C E E B B E E D D Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed Not Muxed | Page 52 of 168 | February 2016 Pin Name PD_06 PD_07 PG_03 PG_04 PD_08 PG_05 PD_09 PF_13 PF_14 PF_15 PG_01 PG_02 PG_03 PG_04 PG_05 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA PD_00 PC_15 PC_14 PC_13 PE_01 PE_02 PB_03 PB_02 PE_11 PE_10 PD_13 PD_12 USB_CLKIN USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB_XTAL USB1_DM USB1_DP USB1_VBUS VDD_DMC VDD_HADC VDD_PCIE VDD_PCIE_RX Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 18. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued) Signal Name VDD_PCIE_TX VDD_RTC VDD_USB Description PCIE TX Supply Voltage RTC VDD USB VDD Rev. PrF Port Not Muxed Not Muxed Not Muxed | Page 53 of 168 | February 2016 Pin Name VDD_PCIE_TX VDD_RTC VDD_USB ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data GPIO MULTIPLEXING FOR 529-BALL CSP_BGA Table 19 through Table 25 identify the pin functions that are multiplexed on the general-purpose I/O pins of the 529-ball CSP_BGA package. Table 19. Signal Multiplexing for Port A Signal Name PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 Multiplexed Function 0 ETH0_TXD0 ETH0_TXD1 ETH0_MDC ETH0_MDIO ETH0_RXD0 ETH0_RXD1 ETH0_RXCLK_REFCLK ETH0_CRS ETH0_RXD2 ETH0_RXD3 ETH0_TXEN ETH0_TXCLK ETH0_TXD2 ETH0_TXD3 ETH0_PTPPPS3 ETH0_PTPPPS2 Multiplexed Function 1 SINC0_D0 SINC0_D1 Multiplexed Function Multiplexed 2 Function 3 SMC0_A21 SMC0_A20 SMC0_A24 SMC0_A23 SMC0_A19 SMC0_A18 SMC0_A17 SMC0_A16 SMC0_A12 SMC0_A11 SMC0_A22 SMC0_A15 SMC0_A14 SMC0_A13 SMC0_A10 SMC0_A09 Multiplexed Function Input Tap Multiplexed Function 2 PPI0_D14 PPI0_D15 PPI0_D16 PPI0_D17 PPI0_D12 PPI0_D13 PWM0_BH TM0_TMR3 TM0_TMR4 CAN1_TX CAN1_RX PWM0_DH PWM0_DL PWM0_CH PWM0_CL TM0_TMR1 Multiplexed Function Input Tap TM0_ACLK3 TM0_ACLK4 Table 20. Signal Multiplexing for Port B Signal Name PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 Multiplexed Function 0 ETH0_PTPPPS1 ETH0_PTPPPS0 ETH0_PTPCLKIN0 ETH0_PTPAUXIN0 MLB0_CLK MLB0_SIG MLB0_DAT LP1_D0 LP1_D1 LP1_D2 LP1_D3 LP1_D4 LP1_D5 LP1_D6 LP1_D7 LP1_ACK Multiplexed Function 1 SINC0_D2 SINC0_CLK0 UART1_TX UART1_RX SINC0_D3 PWM0_AH PWM0_AL TM0_TMR2 TM0_TMR5 PWM0_TRIP0 Rev. PrF | Page 54 of 168 | February 2016 Multiplexed Function 3 SMC0_A08 SMC0_A07 SMC0_A04 SMC0_A03 SMC0_ARDY SMC0_A01 SMC0_A02 SMC0_D15 SMC0_D14 SMC0_D13 SMC0_D12 SMC0_D11 SMC0_D10 SMC0_D09 SMC0_D08 SMC0_AWE TM0_ACI1 ETH0_PTPAUXIN1 ETH0_PTPAUXIN2 ETH0_PTPAUXIN3 TM0_ACI4 CNT0_ZM CNT0_UD CNT0_DG Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 21. Signal Multiplexing for Port C Signal Name PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 PC_15 Multiplexed Function 0 LP1_CLK SPI2_CLK SPI2_MISO SPI2_MOSI SPI2_D2 SPI2_D3 SPI2_SEL1 CAN0_RX CAN0_TX SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_SEL3 UART0_TX UART0_RX UART0_RTS Multiplexed Function 1 PWM0_BL Multiplexed Function 2 SPI0_SEL4 SPI0_SEL1 Multiplexed Function 3 SMC0_ARE SMC0_AMS2 SMC0_AMS3 Multiplexed Function Input Tap SPI2_SS TM0_ACI3 TM0_CLK SPI0_RDY SPI1_SEL1 PPI0_FS3 ACM0_T0 ACM0_A0 ACM0_A1 ACM0_A2 SMC0_A25 Multiplexed Function 2 ACM0_A3 ACM0_A4 TRACE0_D00 TRACE0_D01 TRACE0_D02 TRACE0_D03 TRACE0_D04 TRACE0_D05 TRACE0_D06 TRACE0_D07 TRACE0_CLK Multiplexed Function 3 SMC0_D07 SMC0_AOE PPI0_D19 PPI0_D18 MLB0_CLKOUT SMC0_A06 SMC0_A05 SMC0_D06 SMC0_D05 TM0_ACI0 SMC0_AMS0 Table 22. Signal Multiplexing for Port D Signal Name PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 Multiplexed Function 0 UART0_CTS SPI0_SEL2 LP0_D0 LP0_D1 LP0_D2 LP0_D3 LP0_D4 LP0_D5 LP0_D6 LP0_D7 LP0_CLK LP0_ACK UART2_TX UART2_RX PPI0_D11 PPI0_D10 Multiplexed Function 1 PPI0_D23 PWM1_TRIP0 PWM1_AH PWM1_AL PWM1_BH PWM1_BL PWM1_CH PWM1_CL PWM1_DH PWM1_DL PWM1_SYNC PWM2_TRIP0 PWM2_CH Rev. PrF | Page 55 of 168 | February 2016 Multiplexed Function Input Tap SPI0_SS TM0_ACLK1 TM0_ACLK2 TM0_ACI2 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 23. Signal Multiplexing for Port E Signal Name PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 Multiplexed Function 0 PPI0_D09 PPI0_FS2 PPI0_FS1 PPI0_CLK PPI0_D08 PPI0_D07 PPI0_D06 PPI0_D05 PPI0_D04 PPI0_D03 PPI0_D02 PPI0_D01 PPI0_D00 SPI1_CLK SPI1_MISO SPI1_MOSI Multiplexed Function 1 PWM2_CL SPI0_SEL5 SPI0_SEL6 SPI0_SEL7 PWM2_DH PWM2_SYNC Multiplexed Function 2 Multiplexed Function Input Tap UART1_CTS UART1_RTS SPI2_SEL2 SPI2_SEL3 SPI2_SEL4 SPI2_SEL5 SPI1_SEL2 SPI1_RDY TM0_TMR0 UART2_RTS UART2_CTS SPI2_RDY PPI0_D20 PPI0_D21 PPI0_D22 Multiplexed Function 3 SMC0_D04 C1_FLG0 C2_FLG0 C1_FLG1 C2_FLG1 C1_FLG2 C2_FLG2 C1_FLG3 C2_FLG3 SMC0_D03 SMC0_D02 SMC0_D01 SMC0_D00 SMC0_AMS1 SMC0_ABE0 SMC0_ABE1 Multiplexed Function 1 SPI1_SEL6 SPI1_SEL7 HADC0_EOC_DOUT HADC0_MUX2 HADC0_MUX1 HADC0_MUX0 PWM2_AL PWM2_AH PWM2_BL PWM2_BH Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap TRACE0_D08 TRACE0_D09 TRACE0_D10 TRACE0_D00 TRACE0_D01 TRACE0_D02 MSI0_INT SPI1_SEL5 PWM0_SYNC PWM2_DL SPI1_SEL3 SPI1_SEL4 SPI1_SS Table 24. Signal Multiplexing for Port F Signal Name PF_00 PF_01 PF_02 PF_03 PF_04 PF_05 PF_06 PF_07 PF_08 PF_09 PF_10 PF_11 PF_12 PF_13 PF_14 PF_15 Multiplexed Function 0 TM0_TMR6 TM0_TMR7 MSI0_D0 MSI0_D1 MSI0_D2 MSI0_D3 MSI0_D4 MSI0_D5 MSI0_D6 MSI0_D7 MSI0_CMD MSI0_CLK MSI0_CD ETH1_CRS ETH1_MDC ETH1_MDIO Rev. PrF | Page 56 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 25. Signal Multiplexing for Port G Signal Name PG_00 PG_01 PG_02 PG_03 PG_04 PG_05 Multiplexed Function 0 ETH1_REFCLK ETH1_TXEN ETH1_TXD0 ETH1_TXD1 ETH1_RXD0 ETH1_RXD1 Multiplexed Function 1 TRACE0_CLK TRACE0_D11 TRACE0_D12 TRACE0_D13 TRACE0_D14 TRACE0_D15 Rev. PrF | Multiplexed Function 2 TRACE0_D03 TRACE0_D04 TRACE0_D05 TRACE0_D06 TRACE0_D07 Page 57 of 168 | February 2016 Multiplexed Function 3 Multiplexed Function Input Tap ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data ADSP-SC58X/ADSP-2158X DESIGNER QUICK REFERENCE Table 26 provides a quick reference summary of pin related information for circuit board design. The columns in this table provide the following information: • Reset Termination: The Reset Term column in the table specifies the termination present when the processor is in the reset state. • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applicable) the GPIO multiplexed pin function for every pin. • Reset Drive: The Reset Drive column in the table specifies the active drive on the signal when the processor is in the reset state. • Pin Type: The Type column in the table identifies the I/O type or supply type of the pin. The abbreviations used in this column are a (analog), s (supply), g (ground) and Input/Output/InOut. • Power Domain: The Power Domain column in the table specifies the power supply domain in which the signal resides. • Driver Type: The Driver Type column in the table identifies the driver type used by the pin. The driver types are defined in the output drive currents section of this data sheet. • Internal Termination: The Int Term column in the table specifies the termination present when the processor is not in the reset state. • Description and Notes: The Description and Notes column in the table identifies any special requirements or characteristics for the signal. If no special requirements are listed the signal may be left unconnected if it is not used. Also, for multiplexed general-purpose I/O pins, this column identifies the functions available on the pin. Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference Signal Name DAI0_PIN01 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT DAI0_PIN02 InOut A PullDown none none VDD_EXT DAI0_PIN03 InOut A PullDown none none VDD_EXT DAI0_PIN04 InOut A PullDown none none VDD_EXT DAI0_PIN05 InOut A PullDown none none VDD_EXT DAI0_PIN06 InOut A PullDown none none VDD_EXT DAI0_PIN07 InOut A PullDown none none VDD_EXT DAI0_PIN08 InOut A PullDown none none VDD_EXT DAI0_PIN09 InOut A PullDown none none VDD_EXT DAI0_PIN10 InOut A PullDown none none VDD_EXT DAI0_PIN11 InOut A PullDown none none VDD_EXT DAI0_PIN12 InOut A PullDown none none VDD_EXT DAI0_PIN13 InOut A PullDown none none VDD_EXT DAI0_PIN14 InOut A PullDown none none VDD_EXT Rev. PrF | Page 58 of 168 | February 2016 Description and Notes Desc: DAI0 Pin 1 Notes: No notes Desc: DAI0 Pin 2 Notes: No notes Desc: DAI0 Pin 3 Notes: No notes Desc: DAI0 Pin 4 Notes: No notes Desc: DAI0 Pin 5 Notes: No notes Desc: DAI0 Pin 6 Notes: No notes Desc: DAI0 Pin 7 Notes: No notes Desc: DAI0 Pin 8 Notes: No notes Desc: DAI0 Pin 9 Notes: No notes Desc: DAI0 Pin 10 Notes: No notes Desc: DAI0 Pin 11 Notes: No notes Desc: DAI0 Pin 12 Notes: No notes Desc: DAI0 Pin 13 Notes: No notes Desc: DAI0 Pin 14 Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name DAI0_PIN15 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT DAI0_PIN16 InOut A PullDown none none VDD_EXT DAI0_PIN17 InOut A PullDown none none VDD_EXT DAI0_PIN18 InOut A PullDown none none VDD_EXT DAI0_PIN19 InOut A PullDown none none VDD_EXT DAI0_PIN20 InOut A PullDown none none VDD_EXT DAI1_PIN01 InOut A PullDown none none VDD_EXT DAI1_PIN02 InOut A PullDown none none VDD_EXT DAI1_PIN03 InOut A PullDown none none VDD_EXT DAI1_PIN04 InOut A PullDown none none VDD_EXT DAI1_PIN05 InOut A PullDown none none VDD_EXT DAI1_PIN06 InOut A PullDown none none VDD_EXT DAI1_PIN07 InOut A PullDown none none VDD_EXT DAI1_PIN08 InOut A PullDown none none VDD_EXT DAI1_PIN09 InOut A PullDown none none VDD_EXT DAI1_PIN10 InOut A PullDown none none VDD_EXT DAI1_PIN11 InOut A PullDown none none VDD_EXT DAI1_PIN12 InOut A PullDown none none VDD_EXT DAI1_PIN13 InOut A PullDown none none VDD_EXT DAI1_PIN14 InOut A PullDown none none VDD_EXT DAI1_PIN15 InOut A PullDown none none VDD_EXT DAI1_PIN16 InOut A PullDown none none VDD_EXT DAI1_PIN17 InOut A PullDown none none VDD_EXT DAI1_PIN18 InOut A PullDown none none VDD_EXT Rev. PrF | Page 59 of 168 | February 2016 Description and Notes Desc: DAI0 Pin 15 Notes: No notes Desc: DAI0 Pin 16 Notes: No notes Desc: DAI0 Pin 17 Notes: No notes Desc: DAI0 Pin 18 Notes: No notes Desc: DAI0 Pin 19 Notes: No notes Desc: DAI0 Pin 20 Notes: No notes Desc: DAI1 Pin 1 Notes: No notes Desc: DAI1 Pin 2 Notes: No notes Desc: DAI1 Pin 3 Notes: No notes Desc: DAI1 Pin 4 Notes: No notes Desc: DAI1 Pin 5 Notes: No notes Desc: DAI1 Pin 6 Notes: No notes Desc: DAI1 Pin 7 Notes: No notes Desc: DAI1 Pin 8 Notes: No notes Desc: DAI1 Pin 9 Notes: No notes Desc: DAI1 Pin 10 Notes: No notes Desc: DAI1 Pin 11 Notes: No notes Desc: DAI1 Pin 12 Notes: No notes Desc: DAI1 Pin 13 Notes: No notes Desc: DAI1 Pin 14 Notes: No notes Desc: DAI1 Pin 15 Notes: No notes Desc: DAI1 Pin 16 Notes: No notes Desc: DAI1 Pin 17 Notes: No notes Desc: DAI1 Pin 18 Notes: No notes ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name DAI1_PIN19 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT DAI1_PIN20 InOut A PullDown none none VDD_EXT DMC0_A00 Output B none none none VDD_DMC DMC0_A01 Output B none none none VDD_DMC DMC0_A02 Output B none none none VDD_DMC DMC0_A03 Output B none none none VDD_DMC DMC0_A04 Output B none none none VDD_DMC DMC0_A05 Output B none none none VDD_DMC DMC0_A06 Output B none none none VDD_DMC DMC0_A07 Output B none none none VDD_DMC DMC0_A08 Output B none none none VDD_DMC DMC0_A09 Output B none none none VDD_DMC DMC0_A10 Output B none none none VDD_DMC DMC0_A11 Output B none none none VDD_DMC DMC0_A12 Output B none none none VDD_DMC DMC0_A13 Output B none none none VDD_DMC DMC0_A14 Output B none none none VDD_DMC DMC0_A15 Output B none none none VDD_DMC DMC0_BA0 Output B none none none VDD_DMC DMC0_BA1 Output B none none none VDD_DMC DMC0_BA2 Output B none none none VDD_DMC DMC0_CAS Output B none none none VDD_DMC Rev. PrF | Page 60 of 168 | February 2016 Description and Notes Desc: DAI1 Pin 19 Notes: No notes Desc: DAI1 Pin 20 Notes: No notes Desc: DMC0 Address 0 Notes: No notes Desc: DMC0 Address 1 Notes: No notes Desc: DMC0 Address 2 Notes: No notes Desc: DMC0 Address 3 Notes: No notes Desc: DMC0 Address 4 Notes: No notes Desc: DMC0 Address 5 Notes: No notes Desc: DMC0 Address 6 Notes: No notes Desc: DMC0 Address 7 Notes: No notes Desc: DMC0 Address 8 Notes: No notes Desc: DMC0 Address 9 Notes: No notes Desc: DMC0 Address 10 Notes: No notes Desc: DMC0 Address 11 Notes: No notes Desc: DMC0 Address 12 Notes: No notes Desc: DMC0 Address 13 Notes: No notes Desc: DMC0 Address 14 Notes: No notes Desc: DMC0 Address 15 Notes: No notes Desc: DMC0 Bank Address Input 0 Notes: No notes Desc: DMC0 Bank Address Input 1 Notes: No notes Desc: DMC0 Bank Address Input 2 Notes: No notes Desc: DMC0 Column Address Strobe Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name DMC0_CK Type Output Driver Type C Int Term Reset Term Reset Drive none none L Power Domain VDD_DMC DMC0_CKE Output B none none L VDD_DMC DMC0_CK Output C none none L VDD_DMC DMC0_CS0 Output B none none none VDD_DMC DMC0_DQ00 InOut B none none VDD_DMC DMC0_DQ01 InOut B none none VDD_DMC Desc: DMC0 Data 1 Notes: No notes DMC0_DQ02 InOut B none none VDD_DMC Desc: DMC0 Data 2 Notes: No notes DMC0_DQ03 InOut B none none VDD_DMC Desc: DMC0 Data 3 Notes: No notes DMC0_DQ04 InOut B none none VDD_DMC Desc: DMC0 Data 4 Notes: No notes DMC0_DQ05 InOut B none none VDD_DMC Desc: DMC0 Data 5 Notes: No notes DMC0_DQ06 InOut B none none VDD_DMC Desc: DMC0 Data 6 Notes: No notes DMC0_DQ07 InOut B none none VDD_DMC Desc: DMC0 Data 7 Notes: No notes DMC0_DQ08 InOut B none none VDD_DMC Desc: DMC0 Data 8 Notes: No notes DMC0_DQ09 InOut B Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float none none VDD_DMC Desc: DMC0 Data 9 Notes: No notes Rev. PrF | Page 61 of 168 | February 2016 Description and Notes Desc: DMC0 Clock Notes: No notes Desc: DMC0 Clock enable Notes: No notes Desc: DMC0 Clock (complement) Notes: No notes Desc: DMC0 Chip Select 0 Notes: No notes Desc: DMC0 Data 0 Notes: No notes ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Int Term Reset Term Reset Drive Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float none none none Power Domain VDD_DMC none none VDD_DMC Desc: DMC0 Data 11 Notes: No notes none none VDD_DMC Desc: DMC0 Data 12 Notes: No notes none none VDD_DMC Desc: DMC0 Data 13 Notes: No notes none none VDD_DMC Desc: DMC0 Data 14 Notes: No notes none none VDD_DMC Desc: DMC0 Data 15 Notes: No notes none none VDD_DMC Internal logic none ensures that input signal does not float Internal logic none ensures that input signal does not float none VDD_DMC Desc: DMC0 Data Mask for Lower Byte Notes: No notes Desc: DMC0 Data Strobe for Lower Byte (complement) Notes: No notes none VDD_DMC B none none none VDD_DMC Output B none none none VDD_DMC DMC0_RESET Output B none none none VDD_DMC DMC0_RZQ a B none none none VDD_DMC DMC0_UDM Output B none none none VDD_DMC Signal Name DMC0_DQ10 Type InOut Driver Type B DMC0_DQ11 InOut B DMC0_DQ12 InOut B DMC0_DQ13 InOut B DMC0_DQ14 InOut B DMC0_DQ15 InOut B DMC0_LDM Output B DMC0_LDQS InOut C DMC0_LDQS InOut C DMC0_ODT Output DMC0_RAS Rev. PrF | Page 62 of 168 | February 2016 Description and Notes Desc: DMC0 Data 10 Notes: No notes Desc: DMC0 Data Strobe for Lower Byte Notes: External weak pulldown required in LPDDR mode Desc: DMC0 On-die termination Notes: No notes Desc: DMC0 Row Address Strobe Notes: No notes Desc: DMC0 Reset (DDR3 only) Notes: No notes Desc: DMC0 External calibration resistor connection Notes: Applicable for DDR2 and DDR3 only. External pull-down of 34 ohms need to be added. Desc: DMC0 Data Mask for Upper Byte Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Reset Term Reset Drive Internal logic none ensures that input signal does not float none Power Domain VDD_DMC Internal logic none ensures that input signal does not float none none none VDD_DMC none VDD_DMC B none none none VDD_DMC Output B none none none VDD_DMC DMC1_A01 Output B none none none VDD_DMC DMC1_A02 Output B none none none VDD_DMC DMC1_A03 Output B none none none VDD_DMC DMC1_A04 Output B none none none VDD_DMC DMC1_A05 Output B none none none VDD_DMC DMC1_A06 Output B none none none VDD_DMC DMC1_A07 Output B none none none VDD_DMC DMC1_A08 Output B none none none VDD_DMC DMC1_A09 Output B none none none VDD_DMC DMC1_A10 Output B none none none VDD_DMC DMC1_A11 Output B none none none VDD_DMC DMC1_A12 Output B none none none VDD_DMC DMC1_A13 Output B none none none VDD_DMC DMC1_A14 Output B none none none VDD_DMC DMC1_A15 Output B none none none VDD_DMC DMC1_BA0 Output B none none none VDD_DMC Signal Name DMC0_UDQS Type InOut Driver Type C DMC0_UDQS InOut C DMC0_VREF a DMC0_WE Output DMC1_A00 Int Term Rev. PrF | Page 63 of 168 | February 2016 Description and Notes Desc: DMC0 Data Strobe for Upper Byte Notes: External weak pulldown required in LPDDR mode Desc: DMC0 Data Strobe for Upper Byte (complement) Notes: No notes Desc: DMC0 Voltage Reference Notes: No notes Desc: DMC0 Write Enable Notes: No notes Desc: DMC1 Address 0 Notes: No notes Desc: DMC1 Address 1 Notes: No notes Desc: DMC1 Address 2 Notes: No notes Desc: DMC1 Address 3 Notes: No notes Desc: DMC1 Address 4 Notes: No notes Desc: DMC1 Address 5 Notes: No notes Desc: DMC1 Address 6 Notes: No notes Desc: DMC1 Address 7 Notes: No notes Desc: DMC1 Address 8 Notes: No notes Desc: DMC1 Address 9 Notes: No notes Desc: DMC1 Address 10 Notes: No notes Desc: DMC1 Address 11 Notes: No notes Desc: DMC1 Address 12 Notes: No notes Desc: DMC1 Address 13 Notes: No notes Desc: DMC1 Address 14 Notes: No notes Desc: DMC1 Address 15 Notes: No notes Desc: DMC1 Bank Address Input 0 Notes: No notes ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name DMC1_BA1 Type Output Driver Type B Int Term Reset Term Reset Drive none none none Power Domain VDD_DMC DMC1_BA2 Output B none none none VDD_DMC DMC1_CAS Output B none none none VDD_DMC DMC1_CK Output C none none L VDD_DMC DMC1_CKE Output B none none L VDD_DMC DMC1_CK Output C none none L VDD_DMC DMC1_CS0 Output B none none none VDD_DMC DMC1_DQ00 InOut B none none VDD_DMC DMC1_DQ01 InOut B none none VDD_DMC Desc: DMC1 Data 1 Notes: No notes DMC1_DQ02 InOut B none none VDD_DMC Desc: DMC1 Data 2 Notes: No notes DMC1_DQ03 InOut B none none VDD_DMC Desc: DMC1 Data 3 Notes: No notes DMC1_DQ04 InOut B none none VDD_DMC Desc: DMC1 Data 4 Notes: No notes DMC1_DQ05 InOut B none none VDD_DMC Desc: DMC1 Data 5 Notes: No notes DMC1_DQ06 InOut B none none VDD_DMC Desc: DMC1 Data 6 Notes: No notes DMC1_DQ07 InOut B Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float none none VDD_DMC Desc: DMC1 Data 7 Notes: No notes Rev. PrF | Page 64 of 168 | February 2016 Description and Notes Desc: DMC1 Bank Address Input 1 Notes: No notes Desc: DMC1 Bank Address Input 2 Notes: No notes Desc: DMC1 Column Address Strobe Notes: No notes Desc: DMC1 Clock Notes: No notes Desc: DMC1 Clock enable Notes: No notes Desc: DMC1 Clock (complement) Notes: No notes Desc: DMC1 Chip Select 0 Notes: No notes Desc: DMC1 Data 0 Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Int Term Reset Term Reset Drive Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float none none none Power Domain VDD_DMC none none VDD_DMC Desc: DMC1 Data 9 Notes: No notes none none VDD_DMC Desc: DMC1 Data 10 Notes: No notes none none VDD_DMC Desc: DMC1 Data 11 Notes: No notes none none VDD_DMC Desc: DMC1 Data 12 Notes: No notes none none VDD_DMC Desc: DMC1 Data 13 Notes: No notes none none VDD_DMC Desc: DMC1 Data 14 Notes: No notes none none VDD_DMC Desc: DMC1 Data 15 Notes: No notes none none VDD_DMC C Internal logic none ensures that input signal does not float none VDD_DMC InOut C none VDD_DMC DMC1_ODT Output B Internal logic none ensures that input signal does not float none none Desc: DMC1 Data Mask for Lower Byte Notes: No notes Desc: DMC1 Data Strobe for Lower Byte Notes: External weak pulldown required in LPDDR mode Desc: DMC1 Data Strobe for Lower Byte (complement) Notes: No notes none VDD_DMC DMC1_RAS Output B none none none VDD_DMC DMC1_RESET InOut B none none none VDD_DMC Signal Name DMC1_DQ08 Type InOut Driver Type B DMC1_DQ09 InOut B DMC1_DQ10 InOut B DMC1_DQ11 InOut B DMC1_DQ12 InOut B DMC1_DQ13 InOut B DMC1_DQ14 InOut B DMC1_DQ15 InOut B DMC1_LDM Output B DMC1_LDQS InOut DMC1_LDQS Rev. PrF | Page 65 of 168 | February 2016 Description and Notes Desc: DMC1 Data 8 Notes: No notes Desc: DMC1 On-die termination Notes: No notes Desc: DMC1 Row Address Strobe Notes: No notes Desc: DMC1 Reset (DDR3 only) Notes: No notes ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name DMC1_RZQ Type a Driver Type B Int Term Reset Term Reset Drive none none none Power Domain VDD_DMC DMC1_UDM Output B none none none VDD_DMC DMC1_UDQS InOut C Internal logic none ensures that input signal does not float none VDD_DMC DMC1_UDQS InOut C none VDD_DMC DMC1_VREF a Internal logic none ensures that input signal does not float none none none VDD_DMC DMC1_WE Output B none none none GND g NA none none none HADC0_VIN0 a NA none none none VDD_HADC HADC0_VIN1 a NA none none none VDD_HADC HADC0_VIN2 a NA none none none VDD_HADC HADC0_VIN3 a NA none none none VDD_HADC HADC0_VIN4 a NA none none none VDD_HADC HADC0_VIN5 a NA none none none VDD_HADC HADC0_VIN6 a NA none none none VDD_HADC Rev. PrF | Page 66 of 168 | February 2016 Description and Notes Desc: DMC1 External calibration resistor connection Notes: Applicable for DDR2 and DDR3 only. External pull-down of 34 ohms need to be added. Desc: DMC1 Data Mask for Upper Byte Notes: No notes Desc: DMC1 Data Strobe for Upper Byte Notes: External weak pulldown required in LPDDR mode Desc: DMC1 Data Strobe for Upper Byte (complement) Notes: No notes Desc: DMC1 Voltage Reference Notes: No notes Desc: DMC1 Write Enable Notes: No notes Desc: Ground Notes: No notes Desc: HADC0 Analog Input at channel 0 Notes: If Input not used connect to GND Desc: HADC0 Analog Input at channel 1 Notes: If Input not used connect to GND Desc: HADC0 Analog Input at channel 2 Notes: If Input not used connect to GND Desc: HADC0 Analog Input at channel 3 Notes: If Input not used connect to GND Desc: HADC0 Analog Input at channel 4 Notes: If Input not used connect to GND Desc: HADC0 Analog Input at channel 5 Notes: If Input not used connect to GND Desc: HADC0 Analog Input at channel 6 Notes: If Input not used connect to GND Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name HADC0_VIN7 Type a Driver Type NA Int Term Reset Term Reset Drive none none none Power Domain VDD_HADC HADC0_VREFN s NA none none none VDD_HADC HADC0_VREFP s NA none none none VDD_HADC JTG_TCK Input PullUp none none VDD_EXT JTG_TDI Input PullUp none none VDD_EXT JTG_TDO Output A none none none VDD_EXT JTG_TMS InOut A PullUp none none VDD_EXT JTG_TRST Input PullDown none none VDD_EXT MLB0_CLKN Input TBD none none VDD_EXT MLB0_CLKP Input TBD none none VDD_EXT Desc: MLB0 Differential Clock (+) Notes: No notes MLB0_DATN InOut TBD none none VDD_EXT Desc: MLB0 Differential Data (-) Notes: No notes MLB0_DATP InOut TBD none none VDD_EXT Desc: MLB0 Differential Data (+) Notes: No notes MLB0_SIGN InOut TBD none none VDD_EXT Desc: MLB0 Differential Signal (-) Notes: No notes MLB0_SIGP InOut TBD none none VDD_EXT Desc: MLB0 Differential Signal (+) Notes: No notes PA_00 InOut A Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float Internal logic ensures that input signal does not float PullDown none none VDD_EXT Desc: PORTA Position 0 | EMAC0 Transmit Data 0 | SMC0 Address 21 Notes: No notes Rev. PrF | Page 67 of 168 | February 2016 Description and Notes Desc: HADC0 Analog Input at channel 7 Notes: If Input not used connect to GND Desc: HADC0 Ground Reference for ADC Notes: No notes Desc: HADC0 External Reference for ADC Notes: No notes Desc: JTAG Clock Notes: No notes Desc: JTAG Serial Data In Notes: No notes Desc: JTAG Serial Data Out Notes: No notes Desc: JTAG Mode Select Notes: No notes Desc: JTAG Reset Notes: No notes Desc: MLB0 Differential Clock (-) Notes: No notes ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PA_01 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT PA_02 InOut A PullDown none none VDD_EXT PA_03 InOut A PullDown none none VDD_EXT PA_04 InOut A PullDown none none VDD_EXT PA_05 InOut A PullDown none none VDD_EXT PA_06 InOut A PullDown none none VDD_EXT PA_07 InOut A PullDown none none VDD_EXT PA_08 InOut A PullDown none none VDD_EXT PA_09 InOut A PullDown none none VDD_EXT PA_10 InOut A PullDown none none VDD_EXT PA_11 InOut A PullDown none none VDD_EXT PA_12 InOut A PullDown none none VDD_EXT PA_13 InOut A PullDown none none VDD_EXT Rev. PrF | Page 68 of 168 | February 2016 Description and Notes Desc: PORTA Position 1 | EMAC0 Transmit Data 1 | SMC0 Address 20 Notes: No notes Desc: PORTA Position 2 | EMAC0 Management Channel Clock | SMC0 Address 24 Notes: No notes Desc: PORTA Position 3 | EMAC0 Management Channel Serial Data | SMC0 Address 23 Notes: No notes Desc: PORTA Position 4 | EMAC0 Receive Data 0 | SMC0 Address 19 Notes: No notes Desc: PORTA Position 5 | EMAC0 Receive Data 1 | SMC0 Address 18 Notes: No notes Desc: PORTA Position 6 | EMAC0 RXCLK (GigE) or REFCLK (10/100) | SMC0 Address 17 Notes: No notes Desc: EMAC0 RXCTL (GigE) or CRS (10/100) | PORTA Position 7 | EMAC0 Carrier Sense/RMII Receive Data Valid | SMC0 Address 16 Notes: No notes Desc: PORTA Position 8 | EMAC0 Receive Data 2 | SMC0 Address 12 Notes: No notes Desc: PORTA Position 9 | EMAC0 Receive Data 3 | SMC0 Address 11 Notes: No notes Desc: EMAC0 TXCTL (GigE) or TXEN (10/100) | PORTA Position 10 | EMAC0 Transmit Enable | SMC0 Address 22 Notes: No notes Desc: PORTA Position 11 | EMAC0 Transmit Clock | SMC0 Address 15 Notes: No notes Desc: PORTA Position 12 | EMAC0 Transmit Data 2 | SMC0 Address 14 Notes: No notes Desc: PORTA Position 13 | EMAC0 Transmit Data 3 | SMC0 Address 13 Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PA_14 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT PA_15 InOut A PullDown none none VDD_EXT PB_00 InOut A PullDown none none VDD_EXT PB_01 InOut A PullDown none none VDD_EXT PB_02 InOut A PullDown none none VDD_EXT PB_03 InOut A PullDown none none VDD_EXT PB_04 InOut A PullDown none none VDD_EXT PB_05 InOut A PullDown none none VDD_EXT PB_06 InOut A PullDown none none VDD_EXT PB_07 InOut A PullDown none none VDD_EXT Rev. PrF | Page 69 of 168 | February 2016 Description and Notes Desc: PORTA Position 14 | EMAC0 PTP Pulse-Per-Second Output 3 | SINC0 Data 0 | SMC0 Address 10 Notes: No notes Desc: PORTA Position 15 | EMAC0 PTP Pulse-Per-Second Output 2 | SINC0 Data 1 | SMC0 Address 9 Notes: No notes Desc: PORTB Position 0 | EMAC0 PTP Pulse-Per-Second Output 1 | EPPI0 Data 14 | SINC0 Data 2 | SMC0 Address 8 | TIMER0 Alternate Clock 3 Notes: No notes Desc: PORTB Position 1 | EMAC0 PTP Pulse-Per-Second Output 0 | EPPI0 Data 15 | SINC0 Clock 0 | SMC0 Address 7 | TIMER0 Alternate Clock 4 Notes: No notes Desc: PORTB Position 2 | EMAC0 PTP Clock Input 0 | EPPI0 Data 16 | SMC0 Address 4 | UART1 Transmit Notes: No notes Desc: PORTB Position 3 | EMAC0 PTP Auxiliary Trigger Input 0 | EPPI0 Data 17 | SMC0 Address 3 | UART1 Receive | TIMER0 Alternate Capture Input 1 Notes: No notes Desc: PORTB Position 4 | EPPI0 Data 12 | MLB0 Single-Ended Clock | SINC0 Data 3 | SMC0 Asynchronous Ready | EMAC0 PTP Auxiliary Trigger Input 1 Notes: No notes Desc: PORTB Position 5 | EPPI0 Data 13 | MLB0 Single-Ended Signal | SMC0 Address 1 | EMAC0 PTP Auxiliary Trigger Input 2 Notes: No notes Desc: PORTB Position 6 | MLB0 Single-Ended Data | PWM0 Channel B High Side | SMC0 Address 2 | EMAC0 PTP Auxiliary Trigger Input 3 Notes: No notes Desc: PORTB Position 7 | LP1 Data 0 | PWM0 Channel A High Side | SMC0 Data 15 | TIMER0 Timer 3 Notes: No notes ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PB_08 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT PB_09 InOut A PullDown none none VDD_EXT PB_10 InOut A PullDown none none VDD_EXT PB_11 InOut A PullDown none none VDD_EXT PB_12 InOut A PullDown none none VDD_EXT PB_13 InOut A PullDown none none VDD_EXT PB_14 InOut A PullDown none none VDD_EXT PB_15 InOut A PullDown none none VDD_EXT PCIE0_CLKM InOut TBD PullDown none none VDD_PCIE PCIE0_CLKP InOut TBD PullDown none none VDD_PCIE PCIE0_REF InOut TBD PullDown none none VDD_PCIE PCIE0_RXM InOut TBD PullDown none none VDD_PCIE_RX PCIE0_RXP InOut TBD PullDown none none VDD_PCIE_RX PCIE0_TXM InOut TBD PullDown none none VDD_PCIE_TX Rev. PrF | Page 70 of 168 | February 2016 Description and Notes Desc: PORTB Position 8 | LP1 Data 1 | PWM0 Channel A Low Side | SMC0 Data 14 | TIMER0 Timer 4 Notes: No notes Desc: PORTB Position 9 | CAN1 Transmit | LP1 Data 2 | SMC0 Data 13 Notes: No notes Desc: PORTB Position 10 | CAN1 Receive | LP1 Data 3 | SMC0 Data 12 | TIMER0 Timer 2 | TIMER0 Alternate Capture Input 4 Notes: No notes Desc: PORTB Position 11 | LP1 Data 4 | PWM0 Channel D High Side | SMC0 Data 11 | CNT0 Count Zero Marker Notes: No notes Desc: PORTB Position 12 | LP1 Data 5 | PWM0 Channel D Low Side | SMC0 Data 10 | CNT0 Count Up and Direction Notes: No notes Desc: PORTB Position 13 | LP1 Data 6 | PWM0 Channel C High Side | SMC0 Data 9 Notes: No notes Desc: PORTB Position 14 | LP1 Data 7 | PWM0 Channel C Low Side | SMC0 Data 8 | TIMER0 Timer 5 | CNT0 Count Down and Gate Notes: No notes Desc: PORTB Position 15 | LP1 Acknowledge | PWM0 Shutdown Input 0 | SMC0 Write Enable | TIMER0 Timer 1 Notes: No notes Desc: PCIE0 CLK Notes: No notes Desc: PCIE0 CLK + Notes: No notes Desc: PCIE0 Reference Notes: No notes Desc: PCIE0 RX Notes: No notes Desc: PCIE0 RX + Notes: No notes Desc: PCIE0 TX Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PCIE0_TXP Type InOut Driver Type TBD Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_PCIE_TX PC_00 InOut A PullDown none none VDD_EXT PC_01 InOut A PullDown none none VDD_EXT PC_02 InOut A PullDown none none VDD_EXT PC_03 InOut A PullDown none none VDD_EXT PC_04 InOut A PullDown none none VDD_EXT PC_05 InOut A PullDown none none VDD_EXT PC_06 InOut A PullDown none none VDD_EXT PC_07 InOut A PullDown none none VDD_EXT PC_08 InOut A PullDown none none VDD_EXT PC_09 InOut A PullDown none none VDD_EXT PC_10 InOut A PullDown none none VDD_EXT PC_11 InOut A PullDown none none VDD_EXT PC_12 InOut A PullDown none none VDD_EXT Rev. PrF | Page 71 of 168 | February 2016 Description and Notes Desc: PCIE0 TX + Notes: No notes Desc: PORTC Position 0 | LP1 Clock | PWM0 Channel B Low Side | SMC0 Read Enable | SPI0 Slave Select Output 4 Notes: No notes Desc: PORTC Position 1 | SPI2 Clock Notes: No notes Desc: PORTC Position 2 | SPI2 Master In, Slave Out Notes: No notes Desc: PORTC Position 3 | SPI2 Master Out, Slave In Notes: No notes Desc: PORTC Position 4 | SPI2 Data 2 Notes: No notes Desc: PORTC Position 5 | SPI2 Data 3 Notes: No notes Desc: PORTC Position 6 | SPI2 Slave Select Output 1 | SPI2 Slave Select Input Notes: No notes Desc: PORTC Position 7 | CAN0 Receive | SMC0 Memory Select 2 | SPI0 Slave Select Output 1 | TIMER0 Alternate Capture Input 3 Notes: No notes Desc: PORTC Position 8 | CAN0 Transmit | SMC0 Memory Select 3 Notes: No notes Desc: PORTC Position 9 | SPI0 Clock Notes: No notes Desc: PORTC Position 10 | SPI0 Master In, Slave Out Notes: No notes Desc: PORTC Position 11 | SPI0 Master Out, Slave In | TIMER0 Clock Notes: No notes Desc: PORTC Position 12 | ACM0 External Trigger n | SMC0 Address 25 | SPI0 Ready | SPI0 Slave Select Output 3 Notes: No notes ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PC_13 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT PC_14 InOut A PullDown none none VDD_EXT PC_15 InOut A PullDown none none VDD_EXT PD_00 InOut A PullDown none none VDD_EXT PD_01 InOut A PullDown none none VDD_EXT PD_02 InOut A PullDown none none VDD_EXT PD_03 InOut A PullDown none none VDD_EXT PD_04 InOut A PullDown none none VDD_EXT PD_05 InOut A PullDown none none VDD_EXT PD_06 InOut A PullDown none none VDD_EXT PD_07 InOut A PullDown none none VDD_EXT Rev. PrF | Page 72 of 168 | February 2016 Description and Notes Desc: PORTC Position 13 | ACM0 ADC Control Signals | SPI1 Slave Select Output 1 | UART0 Transmit Notes: No notes Desc: PORTC Position 14 | ACM0 ADC Control Signals | UART0 Receive | TIMER0 Alternate Capture Input 0 Notes: No notes Desc: PORTC Position 15 | ACM0 ADC Control Signals | EPPI0 Frame Sync 3 (FIELD) | SMC0 Memory Select 0 | UART0 Request to Send Notes: No notes Desc: PORTD Position 0 | ACM0 ADC Control Signals | EPPI0 Data 23 | SMC0 Data 7 | UART0 Clear to Send Notes: No notes Desc: PORTD Position 1 | ACM0 ADC Control Signals | SMC0 Output Enable | SPI0 Slave Select Output 2 | SPI0 Slave Select Input Notes: No notes Desc: PORTD Position 2 | LP0 Data 0 | PWM1 Shutdown Input 0 | TRACE0 Trace Data 0 Notes: No notes Desc: PORTD Position 3 | LP0 Data 1 | PWM1 Channel A High Side | TRACE0 Trace Data 1 Notes: No notes Desc: PORTD Position 4 | LP0 Data 2 | PWM1 Channel A Low Side | TRACE0 Trace Data 2 Notes: No notes Desc: PORTD Position 5 | LP0 Data 3 | PWM1 Channel B High Side | TRACE0 Trace Data 3 Notes: No notes Desc: PORTD Position 6 | LP0 Data 4 | PWM1 Channel B Low Side | TRACE0 Trace Data 4 Notes: No notes Desc: PORTD Position 7 | LP0 Data 5 | PWM1 Channel C High Side | TRACE0 Trace Data 5 Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PD_08 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT PD_09 InOut A PullDown none none VDD_EXT PD_10 InOut A PullDown none none VDD_EXT PD_11 InOut A PullDown none none VDD_EXT PD_12 InOut A PullDown none none VDD_EXT PD_13 InOut A PullDown none none VDD_EXT PD_14 InOut A PullDown none none VDD_EXT PD_15 InOut A PullDown none none VDD_EXT PE_00 InOut A PullDown none none VDD_EXT PE_01 InOut A PullDown none none VDD_EXT Rev. PrF | Page 73 of 168 | February 2016 Description and Notes Desc: PORTD Position 8 | LP0 Data 6 | PWM1 Channel C Low Side | TRACE0 Trace Data 6 | TIMER0 Alternate Clock 1 Notes: No notes Desc: PORTD Position 9 | LP0 Data 7 | PWM1 Channel D High Side | TRACE0 Trace Data 7 | TIMER0 Alternate Clock 2 Notes: No notes Desc: PORTD Position 10 | LP0 Clock | PWM1 Channel D Low Side | TRACE0 Trace Clock Notes: No notes Desc: PORTD Position 11 | LP0 Acknowledge | PWM1 PWMTMR Grouped Notes: No notes Desc: PORTD Position 12 | EPPI0 Data 19 | SMC0 Address 6 | UART2 Transmit Notes: No notes Desc: PORTD Position 13 | EPPI0 Data 18 | SMC0 Address 5 | UART2 Receive | TIMER0 Alternate Capture Input 2 Notes: No notes Desc: PORTD Position 14 | EPPI0 Data 11 | MLB0 Single-Ended Clock Out | PWM2 Shutdown Input 0 | SMC0 Data 6 Notes: No notes Desc: PORTD Position 15 | EPPI0 Data 10 | PWM2 Channel C High Side | SMC0 Data 5 Notes: No notes Desc: PORTE Position 0 | EPPI0 Data 9 | PWM2 Channel C Low Side | SMC0 Data 4 Notes: No notes Desc: PORTE Position 1 | EPPI0 Frame Sync 2 (VSYNC) | SPI0 Slave Select Output 5 | SHARC Core 1 Flag Pin | UART1 Clear to Send Notes: No notes ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PE_02 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT PE_03 InOut A PullDown none none VDD_EXT PE_04 InOut A PullDown none none VDD_EXT PE_05 InOut A PullDown none none VDD_EXT PE_06 InOut A PullDown none none VDD_EXT PE_07 InOut A PullDown none none VDD_EXT PE_08 InOut A PullDown none none VDD_EXT PE_09 InOut A PullDown none none VDD_EXT PE_10 InOut A PullDown none none VDD_EXT PE_11 InOut A PullDown none none VDD_EXT Rev. PrF | Page 74 of 168 | February 2016 Description and Notes Desc: PORTE Position 2 | EPPI0 Frame Sync 1 (HSYNC) | SPI0 Slave Select Output 6 | SHARC Core 2 Flag Pin | UART1 Request to Send Notes: No notes Desc: PORTE Position 3 | EPPI0 Clock | SPI0 Slave Select Output 7 | SPI2 Slave Select Output 2 | SHARC Core 1 Flag Pin Notes: No notes Desc: PORTE Position 4 | EPPI0 Data 8 | PWM2 Channel D High Side | SPI2 Slave Select Output 3 | SHARC Core 2 Flag Pin Notes: No notes Desc: PORTE Position 5 | EPPI0 Data 7 | PWM2 PWMTMR Grouped | SPI2 Slave Select Output 4 | SHARC Core 1 Flag Pin Notes: No notes Desc: PORTE Position 6 | EPPI0 Data 6 | SPI2 Slave Select Output 5 | SHARC Core 2 Flag Pin Notes: No notes Desc: PORTE Position 7 | EPPI0 Data 5 | SPI1 Slave Select Output 2 | SHARC Core 1 Flag Pin Notes: No notes Desc: PORTE Position 8 | EPPI0 Data 4 | SPI1 Ready | SPI1 Slave Select Output 5 | SHARC Core 2 Flag Pin Notes: No notes Desc: PORTE Position 9 | EPPI0 Data 3 | PWM0 PWMTMR Grouped | SMC0 Data 3 | TIMER0 Timer 0 Notes: No notes Desc: PORTE Position 10 | EPPI0 Data 2 | PWM2 Channel D Low Side | SMC0 Data 2 | UART2 Request to Send Notes: No notes Desc: PORTE Position 11 | EPPI0 Data 1 | SMC0 Data 1 | SPI1 Slave Select Output 3 | UART2 Clear to Send | SPI1 Slave Select Input Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PE_12 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT PE_13 InOut A PullDown none none VDD_EXT PE_14 InOut A PullDown none none VDD_EXT PE_15 InOut A PullDown none none VDD_EXT PF_00 InOut A PullDown none none VDD_EXT PF_01 InOut A PullDown none none VDD_EXT PF_02 InOut A PullDown/Progra none mmable PullUp none VDD_EXT PF_03 InOut A PullDown/Progra none mmable PullUp none VDD_EXT PF_04 InOut A PullDown/Progra none mmable PullUp none VDD_EXT PF_05 InOut A PullDown/Progra none mmable PullUp none VDD_EXT PF_06 InOut A PullDown/Progra none mmable PullUp none VDD_EXT PF_07 InOut A PullDown/Progra none mmable PullUp none VDD_EXT Rev. PrF | Page 75 of 168 | February 2016 Description and Notes Desc: PORTE Position 12 | EPPI0 Data 0 | SMC0 Data 0 | SPI1 Slave Select Output 4 | SPI2 Ready Notes: No notes Desc: PORTE Position 13 | EPPI0 Data 20 | SMC0 Memory Select 1 | SPI1 Clock Notes: No notes Desc: PORTE Position 14 | EPPI0 Data 21 | SMC0 Byte Enable 0 | SPI1 Master In, Slave Out Notes: No notes Desc: PORTE Position 15 | EPPI0 Data 22 | SMC0 Byte Enable 1 | SPI1 Master Out, Slave In Notes: No notes Desc: PORTF Position 0 | SPI1 Slave Select Output 6 | TIMER0 Timer 6 Notes: No notes Desc: PORTF Position 1 | SPI1 Slave Select Output 7 | TIMER0 Timer 7 Notes: No notes Desc: PORTF Position 2 | HADC0 End of Conversion / Serial Data Out | MSI0 Data 0 Notes: No notes Desc: PORTF Position 3 | HADC0 Controls to external multiplexer | MSI0 Data 1 Notes: No notes Desc: PORTF Position 4 | HADC0 Controls to external multiplexer | MSI0 Data 2 Notes: No notes Desc: PORTF Position 5 | HADC0 Controls to external multiplexer | MSI0 Data 3 Notes: No notes Desc: PORTF Position 6 | MSI0 Data 4 | PWM2 Channel A Low Side Notes: No notes Desc: PORTF Position 7 | MSI0 Data 5 | PWM2 Channel A High Side Notes: No notes ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PF_08 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown/Progra none mmable PullUp none Power Domain VDD_EXT PF_09 InOut A PullDown/Progra none mmable PullUp none VDD_EXT PF_10 InOut A PullDown/Progra none mmable PullUp none VDD_EXT PF_11 InOut A PullDown none none VDD_EXT PF_12 InOut A PullDown none none VDD_EXT PF_13 InOut A PullDown none none VDD_EXT PF_14 InOut A PullDown none none VDD_EXT PF_15 InOut A PullDown none none VDD_EXT PG_00 InOut A PullDown none none VDD_EXT PG_01 InOut A PullDown none none VDD_EXT PG_02 InOut A PullDown none none VDD_EXT PG_03 InOut A PullDown none none VDD_EXT Rev. PrF | Page 76 of 168 | February 2016 Description and Notes Desc: PORTF Position 8 | MSI0 Data 6 | PWM2 Channel B Low Side Notes: No notes Desc: PORTF Position 9 | MSI0 Data 7 | PWM2 Channel B High Side Notes: No notes Desc: PORTF Position 10 | MSI0 Command Notes: No notes Desc: PORTF Position 11 | MSI0 Clock Notes: No notes Desc: PORTF Position 12 | MSI0 Card Detect Notes: No notes Desc: PORTF Position 13 | EMAC1 Carrier Sense/RMII Receive Data Valid | MSI0 eSDIO Interrupt Input | TRACE0 Trace Data | TRACE0 Trace Data 8 Notes: No notes Desc: PORTF Position 14 | EMAC1 Management Channel Clock | TRACE0 Trace Data | TRACE0 Trace Data 9 Notes: No notes Desc: PORTF Position 15 | EMAC1 Management Channel Serial Data | TRACE0 Trace Data | TRACE0 Trace Data 10 Notes: No notes Desc: PORTG Position 0 | EMAC1 Reference Clock | TRACE0 Trace Clock Notes: No notes Desc: PORTG Position 1 | EMAC1 Transmit Enable | TRACE0 Trace Data | TRACE0 Trace Data 11 Notes: No notes Desc: PORTG Position 2 | EMAC1 Transmit Data 0 | TRACE0 Trace Data | TRACE0 Trace Data 12 Notes: No notes Desc: PORTG Position 3 | EMAC1 Transmit Data 1 | TRACE0 Trace Data | TRACE0 Trace Data 13 Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name PG_04 Type InOut Driver Type A Int Term Reset Term Reset Drive PullDown none none Power Domain VDD_EXT PG_05 InOut A PullDown none none VDD_EXT RTC0_CLKIN a NA none none none VDD_RTC RTC0_XTAL a NA none none none VDD_RTC SYS_BMODE0 Input NA PullDown none none VDD_EXT SYS_BMODE1 Input NA PullDown none none VDD_EXT SYS_BMODE2 Input NA PullDown none none VDD_EXT SYS_CLKIN0 a NA none none none VDD_EXT SYS_CLKIN1 a NA none none none VDD_EXT SYS_CLKOUT a A none none none SYS_FAULT InOut A none none none SYS_FAULT InOut A none none none SYS_HWRST Input NA none none none VDD_EXT SYS_RESOUT Output A none none L VDD_EXT SYS_XTAL0 a NA none none none VDD_EXT SYS_XTAL1 a NA none none none VDD_EXT TWI0_SCL InOut D none none none VDD_EXT TWI0_SDA InOut D none none none VDD_EXT Rev. PrF | Page 77 of 168 | February 2016 Description and Notes Desc: PORTG Position 4 | EMAC1 Receive Data 0 | TRACE0 Trace Data | TRACE0 Trace Data 14 Notes: No notes Desc: PORTG Position 5 | EMAC1 Receive Data 1 | TRACE0 Trace Data | TRACE0 Trace Data 15 Notes: No notes Desc: RTC0 Crystal input / external oscillator connection Notes: Connect to GND if not used Desc: RTC0 Crystal output Notes: No notes Desc: Boot Mode Control n Notes: No notes Desc: Boot Mode Control n Notes: No notes Desc: Boot Mode Control n Notes: No notes Desc: Clock/Crystal Input Notes: No notes Desc: Clock/Crystal Input Notes: Connect to GND if not used Desc: Processor Clock Output Notes: No notes Desc: Active-High Fault Output Notes: External pulldown required to keep signal in deasserted state Desc: Active-Low Fault Output Notes: External pullup required to keep signal in de-asserted state Desc: Processor Hardware Reset Control Notes: No notes Desc: Reset Output Notes: No notes Desc: Crystal Output Notes: No notes Desc: Crystal Output Notes: No notes Desc: TWI0 Serial Clock Notes: External pullup required Desc: TWI0 Serial Data Notes: External pullup required ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name TWI1_SCL Type InOut Driver Type D Int Term Reset Term Reset Drive none none none Power Domain VDD_EXT TWI1_SDA InOut D none none none VDD_EXT TWI2_SCL InOut D none none none VDD_EXT TWI2_SDA InOut D none none none VDD_EXT USB0_DM InOut F none none none VDD_USB USB0_DP InOut F none none none VDD_USB USB0_ID InOut none none none VDD_USB USB0_VBC InOut E none none none VDD_USB USB0_VBUS InOut G none none none VDD_USB USB1_DM InOut F none none none VDD_USB USB1_DP InOut F none none none VDD_USB USB1_VBUS InOut G none none none VDD_USB USB_CLKIN a none none none USB_XTAL a none none none VDD_DMC s NA none none none VDD_EXT s NA none none none VDD_HADC s NA none none none VDD_INT s NA none none none Rev. PrF | Page 78 of 168 | February 2016 Description and Notes Desc: TWI1 Serial Clock Notes: External pullup required Desc: TWI1 Serial Data Notes: External pullup required Desc: TWI2 Serial Clock Notes: External pullup required Desc: TWI2 Serial Data Notes: External pullup required Desc: USB0 Data Notes: Add External Pull Down if not used Desc: USB0 Data + Notes: Add External Pull Down if not used Desc: USB0 OTG ID Notes: Connect to GND when USB is not used Desc: USB0 VBUS Control Notes: Add External pull down if not used Desc: USB0 Bus Voltage Notes: Connect to GND if not used Desc: USB1 Data Notes: Add External Pull Down if not used Desc: USB1 Data + Notes: Add External Pull Down if not used Desc: USB1 Bus Voltage Notes: Connect to GND if not used Desc: USB0/USB1 Clock/Crystal Input Notes: Services both USB0 and USB1. Connect to GND if not used. Desc: USB0/USB1 Crystal Notes: Services both USB0 and USB1 Desc: DMC VDD Notes: No notes Desc: External Voltage Domain Notes: No notes Desc: HADC VDD Notes: No notes Desc: Internal Voltage Domain Notes: No notes Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 26. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued) Signal Name VDD_PCIE Type s Driver Type NA Int Term Reset Term Reset Drive none none none VDD_PCIE_RX s NA none none none VDD_PCIE_TX s NA none none none VDD_RTC s NA none none none VDD_USB s NA none none none Rev. PrF | Page 79 of 168 | Power Domain February 2016 Description and Notes Desc: PCIE Supply Voltage Notes: Connect to GND if not used Desc: PCIE RX Supply Voltage Notes: Connect to GND if not used Desc: PCIE TX Supply Voltage Notes: Connect to GND if not used Desc: RTC VDD Notes: No notes Desc: USB VDD Notes: Connect to VDD_EXT when USB is not used ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data SPECIFICATIONS For information about product specifications please contact your Analog Devices, Inc. representative. OPERATING CONDITIONS 450 MHz 1 Parameter Description Min Nominal Max Unit VDD_INT VDD_EXT VDD_HADC VDD_DMC2 Internal (Core) Supply Voltage External (I/O) Supply Voltage Analog Power Supply Voltage DDR2/LPDDR Controller Supply Voltage DDR3 Controller Supply Voltage USB Supply Voltage RTC Voltage PCIe Core Transmit Voltage PCIe Core Receive Voltage PCIe Voltage DDR2 Reference Voltage HADC Reference Voltage High Level Input Voltage @ VDD_EXT = Max Low Level Input Voltage @ VDD_EXT = Min Low Level Input Voltage @ VDD_DMC = Min High Level Input Voltage @ VDD_DMC = Max Low Level Input Voltage @ VDD_DMC = Min High Level Input Voltage @ VDD_DMC = Max Junction Temperature 349-Lead CSP_BGA @ TAMBIENT 0°C to +70°C Junction Temperature 349-Lead CSP_BGA @ TAMBIENT –40°C to +105°C Junction Temperature 529-Lead CSP_BGA @ TAMBIENT 0°C to +70°C Junction Temperature 529-Lead CSP_BGA @ TAMBIENT –40°C to +85°C 1.05 3.13 3.13 1.7 1.425 3.13 3.13 1.05 1.05 3.13 0.49 × VDD_DMC 2.5 2.0 1.1 3.3 3.3 1.8 1.5 3.3 3.3 1.1 1.1 3.3 0.50 × VDD_DMC 3.30 1.15 3.47 3.47 1.9 1.575 3.47 3.47 1.15 1.15 3.47 0.51 × VDD_DMC VDD_HADC VDD_USB3 VDD_RTC VDD_PCIE_TX VDD_PCIE_RX VDD_PCIE VDDR_VREF VHADC_REF4 VIH5 VIL5 VIL_DDR2/36 VIH_DDR2/36 VIL_LPDDR7 VIH_LPDDR7 TJ TJ TJ TJ 0.8 × VDD_DMC TBD TBD V V V V V V V V V V V V V V V V V V °C –40 133 °C TBD TBD °C TBD TBD °C 0.8 VREF – 0.25 VREF + 0.25 0.2 × VDD_DMC 1 Specifications subject to change without notice. Applies to DDR2/DDR3/LPDDR signals. 3 If not used, VDD_USB should be connected to 3.3V. 4 VHADC_VREF should always be less than VDD_HADC. 5 Parameter value applies to all input and bidirectional pins except all the TWI, DMC, USB, PCIe, and MLB pins. 6 This parameter applies to all DMC0/1 signals in DDR2/DDR3 mode. VREF is the voltage applied to pin VREF_DMC, nominally VDD_DMC/2. 7 This parameter applies to DMC0/1 signals in LPDDR mode. 2 Table 27. TWI_VSEL Selections and VDD_EXT/VBUSTWI 1 VDD_EXT Nominal VBUSTWI Min VBUSTWI Nominal VBUSTWI Max Unit TWI0001 3.30 3.13 3.30 3.47 V TWI100 3.30 4.75 5.00 5.25 V Designs must comply with the VDD_EXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset. Rev. PrF | Page 80 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Clock Related Operating Conditions Table 28 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the tables applies to all speed grades except where expressly noted. Table 28. Clock Operating Conditions Parameter Restriction fCCLK Core Clock Frequency fSYSCLK SYSCLK Frequency fSCLK0 SCLK0 Frequency1 fSYSCLK ≥ fSCLK0 fSCLK1 SCLK1 Frequency fSYSCLK ≥ fSCLK1 fDCLK fDCLK Min Typ fCCLK ≥ fSYSCLK Max Unit 450 MHz 225 MHz 112.5 MHz 112.5 MHz LPDDR Clock Frequency 200 MHz DDR2 Clock Frequency 400 MHz fDCLK DDR3 Clock Frequency 450 MHz fOCLK Output Clock Frequency TBD MHz fSYS_CLKOUTJ SYS_CLKOUT Period Jitter 2, 3 30 ±1 % fPCLKPROG Programmed PPI Clock When Transmitting Data and Frame Sync 75 MHz fPCLKPROG Programmed PPI Clock When Receiving Data or Frame Sync 45 MHz fPCLKEXT ≤ fSCLK1 75 MHz fPCLKEXT ≤ fSCLK1 45 MHz 150 MHz fPCLKEXT External PPI Clock When Receiving Data and Frame Sync fPCLKEXT External PPI Clock Transmitting Data or Frame Sync4, 5 fLCLKTPROG Programmed Link Port Transmit Clock fLCLKREXT External Link Port Receive Clock 4, 5 4, 5 150 MHz fSPTCLKPROG Programmed SPT Clock When Transmitting Data and Frame Sync fLCLKEXT ≤ fCLKO8 56.25 MHz fSPTCLKPROG Programmed SPT Clock When Receiving Data or Frame Sync 28.125 MHz 4, 5 fSPTCLKEXT External SPT Clock When Receiving Data and Frame Sync fSPTCLKEXT External SPT Clock Transmitting Data or Frame Sync4, 5 fSPTCLKEXT ≤ fSCLK0 56.25 MHz fSPTCLKEXT ≤ fSCLK0 28.125 MHz fSPICLKPROG Programmed SPI Clock When Transmitting Data 75 MHz fSPICLKPROG Programmed SPI Clock When Receiving Data 75 MHz fSPICLKEXT External SPI Clock When Receiving Data4, 5 fSPICLKEXT ≤ fSCLK1 75 MHz fSPICLKEXT External SPI Clock When Transmitting Data4, 5 fSPICLKEXT ≤ fSCLK1 45 MHz fACLKPROG Programmed ACM Clock 56.25 MHz 1 The minimum frequency for SCLK0 applies only when the USB is used. SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due to the dependency on these factors the measured jitter may be higher or lower than this typical specification for each end application. 3 The value in the Typ field is the percentage of the SYS_CLKOUT period. 4 The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the AC timing specifications section for that peripheral. Pay particular attention to setup and hold times for VDD_EXT = 1.8 V which may preclude the maximum frequency listed here. 5 The peripheral external clock frequency must also be less than or equal to the fSCLK (fSCLK0 or fSCLK1) that clocks the peripheral. 2 Rev. PrF | Page 81 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 29. Phase-Locked Loop Operating Conditions Parameter fPLLCLK Min 250 PLL Clock Frequency CSEL (1-31) SYSSEL (1-31) SYS_CLKIN PLL CCLK S0SEL (1-7) SCLK0 S1SEL (1-7) SCLK1 SYSCLK PLLCLK DSEL (1-31) DCLK OSEL (1-127) OUTCLK Figure 8. Clock Relationships and Divider Values Rev. PrF | Page 82 of 168 | February 2016 Max 900 Unit MHz Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ELECTRICAL CHARACTERISTICS 450 MHz Parameter1 2 VOH 2 VOL VOH_DDR24 VOL_DDR24 VOH_DDR24 VOL_DDR24 VOH_DDR35 VOL_DDR35 VOH_DDR35 VOL_DDR35 VOH_LPDDR6 VOL_LPDDR6 IIH7, 8 IIL7 IIL_PU8 IIH_PD9 IOZH10 IOZL10 IDD_INT11 CIN12 IDD_IDLE Description Test Conditions/Comments Min 3 High Level Output Voltage Low Level Output Voltage High Level Output Voltage for DDR2 DS = 40 ohm Low Level Output Voltage for DDR2 DS = 40 ohm High Level Output Voltage for DDR2 DS = 60 ohm Low Level Output Voltage for DDR2 DS = 60 ohm High Level Output Voltage for DDR3 DS = 40 ohm Low Level Output Voltage for DDR3 DS = 60 ohm @ VDD_EXT = Min, IOH = –1.0 mA @ VDD_EXT = Min, IOL = 1.0 mA3 @ VDD_DDR = Min, IOH = –7.0 mA High Level Output Voltage for DDR3 DS = 60 ohm Low Level Output Voltage for DDR3 DS = 60 ohm High Level Output Voltage for LPDDR Low Level Output Voltage for LPDDR High Level Input Current @ VDD_DDR = Min, IOH = –5.0 mA Low Level Input Current Low Level Input Current Pull-up High Level Input Current Pull-down Three-State Leakage Current Three-State Leakage Current Supply Current (Internal) Input Capacitance VDD_INT Current in Idle Typ 0.32 V 1.38 V 0.32 1.105 V V @ VDD_DDR = Min, IOL = 5.0 mA 0.32 1.105 V V @ VDD_DDR = Min, IOL = 5.0 mA @ VDD_DDR = Min, IOH = –9.0 mA 0.4 V V V 1.38 @ VDD_DDR = Min, IOL = 5.0 mA @ VDD_DDR = Min, IOH = –7.0 mA Unit 2.4 @ VDD_DDR = Min, IOL = 7.0 mA @ VDD_DDR = Min, IOH = –5.0 mA Max 0.32 1.38 V V @ VDD_DDR = Min, IOL = 9.0 mA 0.32 V @ VDD_EXT = Max, VIN = VDD_EXT Max @ VDD_EXT = Max, VIN = 0 V @ VDD_EXT = Max, VIN = 0 V 10 μA 10 200 μA μA @ VDD_EXT = Max, VIN = 0 V 200 μA @ VDD_EXT/VDD_DDR = Max, VIN = VDD_EXT/VDD_DDR Max @ VDD_EXT/VDD_DDR = Max, VIN = 0 V fCCLK > 0 MHz TCASE = 25°C fCCLK = 450 MHz ASFSHARC1 = 0.27 ASFSHARC2 = 0.27 ASFA5 = 0.07 fSYSCLK = 225 MHz fSCLK0/1 = 112.5 MHz (Other clocks are disabled) No Peripheral or DMA activity TJ = 25°C VDD_INT = 1.1 V 10 μA 10 μA TBD 5 mA pF Rev. PrF | Page 83 of 168 | February 2016 435 mA ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data 450 MHz Parameter1 Description Test Conditions/Comments IDD_TYP VDD_INT Current IDD_INT VDD_INT Current fCCLK = 450 MHz ASFSHARC1 = 1.0 ASFSHARC2 = 1.0 ASFA5 = 0.64 fSYSCLK = 225 MHz fSCLK0/1 = 112.5 MHz (Other clocks are disabled) FFT accelerator operating at fSYSCLK/4 DMA data rate = 500 MB/s TJ = 25°C VDD_INT = 1.1 V fCCLK 0 MHz fSCLK0/1 0 MHz Min 1 Typ Max 1100 Unit mA See IDDINT_TOT equation mA Specifications subject to change without notice. Applies to all output and bidirectional pins except TWI, DMC, USB, PCIe, and MLB. 3 See Output Drive Currents for typical drive current capabilities. 4 Applies to all DMC output and bidirectional signals in DDR2 mode. 5 Applies to all DMC output and bidirectional signals in DDR3 mode. 6 Applies to all DMC output and bidirectional signals in LPDDR mode. 7 Applies to input pins: SYS_BMODE0-2, SYS_CLKIN0, SYS_CLKIN1, SYS_HWRST, JTG_TDI, JTG_TMS, and USB0_CLKIN. 8 Applies to input pins with internal pull-ups: JTG_TDI, JTG_TMS, and JTG_TCK. 9 Applies to signals: JTAG_TRST, USB0_VBUS, USB1_VBUS. 10 Applies to signals: PA0-15, PB0-15, PC0-15, PD0-15, PE0-15, PF0-15, PG0-5, DAI0_PINx, DAI1_PINx, DMC0_DQx, DMC0_LDQS, DMC0_UDQS, DMC0_LDQS, DMC0_UDQS, SYS_FAULT, SYS_FAULT, JTG_TDO, USB0_ID, USBx_DM, USBx_DP, and USBx_VBC. 11 See Engineer-to-Engineer Note EE-TBD “Estimating Power Dissipation for ADSP-215xx SHARC Processors” for further information. 12 Applies to all signal pins. 2 Rev. PrF | Page 84 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Total Internal Power Dissipation Application-Dependent Current Total power dissipation has two components: The application-dependent currents include the dynamic current in the core clock domain of the two SHARC+ cores and the ARM Cortex-A5 core and accelerator currents. 1. Static, including leakage current 2. Dynamic, due to transistor switching characteristics for each clock domain Many operating conditions can also affect power dissipation, including temperature, voltage, operating frequency, and processor activity. The following equation describes the internal current consumption. IDDINT_TOT = IDDINT_STATIC + IDDINT_CCLK_SHARC1_DYN + IDDINT_CCLK_SHARC2_DYN + IDDINT_CCLK_A5_DYN + IDDINT_DCLK_DYN + IDDINT_SYSCLK_DYN + IDDINT_SCLK0_DYN + IDDINT_SCLK1_DYN + IDDINT_OCLK_DYN + IDDINT_ACCL_DYN + IDDINT_USB_DYN + IDDINT_MLB_DYN + IDDINT_GIGE_DYN + IDDINT_DMA_DR_DYN IDDINT_STATIC is the only item present that is part of the static power dissipation component. IDDINT_STATIC is specified as a function of voltage (VDD_INT) and temperature (see Table 30). There are 13 different items that contribute to the dynamic power dissipation. These components fall into four broad categories: application-dependent currents, clock currents, currents from high-speed peripheral operation, and data transmission currents. Table 30. Static Current—IDDINT_STATIC (mA) Core clock (CCLK) use is subject to an activity scaling factor (ASF) that represents application code running on the processor cores (Table 31 andTable 32). The ASF is combined with the CCLK frequency and VDD_INT dependent data in Table 33 to calculate this portion. IDDINT_CCLK_SHARC1_DYN = Table 33 × ASFSHARC1 IDDINT_CCLK_SHARC2_DYN = Table 33 × ASFSHARC2 IDDINT_CCLK_A5_DYN = Table 34 × ASFA5 Table 31. Activity Scaling Factors for SHARC+ Core1 and Core2 (ASFSHARC1 and ASFSHARC2) IDDINT Power Vector ASF IDD-IDLE 0.27 IDD-NOP 0.51 IDD-TYP_3070 0.72 IDD-TYP_5050 0.86 IDD-TYP_7030 1.00 IDD-PEAK_100 1.13 Table 32. Activity Scaling Factors for ARM Cortex-A5 Core (ASFA5) –40 1.00 3 Voltage (VDD_INT) 1.05 1.10 1.15 4 5 6 –20 7 8 10 12 14 0 14 16 19 23 27 25 30 35 41 48 56 40 48 55 64 74 86 55 73 84 97 112 128 70 111 127 145 166 189 85 166 188 213 242 275 fCCLK (MHz) 100 239 269 304 343 388 105 268 302 340 384 115 337 378 425 125 426 477 534 133 502 560 625 TJ (°C) 1.20 8 IDDINT Power Vector ASF IDD-IDLE 0.07 IDD-DHRYSTONE 0.64 IDD-PEAK 1.26 Table 33. CCLK Dynamic Current per SHARC+ Core (mA, with ASF = 1.00) 450 1.000 288 Voltage (VDD_INT) 1.050 1.100 1.150 302.4 316.8 331.2 1.200 345.6 433 400 256 268.8 281.6 294.4 307.2 478 538 350 224 235.2 246.4 257.6 268.8 599 672 300 192 201.6 211.2 220.8 230.4 700 784 250 160 168 176 184 192 200 128 134.4 140.8 147.2 153.6 150 96 100.8 105.6 110.4 115.2 100 64 67.2 70.4 73.6 76.8 Rev. PrF | Page 85 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 34. CCLK Dynamic Current per ARM Cortex-A5 Core (mA, with ASF = 1.00) Current from High Speed Peripheral Operation The following modules contribute significantly to power dissipation and a single term is added when they are used. 450 1.000 49.5 Voltage (VDD_INT) 1.050 1.100 1.150 52.0 54.5 56.9 1.200 59.4 400 44.0 46.2 48.4 50.6 52.8 350 38.5 40.4 42.4 44.3 46.2 300 33.0 34.7 36.3 38.0 39.6 250 27.5 28.9 30.3 31.6 33.0 200 22.0 23.1 24.2 25.3 26.4 150 16.5 17.3 18.2 19.0 19.8 100 11.0 11.6 12.1 12.7 13.2 fCCLK (MHz) IDDINT_USB_DYN = 20 mA (if USB enabled) IDDINT_MLB_DYN = 10 mA (if MLB 6-pin interface is enabled) IDDINT_GIGE_DYN = 10 mA (if Gigabit Ethernet MAC controller is enabled) Data Transmission Current The data transmission current represents the power dissipated when transmitting data. This current is proportional to the data rate. Refer to the power calculator of this product to estimate IDDINT_DMA_DR_DYN based on the bandwidth of the data transfer. The following equation is used to compute the power dissipation when the FFT accelerator is used: IDDINT_ACCL_DYN (mA) = ASFACCL × fSYSCLK (MHz) × VDD_INT (V) Table 35. Activity Scaling Factors for FFT Accelerator (ASFA5) IDDINT Power Vector ASFACCL Unused 0.0 IDD-TYPP 0.4 Clock Current The dynamic clock currents provide the total power dissipated by all transistors switching in the clock paths. The power dissipated by each clock domain is dependent on voltage (VDD_INT), operating frequency and a unique scaling factor. IDDINT_SYSCLK_DYN (mA) = 0.80 × fSYSCLK (MHz) × VDD_INT (V) IDDINT_SCLK0_DYN (mA) = 0.40 × fSCLK0 (MHz) × VDD_INT (V) IDDINT_SCLK1_DYN (mA) = 0.04 × fSCLK1 (MHz) × VDD_INT (V) IDDINT_DCLK_DYN (mA) = 0.14 × fDCLK (MHz) × VDD_INT (V) IDDINT_OCLK_DYN (mA) = 0.005 × fOCLK (MHz) × VDD_INT (V) Rev. PrF | Preliminary Technical Data Page 86 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ABSOLUTE MAXIMUM RATINGS ESD SENSITIVITY Stresses at or above those listed in Table 36 may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Table 36. Absolute Maximum Ratings Parameter Internal (Core) Supply Voltage (VDD_INT) External (I/O) Supply Voltage (VDD_EXT) DDR2/LPDDR Controller Supply Voltage (VDD_DMC) DDR3 Controller Supply Voltage (VDD_DMC) USB PHY Supply Voltage (VDD_USB) Real Time Clock Supply Voltage (VDD_RTC) PCIe Transmit Supply Voltage (VDD_PCIE_TX) PCIe Receive Supply Voltage (VDD_PCIE_RX) PCIe Supply Voltage (VDD_PCIE) HADC Supply Voltage (VDD_HADC) HADC Reference Voltage (VHADC_REF) DDR2/LPDDR Input Voltage DDR3 Input Voltage Input Voltage Output Voltage Swing Storage Temperature Range Junction Temperature While Biased PACKAGE INFORMATION Rating –0.33 V to +1.20 V –0.33 V to +3.60 V The information presented in Figure 9 and Table 38 provides details about the package branding for the processors. For a complete listing of product availability, see Pre Release Products on Page 167. –0.33 V to +1.90 V –0.33 V to +1.60 V –0.33 V to +3.60 V –0.33 V to +3.60 V a ADSP-SC589 –0.33 V to +1.20 V tppZccc vvvvvv.x n.n –0.33 V to +1.20 V #yyww country_of_origin –0.33 V to +3.60 V –0.33 V to +3.60 V –0.33 V to +3.60 V –0.33 V to +1.90 V –0.33 V to +1.60 V –0.33 V to +3.60 V –0.33 V to VDD_EXT +0.5 V –65C to +150C 133C Figure 9. Product Information on Package1 1 Table 38. Package Brand Information Brand Key ADSP-SC589 t pp Z ccc vvvvvv.x n.n # yyww Table 37. Max Duty Cycle for Input Transient Voltage1, 2 Maximum Duty Cycle (%)2 100 50 40 25 20 15 10 VIN Min (V)3 TBD TBD TBD TBD TBD TBD TBD VIN Max (V)3 TBD TBD TBD TBD TBD TBD TBD Exact brand may differ, depending on package type. 1 See available products in Pre Release Products. 1 Applies to all signal balls with the exception of SYS_CLKIN0, SYS_CLKIN1, SYS_XTAL0, SYS_XTAL1, and all the USB, TWI, PCI, and DMC0 signals. 2 Applies only when VDD_EXT is within specifications. When VDD_EXT is outside specifications, the range is VDD_EXT ± 0.2 V. 3 The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of the specified voltages, and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. Rev. PrF | Field Description Product Name1 Temperature Range Package Type RoHS Compliant Option See Ordering Guide Assembly Lot Code Silicon Revision RoHS Compliant Designation Date Code Page 87 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data TIMING SPECIFICATIONS Specifications are subject to change without notice. Power-Up Reset Timing Table 39 and Figure 10 show the relationship between power supply startup and processor reset timing, related to the clock generation unit (CGU) and reset control unit (RCU). In Figure 10, VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, VDD_HADC, VDD_RTC, VDD_PCI_TX, VDD_PCI_RX, and VDD_PCI_CORE. Table 39. Power-Up Reset Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirement tRST_IN_PWR SYS_HWRST Deasserted after VDD_SUPPLIES (VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, 11 × tCKIN VDD_HADC, VDD_RTC, VDD_PCI_TX, VDD_PCI_RX, VDD_PCI_CORE) and SYS_CLKIN are Stable and within Specification SYS_HWRST tRST_IN_PWR SYS_CLKIN0/1 V DD_SUPPLIES NOTE: V REFER TO V ,V ,V ,V ,V ,V ,V ,V , AND V . DD_SUPPLIES DD_INT DD_EXT DD_DMC DD_USB DD_HADC DD_RTC DD_PCI_TX DD_PCI_RX DD_PCI_CORE Figure 10. Power-Up Reset Timing Rev. PrF | Page 88 of 168 | February 2016 ns Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Clock and Reset Timing Table 40 and Figure 11 describe clock and reset operations related to the clock generation unit (CGU) and reset control unit (RCU). Per the CCLK, SYSCLK, SCLK, DCLK, and OCLK timing specifications in Table 28 in Clock Related Operating Conditions on Page 81, combinations of SYS_CLKIN and clock multipliers must not select clock rates in excess of the processor’s maximum instruction rate. Table 40. Clock and Reset Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit SYS_CLKIN Frequency (Crystal)1, 2, 3 20 50 MHz SYS_CLKIN Frequency (External CLKIN)1, 2, 3 20 50 MHz Timing Requirements fCKIN 1 tCKINL CLKIN Low Pulse tCKINH CLKIN High Pulse1 tWRST RESET Asserted Pulse Width Low 4 10 ns 10 ns 11 × tCKIN ns 1 Applies to PLL bypass mode and PLL non bypass mode. The tCKIN period (see Figure 11) equals 1/fCKIN. 3 If the CGU_CTL.DF bit is set, the minimum fCKIN specification is 40 MHz. 4 Applies after power-up sequence is complete. See Table 39 and Figure 10 for power-up reset timing. 2 fCKIN SYS_CLKIN0/1 tCKINL tCKINH tWRST SYS_HWRST Figure 11. Clock and Reset Timing Rev. PrF | Page 89 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Asynchronous Read Table 41 and Figure 12 show asynchronous memory read timing, related to the static memory controller (SMC). Table 41. Asynchronous Memory Read All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSDATARE DATA in Setup Before SMC0_ARE High 5.1 tHDATARE DATA in Hold After SMC0_ARE High 0.7 tDARDYARE SMC0_ARDY Valid After SMC0_ARE Low1, 2 ns ns (RAT – 2.5) × tSCLK0 – 17.5 ns Switching Characteristics tAMSARE ADDR/SMC0_AMSx Assertion Before SMC0_ARE (PREST + RST + PREAT) × tSCLK0 – 2 Low3 ns tAOEARE SMC0_AOE Assertion Before SMC0_ARE Low (RST + PREAT) × tSCLK0 – 2 ns tHARE Output4 Hold After SMC0_ARE High5 RHT × tSCLK0 –2 ns RAT × tSCLK0 – 2 ns 6 tWARE SMC0_ARE Active Low Width tDAREARDY SMC0_ARE High Delay After SMC0_ARDY Assertion1 2.5 × tSCLK0 3.5 × tSCLK0 + 17.5 1 SMC0_BxCTL.ARDYEN bit = 1. RAT value set using the SMC_BxTIM.RAT bits. 3 PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits. 4 Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE, SMC0_ABEx. 5 RHT value set using the SMC_BxTIM.RHT bits. 6 SMC0_BxCTL.ARDYEN bit = 0. 2 SMC0_ARE SMC0_AMSx tWARE tHARE tAMSARE SMC0_Ax tAOEARE SMC0_AOE tDARDYARE tDAREARDY SMC0_ARDY tSDATARE SMC0_Dx (DATA) Figure 12. Asynchronous Read Rev. PrF | Page 90 of 168 | February 2016 tHDATARE ns Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Asynchronous Flash Read Table 42 and Figure 13 show asynchronous flash memory read timing, related to the static memory controller (SMC). Table 42. Asynchronous Flash Read All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Switching Characteristics tAMSADV SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV Low1 PREST × tSCLK0 – 2 tWADV SMC0_NORDV Active Low Width2 RST × tSCLK0 – 2 ns tDADVARE SMC0_ARE Low Delay From SMC0_NORDV High3 PREAT × tSCLK0 – 2 ns tHARE Output4 Hold After SMC0_ARE High5 RHT × tSCLK0 – 2 ns SMC0_ARE Active Low Width7 RAT × tSCLK0 – 2 ns 6 tWARE 1 PREST value set using the SMC_BxETIM.PREST bits. RST value set using the SMC_BxTIM.RST bits. 3 PREAT value set using the SMC_BxETIM.PREAT bits. 4 Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE. 5 RHT value set using the SMC_BxTIM.RHT bits. 6 SMC0_BxCTL.ARDYEN bit = 0. 7 RAT value set using the SMC_BxTIM.RAT bits. 2 SMC0_Ax (NOR_Ax) SMC0_AMSx (NOR_CE) tAMSADV tWADV SMC0_AOE (NOR_ADV) tDADVARE tWARE tHARE SMC0_ARE (NOR_OE) SMC0_Dx (NOR_Dx) READ LATCHED DATA Figure 13. Asynchronous Flash Read Rev. PrF | Page 91 of 168 | February 2016 ns ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Asynchronous Page Mode Read Table 43 and Figure 14 show asynchronous memory page mode read timing, related to the static memory controller (SMC). Table 43. Asynchronous Page Mode Read All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Switching Characteristics tAV SMC0_Ax (Address) Valid for First Address Min Width1 (PREST + RST + PREAT + RAT) × tSCLK0 – 2 ns tAV1 SMC0_Ax (Address) Valid for Subsequent SMC0_Ax (Address) Min Width PGWS × tSCLK0 – 2 ns tWADV SMC0_NORDV Active Low Width2 RST × tSCLK0 – 2 ns 3 tHARE Output Hold After SMC0_ARE High tWARE5 SMC0_ARE Active Low Width6, 7 4 RHT × tSCLK0 – 2 ns (RAT + (Nw – 1) × PGWS) × tSCLK0 – 2 ns 1 PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits. RST value set using the SMC_BxTIM.RST bits. 3 Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE. 4 RHT value set using the SMC_BxTIM.RHT bits. 5 SMC_BxCTL.ARDYEN bit = 0. 6 RAT value set using the SMC_BxTIM.RAT bits. 7 Nw = Number of 16-bit data words read. 2 READ LATCHED DATA SMC0_Ax (NOR_Ax) READ LATCHED DATA READ LATCHED DATA READ LATCHED DATA tAV tAV1 tAV1 tAV1 A0 A0 + 1 A0 + 2 A0 + 3 SMC0_AMSx (NOR_CE) SMC0_AOE NOR_ADV tWADV tWARE SMC0_ARE (NOR_OE) tHARE SMC0_Dx (NOR_Dx) D0 D1 Figure 14. Asynchronous Page Mode Read Rev. PrF | Page 92 of 168 | February 2016 D2 D3 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Asynchronous Write Table 44 and Figure 15 show asynchronous memory write timing, related to the static memory controller (SMC). Table 44. Asynchronous Memory Write All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit (WAT – 2.5) × tSCLK0 – 17.5 ns Timing Requirement tDARDYAWE1 SMC0_ARDY Valid After SMC0_AWE Low 2 Switching Characteristics tENDAT DATA Enable After SMC0_AMSx Assertion –3.5 tDDAT DATA Disable After SMC0_AMSx Deassertion ns 2.5 3 ns tAMSAWE ADDR/SMC0_AMSx Assertion Before SMC0_AWE Low (PREST + WST + PREAT) × tSCLK0 – 2 ns tHAWE Output4 Hold After SMC0_AWE High5 ns tWAWE 6 SMC0_AWE Active Low Width tDAWEARDY1 WHT × tSCLK0 – 3.5 2 WAT × tSCLK0 – 2 SMC0_AWE High Delay After SMC0_ARDY Assertion ns 2.5 × tSCLK0 3.5 × tSCLK0 + 17.5 1 SMC_BxCTL.ARDYEN bit = 1. WAT value set using the SMC_BxTIM.WAT bits. 3 PREST, WST, PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.WST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits. 4 Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx. 5 WHT value set using the SMC_BxTIM.WHT bits. 6 SMC_BxCTL.ARDYEN bit = 0. 2 SMC0_AWE SMC0_ABEx SMC0_Ax (ADDRESS) tAMSAWE tWAWE tHAWE SMC0_ARDY tDARDYAWE tDAWEARDY SMC0_AMSx SMC0_Dx (DATA) tDDAT tENDAT Figure 15. Asynchronous Write Rev. PrF | Page 93 of 168 | February 2016 ns ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Asynchronous Flash Write Table 45 and Figure 16 show asynchronous flash memory write timing, related to the static memory controller (SMC). Table 45. Asynchronous Flash Write All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Switching Characteristics tAMSADV SMC0_Ax/SMC0_AMSx Assertion Before ADV Low1 tDADVAWE SMC0_AWE Low Delay From ADV High tWADV NR_ADV Active Low Width3 tHAWE Output4 Hold After SMC0_AWE High5 tWAWE 6 SMC0_AWE Active Low Width PREST × tSCLK0 – 2 2 7 ns PREAT × tSCLK0 – 2 ns WST × tSCLK0 – 2 ns WHT × tSCLK0 – 3.5 ns WAT × tSCLK0 – 2 ns 1 PREST value set using the SMC_BxETIM.PREST bits. 2 PREAT value set using the SMC_BxETIM.PREAT bits. 3 WST value set using the SMC_BxTIM.WST bits. 4 Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx. 5 WHT value set using the SMC_BxTIM.WHT bits. 6 SMC_BxCTL.ARDYEN bit = 0. 7 WAT value set using the SMC_BxTIM.WAT bits. NOR_A 25-1 (SMC0_Ax) NOR_CE (SMC0_AMSx) tAMSADV tWADV NOR_ADV (SMC0_AOE) tWAWE tDADVAWE tHAWE NOR_WE (SMC0_AWE) NOR_DQ 15-0 (SMC0_Dx) Figure 16. Asynchronous Flash Write All Accesses Table 46 describes timing that applies to all memory accesses, related to the static memory controller (SMC). Table 46. All Accesses All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Switching Characteristic tTURN SMC0_AMSx Inactive Width (IT + TT) × tSCLK0 – 2 Rev. PrF | Page 94 of 168 | February 2016 ns Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 DDR2 SDRAM Clock and Control Cycle Timing Table 47 and Figure 17 show DDR2 SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC). Table 47. DDR2 SDRAM Clock and Control Cycle Timing, VDD_DMCx Nominal 1.8 V1 All specifications are based on simulation data and are subject to change without notice. 400 MHz2 Parameter Min Max Unit Switching Characteristics 1 2 tCK Clock Cycle Time (CL = 2 Not Supported) 2.5 tCH Minimum Clock Pulse Width 0.48 0.52 ns tCK tCL Maximum Clock Pulse Width 0.48 0.52 tCK tIS Control/Address Setup Relative to DMCx_CK Rise 175 ps tIH Control/Address Hold Relative to DMCx_CK Rise 250 ps Specifications apply to both DMC0 and DMC1. In order to ensure proper operation of the DDR2, all the DDR2 guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD). tCK tCH tCL DMCx_CK DMCx_CK tIS tIH DMCx_Ax DMCx CONTROL NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE. ADDRESS = DMCx_A0-A15, AND DMCx_BA0-BA2. Figure 17. DDR2 SDRAM Clock and Control Cycle Timing Rev. PrF | Page 95 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data DDR2 SDRAM Read Cycle Timing Table 48 and Figure 18 show DDR2 SDRAM read cycle timing, related to the dynamic memory controller (DMC). Table 48. DDR2 SDRAM Read Cycle Timing, VDD_DMCx Nominal 1.8 V1 All specifications are based on simulation data and are subject to change without notice. 400 MHz2 Parameter Min Max Unit 0.2 ns Timing Requirements 1 2 tDQSQ DMCx_DQS-DMCx_DQ Skew for DMCx_DQS and Associated DMCx_DQ Signals tQH DMCx_DQ, DMCx_DQS Output Hold Time From DMCx_DQS 0.9 ns tRPRE Read Preamble 0.9 tCK tRPST Read Postamble 0.4 tCK Specifications apply to both DMC0 and DMC1. In order to ensure proper operation of the DDR2, all the DDR2 guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD). tCK tCH tCL DMCx_CKx DMCx_CKx DMCx_Ax DMCx CONTROL tRPRE DMCx_LDQS/DMCx_UDQS DMCx_LDQS/DMCx_UDQS tDQSQ tDQSQ tRPST tQH tQH DMCx_DQx NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE. ADDRESS = DMCx_A00-13, AND DMCx_BA0-1. Figure 18. DDR2 SDRAM Controller Input AC Timing Rev. PrF | Page 96 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 DDR2 SDRAM Write Cycle Timing Table 49 and Figure 19 show DDR2 SDRAM write cycle timing, related to the dynamic memory controller (DMC). Table 49. DDR2 SDRAM Write Cycle Timing, VDD_DMCx Nominal 1.8 V1 All specifications are based on simulation data and are subject to change without notice. 400 MHz2 Parameter Min Max 0.15 Unit Switching Characteristics tDQSS DMCx_DQS Latching Rising Transitions to Associated Clock Edges3 –0.15 tDS Last Data Valid to DMCx_DQS Delay 0.1 ns tDH DMCx_DQS to First Data Invalid Delay 0.15 ns tCK tDSS DMCx_DQS Falling Edge to Clock Setup Time 0.2 tCK tDSH DMCx_DQS Falling Edge Hold Time From DMCx_CK 0.2 tCK tDQSH DMCx_DQS Input High Pulse Width 0.35 tCK tDQSL DMCx_DQS Input Low Pulse Width 0.35 tCK tWPRE Write Preamble 0.35 tCK tWPST Write Postamble 0.4 tCK tIPW Address and Control Output Pulse Width 0.6 tCK tDIPW DMCx_DQ and DMCx_DM Output Pulse Width 0.35 tCK 1 Specifications apply to both DMC0 and DMC1. In order to ensure proper operation of the DDR2, all the DDR2 guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD). 3 Write command to first DMCx_DQS delay = WL × tCK + tDQSS. 2 DMCx_CK DMCx_CK tIPW DMCx_Ax DMCx CONTROL tDSH tDSS tDQSS DMCx_LDQS/DMCx_UDQS DMCx_LDQS/DMCx_UDQS DMC0_DQSn DMC0_DQSn tWPRE tDQSL tDS tDH tDQSH tDIPW DMCx_LDM DMCx_UDM DMCx_DQx NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE. ADDRESS = DMCx_A00-13, AND DMCx_BA0-1. Figure 19. DDR2 SDRAM Controller Output AC Timing Rev. PrF | Page 97 of 168 | February 2016 tWPST ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Table 50 and Figure 20 show mobile DDR SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC). Table 50. Mobile DDR SDRAM Clock and Control Cycle Timing, VDD_DMCx Nominal 1.8 V1 All specifications are based on simulation data and are subject to change without notice. 200 MHz2 Parameter Min Max Unit Switching Characteristics 1 2 tCK Clock Cycle Time (CL = 2 Not Supported) 5 tCH Minimum Clock Pulse Width 0.45 0.55 ns tCK tCL Maximum Clock Pulse Width 0.45 0.55 tCK tIS Control/Address Setup Relative to DMCx_CK Rise 1 ns tIH Control/Address Hold Relative to DMCx_CK Rise 1 ns Specifications apply to both DMC0 and DMC1. In order to ensure proper operation of LPDDR, all the LPDDR guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD). tCK tCH tCL DMCx_CK DMCx_CK tIS tIH DMCx_Ax DMCx CONTROL NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE. ADDRESS = DMCx_A0-A15, AND DMCx_BA0-BA2. Figure 20. Mobile DDR SDRAM Clock and Control Cycle Timing Rev. PrF | Page 98 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Mobile DDR SDRAM Read Cycle Timing Table 51 and Figure 21 show mobile DDR SDRAM read cycle timing, related to the dynamic memory controller (DMC). Table 51. Mobile DDR SDRAM Read Cycle Timing, VDD_DMCx Nominal 1.8 V1 All specifications are based on simulation data and are subject to change without notice. 200 MHz2 Parameter Min Max Unit 0.4 ns Timing Requirements 1 2 tQH DMCx_DQ, DMCx_DQS Output Hold Time From DMCx_DQS tDQSQ DMCx_DQS-DMCx_DQ Skew for DMCx_DQS and Associated DMCx_DQ Signals 1.75 ns tRPRE Read Preamble 0.9 1.1 tCK tRPST Read Postamble 0.4 0.6 tCK Specifications apply to both DMC0 and DMC1. In order to ensure proper operation of LPDDR, all the LPDDR guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD). DMCx_CK tRPRE tRPST DMCx_LDQS/DMCx_HDQS tQH DMCx_DQx (DATA) Dn Dn+1 Dn+2 tDQSQ Figure 21. Mobile DDR SDRAM Controller Input AC Timing Rev. PrF | Page 99 of 168 | February 2016 Dn+3 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Mobile DDR SDRAM Write Cycle Timing Table 52 and Figure 22 show mobile DDR SDRAM write cycle timing, related to the dynamic memory controller (DMC). Table 52. Mobile DDR SDRAM Write Cycle Timing, VDD_DMCx Nominal 1.8 V1 All specifications are based on simulation data and are subject to change without notice. 200 MHz2 Parameter Min Max 1.25 Unit Switching Characteristics tDQSS3 DMCx_DQS Latching Rising Transitions to Associated Clock Edges 0.75 tDS Last Data Valid to DMCx_DQS Delay (Slew > 1 V/ns) 0.48 ns tDH DMCx_DQS to First Data Invalid Delay (Slew > 1 V/ns) 0.48 ns tDSS DMCx_DQS Falling Edge to Clock Setup Time 0.2 tCK tDSH DMCx_DQS Falling Edge Hold Time From DMCx_CK 0.2 tCK tDQSH DMCx_DQS Input High Pulse Width 0.4 tCK tDQSL DMCx_DQS Input Low Pulse Width 0.4 tCK tWPRE Write Preamble 0.25 tCK tWPST Write Postamble 0.4 tCK tIPW Address and Control Output Pulse Width 2.3 ns tDIPW DMCx_DQ and DMCx_DM Output Pulse Width 1.8 ns 1 Specifications apply to both DMC0 and DMC1. In order to ensure proper operation of LPDDR, all the LPDDR guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD). 3 Write command to first DMCx_DQS delay = WL × tCK + tDQSS. 2 DMCx_CK tDSS tDSH tDQSS DMCx_LDQS/DMCx_HDQS tWPRE tDS tDQSL tDH tDQSH tWPST tDIPW DMCx_DQ0-15/ DMCx_LDQM/DMCx_HDQM Dn Dn+1 Dn+2 Dn+3 tDIPW DMCx CONTROL Write CMD NOTE: CONTROL = DMCx_CSx, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE. ADDRESS = DMCx_A00-13, AND DMCx_BA0-1. tIPW Figure 22. Mobile DDR SDRAM Controller Output AC Timing Rev. PrF | Page 100 of 168 | February 2016 tCK Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 DDR3 SDRAM Clock and Control Cycle Timing Table 53 and Figure 23 show mobile DDR3 SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC). Table 53. DDR3 SDRAM Clock and Control Cycle Timing VDD_DMCx Nominal 1.5 V1 All specifications are based on simulation data and are subject to change without notice. 450 MHz2 Parameter Min Max Unit Timing Requirements 1 2 tCK Clock Cycle Time (CL = 2 Not Supported) 2.22 tCH Minimum Clock Pulse Width 0.47 0.53 ns tCK tCL Maximum Clock Pulse Width 0.47 0.53 tCK tIS Control/Address Setup Relative to DMCx_CK Rise 0.2 ns tIH Control/Address Hold Relative to DMCx_CK Rise 0.275 ns Specifications apply to both DMC0 and DMC1. In order to ensure proper operation of the DDR3, all the DDR3 guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD). tCK tCH tCL DMCx_CK DMCx_CK tIS tIH DMCx_Ax DMCx CONTROL NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE. ADDRESS = DMCx_A0-A15, AND DMCx_BA0-BA2. Figure 23. DDR3 SDRAM Clock and Control Cycle Timing Rev. PrF | Page 101 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data DDR3 SDRAM Read Cycle Timing Table 54 and Figure 24 show mobile DDR3 SDRAM read cycle timing, related to the dynamic memory controller (DMC). Table 54. DDR3 SDRAM Read Cycle Timing VDD_DMCx Nominal 1.5 V1 All specifications are based on simulation data and are subject to change without notice. 450 MHz2 Parameter Min Max Unit 0.2 ns Timing Requirements 1 2 tDQSQ DMCx_DQS-DMCx_DQ Skew for DMCx_DQS and Associated DMCx_DQ Signals tQH DMCx_DQ, DMCx_DQS Output Hold Time From DMCx_DQS 0.38 tCK tRPRE Read Preamble 0.9 tCK tRPST Read Postamble 0.3 tCK Specifications apply to both DMC0 and DMC1. In order to ensure proper operation of the DDR3, all the DDR3 guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD). tCK tCH tCL DMCx_CKx DMCx_CKx DMCx_Ax DMCx CONTROL tRPRE DMCx_LDQS/DMCx_UDQS DMCx_LDQS/DMCx_UDQS tDQSQ tDQSQ tRPST tQH tQH DMCx_DQx NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE. ADDRESS = DMCx_A00-13, AND DMCx_BA0-1. Figure 24. DDR3 SDRAM Controller Input AC Timing Rev. PrF | Page 102 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 DDR3 SDRAM Write Cycle Timing Table 55 and Figure 25 show mobile DDR3 SDRAM output ac timing, related to the dynamic memory controller (DMC). Table 55. DDR3 SDRAM Write Cycle Timing VDD_DMCx Nominal 1.5 V1 All specifications are based on simulation data and are subject to change without notice. 450 MHz2 Parameter Min Max 0.25 Unit Switching Characteristics tDQSS DMCx_DQS Latching Rising Transitions to Associated Clock Edges3 –0.25 tDS Last Data Valid to DMCx_DQS Delay (Slew > 1 V/ns) 0.125 ns tDH DMCx_DQS to First Data Invalid Delay (Slew > 1 V/ns) 0.150 ns tDSS DMCx_DQS Falling Edge to Clock Setup Time 0.2 tCK tDSH DMCx_DQS Falling Edge Hold Time From DMCx_CK 0.2 tCK tDQSH DMCx_DQS Input High Pulse Width 0.45 0.55 tCK tDQSL DMCx_DQS Input Low Pulse Width 0.45 0.55 tCK tWPRE Write Preamble 0.9 tCK tWPST Write Postamble 0.3 tCK tIPW Address and Control Output Pulse Width 0.840 ns tDIPW DMCx_DQ and DMCx_DM Output Pulse Width 0.550 ns tCK 1 Specifications apply to both DMC0 and DMC1. In order to ensure proper operation of the DDR3, all the DDR3 guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD). 3 Write command to first DMCx_DQS delay = WL × tCK + tDQSS. 2 DMCx_CK DMCx_CK tIPW DMCx_Ax DMCx CONTROL tDSH tDSS tDQSS DMCx_LDQS/DMCx_UDQS DMCx_LDQS/DMCx_UDQS DMC0_DQSn DMC0_DQSn tDQSL tWPRE tDS tDH DMCx_LDM DMCx_UDM DMCx_DQx NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE. ADDRESS = DMCx_A00-13, AND DMCx_BA0-1. Figure 25. DDR3 SDRAM Controller Output AC Timing Rev. PrF | Page 103 of 168 | February 2016 tDQSH tDIPW tWPST ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Enhanced Parallel Peripheral Interface Timing The following tables and figures describe enhanced parallel peripheral interface (EPPI) timing operations. The POLC bits in the EPPI_CTL register may be used to set the sampling/driving edges of the EPPI clock. When internally generated, the programmed PPI clock (fPCLKPROG) frequency in MHz is set by the following equation where VALUE is a field in the EPPI_CLKDIV register that can be set from 0 to 65535: f SCLK0 f PCLKPROG = -------------------------- VALUE + 1 1 t PCLKPROG = ----------------f PCLKPROG When externally generated the EPPI_CLK is called fPCLKEXT: 1 t PCLKEXT = -------------f PCLKEXT Table 56. Enhanced Parallel Peripheral Interface—Internal Clock All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSFSPI External FS Setup Before EPPI_CLK 6.5 ns tHFSPI External FS Hold After EPPI_CLK 0 ns tSDRPI Receive Data Setup Before EPPI_CLK 6.5 ns tHDRPI Receive Data Hold After EPPI_CLK 0 ns tSFS3GI External FS3 Input Setup Before EPPI_CLK Fall Edge in Clock Gating Mode 14 ns tHFS3GI External FS3 Input Hold Before EPPI_CLK Fall Edge in Clock Gating Mode 0 ns Switching Characteristics 1 tPCLKW EPPI_CLK Width1 0.5 × tPCLKPROG – 1.5 ns tPCLK EPPI_CLK Period1 tPCLKPROG – 1.5 ns tDFSPI Internal FS Delay After EPPI_CLK tHOFSPI Internal FS Hold After EPPI_CLK tDDTPI Transmit Data Delay After EPPI_CLK tHDTPI Transmit Data Hold After EPPI_CLK 3.5 –0.5 ns 3.5 –0.5 See Table 28 in Clock Related Operating Conditions on Page 81 for details on the minimum period that may be programmed for tPCLKPROG. Rev. PrF | Page 104 of 168 | February 2016 ns ns ns ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data FRAME SYNC DRIVEN DATA SAMPLED POLC[1:0] = 10 EPPI_CLK POLC[1:0] = 01 tDFSPI tPCLKW tHOFSPI tPCLK EPPI_FS1/2 tSDRPI tHDRPI EPPI_D00-23 Figure 26. PPI Internal Clock GP Receive Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN DATA DRIVEN DATA DRIVEN tPCLK POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tDFSPI tPCLKW tHOFSPI EPPI_FS1/2 tHDTPI tDDTPI EPPI_D00-23 Figure 27. PPI Internal Clock GP Transmit Mode with Internal Frame Sync Timing DATA SAMPLED / FRAME SYNC SAMPLED DATA SAMPLED / FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPI tPCLKW tHFSPI tPCLK PPI_FS1/2 tSDRPI tHDRPI PPI_D00-23 Figure 28. PPI Internal Clock GP Receive Mode with External Frame Sync Timing Rev. PrF | Page 105 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data DATA DRIVEN / FRAME SYNC SAMPLED POLC[1:0] = 11 PPI_CLK POLC[1:0] = 00 tSFSPI tHFSPI tPCLKW tPCLK PPI_FS1/2 tDDTPI tHDTPI PPI_D00-23 Figure 29. PPI Internal Clock GP Transmit Mode with External Frame Sync Timing EPPI_CLK tHFS3GI tSFS3GI EPPI_FS3 Figure 30. Clock Gating Mode with Internal Clock and External Frame Sync Timing Table 57. Enhanced Parallel Peripheral Interface—External Clock All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tPCLKW EPPI_CLK Width1 1 0.5 × tPCLKEXT – 0.5 ns tPCLK EPPI_CLK Period tPCLKEXT – 1 ns tSFSPE External FS Setup Before EPPI_CLK 2 ns tHFSPE External FS Hold After EPPI_CLK 3.7 ns tSDRPE Receive Data Setup Before EPPI_CLK 2 ns tHDRPE Receive Data Hold After EPPI_CLK 3.7 ns Switching Characteristics 1 tDFSPE Internal FS Delay After EPPI_CLK 15.3 tHOFSPE Internal FS Hold After EPPI_CLK tDDTPE Transmit Data Delay After EPPI_CLK tHDTPE Transmit Data Hold After EPPI_CLK 2.4 ns 15.3 2.4 ns ns ns This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external EPPI_CLK ideal maximum frequency see the fPCLKEXT specification in Table 28 in Clock Related Operating Conditions on Page 81. Rev. PrF | Page 106 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data FRAME SYNC DRIVEN DATA SAMPLED POLC[1:0] = 10 EPPI_CLK POLC[1:0] = 01 tDFSPE tPCLKW tHOFSPE tPCLK EPPI_FS1/2 tSDRPE tHDRPE EPPI_D00-23 Figure 31. PPI External Clock GP Receive Mode with Internal Frame Sync Timing FRAME SYNC DRIVEN DATA DRIVEN DATA DRIVEN tPCLK POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tDFSPE tPCLKW tHOFSPE EPPI_FS1/2 tDDTPE tHDTPE EPPI_D00-23 Figure 32. PPI External Clock GP Transmit Mode with Internal Frame Sync Timing DATA SAMPLED / FRAME SYNC SAMPLED DATA SAMPLED / FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPE tPCLKW tHFSPE tPCLK EPPI_FS1/2 tSDRPE tHDRPE EPPI_D00-23 Figure 33. PPI External Clock GP Receive Mode with External Frame Sync Timing Rev. PrF | Page 107 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data DATA DRIVEN / FRAME SYNC SAMPLED POLC[1:0] = 11 EPPI_CLK POLC[1:0] = 00 tSFSPE tHFSPE tPCLKW tPCLK EPPI_FS1/2 tDDTPE tHDTPE EPPI_D00-23 Figure 34. PPI External Clock GP Transmit Mode with External Frame Sync Timing Rev. PrF | Page 108 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Link Ports In link port (LP) receive mode, the link port clock is supplied externally and is called fLCLKREXT: 1 t LCLKREXT = --------------f LCLKREXT In link port transmit mode, the programmed link port clock (fLCLKTPROG) frequency in MHz is set by the following equation where VALUE is a field in the LP_DIV register that can be set from 1 to 255: f CLKO8 f LCLKTPROG = -------------------------- VALUE 2 In the case where VALUE = 0, fLCLKTPROG = fCLKO8. For all settings of VALUE the following equation also holds: 1 t LCLKTPROG = -----------------f LCLKTPROG Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path length difference between LPx_Dx (data) and LPx_CLK. Setup skew is the maximum delay that can be introduced in LPx_Dx relative to LPx_CLK: (setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is the maximum delay that can be introduced in LPx_CLK relative to LPx_Dx: (hold skew = tLCLKTWL min – tHLDCH – tHLDCL). Table 58. Link Ports—Receive1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit 150 MHz Timing Requirements fLCLKREXT LPx_CLK Frequency tSLDCL Data Setup Before LPx_CLK Low 0.9 ns tHLDCL Data Hold After LPx_CLK Low 1.4 ns 2 tLCLKEW LPx_CLK Period tLCLKREXT – 0.42 ns tLCLKRWL LPx_CLK Width Low2 0.5 × tLCLKREXT ns tLCLKRWH LPx_CLK Width High2 0.5 × tLCLKREXT ns Switching Characteristic tDLALC LPx_ACK Low Delay After LPx_CLK Low3 1.5 × tCLKO8 + 4 1 2.5 × tCLKO8 + 12 ns Specifications apply to LP1 and LP2. This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LPx_CLK. For the external LPx_CLK ideal maximum frequency see the fLCLKTEXT specification in Table 28 in Clock Related Operating Conditions on Page 81. 3 LPx_ACK goes low with tDLALC relative to rise of LPx_CLK after first byte, but does not go low if the receiver's link buffer is not about to fill. 2 Rev. PrF | Page 109 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 tLCLKEW tLCLKRWH tLCLKRWL LPx_CLK tHLDCL tSLDCL LPx_D7–0 IN tDLALC LPx_ACK (OUT) Figure 35. Link Ports—Receive Rev. PrF | Page 110 of 168 | February 2016 Preliminary Technical Data Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 59. Link Ports—Transmit1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSLACH LPx_ACK Setup Before LPx_CLK Low 2 × tCLKO8 + 13.5 ns tHLACH LPx_ACK Hold After LPx_CLK Low –5.5 ns Switching Characteristics tDLDCH Data Delay After LPx_CLK High tHLDCH Data Hold After LPx_CLK High –0.8 LPx_CLK Width Low 0.33 × tLCLKTPROG 0.6 × tLCLKTPROG ns LPx_CLK Width High 0.45 × tLCLKTPROG 0.66 × tLCLKTPROG ns LPx_CLK Period N × tLCLKTPROG – 0.5 LPx_CLK Low Delay After LPx_ACK High tCLKO8 + 4 tLCLKTWL 2 tLCLKTWH2 tLCLKTW tDLACLK 1 2 2 1.6 ns ns ns 2 × tCLKO8 + 1 × tLPCLK + 10 Specifications apply to LP1 and LP2 See Table 28 in Clock Related Operating Conditions on Page 81 for details on the minimum period that may be programmed for tLCLKTPROG. tLCLKTWH LAST BYTE TRANSMITTED tLCLKTWL FIRST BYTE TRANSMITTED1 LPx_CLK tDLDCH tHLDCH LPx_Dx (DATA) OUT tSLACH tHLACH tDLACLK LPx_ACK (IN) NOTES The tSLACH and tHLACH specifications apply only to the LPx_CLK falling edge. If these specifications are met, LPx_CLK would extend and the dotted LPx_CLK falling edge would not occur as shown. The position of the dotted falling edge can be calculated using the tLCLKTWH specification. tLCLKTWH Min should be used for tSLACH and tLCLKTWH Max for tHLACH. Figure 36. Link Ports—Transmit Rev. PrF | Page 111 of 168 | February 2016 ns ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Serial Ports To determine whether serial port (SPORT) communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SPTx_CLK) width. In Figure 37 either the rising edge or the falling edge of SPTx_CLK (external or internal) can be used as the active sampling edge. When externally generated, the SPORT clock is called fSPTCLKEXT: 1 t SPTCLKEXT = -----------------------f SPTCLKEXT When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in MHz is set by the following equation where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65535: f SCLK0 f SPTCLKPROG = ------------------------------ CLKDIV + 1 1 t SPTCLKPROG = --------------------------f SPTCLKPROG Table 60. Serial Ports—External Clock1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSFSE Frame Sync Setup Before SPTx_CLK 2 (Externally Generated Frame Sync in either Transmit or Receive Mode)2 ns tHFSE Frame Sync Hold After SPTx_CLK 2.7 (Externally Generated Frame Sync in either Transmit or Receive Mode)2 ns tSDRE Receive Data Setup Before Receive SPTx_CLK2 2 ns 2.7 ns 0.5 × tSPTCLKEXT – 1.5 ns tSPTCLKEXT – 1.5 ns tHDRE Receive Data Hold After SPTx_CLK tSPTCLKW SPTx_CLK Width3 tSPTCLK SPTx_CLK Period 2 3 Switching Characteristics tDFSE Frame Sync Delay After SPTx_CLK (Internally Generated Frame Sync in either Transmit or Receive Mode)4 tHOFSE Frame Sync Hold After SPTx_CLK 2 (Internally Generated Frame Sync in either Transmit or Receive Mode)4 tDDTE Transmit Data Delay After Transmit SPTx_CLK4 tHDTE Transmit Data Hold After Transmit SPTx_CLK 4 14.5 ns 14 2 1 ns ns ns Specifications apply to all eight SPORTs. 2 Referenced to sample edge. 3 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPTx_CLK. For the external SPTx_CLK ideal maximum frequency see the fSPTCLKEXT specification in Table 28 in Clock Related Operating Conditions on Page 81. 4 Referenced to drive edge. Rev. PrF | Page 112 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Table 61. Serial Ports—Internal Clock1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSFSI tHFSI tSDRI tHDRI Frame Sync Setup Before SPTx_CLK (Externally Generated Frame Sync in either Transmit or Receive Mode)2 12 Frame Sync Hold After SPTx_CLK (Externally Generated Frame Sync in either Transmit or Receive Mode)2 –0.5 Receive Data Setup Before SPTx_CLK2 3.4 ns 1.5 ns Receive Data Hold After SPTx_CLK ns ns 2 Switching Characteristics tDFSI Frame Sync Delay After SPTx_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)3 tHOFSI Frame Sync Hold After SPTx_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)3 tDDTI Transmit Data Delay After SPTx_CLK3 tHDTI Transmit Data Hold After SPTx_CLK tSCLKIW SPTx_CLK Width4 tSPTCLK 4 SPTx_CLK Period 3.5 –2.5 ns 3.5 3 ns 0.5 × tSPTCLKPROG – 1.5 ns tSPTCLKPROG – 1.5 ns Specifications apply to all eight SPORTs. Referenced to the sample edge. 3 Referenced to drive edge. 4 See Table 28 in Clock Related Operating Conditions on Page 81 for details on the minimum period that may be programmed for tSPTCLKPROG. 2 | Page 113 of 168 | ns –2.5 1 Rev. PrF ns February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE Preliminary Technical Data DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW SPTx_A/BCLK (SPORT CLOCK) SPTx_A/BCLK (SPORT CLOCK) tDFSI tDFSE tSFSI tHOFSI tHFSI tSFSE tHFSE tSDRE tHDRE tHOFSE SPTx_A/BFS (FRAME SYNC) SPTx_A/BFS (FRAME SYNC) tSDRI tHDRI SPTx_A/BDx (DATA CHANNEL A/B) SPTx_A/BDx (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLKW SPTx_A/BCLK (SPORT CLOCK) SPTx_A/BCLK (SPORT CLOCK) tDFSI tDFSE tHOFSI tSFSI tHFSI tSFSE tHOFSE SPTx_A/BFS (FRAME SYNC) SPTx_A/BFS (FRAME SYNC) tDDTI tDDTE tHDTI tHDTE SPTx_A/BDx (DATA CHANNEL A/B) SPTx_A/BDx (DATA CHANNEL A/B) Figure 37. Serial Ports Rev. PrF | Page 114 of 168 | February 2016 tHFSE Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 62. Serial Ports—Enable and Three-State1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit 14 ns Switching Characteristics tDDTEN Data Enable from External Transmit SPTx_CLK2 tDDTTE Data Disable from External Transmit SPTx_CLK2 tDDTIN Data Enable from Internal Transmit SPTx_CLK2 tDDTTI Data Disable from Internal Transmit SPTx_CLK 1 ns –2.5 ns 2 2.8 1 Specifications apply to all eight SPORTs. 2 Referenced to drive edge. DRIVE EDGE DRIVE EDGE SPTx_CLK (SPORT CLOCK EXTERNAL) tDDTEN tDDTTE SPTx_A/BDx (DATA CHANNEL A/B) DRIVE EDGE DRIVE EDGE SPTx_CLK (SPORT CLOCK INTERNAL) tDDTIN tDDTTI SPTx_A/BDx (DATA CHANNEL A/B) Figure 38. Serial Ports—Enable and Three-State Rev. PrF | Page 115 of 168 | February 2016 ns ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data The SPTx_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection registers) the SPTx_TDV is asserted for communication with external devices. Table 63. Serial Ports—TDV (Transmit Data Valid)1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Switching Characteristics tDRDVEN Data-Valid Enable Delay from Drive Edge of External Clock2 2 2 tDFDVEN Data-Valid Disable Delay from Drive Edge of External Clock tDRDVIN Data-Valid Enable Delay from Drive Edge of Internal Clock2 tDFDVIN Data-Valid Disable Delay from Drive Edge of Internal Clock2 14 –2.5 Specifications apply to all eight SPORTs. 2 Referenced to drive edge. DRIVE EDGE DRIVE EDGE SPTx_CLK (SPORT CLOCK EXTERNAL) tDRDVEN tDFDVEN SPTx_A/BTDV DRIVE EDGE DRIVE EDGE SPTx_CLK (SPORT CLOCK INTERNAL) tDRDVIN tDFDVIN SPTx_A/BTDV Figure 39. Serial Ports—Transmit Data Valid Internal and External Clock | Page 116 of 168 | February 2016 ns ns 3.5 1 Rev. PrF ns ns Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 64. Serial Ports—External Late Frame Sync1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit 14 ns Switching Characteristics 1 2 tDDTLFSE Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 02 tDDTENFS Data Enable for MCE = 1, MFD = 02 0.5 ns Specifications apply to all eight SPORTs. The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as standard serial mode, and MCE = 1, MFD = 0. DRIVE SAMPLE DRIVE SPTx_A/BCLK (SPORT CLOCK) tHFSE/I tSFSE/I SPTx_A/BFS (FRAME SYNC) tDDTE/I tDDTENFS tHDTE/I SPTx_A/BDx (DATA CHANNEL A/B) 1ST BIT 2ND BIT tDDTLFSE Figure 40. External Late Frame Sync Rev. PrF | Page 117 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Sample Rate Converter—Serial Input Port The ASRC input signals are routed from the DAIx_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 65 are valid at the DAIx_P20–1 pins. Table 65. ASRC, Serial Input Port All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSRCSFS1 1 1 Frame Sync Setup Before Serial Clock Rising Edge 4 ns tSRCHFS Frame Sync Hold After Serial Clock Rising Edge 5.5 ns tSRCSD1 Data Setup Before Serial Clock Rising Edge 4 ns tSRCHD1 Data Hold After Serial Clock Rising Edge 5.5 ns tSRCCLKW Clock Width tSCLK0 – 1 ns tSRCCLK Clock Period 2 × tSCLK0 ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK tSRCCLKW DAIx_PIN20–1 (SCLK) tSRCSFS tSRCHFS DAIx_PIN20–1 (FS) tSRCSD tSRCHD DAIX_PIN20–1 (SDATA) Figure 41. ASRC Serial Input Port Timing Rev. PrF | Page 118 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Sample Rate Converter—Serial Output Port For the serial output port, the frame sync is an input, and it should meet setup and hold times with regard to SCLK on the output port. The serial data output has a hold time and delay specification with regard to serial clock. Note that serial clock rising edge is the sampling edge, and the falling edge is the drive edge. Table 66. ASRC, Serial Output Port All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSRCSFS1 Frame Sync Setup Before Serial Clock Rising Edge 4 ns tSRCHFS1 Frame Sync Hold After Serial Clock Rising Edge 5.5 ns tSRCCLKW Clock Width tSCLK0 – 1 ns tSRCCLK Clock Period 2 × tSCLK0 ns Switching Characteristics 1 tSRCTDD1 Transmit Data Delay After Serial Clock Falling Edge tSRCTDH1 Transmit Data Hold After Serial Clock Falling Edge 13 1 ns ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN, SCLK0, or any of the DAI pins. SAMPLE EDGE tSRCCLK tSRCCLKW DAIx_PIN20–1 (SCLK) tSRCSFS tSRCHFS DAIx_PIN20–1 (FS) tSRCTDD tSRCTDH DAIx_PIN20–1 (SDATA) Figure 42. ASRC Serial Output Port Timing Rev. PrF | Page 119 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Serial Peripheral Interface (SPI) Port—Master Timing Table 67 and Figure 43 describe serial peripheral interface (SPI) port master operations. When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in MHz is set by the following equation where BAUD is a field in the SPIx_CLK register that can be set from 0 to 65535: f SCLK1 f SPICLKPROG = --------------------------- BAUD + 1 1 t SPICLKPROG = -------------------------f SPICLKPROG Note that: • In dual mode data transmit the SPIx_MISO signal is also an output. • In quad mode data transmit the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also outputs. • In dual mode data receive the SPIx_MOSI signal is also an input. • In quad mode data receive the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also inputs. • Quad mode is supported by SPI2 only. Table 67. Serial Peripheral Interface (SPI) Port—Master Timing1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSSPIDM Data Input Valid to SPIx_CLK Edge (Data Input Setup) 3.2 ns tHSPIDM SPIx_CLK Sampling Edge to Data Input Invalid 1.2 ns [tSCLK1 – 2] or [18] ns Switching Characteristics tSDSCIM SPIx_SEL low to First SPI_CLK Edge for CPHA = 12 SPIx_SEL low to First SPI_CLK Edge for CPHA = 0 2 [1.5 × tSCLK1 – 2] or [13] ns tSPICHM SPIx_CLK High Period3 0.5 × tSPICLKPROG – 1 ns tSPICLM SPIx_CLK Low Period3 0.5 × tSPICLKPROG – 1 ns tSPICLK SPIx_CLK Period3 tSPICLKPROG – 1 ns [1.5 × tSCLK1 –2] or [13] ns [tSCLK1 –2] or [18] ns tHDSM Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 1 2 Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 02 2, 4 tSPITDM Sequential Transfer Delay tDDSPIDM SPIx_CLK Edge to Data Out Valid (Data Out Delay) [tSCLK1 – 1] or [19] tHDSPIDM SPIx_CLK Edge to Data Out Invalid (Data Out Hold) ns 2.6 –1.5 1 All specifications apply to all three SPIs. Whichever is greater. 3 See Table 28 in Clock Related Operating Conditions on Page 81 for details on the minimum period that may be programmed for tSPICLKPROG. 4 Applies to sequential mode with STOP ≥ 1. 2 Rev. PrF | Page 120 of 168 | February 2016 ns ns Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 SPIx_SEL (OUTPUT) tSDSCIM tSPICLM tSPICHM tSPICLK tHDSM SPIx_CLK (OUTPUT) tHDSPIDM tDDSPIDM DATA OUTPUTS (SPIx_MOSI) tSSPIDM CPHA = 1 tHSPIDM DATA INPUTS (SPIx_MISO) tHDSPIDM tDDSPIDM DATA OUTPUTS (SPIx_MOSI) CPHA = 0 tSSPIDM tHSPIDM DATA INPUTS (SPIx_MISO) Figure 43. Serial Peripheral Interface (SPI) Port—Master Timing Rev. PrF | Page 121 of 168 | February 2016 tSPITDM ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Serial Peripheral Interface (SPI) Port—Slave Timing Table 68 and Figure 44 describe serial peripheral interface (SPI) port slave operations. Note that: • In dual mode data transmit the SPIx_MOSI signal is also an output. • In quad mode data transmit the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also outputs. • In dual mode data receive the SPIx_MISO signal is also an input. • In quad mode data receive the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also inputs. • In SPI slave mode the SPI clock is supplied externally and is called fSPICLKEXT: 1 t SPICLKEXT = ----------------------f SPICLKEXT • Quad mode is supported by SPI2 only. Table 68. Serial Peripheral Interface (SPI) Port—Slave Timing1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSPICHS SPIx_CLK High Period2 0.5 × tSPICLKEXT – 1 ns tSPICLS SPIx_CLK Low Period2 0.5 × tSPICLKEXT – 1 ns tSPICLKEXT – 1 ns 5 ns 2 tSPICLK SPIx_CLK Period tHDS Last SPIx_CLK Edge to SPIx_SS Not Asserted tSPITDS Sequential Transfer Delay tSPICLK – 1 ns tSDSCI SPIx_SS Assertion to First SPIx_CLK Edge 10.5 ns tSSPID Data Input Valid to SPIx_CLK Edge (Data Input Setup) 2 ns tHSPID SPIx_CLK Sampling Edge to Data Input Invalid 1.6 ns Switching Characteristics tDSOE SPIx_SS Assertion to Data Out Active 0 14 ns tDSDHI SPIx_SS Deassertion to Data High Impedance 0 12.5 ns tDDSPID SPIx_CLK Edge to Data Out Valid (Data Out Delay) tHDSPID SPIx_CLK Edge to Data Out Invalid (Data Out Hold) 1 2 14 0 ns ns All specifications apply to all three SPIs. This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external SPIx_CLK ideal maximum frequency see the fSPICLKTEXT specification in Table 28 in Clock Related Operating Conditions on Page 81. Rev. PrF | Page 122 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 SPIx_SS (INPUT) tSDSCI tSPICLS tSPICHS tHDS tSPICLK SPIx_CLK (INPUT) tDSOE tDDSPID tDDSPID tHDSPID tDSDHI DATA OUTPUTS (SPIx_MISO) CPHA = 1 tSSPID tHSPID DATA INPUTS (SPIx_MOSI) tDSOE tHDSPID tDDSPID tDSDHI DATA OUTPUTS (SPIx_MISO) tHSPID CPHA = 0 tSSPID DATA INPUTS (SPIx_MOSI) Figure 44. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. PrF | Page 123 of 168 | February 2016 tSPITDS ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Serial Peripheral Interface (SPI) Port—SPIx_RDY Slave Timing Table 69. SPI Port—SPIx_RDY Slave Timing1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Switching Characteristics 1 tDSPISCKRDYSR SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode Receive 3 × tSCLK1 4 × tSCLK1 + 10 ns tDSPISCKRDYST SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode Transmit 4 × tSCLK1 5 × tSCLK1 + 10 ns All specifications apply to all three SPIs. tDSPISCKRDYSR SPIx_CLK (CPOL = 0) CPHA = 0 SPIx_CLK (CPOL = 1) SPIx_CLK (CPOL = 0) CPHA = 1 SPIx_CLK (CPOL = 1) SPIx_RDY (O) Figure 45. SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode Receive (FCCH = 0) tDSPISCKRDYST SPIx_CLK (CPOL = 1) CPHA = 0 SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) CPHA = 1 SPIx_CLK (CPOL = 0) SPIx_RDY (O) Figure 46. SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode Transmit (FCCH = 1) Rev. PrF | Page 124 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing In Figure 47 and Figure 48, the outputs can be SPIx_MOSI SPIx_MISO, SPIx_D2, and/or SPIx_D3 depending on the mode of operation. Table 70. SPI Port ODM Master Mode Timing1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Switching Characteristics 1 tHDSPIODMM SPIx_CLK Edge to High Impedance from Data Out Valid –1 tDDSPIODMM SPIx_CLK Edge to Data Out Valid from High Impedance –1 ns 6 ns Max Unit All specifications apply to all three SPIs. tHDSPIODMM tHDSPIODMM SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) OUTPUT (CPHA = 1) OUTPUT (CPHA = 0) tDDSPIODMM tDDSPIODMM Figure 47. ODM Master Table 71. SPI Port—ODM Slave Mode1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Timing Requirements 1 tHDSPIODMS SPIx_CLK Edge to High Impedance from Data Out Valid tDDSPIODMS SPIx_CLK Edge to Data Out Valid from High Impedance 0 ns 11 All specifications apply to all three SPIs. tHDSPIODMS tHDSPIODMS SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) OUTPUT (CPHA = 1) OUTPUT (CPHA = 0) tDDSPIODMS tDDSPIODMS Figure 48. ODM Slave Rev. PrF | Page 125 of 168 | February 2016 ns ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Serial Peripheral Interface (SPI) Port—SPIx_RDY Master Timing SPIx_RDY is used to provide flow control. The CPOL and CPHA bits are set in SPIx_CTL, while LEADX, LAGX, and STOP are in SPIx_DLY. Table 72. SPI Port—SPIx_RDY Master Timing1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSRDYSCKM0 Minimum Setup Time for SPIx_RDY Deassertion in Master (2 + 2 × BAUD2) × tSCLK1 + 10 Mode Before Last Valid SPIx_CLK Edge of Valid Data Transfer to Block Subsequent Transfer with CPHA = 0 ns tSRDYSCKM1 Minimum Setup Time for SPIx_RDY Deassertion in Master (2 + 2 × BAUD2) × tSCLK1 + 10 Mode Before Last Valid SPIx_CLK Edge of Valid Data Transfer to Block Subsequent Transfer with CPHA = 1 ns Switching Characteristic tSRDYSCKM 1 2 Time Between Assertion of SPIx_RDY by Slave and First Edge 4.5 × tSCLK1 of SPIx_CLK for New SPI Transfer with CPHA/CPOL = 0 and BAUD = 0 (STOP, LEAD, LAG = 0) 5.5 × tSCLK1 + 10 ns Time Between Assertion of SPIx_RDY by Slave and First Edge 4 × tSCLK1 of SPIx_CLK for New SPI Transfer with CPHA/CPOL = 1 and BAUD = 0 (STOP, LEAD, LAG = 0) 5 × tSCLK1 + 10 ns Time Between Assertion of SPIx_RDY by Slave and First Edge (1 + 1.5 × BAUD2) × tSCLK1 of SPIx_CLK for New SPI Transfer with CPHA/CPOL = 0 and BAUD ≥ 1 (STOP, LEAD, LAG = 0) (2 + 2.5 × BAUD2) × tSCLK1 + 10 ns Time Between Assertion of SPIx_RDY by Slave and First Edge (1 + 1 × BAUD2) × tSCLK1 of SPIx_CLK for New SPI Transfer with CPHA/CPOL = 1 and BAUD ≥ 1 (STOP, LEAD, LAG = 0) (2 + 2 × BAUD2) × tSCLK1 + 10 ns All specifications apply to all three SPIs. BAUD value set using the SPIx_CLK.BAUD bits. BAUD value = SPIx_CLK.BAUD bits + 1. tSRDYSCKM0 SPIx_RDY SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) Figure 49. SPIx_RDY Setup Before SPIx_CLK with CPHA = 0 Rev. PrF | Page 126 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 tSRDYSCKM1 SPIx_RDY SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) Figure 50. SPIx_RDY Setup Before SPIx_CLK with CPHA = 1 tSRDYSCKM SPIx_RDY SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) Figure 51. SPIx_CLK Switching Diagram after SPIx_RDY Assertion, CPHA = x Rev. PrF | Page 127 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAIx_PIN20-1). Table 73. Precision Clock Generator (Direct Pin Routing) All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tPCGIP Input Clock Period tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input 4.5 Clock tSCLK × 2 ns ns tHTRIG PCG Trigger Hold After Falling Edge of PCG Input Clock ns 3 Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge Delay 2.5 After PCG Input Clock 13.5 ns ns tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × tPCGIP) 13.5 + (2.5 × tPCGIP) tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIP) 13.5 + ((2.5 + D – PH) × tPCGIP) ns tPCGOW1 Output Clock Period 2 × tPCGIP – 1 ns D = FSxDIV, PH = FSxPHASE. For more information, see the “Precision Clock Generators” chapter of the hardware reference manual. 1 Normal mode of operation. tSTRIG tHTRIG DAIx_PIN20–1 PCG_TRIGx_I DAIx_PIN20–1 PCG_EXTx_I (CLKIN) tPCGIP tDPCGIO DAIx_PIN20–1 PCG_CLKx_O tDTRIGCLK tDPCGIO DAIx_PIN20–1 PCG_FSx_O tDTRIGFS Figure 52. Precision Clock Generator (Direct Pin Routing) Rev. PrF | Page 128 of 168 | February 2016 tPCGOW Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 General-Purpose IO Port Timing Table 74 and Figure 53 describe I/O timing, related to the general-purpose ports (PORT). Table 74. General-Purpose Port Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirement tWFI General-Purpose Port Pin Input Pulse Width 2 × tSCLK0 – 1.5 ns tWFI GPIO INPUT Figure 53. General-Purpose Port Timing GPIO Timer Cycle Timing Table 75, Table 76, and Figure 54 describe timer expired operations, related to the general-purpose timer (TIMER). The input signal is asynchronous in “width capture mode” and “external clock mode” and has an absolute maximum input frequency of (fSCLK/4) MHz. The Width Value value is the timer period assigned in the TMx_TMRn_WIDTH register and can range from 1 to 232 – 1. Note that when externally generated, the TMR clock is called fTMRCLKEXT: 1 t TMRCLKEXT = ------------------------f TMRCLKEXT Table 75. Timer Cycle Timing (Internal Mode) All specifications are based on simulation data and are subject to change without notice. Parameter Min Timing Requirements tWL Timer Pulse Width Input Low (Measured In SCLK Cycles)1 2 × tSCLK tWH Timer Pulse Width Input High (Measured In SCLK Cycles)1 2 × tSCLK Switching Characteristic tHTO Timer Pulse Width Output (Measured In SCLK Cycles)2 tSCLK × WIDTH – 1.5 Max Unit ns ns tSCLK × WIDTH + 1.5 ns 1 The minimum pulse width applies for TMx signals in width capture and external clock modes. 2 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1). Table 76. Timer Cycle Timing (External Mode) All specifications are based on simulation data and are subject to change without notice. Parameter Min Timing Requirements tWL Timer Pulse Width Input Low (Measured In EXT_CLK Cycles)1 2 × tEXT_CLK tWH Timer Pulse Width Input High (Measured In EXT_CLK Cycles)1 2 × tEXT_CLK tEXT_CLK Timer External Clock Period2 tTMRCLKEXT Switching Characteristic tHTO Timer Pulse Width Output (Measured In EXT_CLK Cycles)3 tEXT_CLK × WIDTH – 1.5 1 Max Unit ns ns ns tEXT_CLK × WIDTH + 1.5 ns The minimum pulse width applies for TMx signals in width capture and external clock modes. 2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external TMR_CLK. For the external TMR_CLK maximum frequency see the fTMRCLKEXT specification in Table 28 in Clock Related Operating Conditions. 3 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1). Rev. PrF | Page 129 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data TMR OUTPUT tHTO TMR INPUT tWH, tWL Figure 54. Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 and DAI1) Table 77 and Figure 55 describe I/O timing, related to the digital audio interface (DAI). For direct pin connections only (for example DAIx_PB01_I to DAIx_PB02_O). Table 77. DAI/DAI Pin to Pin Routing All specifications are based on simulation data and are subject to change without notice. Parameter Min Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid 1.5 Max Unit 12 ns DAI_Pn tDPIO DAI_Pm Figure 55. DAI Pin to Pin Direct Routing Up/Down Counter/Rotary Encoder Timing Table 78 and Figure 56 describe timing, related to the general-purpose counter (CNT). Table 78. Up/Down Counter/Rotary Encoder Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirement tWCOUNT Up/Down Counter/Rotary Encoder Input Pulse Width CNT0_UD CNT0_DG CNT0_ZM tWCOUNT Figure 56. Up/Down Counter/Rotary Encoder Timing Rev. PrF | Page 130 of 168 | February 2016 2 × tSCLK0 ns Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Pulse Width Modulator (PWM) Timing Table 79 and Figure 57 describe timing, related to the pulse width modulator (PWM). Table 79. PWM Timing1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirement tES External Sync Pulse Width 2 × tSCLK0 ns Switching Characteristics tDODIS tDOE Output Inactive (OFF) After Trip Input2 Output Delay After External Sync 2, 3 2 × tSCLK0 + 5.5 15 ns 5 × tSCLK0 + 14 ns 1 All specifications apply to all three PWMs. PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL. 3 When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is asynchronous to the peripheral clock. 2 PWMx_SYNC (AS INPUT) tES tDOE OUTPUT tDODIS PWMx_TRIP Figure 57. PWM Timing Rev. PrF | Page 131 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Pulse Width Modulator (PWM)— Heightened-Precision Mode Timing Table 80 and Table 81 and Figure 58 and Figure 59 describe heightened-precision pulse width modulator (PWM) operations. Table 80. PWM—Heightened-Precision Mode, Output Pulse All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Switching Characteristics tHPWMW HP-PWM Output Pulse Width1, 2 (N + m × 0.25) × tSCLK – 0.5 (N + m × 0.25) × tSCLK + 0.5 Unit ns 1 N is the DUTY bit field (coarse duty) from the duty register. m is the ENHDIV (Enhanced Precision Divider bits) value from the HP duty register. 2 Applies to individual PWM channel with 50% duty cycle. Other PWM channels within the same unit are toggling at the same time. No other GPIO pins are toggling. PWMOUTPUT t HPWMW Figure 58. PWM Heightened-Precision Mode Timing, Output Pulse Table 81. PWM—Heightened-Precision Mode, Output Skew All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Switching Characteristics tHPWMS HP-PWM Output Skew 1 1.0 1 Unit ns Output edge difference between any two PWM channels (AH, AL, BH, BL, CH, CL, DH and DL) in the same PWM unit (a unit is PWMx where x = 0, 1, 2), with the same heightened-precision edge placement. PWM OUTPUTS t HPWMS PWM OUTPUTS Figure 59. PWM Heightened-Precision Mode Timing, Output Skew Rev. PrF | Page 132 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ADC Controller Module (ACM) Timing Table 82 and Figure 60 describe ADC control module (ACM) operations. When internally generated, the programmed ACM clock (fACLKPROG) frequency in MHz is set by the following equation where CKDIV is a field in the ACM_TC0 register and ranges from 1 to 255: f SCLK1 f ACLKPROG = --------------------CKDIV + 1 1 t ACLKPROG = -----------------f ACLKPROG Setup cycles (SC) in Table 82 is also a field in the ACM_TC0 register and ranges from 0 to 4095. Hold Cycles (HC) is a field in the ACM_TC1 register that ranges from 0 to 15. Table 82. ACM Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tSDR SPORT DRxPRI/DRxSEC Setup Before ACMx_CLK 3.5 ns tHDR SPORT DRxPRI/DRxSEC Hold After ACMx_CLK 1.5 ns ns Switching Characteristics 1 tSCTLCS ACM Controls (ACMx_A[4:0]) Setup Before Assertion of CS (SC + 1) × tSCLK1 – 3 tHCTLCS ACM Control (ACMx_A[4:0]) Hold After Deassertion of CS HC × tACLKPROG – 1 ns tACLKW ACM Clock Pulse Width1 (0.5 × tACLKPROG) – 1.5 ns tACLK ACM Clock Period1 tACLKPROG – 1.5 ns tHCSACLK CS Hold to ACMx_CLK Edge –2.5 ns tSCSACLK CS Setup to ACMx_CLK Edge tACLKPROG – 3.5 ns See Table 28 in Clock Related Operating Conditions on Page 81 for details on the minimum period that may be programmed for tACLKPROG. DAIx_PIN20–1 (ACM0_FS/CS) CSPOL = 1/0 tSCSACLK DAIx_PIN20–1 (ACM_CLK) CLKPOL = 1/0 tACLK tACLKW tHCSACLK DAIx_PIN20–1 (ACM_A0-4) tSDR t SCTLCS DAIx_PIN20–1 (ACM0_T0) Figure 60. ACM Timing Rev. PrF | Page 133 of 168 | February 2016 tHDR t HCTLCS ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The universal asynchronous receiver-transmitter (UART) ports receive and transmit operations are described in the hardware reference manual. Controller Area Network (CAN) Interface The controller area network (CAN) interface timing is described in the hardware reference manual. Rev. PrF | Page 134 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Table 83 describes the universal serial bus (USB) On-The-Go receive and transmit operations. Table 83. USB On-The-Go—Receive and Transmit Timing1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements 1 fUSBS USB_XI Frequency 24 24 MHz fsUSB USB_XI Clock Frequency Stability –50 +50 ppm This specification is supported by USB0. PCI Express (PCIe) For more information about PCI Express (PCIe), see the following standards: • PCI Express Base 3.0 Specification, Revision 1.0, PCI-SIG • PCI Express 2.0 Card Electromechanical Specification, Revision 2.0, PCI-SIG • PHY Interface for the PCI Express Architecture, Revision 2.0, Intel Corporation • PCI-SIG Engineering Change Request: L1 Substates, February 1, 2012, PCI-SIG • IEEE Standard 1149.1-2001, IEEE • IEEE Standard 1149.6-2003, IEEE Rev. PrF | Page 135 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data 10/100 Ethernet MAC Controller (EMAC) Timing (ETH0 and ETH1) Table 84 through Table 86 and Figure 61 through Figure 63 describe the 10/100 Ethernet MAC Controller (EMAC) operations. Table 84. 10/100 Ethernet MAC Controller (EMAC) Timing: RMII Receive Signal1 All specifications are based on simulation data and are subject to change without notice. Parameter2 Min Max Unit None 50 + 1% MHz tREFCLK × 65% Timing Requirements 1 2 tREFCLKF ETHx_REFCLK Frequency (fSCLK0 = SCLK0 Frequency) tREFCLKW ETHx_REFCLK Width (tREFCLK = ETHx_REFCLK Period) tREFCLK × 35% tREFCLKIS Rx Input Valid to RMII ETHx_REFCLK Rising Edge (Data In Setup) 1.75 ns ns tREFCLKIH RMII ETHx_REFCLK Rising Edge to Rx Input Invalid (Data In Hold) 1.6 ns These specifications apply to ETH0 and ETH1. RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER. tREFCLK ETH0_REFCLK tREFCLKW ETH0_RXD1–0 ETH0_CRS tREFCLKIS tREFCLKIH Figure 61. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal Table 85. 10/100 Ethernet MAC Controller (EMAC) Timing: RMII Transmit Signal1 All specifications are based on simulation data and are subject to change without notice. Parameter2 Min Max Unit 11.9 ns Switching Characteristics tREFCLKOV RMII ETHx_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid) tREFCLKOH RMII ETHx_REFCLK Rising Edge to Transmit Output Invalid (Data Out Hold) 2 1 These specifications apply to ETH0 and ETH1. 2 RMII outputs synchronous to RMII REF_CLK are ETxD1–0. tREFCLK ETH0_REFCLK tREFCLKOH ETH0_TXD1–0 ETH0_TXEN tREFCLKOV Figure 62. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal Rev. PrF | Page 136 of 168 | February 2016 ns Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Table 86. 10/100 Ethernet MAC Controller (EMAC) Timing: RMII Station Management1 All specifications are based on simulation data and are subject to change without notice. Parameter2 Min Max Unit Timing Requirements tMDIOS ETHx_MDIO Input Valid to ETHx_MDC Rising Edge (Setup) 10.8 ns tMDCIH ETHx_MDC Rising Edge to ETHx_MDIO Input Invalid (Hold) 0 ns Switching Characteristics 1 2 tMDCOV ETHx_MDC Falling Edge to ETHx_MDIO Output Valid tMDCOH ETHx_MDC Falling Edge to ETHx_MDIO Output Invalid (Hold) tSCLK0 + 2 tSCLK0 –2.9 ns ns These specifications apply to ETH0 and ETH1. ETHx_MDC/ETHx_MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. ETHx_MDC is an output clock whose minimum period is programmable as a multiple of the system clock SCLK0. ETHx_MDIO is a bidirectional data line. ETH0_MDC (OUTPUT) tMDCOH ETH0_MDIO (OUTPUT) tMDCOV ETH0_MDIO (INPUT) tMDIOS tMDCIH Figure 63. 10/100 Ethernet MAC Controller Timing: RMII Station Management Rev. PrF | Page 137 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Gigabit Ethernet MAC Controller (EMAC) Timing Table 87 and Figure 64 describe the Gigabit Ethernet MAC Controller (EMAC) timing. Table 87. Gigabit Ethernet MAC Controller (EMAC) Timing: RGMII 1 All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements TsetupR Data to Clock Input Setup at Receiver 1 ns TholdR Data to Clock Input Hold at Receiver 1 ns tGREFCLKF RGMII Receive Clock Period 8 ns tGREFCLKW RGMII Receive Clock Pulse Width 4 ns – 0.5 ns Switching Characteristics 1 TskewT_min Data to Clock Output Skew at Transmitter MIN TskewT_max Data to Clock Output Skew at Transmitter MAX 0.5 ns Tcyc Clock Cycle Duration 7.2 8.8 ns Duty_G Duty Cycle for Gigabit MIN 0.45 × 8 0.55 × 8 ns This specification is supported by ETH0 only (10/100/1000 Ethernet MAC Controller). ETH_TXCLK (AT TRANSMITTER) TskewT ETH_TXD0–3 TXD3–0 TXD8–5 TXD7–4 TXD4 TXEN TXD9 TXERR ETH_TXD0–3 ETH_TXCTL_TXEN TskewR ETH_TXCLK (AT RECEIVER) ETH_RXCLK_REFCLK (AT TRANSMITTER) TskewT ETH_RXD0–3 RXD3–0 RXD8–5 RXD7–4 RXD4 RXEN RXD9 RXERR ETH_RXD0–3 ETH_RXCTL_CRS TsetupR TskewR ETH_RXCLK_REFCLK (AT RECEIVER) TholdR Figure 64. Gigabit Ethernet MAC Controller Timing: RGMII Rev. PrF | Page 138 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Sinus Cardinalis (SINC) Filter Timing The programmed sinus cardinalis (SINC) filter clock (fSINCLKPROG) frequency in MHz is set by the following equation where MDIV is a field in the CLK Control register that can be set from 4 to 63: f SCLK f SINCLKPROG = ------------ MDIV 1 t SINCLKPROG = --------------------------f SINCLKPROG Table 88. SINC Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Timing Requirements tSSINC SINC0_Dx Setup Before SINC0_CLKx Rise 13.5 tHSINC SINC0_Dx Hold After SINC0_CLKx Rise 0 Switching Characteristics tSINCLK SINC0_CLKx Period1 tSINCLKPROG – 2.5 tSINCLKW SINC0_CLKx Width1 0.5 × tSINCLKPROG – 2.5 1 Max See Table 28 in Clock Related Operating Conditions on Page 81 for details on the minimum period that may be programmed for tSINCLKPROG. tSINCLK tSINCLKW tSINCLKW SINC0_CLKx tSSINC tHSINC SINC_Dx Figure 65. SINC Timing Rev. PrF | Page 139 of 168 | February 2016 Unit ns ns ns ns ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Sony/Philips Digital Interface (S/PDIF) Transmitter Serial data input to the Sony/Philips Digital Interface (S/PDIF) transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 66 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right-justified to the next frame sync transition. Table 89. S/PDIF Transmitter Right-Justified Mode All specifications are based on simulation data and are subject to change without notice. Parameter Timing Requirement tRJD Frame Sync to MSB Delay in Right-Justified Mode 16-Bit Word Mode 18-Bit Word Mode 20-Bit Word Mode 24-Bit Word Mode Nominal Unit 16 14 12 8 SCLK SCLK SCLK SCLK LEFT/RIGHT CHANNEL DAI_P20–1 FS DAI_P20–1 SCLK tRJD DAI_P20–1 SDATA LSB MSB MSB–1 MSB–2 Figure 66. Right-Justified Mode Rev. PrF | Page 140 of 168 | February 2016 LSB+2 LSB+1 LSB Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Figure 67 shows the default I2S-justified mode. The frame sync is low for the left channel and HI for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition but with a delay. Table 90. S/PDIF Transmitter I2S Mode All specifications are based on simulation data and are subject to change without notice. Parameter Nominal Timing Requirement tI2SD Frame Sync to MSB Delay in I2S Mode 1 Unit SCLK LEFT/RIGHT CHANNEL DAI_P20–1 FS DAI_P20–1 SCLK tI2SD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB Figure 67. I2S-Justified Mode Figure 68 shows the left-justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition with no delay. Table 91. S/PDIF Transmitter Left-Justified Mode All specifications are based on simulation data and are subject to change without notice. Parameter Nominal Timing Requirement tLJD Frame Sync to MSB Delay in Left-Justified Mode 0 DAI_P20–1 FS LEFT/RIGHT CHANNEL DAI_P20–1 SCLK tLJD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB Figure 68. Left-Justified Mode Rev. PrF | Page 141 of 168 | February 2016 Unit SCLK ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 92. Input signals are routed to the DAIx_Pin20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAIx_Pin20–1 pins. Table 92. S/PDIF Transmitter Input Data Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements 1 tSISFS1 Frame Sync Setup Before Serial Clock Rising Edge 3 ns tSIHFS1 Frame Sync Hold After Serial Clock Rising Edge 3 ns tSISD1 Data Setup Before Serial Clock Rising Edge 3 ns tSIHD1 Data Hold After Serial Clock Rising Edge 3 ns tSITXCLKW Transmit Clock Width 9 ns tSITXCLK Transmit Clock Period 20 ns tSISCLKW Clock Width 36 ns tSISCLK Clock Period 80 ns The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSITXCLKW tSITXCLK DAIx_PIN20–1 (TxCLK) tSISCLK tSISCLKW DAIx_PIN20–1 (SCLK) tSISFS tSIHFS DAIx_PIN20–1 (FS) tSISD tSIHD DAIx_PIN20–1 (SDATA) Figure 69. S/PDIF Transmitter Input Timing Rev. PrF | Page 142 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Sony/Philips Digital Interface (S/PDIF) Receiver The following section describes timing as it relates to the Sony/Philips Digital Interface (S/PDIF) receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 93. S/PDIF Receiver Internal Digital PLL Mode Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit 5 ns Switching Characteristics tDFSI Frame Sync Delay After Serial Clock tHOFSI Frame Sync Hold After Serial Clock tDDTI Transmit Data Delay After Serial Clock tHDTI Transmit Data Hold After Serial Clock –2 5 –2 SAMPLE EDGE DRIVE EDGE DAIx_PIN20–1 (SCLK) tDFSI tHOFSI DAIx_PIN20–1 (FS) tDDTI tHDTI DAIx_PIN20–1 (DATA CHANNEL A/B) Figure 70. S/PDIF Receiver Internal Digital PLL Mode Timing Rev. PrF | Page 143 of 168 | ns February 2016 ns ns ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Media Local Bus (MLB) All the numbers given are applicable for all media local bus (MLB) speed modes (1024 FS, 512 FS, and 256 FS) for 3-pin, unless otherwise specified. Please refer to the Media Local Bus Specification version 4.2 for more details. Table 94. MLB Interface, 3-Pin Specifications All specifications are based on simulation data and are subject to change without notice. Parameter Min Typ MLB Clock Period tMLBCLK 20.3 1024 FS 40 512 FS 81 256 FS tMCKL tMCKH tMCKR tMCKF tMPWV1 tDSMCF tDHMCF tMCFDZ tMCDRV tMDZH2 CMLB 1 2 MLBCLK Low Time 1024 FS 512 FS 256 FS MLBCLK High Time 1024 FS 512 FS 256 FS MLBCLK Rise Time (VIL to VIH) 1024 FS 512 FS/256 FS MLBCLK Fall Time (VIH to VIL) 1024 FS 512 FS/256 FS MLBCLK Pulse Width Variation 1024 FS 512 FS/256 DAT/SIG Input Setup Time DAT/SIG Input Hold Time DAT/SIG Output Time to Three-state DAT/SIG Output Data Delay From MLBCLK Rising Edge Bus Hold Time 1024 FS 512 FS/256 DAT/SIG Pin Load 1024 FS 512 FS/256 Max Unit ns ns ns 6.1 14 30 ns ns ns 9.3 14 30 ns ns ns 1 2 0 1 3 ns ns 1 3 ns ns 0.7 2.0 nspp nspp 15 8 ns ns ns ns 2 4 ns ns 40 60 pf pf Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp). The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. Rev. PrF | Page 144 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 MLB_SIG/ MLB_DAT (Rx, Input) VALID tDHMCF tDSMCF tMCKH MLB_CLK tMCKR tMCKL tMCKF tMLBCLK tMCFDZ tMCDRV tMDZH MLB_SIG/ MLB_DAT (Tx, Output) VALID Figure 71. Media Local Bus Timing (3-Pin Interface) The ac timing specifications of MLB 6-pin interface is detailed below. Please refer to the Media Local Bus Specification version 4.2 for more details. Table 95. MLB Interface, 6-Pin Specifications All specifications are based on simulation data and are subject to change without notice. Parameter Min Typ Max Unit tMT Differential transition time at the input pin 1 ns (Figure 72) MLBCP/N external clock operating 67.584 102.4 MHz fMCKE frequency1 (Figure 73) fMCKR Recovered clock operating frequency 90.112 (internal, not observable at pins, only for 135.168 timing references) (Figure 73) 102.4 204.8 MHz MHz tDELAY Transmitter MLBSP/N (MLBDP/N) output valid from transition of MLBCP/N (low-tohigh)2 (Figure 74) Disable turnaround time from transition of MLBCP/N (low-to-high)2 (Figure 75) 5 2.5 ns ns 7 3.5 11.2 5.6 ns ns ns ns ns ns ns tPHZ tPLZ tSU tHD 0.6 0.6 0.6 0.6 Enable turnaround time from transition of 0.6 MLBCP/N (low-to-high)2 (Figure 75) 0.6 MLBSP/N (MLBDP/N) valid to transition of 1 MLBCP/N (low-to-high)2 (Figure 74) 0.5 MLBSP/N (MLBDP/N) hold from transition 0.6 of MLBCP/N (low-to-high)2, 3 (Figure 74) 1 Comment 20% to 80% VIN+/– 80% to 20% VIN+/– 1536 × FS at 44.0 kHz 2048 × FS at 50.0 kHz 2048 × FS at 50.0 kHz 3072 × FS at 44.0 kHz 4096 × FS at 50.0 kHz when fMCKR = 2048 × FS when fMCKR = 3072 × FS or 4096 × FS when fMCKR = 2048 × FS when fMCKR = 3072 × FS or 4096 × FS when fMCKR = 2048 × FS when fMCKR = 3072 × FS or 4096 × FS when fMCKR = 2048 × FS when fMCKR = 3072 × FS or 4096 × FS fMCKE (max) and fMCKR (max) include maximum cycle-to-cycle system jitter (tJITTER) of 600ps for a bit error rate of 10E-9. tDELAY, tPHZ, tPLZ, tSU, tHD may also be referenced from a low-to-high transition of the recovered clock for 2:1 recovered to external clock ratios. 3 Receivers must latch MLBSP/N (MLBDP/N) data within tHD (min) of the rising edge of MLBCP/N. 2 Rev. PrF | Page 145 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 MLBCP/N MLBDP/N MLBSP/N tMT tMT 80% 20% Figure 72. Media Local Bus 6-Pin Transition Time MLBCP/N 1/fMCKE RECOVERED CLOCK (1:1) T1:1 RECOVERED CLOCK (2:1) T2:1 T2:1 NOTE: T1:1 = 1/fMCKE T2:1 = 1/(2 × fMCKE) Figure 73. Media Local Bus 6-Pin Clock Definitions Rev. PrF | Page 146 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data 1/fMCKE MLBCP/N RECOVERED CLOCK 1/fMCKR tDELAY tDELAY MLBSP/N MLBDP/N (TRANSMIT) tSU tSU MLBSP/N MLBDP/N (RECEIVE) VALID VALID tHD tHD 1/fMCKE MLBCP/N 1/fMCKR RECOVERED CLOCK tDELAY tDELAY MLBSP/N MLBDP/N (TRANSMIT) tSU MLBSP/N MLBDP/N (RECEIVE) VALID VALID tHD tHD Figure 74. Media Local Bus 6-Pin Delay, Setup, and Hold Times Rev. PrF | Page 147 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 MLBCP/N RECOVERED CLOCK (1:1) tPHZ MLBDP/N MLNSP/N tPLZ MLBCP/N RECOVERED CLOCK (2:1) tPHZ MLBDP/N MLNSP/N tPLZ Figure 75. Media Local Bus 6-Pin Disable and Enable Turnaround Times Rev. PrF | Page 148 of 168 | February 2016 Preliminary Technical Data Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Mobile Storage Interface (MSI) Controller Timing Table 96 and Figure 76 show I/O timing, related to the mobile storage interface (MSI). Table 96. MSI Controller Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tISU Input Setup Time 4.8 ns tIH Input Hold Time –0.5 ns Switching Characteristics 1 fPP Clock Frequency Data Transfer Mode1 50 MHz tWL Clock Low Time 8 ns tWH Clock High Time 8 ns tTLH Clock Rise Time 3 ns tTHL Clock Fall Time 3 ns tODLY Output Delay Time During Data Transfer Mode 2 ns tOH Output Hold Time –1.8 ns tPP = 1/fPP VOH (MIN) tPP MSI_CLK tTHL tISU tTLH tWL tIH VOL (MAX) tWH INPUT tODLY tOH OUTPUT NOTES: 1 INPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS. 2 OUTPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS. Figure 76. MSI Controller Timing Rev. PrF | Page 149 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Program Trace Macrocell (PTM) Timing Table 97 and Figure 77 provide I/O timing, related to the program trace macrocell (PTM). Table 97. Trace Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit 5 ns Switching Characteristics tDTRD TRACE Data Delay From Trace Clock MAX tHTRD TRACE Data Hold From Trace Clock MIN 2 ns tPTRCK TRACE Clock Period MIN 12.32 ns tPTRCK TRACE0_CLK tHTRD D0 TRACE0_DX tDTRD D1 tDTRD Figure 77. Trace Timing Rev. PrF | Page 150 of 168 | tHTRD February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Debug Interface (JTAG Emulation Port) Timing Table 98 and Figure 78 provide I/O timing, related to the debug interface (JTAG Emulator Port). Table 98. JTAG Port Timing All specifications are based on simulation data and are subject to change without notice. Parameter Min Max Unit Timing Requirements tTCK JTG_TCK Period 20 tSTAP JTG_TDI, JTG_TMS Setup Before JTG_TCK High 4 ns tHTAP JTG_TDI, JTG_TMS Hold After JTG_TCK High 4 ns tSSYS System Inputs Setup Before JTG_TCK High1 4 ns 4 ns 4 TCK 1 tHSYS System Inputs Hold After JTG_TCK High tTRSTW JTG_TRST Pulse Width (measured in JTG_TCK cycles)2 ns Switching Characteristics tDTDO JTG_TDO Delay from JTG_TCK Low System Outputs Delay After JTG_TCK Low tDSYS 3 1 12 ns 17 ns System Inputs = MLB0_CLKP, MLB0_DATP, MLB0_SIGP, DAI0_PIN20-01, DAI1_PIN20-01, DMC0_A15-0, DMC1_A15-0, DMC0_DQ15-0, DMC1_DQ15-0, DMC0_RESET, DMC1_RESET, PA_15-0, PB_15-0, PC_15-0, PD_15-0, PE_15-0, PF_15-0, PG_5-0, SYS_BMODE2-0, SYS_FAULT, SYS_FAULT, SYS_RESOUT, TWI2-0_SCL, TWI2-0_SDA2. 2 50 MHz Maximum. 3 System Outputs = DMC0_A15-0, DMC0_BA2-0, DMC0_CAS, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ15-0, DMC0_LDM, DMC0_LDQS, DMC0_ODT, DMC0_RAS, DMC0_RESET, DMC0_UDM, DMC0_UDQS, DMC0_WE, DMC1_A15-0, DMC1_BA2-0, DMC1_CAS, DMC1_CK, DMC1_CKE, DMC1_CS0, DMC1_DQ15-0, DMC1_LDM, DMC1_LDQS, DMC1_ODT, DMC1_RAS, DMC1_RESET, DMC1_UDM, DMC1_UDQS, DMC1_WE, MLB0_DATP, MLB0_SIGP, PA_15-0, PB_15-0, PC_15-0, PCIE_TXP, PD_15-0, PE_15-0, PF_15-0, PG_5-0, SYS_BMODE2-0, SYS_CLKOUT, SYS_FAULT, SYS_FAULT, SYS_RESOUT, TWI2-0_SCL, TWI2-0_SDA. tTCK JTG_TCK tSTAP tHTAP JTG_TMS JTG_TDI tDTDO JTG_TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 78. JTAG Port Timing Rev. PrF | Page 151 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ENVIRONMENTAL CONDITIONS To determine the junction temperature on the application printed circuit board, use the following equation: T J = T CASE + JT P D where: TJ = Junction temperature (°C). TCASE = Case temperature (°C) measured by customer at top center of package. JT = From Table 99 and Table 100. PD = Power dissipation (see Total Internal Power Dissipation for the method to calculate PD). Values of JA are provided for package comparison and printed circuit board design considerations. JA can be used for a first order approximation of TJ by the equation: T J = T A + JA P D where: TA = ambient temperature (°C). Values of JC are provided for package comparison and printed circuit board design considerations when an external heat sink is required. In Table 99 and Table 100, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6. The junction-tocase measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 6 layer PCB with 101.6 mm × 152.4 mm dimensions. Table 99. Thermal Characteristics for ADSP-SC584 19 mm × 19 mm 349 CSP_BGA Parameter JA JC JT Test Conditions/Comments Typical 0 linear m/s air flow 13.3 3.65 0 linear m/s air flow 0.08 Unit °C/W °C/W °C/W Table 100. Thermal Characteristics for ADSP-SC589 19 mm × 19 mm 529 CSP_BGA Parameter JA JC JT Test Conditions/Comments Typical 0 linear m/s air flow 13.4 3.63 0 linear m/s air flow 0.08 Rev. PrF Unit °C/W °C/W °C/W | Page 152 of 168 | February 2016 Preliminary Technical Data Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ADSP-SC58x/ADSP-2158x 349-BALL BGA BALL ASSIGNMENTS ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Numerical by Ball Number) lists the 349-ball BGA package by ball number. ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Alphabetical by Pin Name) lists the 349-ball BGA package by pin name. ADSP-SC58x/ADSP-2158x 349-BALL BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER) Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Pin Name GND DMC0_A06 DMC0_A04 DMC0_RAS DMC0_CKE DMC0_DQ15 DMC0_DQ13 DMC0_UDQS DMC0_UDQS DMC0_DQ09 DMC0_VREF DMC0_CK DMC0_CK DMC0_DQ06 DMC0_LDQS DMC0_LDQS DMC0_DQ01 GND PD_00 PD_03 PD_06 GND DMC0_A07 GND DMC0_A02 DMC0_A00 DMC0_ODT DMC0_DQ14 DMC0_DQ12 GND DMC0_DQ11 DMC0_DQ10 DMC0_DQ08 DMC0_DQ07 DMC0_DQ05 DMC0_DQ04 DMC0_DQ03 DMC0_DQ02 DMC0_DQ00 PC_13 PD_02 Ball No. B20 B21 B22 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D01 D02 D03 D11 D12 D20 D21 D22 E01 E02 E03 E05 E20 E21 E22 F01 Pin Name PD_05 GND PD_08 DMC0_A10 DMC0_A09 GND DMC0_A08 DMC0_A03 DMC0_CAS DMC0_BA0 DMC0_A01 DMC0_RZQ DMC0_WE DMC0_CS0 GND DMC0_LDM DMC0_UDM PD_01 PC_14 SYS_CLKOUT PC_15 PD_04 GND PD_07 PD_11 DMC0_A11 DMC0_A12 DMC0_BA2 VDD_INT VDD_INT PD_10 PD_09 PD_12 DMC0_A14 DMC0_A15 DMC0_A13 DMC0_A05 VDD_INT PD_13 PD_14 DMC0_RESET Rev. PrF | Ball No. F02 F03 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F20 F21 F22 G01 G02 G03 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G20 G21 G22 H01 H02 H03 H06 H07 H16 Page 153 of 168 | Pin Name PC_11 DMC0_BA1 VDD_DMC VDD_INT VDD_INT VDD_INT VDD_INT VDD_DMC VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT PD_15 PE_00 PC_12 PC_10 PC_04 VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_INT PE_01 PE_02 PC_08 PC_07 SYS_FAULT VDD_DMC VDD_DMC GND February 2016 Ball No. H17 H20 H21 H22 J01 J02 J03 J06 J09 J10 J11 J12 J13 J14 J17 J20 J21 J22 K01 K02 K03 K06 K08 K09 K10 K11 K12 K13 K14 K15 K17 K20 K21 K22 L01 L02 L03 L04 L06 L08 L09 Pin Name VDD_DMC VDD_INT PE_03 PE_04 PC_05 PC_06 JTG_TDI VDD_DMC GND GND GND GND GND GND VDD_EXT VDD_INT PE_05 PE_06 PC_03 PC_02 SYS_FAULT VDD_INT GND GND GND GND GND GND GND GND VDD_EXT VDD_INT PE_08 PE_07 PC_01 SYS_HWRST PC_09 VDD_INT VDD_INT GND GND ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Ball No. L10 L11 L12 L13 L14 L15 L17 L19 L20 L21 L22 M01 M02 M03 M04 M06 M08 M09 M10 M11 M12 M13 M14 M15 M17 M19 M20 M21 M22 N01 N02 N03 N06 N08 N09 N10 N11 N12 N13 N14 N15 N17 N20 N21 N22 P01 P02 Pin Name GND GND GND GND GND GND VDD_EXT VDD_INT PE_11 PE_10 PE_09 JTG_TRST JTG_TMS JTG_TCK VDD_INT VDD_INT GND GND GND GND GND GND GND GND VDD_EXT VDD_INT PE_13 PE_15 PE_12 SYS_XTAL1 SYS_BMODE0 PC_00 VDD_EXT GND GND GND GND GND GND GND GND VDD_EXT DAI1_PIN04 DAI1_PIN02 PE_14 SYS_CLKIN1 SYS_BMODE1 Ball No. P03 P06 P09 P10 P11 P12 P13 P14 P17 P20 P21 P22 R01 R02 R03 R06 R07 R16 R17 R20 R21 R22 T01 T02 T03 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T20 T21 T22 U01 U02 U03 U06 U07 U08 U09 Pin Name JTG_TDO VDD_EXT GND GND GND GND GND GND VDD_EXT DAI1_PIN01 DAI1_PIN05 DAI1_PIN03 GND PB_15 PB_14 VDD_EXT GND GND VDD_EXT DAI1_PIN08 DAI1_PIN07 DAI1_PIN06 SYS_XTAL0 SYS_BMODE2 DAI0_PIN07 VDD_EXT GND GND GND GND GND GND GND GND GND GND VDD_EXT DAI1_PIN12 DAI1_PIN10 DAI1_PIN09 SYS_CLKIN0 SYS_RESOUT PB_07 VDD_EXT VDD_EXT VDD_USB VDD_INT Rev. PrF | Ball No. U10 U11 U12 U13 U14 U15 U16 U17 U20 U21 U22 V01 V02 V03 V20 V21 V22 W01 W02 W03 W11 W12 W20 W21 W22 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Page 154 of 168 | Pin Name VDD_INT VDD_INT VDD_INT VDD_INT VDD_EXT VDD_EXT VDD_EXT VDD_EXT DAI1_PIN20 DAI1_PIN11 DAI1_PIN19 PB_13 PB_12 DAI0_PIN20 PA_00 PA_01 PA_02 PB_10 PB_11 DAI0_PIN19 VDD_INT VDD_INT PA_05 PA_03 PA_04 PB_09 PB_08 DAI0_PIN12 DAI0_PIN06 DAI0_PIN02 DAI0_PIN03 DAI0_PIN01 USB0_VBC TWI0_SCL TWI1_SDA VDD_HADC GND HADC0_VIN6 PB_06 PB_00 PB_04 PB_01 PA_10 PA_15 GND PA_06 PA_08 February 2016 Preliminary Technical Data Ball No. AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Pin Name DAI0_PIN11 GND DAI0_PIN10 DAI0_PIN04 DAI0_PIN05 USB0_ID USB0_VBUS TWI2_SCL TWI2_SDA TWI0_SDA HADC0_VIN2 HADC0_VIN5 HADC0_VIN4 HADC0_VIN7 PB_05 PB_02 PA_14 PB_03 PA_12 PA_11 GND PA_09 GND DAI0_PIN09 DAI0_PIN08 USB_CLKIN USB_XTAL USB0_DP USB0_DM TWI1_SCL HADC0_VREFP HADC0_VREFN HADC0_VIN0 HADC0_VIN1 HADC0_VIN3 MLB0_SIGP MLB0_SIGN MLB0_DATP MLB0_DATN MLB0_CLKP MLB0_CLKN PA_13 PA_07 GND Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ADSP-SC58x/ADSP-2158x 349-BALL BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME) Pin Name DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN19 DAI0_PIN20 DAI1_PIN01 DAI1_PIN02 DAI1_PIN03 DAI1_PIN04 DAI1_PIN05 DAI1_PIN06 DAI1_PIN07 DAI1_PIN08 DAI1_PIN09 DAI1_PIN10 DAI1_PIN11 DAI1_PIN12 DAI1_PIN19 DAI1_PIN20 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_A14 DMC0_A15 DMC0_BA0 DMC0_BA1 DMC0_BA2 Ball No. Y07 Y05 Y06 AA04 AA05 Y04 T03 AB03 AB02 AA03 AA01 Y03 W03 V03 P20 N21 P22 N20 P21 R22 R21 R20 T22 T21 U21 T20 U22 U20 B04 C08 B03 C05 A03 E05 A02 B01 C04 C02 C01 D01 D02 E03 E01 E02 C07 F03 D03 Pin Name DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_RESET DMC0_RZQ DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. C06 A13 A05 A12 C11 B17 A17 B16 B15 B14 B13 A14 B12 B11 A10 B10 B09 B07 A07 B06 A06 C13 A16 A15 B05 A04 F01 C09 C14 A09 A08 A11 C10 A01 A18 A22 AA02 AA21 AB01 AB22 B02 B08 B21 C03 C12 C20 H16 Rev. PrF | Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Page 155 of 168 | February 2016 Ball No. J09 J10 J11 J12 J13 J14 K08 K09 K10 K11 K12 K13 K14 K15 L08 L09 L10 L11 L12 L13 L14 L15 M08 M09 M10 M11 M12 M13 M14 M15 N08 N09 N10 N11 N12 N13 N14 N15 P09 P10 P11 P12 P13 P14 R01 R07 R16 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VIN4 HADC0_VIN5 HADC0_VIN6 HADC0_VIN7 HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST MLB0_CLKN MLB0_CLKP MLB0_DATN MLB0_DATP MLB0_SIGN MLB0_SIGP PA_00 PA_01 PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 Ball No. T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 Y12 Y20 AB11 AB12 AA11 AB13 AA13 AA12 Y13 AA14 AB10 AB09 M03 J03 P03 M02 M01 AB19 AB18 AB17 AB16 AB15 AB14 V20 V21 V22 W21 W22 W20 Y21 AB21 Y22 AA22 Y18 AA20 AA19 AB20 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Pin Name PA_14 PA_15 PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 PC_11 PC_12 PC_13 PC_14 PC_15 PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 Ball No. AA17 Y19 Y15 Y17 AA16 AA18 Y16 AA15 Y14 U03 Y02 Y01 W01 W02 V02 V01 R03 R02 N03 L01 K02 K01 G03 J01 J02 H02 H01 L03 G02 F02 G01 B18 C16 C18 A19 C15 B19 A20 C19 B20 A21 C21 B22 D21 D20 C22 D22 E21 Pin Name PD_14 PD_15 PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 SYS_BMODE0 SYS_BMODE1 SYS_BMODE2 SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT SYS_FAULT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB_CLKIN USB_XTAL VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC Rev. PrF Ball No. E22 F21 F22 G21 G22 H21 H22 J21 J22 K22 K21 L22 L21 L20 M22 M20 N22 M21 N02 P02 T02 U01 P01 C17 H03 K03 L02 U02 T01 N01 Y09 AA10 AB08 Y10 AA08 AA09 AB07 AB06 AA06 Y08 AA07 AB04 AB05 F06 F11 G06 G07 G08 | Pin Name VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_HADC VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT Page 156 of 168 | February 2016 Preliminary Technical Data Ball No. G09 G10 G11 G12 G13 G14 G15 G16 G17 H06 H07 H17 J06 J17 K17 L17 M17 N06 N17 P06 P17 R06 R17 T06 T17 U06 U07 U14 U15 U16 U17 Y11 D11 D12 E20 F07 F08 F09 F10 F12 F13 F14 F15 F16 F17 F20 G20 H20 Pin Name VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_USB Ball No. J20 K06 K20 L04 L06 L19 M04 M06 M19 U09 U10 U11 U12 U13 W11 W12 U08 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Figure 79 shows an overview of signal placement on the 349-ball CSP_BGA. TOP VIEW A1 BALL CORNER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A B C D E F GND G I/O SIGNALS H J VDD_EXT K VDD_INT L VDD_DDR M U VDD_USB N H VDD_HADC P R T U U V W Y H AA AB 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A1 BALL CORNER 1 A B C D E F G H J K L M N P R T U U V W Y H AA AB BOTTOM VIEW Figure 79. 349-Ball CSP_BGA Configuration Rev. PrF | Page 157 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data ADSP-SC58x/ADSP-2158x 529-BALL BGA BALL ASSIGNMENTS ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Numerical by Ball Number) lists the 529-ball BGA package by ball number. ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Alphabetical by Pin Name) lists the 529-ball BGA package by pin name. ADSP-SC58x/ADSP-2158x 529-BALL BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER) Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 Pin Name GND DMC0_UDQS DMC0_CK DMC0_CK DMC0_DQ09 DMC0_LDQS DMC0_LDQS DMC0_DQ05 DMC0_DQ03 DMC0_DQ01 DMC1_DQ03 DMC1_DQ00 DMC1_LDQS DMC1_LDQS DMC1_VREF DMC1_CK DMC1_CK DMC1_DQ09 DMC1_UDQS DMC1_UDQS DMC1_DQ13 DMC1_DQ15 GND DMC0_UDQS DMC0_DQ12 DMC0_DQ11 DMC0_DQ10 DMC0_DQ08 DMC0_DQ06 DMC0_DQ07 DMC0_DQ04 DMC0_DQ02 DMC0_DQ00 DMC1_DQ01 DMC1_DQ02 DMC1_DQ04 DMC1_DQ05 DMC1_DQ06 DMC1_DQ07 DMC1_DQ08 DMC1_DQ10 Ball No. B19 B20 B21 B22 B23 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 Pin Name DMC1_DQ11 DMC1_DQ12 DMC1_DQ14 PD_00 PD_04 DMC0_DQ14 DMC0_DQ13 DMC0_CS0 DMC0_CKE DMC0_LDM DMC1_RESET DMC1_A03 DMC1_A00 DMC1_A01 DMC1_A04 DMC1_A06 DMC1_BA1 DMC1_ODT DMC1_CS0 DMC1_LDM DMC1_UDM DMC1_A14 DMC1_A12 DMC1_A13 PC_13 PD_01 PD_06 PD_05 DMC0_VREF DMC0_DQ15 DMC0_BA0 DMC0_BA2 DMC0_ODT DMC0_UDM DMC1_A05 DMC1_WE DMC1_A07 DMC1_A02 DMC1_BA0 DMC1_A08 DMC1_CKE Rev. PrF | Ball No. D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 F01 F02 F03 F04 F05 F06 F07 F08 Page 158 of 168 | Pin Name DMC1_BA2 DMC1_CAS DMC1_RAS DMC1_A09 DMC1_A15 DMC1_A10 DMC1_A11 PC_14 PD_10 PD_09 DMC0_A04 DMC0_RAS DMC0_BA1 DMC0_WE DMC0_RZQ GND GND GND GND VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT DMC1_RZQ PC_15 PD_08 PD_14 PD_11 DMC0_A01 DMC0_A06 DMC0_CAS DMC0_A02 DMC0_A07 GND VDD_INT VDD_INT February 2016 Ball No. F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 H01 H02 H03 Pin Name GND VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT GND VDD_INT VDD_INT VDD_INT PE_06 PD_02 PD_13 PD_12 DMC0_A13 DMC0_A09 DMC0_A03 DMC0_A11 VDD_INT VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_INT PE_04 PE_13 PE_01 PE_00 DMC0_A14 DMC0_A12 DMC0_A05 Preliminary Technical Data Ball No. H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 K01 K02 K03 K04 Pin Name DMC0_A00 VDD_INT VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_INT SYS_CLKOUT PE_12 PE_05 PE_02 DMC0_A15 DMC0_A10 DMC0_A08 PC_08 VDD_INT VDD_DMC GND GND GND GND GND GND GND GND GND GND GND VDD_EXT PD_03 PD_07 PF_14 PF_01 PE_07 DMC0_RESET PC_11 PC_06 PC_09 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Ball No. K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 M01 M02 M03 M04 M05 Pin Name VDD_INT VDD_DMC GND GND GND GND GND GND GND GND GND GND GND VDD_EXT VDD_INT PD_15 PF_11 PF_06 PE_10 PC_04 PC_12 PC_07 PC_10 VDD_INT VDD_DMC GND GND GND GND GND GND GND GND GND GND GND VDD_EXT VDD_INT PE_03 PF_09 PE_09 PE_14 PC_01 PC_05 PC_02 SYS_FAULT VDD_INT Rev. PrF | Ball No. M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 P01 P02 P03 P04 P05 P06 Page 159 of 168 | Pin Name VDD_DMC GND GND GND GND GND GND GND GND GND GND GND VDD_EXT PE_08 PE_11 PF_03 PF_00 PF_02 JTG_TMS JTG_TRST SYS_HWRST PC_03 VDD_INT VDD_EXT GND GND GND GND GND GND GND GND GND GND GND VDD_EXT VDD_INT PE_15 PF_04 PF_05 PF_07 JTG_TDO JTG_TDI SYS_FAULT JTG_TCK VDD_INT VDD_EXT February 2016 Ball No. P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 T01 T02 T03 T04 T05 T06 T07 Pin Name GND GND GND GND GND GND GND GND GND GND GND VDD_EXT PF_10 PF_08 PF_15 PF_12 PG_00 SYS_XTAL1 SYS_BMODE1 SYS_BMODE2 SYS_BMODE0 VDD_INT VDD_EXT GND GND GND GND GND GND GND GND GND GND GND VDD_EXT VDD_INT PG_01 PG_05 PG_04 PF_13 SYS_CLKIN1 PB_15 GND PB_14 VDD_INT VDD_EXT GND ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Ball No. T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 V01 V02 V03 V04 V05 V06 V07 V08 V09 Pin Name GND GND GND GND GND GND GND GND GND GND VDD_EXT VDD_INT DAI1_PIN03 PG_03 PG_02 DAI1_PIN01 SYS_XTAL0 SYS_RESOUT PC_00 DAI0_PIN20 VDD_INT VDD_EXT GND GND GND GND GND GND GND GND GND GND GND VDD_EXT DAI1_PIN08 DAI1_PIN07 DAI1_PIN04 DAI1_PIN05 DAI1_PIN02 SYS_CLKIN0 PB_13 DAI0_PIN19 DAI0_PIN12 VDD_INT VDD_EXT VDD_PCIE_RX VDD_PCIE_TX VDD_EXT Ball No. V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Pin Name VDD_EXT VDD_EXT HADC0_VIN4 VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_INT DAI1_PIN16 DAI1_PIN06 DAI1_PIN12 DAI1_PIN09 PB_12 PB_09 DAI0_PIN18 DAI0_PIN11 VDD_INT VDD_INT VDD_PCIE VDD_INT VDD_INT VDD_INT VDD_INT HADC0_VIN6 VDD_INT VDD_RTC VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT DAI1_PIN20 DAI1_PIN11 DAI1_PIN10 DAI1_PIN13 PB_11 PB_10 DAI0_PIN17 DAI0_PIN08 DAI0_PIN05 DAI0_PIN10 USB0_ID VDD_USB USB0_VBC TWI0_SCL TWI2_SDA Rev. PrF | Ball No. Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 Page 160 of 168 | Pin Name HADC0_VIN0 HADC0_VIN7 GND PB_05 PA_14 PA_13 PA_12 PA_10 PA_00 DAI1_PIN14 DAI1_PIN17 DAI1_PIN15 PB_08 PB_07 DAI0_PIN16 DAI0_PIN07 DAI0_PIN06 DAI0_PIN01 PCIE0_REF USB1_VBUS USB0_VBUS TWI1_SCL TWI1_SDA HADC0_VIN1 HADC0_VIN5 PB_06 PB_02 PB_04 PB_03 PB_00 PA_09 PA_05 PA_01 DAI1_PIN19 DAI1_PIN18 DAI0_PIN15 DAI0_PIN14 DAI0_PIN09 DAI0_PIN13 DAI0_PIN04 DAI0_PIN02 DAI0_PIN03 USB_XTAL USB_CLKIN TWI2_SCL TWI0_SDA HADC0_VREFN HADC0_VIN2 February 2016 Preliminary Technical Data Ball No. AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Pin Name HADC0_VIN3 RTC0_XTAL MLB0_SIGN MLB0_DATN MLB0_CLKN PA_15 PA_11 PA_06 PA_04 PA_02 GND PCIE0_RXP PCIE0_RXM PCIE0_CLKM PCIE0_CLKP PCIE0_TXP PCIE0_TXM USB1_DM USB1_DP USB0_DP USB0_DM HADC0_VREFP VDD_HADC GND RTC0_CLKIN MLB0_SIGP MLB0_DATP MLB0_CLKP PB_01 PA_07 PA_08 PA_03 GND Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ADSP-SC58x/ADSP-2158x 529-BALL BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME) Pin Name DAI0_PIN01 DAI0_PIN02 DAI0_PIN03 DAI0_PIN04 DAI0_PIN05 DAI0_PIN06 DAI0_PIN07 DAI0_PIN08 DAI0_PIN09 DAI0_PIN10 DAI0_PIN11 DAI0_PIN12 DAI0_PIN13 DAI0_PIN14 DAI0_PIN15 DAI0_PIN16 DAI0_PIN17 DAI0_PIN18 DAI0_PIN19 DAI0_PIN20 DAI1_PIN01 DAI1_PIN02 DAI1_PIN03 DAI1_PIN04 DAI1_PIN05 DAI1_PIN06 DAI1_PIN07 DAI1_PIN08 DAI1_PIN09 DAI1_PIN10 DAI1_PIN11 DAI1_PIN12 DAI1_PIN13 DAI1_PIN14 DAI1_PIN15 DAI1_PIN16 DAI1_PIN17 DAI1_PIN18 DAI1_PIN19 DAI1_PIN20 DMC0_A00 DMC0_A01 DMC0_A02 DMC0_A03 DMC0_A04 DMC0_A05 Ball No. AA06 AB06 AB07 AB05 Y05 AA05 AA04 Y04 AB03 Y06 W04 V04 AB04 AB02 AB01 AA03 Y03 W03 V03 U04 T23 U23 T20 U21 U22 V21 U20 U19 V23 W22 W21 V22 W23 Y21 Y23 V20 Y22 AA23 AA22 W20 H04 F01 F04 G03 E01 H03 Pin Name DMC0_A06 DMC0_A07 DMC0_A08 DMC0_A09 DMC0_A10 DMC0_A11 DMC0_A12 DMC0_A13 DMC0_A14 DMC0_A15 DMC0_BA0 DMC0_BA1 DMC0_BA2 DMC0_CAS DMC0_CK DMC0_CKE DMC0_CK DMC0_CS0 DMC0_DQ00 DMC0_DQ01 DMC0_DQ02 DMC0_DQ03 DMC0_DQ04 DMC0_DQ05 DMC0_DQ06 DMC0_DQ07 DMC0_DQ08 DMC0_DQ09 DMC0_DQ10 DMC0_DQ11 DMC0_DQ12 DMC0_DQ13 DMC0_DQ14 DMC0_DQ15 DMC0_LDM DMC0_LDQS DMC0_LDQS DMC0_ODT DMC0_RAS DMC0_RESET DMC0_RZQ DMC0_UDM DMC0_UDQS DMC0_UDQS DMC0_VREF DMC0_WE Ball No. F02 F05 J03 G02 J02 G04 H02 G01 H01 J01 D03 E03 D04 F03 A04 C04 A03 C03 B10 A10 B09 A09 B08 A08 B06 B07 B05 A05 B04 B03 B02 C02 C01 D02 C05 A07 A06 D05 E02 K01 E05 D06 B01 A02 D01 E04 Rev. PrF | Pin Name DMC1_A00 DMC1_A01 DMC1_A02 DMC1_A03 DMC1_A04 DMC1_A05 DMC1_A06 DMC1_A07 DMC1_A08 DMC1_A09 DMC1_A10 DMC1_A11 DMC1_A12 DMC1_A13 DMC1_A14 DMC1_A15 DMC1_BA0 DMC1_BA1 DMC1_BA2 DMC1_CAS DMC1_CK DMC1_CKE DMC1_CK DMC1_CS0 DMC1_DQ00 DMC1_DQ01 DMC1_DQ02 DMC1_DQ03 DMC1_DQ04 DMC1_DQ05 DMC1_DQ06 DMC1_DQ07 DMC1_DQ08 DMC1_DQ09 DMC1_DQ10 DMC1_DQ11 DMC1_DQ12 DMC1_DQ13 DMC1_DQ14 DMC1_DQ15 DMC1_LDM DMC1_LDQS DMC1_LDQS DMC1_ODT DMC1_RAS DMC1_RESET Page 161 of 168 | February 2016 Ball No. C08 C09 D10 C07 C10 D07 C11 D09 D12 D17 D19 D20 C18 C19 C17 D18 D11 C12 D14 D15 A16 D13 A17 C14 A12 B11 B12 A11 B13 B14 B15 B16 B17 A18 B18 B19 B20 A21 B21 A22 C15 A13 A14 C13 D16 C06 Pin Name DMC1_RZQ DMC1_UDM DMC1_UDQS DMC1_UDQS DMC1_VREF DMC1_WE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. E19 C16 A20 A19 A15 D08 A01 A23 AC01 AC14 AC23 E06 E07 E08 E09 F06 F09 F16 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 L07 L08 L09 L10 L11 L12 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball No. L13 L14 L15 L16 L17 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HADC0_VIN0 HADC0_VIN1 HADC0_VIN2 HADC0_VIN3 HADC0_VIN4 HADC0_VIN5 HADC0_VIN6 HADC0_VIN7 HADC0_VREFN HADC0_VREFP JTG_TCK JTG_TDI JTG_TDO JTG_TMS JTG_TRST MLB0_CLKN MLB0_CLKP MLB0_DATN MLB0_DATP MLB0_SIGN MLB0_SIGP PA_00 PA_01 Rev. PrF Ball No. R17 T03 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 Y14 Y12 AA12 AB13 AB14 V12 AA13 W12 Y13 AB12 AC12 P04 P02 P01 N01 N02 AB18 AC18 AB17 AC17 AB16 AC16 Y20 AA21 | Pin Name PA_02 PA_03 PA_04 PA_05 PA_06 PA_07 PA_08 PA_09 PA_10 PA_11 PA_12 PA_13 PA_14 PA_15 PB_00 PB_01 PB_02 PB_03 PB_04 PB_05 PB_06 PB_07 PB_08 PB_09 PB_10 PB_11 PB_12 PB_13 PB_14 PB_15 PCIE0_CLKM PCIE0_CLKP PCIE0_REF PCIE0_RXM PCIE0_RXP PCIE0_TXM PCIE0_TXP PC_00 PC_01 PC_02 PC_03 PC_04 PC_05 PC_06 PC_07 PC_08 PC_09 PC_10 Page 162 of 168 | February 2016 Preliminary Technical Data Ball No. AB23 AC22 AB22 AA20 AB21 AC20 AC21 AA19 Y19 AB20 Y18 Y17 Y16 AB19 AA18 AC19 AA15 AA17 AA16 Y15 AA14 AA02 AA01 W02 Y02 Y01 W01 V02 T04 T02 AC04 AC05 AA07 AC03 AC02 AC07 AC06 U03 M01 M03 N04 L01 M02 K03 L03 J04 K04 L04 Pin Name PC_11 PC_12 PC_13 PC_14 PC_15 PD_00 PD_01 PD_02 PD_03 PD_04 PD_05 PD_06 PD_07 PD_08 PD_09 PD_10 PD_11 PD_12 PD_13 PD_14 PD_15 PE_00 PE_01 PE_02 PE_03 PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 PF_00 PF_01 PF_02 PF_03 PF_04 PF_05 PF_06 PF_07 PF_08 PF_09 PF_10 Ball No. K02 L02 C20 D21 E20 B22 C21 F21 J19 B23 C23 C22 J20 E21 D23 D22 E23 F23 F22 E22 K20 G23 G22 H23 L20 G20 H22 F20 J23 M19 L22 K23 M20 H21 G21 L23 N20 M22 J22 M23 M21 N21 N22 K22 N23 P20 L21 P19 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Pin Name PF_11 PF_12 PF_13 PF_14 PF_15 PG_00 PG_01 PG_02 PG_03 PG_04 PG_05 RTC0_CLKIN RTC0_XTAL SYS_BMODE0 SYS_BMODE1 SYS_BMODE2 SYS_CLKIN0 SYS_CLKIN1 SYS_CLKOUT SYS_FAULT SYS_FAULT SYS_HWRST SYS_RESOUT SYS_XTAL0 SYS_XTAL1 TWI0_SCL TWI0_SDA TWI1_SCL TWI1_SDA TWI2_SCL TWI2_SDA USB0_DM USB0_DP USB0_ID USB0_VBC USB0_VBUS USB1_DM USB1_DP USB1_VBUS USB_CLKIN USB_XTAL VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC Ball No. K21 P22 R23 J21 P21 P23 R20 T22 T21 R22 R21 AC15 AB15 R04 R02 R03 V01 T01 H20 P03 M04 N03 U02 U01 R01 Y10 AB11 AA10 AA11 AB10 Y11 AC11 AC10 Y07 Y09 AA09 AC08 AC09 AA08 AB09 AB08 G06 G07 G08 G09 G10 G11 G12 Pin Name VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_DMC VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_EXT VDD_HADC Ball No. G13 G14 G15 G16 G17 G18 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 J06 K06 L06 M06 J18 K18 L18 M18 N06 N18 P06 P18 R06 R18 T06 T18 U06 U18 V06 V09 V10 V11 V13 V14 V15 V16 V17 V18 AC13 Rev. PrF | Pin Name VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT VDD_INT Page 163 of 168 | February 2016 Preliminary Technical Data Ball No. E10 E11 E12 E13 E14 E15 E16 E17 E18 F07 F08 F10 F11 F12 F13 F14 F15 F17 F18 F19 G05 G19 H05 H19 J05 K05 K19 L05 L19 M05 N05 N19 P05 R05 R19 T05 T19 U05 V05 V19 W05 W06 W08 W09 W10 W11 W13 W15 Pin Name VDD_INT VDD_INT VDD_INT VDD_INT VDD_PCIE VDD_PCIE_RX VDD_PCIE_TX VDD_RTC VDD_USB Ball No. W16 W17 W18 W19 W07 V07 V08 W14 Y08 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Figure 80 shows an overview of signal placement on the 529-ball CSP_BGA. TOP VIEW A1 BALL CORNER 1 2 3 4 5 6 7 8 V C T W P 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A B C D E F G H J K L M N P R T U R Y U AA AB AC H 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A1 BALL CORNER 1 A B C D E F GND G I/O SIGNALS H VDD_EXT J VDD_INT K L VDD_DDR U VDD_USB R VDD_RTC P VDD_PCIE H VDD_HADC T C VDD_CORE_PCIRX U T VDD_CORE_PCITX M N P R T R C V P W Y U AA AB H AC BOTTOM VIEW Figure 80. 529-Ball CSP_BGA Configuration Rev. PrF | Page 164 of 168 | February 2016 Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 OUTLINE DIMENSIONS Dimensions for the 19 mm × 19 mm 349-ball CSP_BGA package in Figure 81 are shown in millimeters. A1 BALL CORNER 19.10 19.00 SQ 18.90 A1 BALL CORNER 22 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 A C G 16.80 BSC SQ J F H K L M N 0.80 BSC B D E P R T U W AA TOP VIEW 1.50 1.36 1.21 1.10 REF V Y AB BOTTOM VIEW DETAIL A DETAIL A 1.11 1.01 0.91 0.35 NOM 0.30 MIN SEATING PLANE 0.50 COPLANARITY 0.20 0.45 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2. Figure 81. 349-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-349-1) Dimensions shown in millimeters Rev. PrF | Page 165 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data Dimensions for the 19 mm × 19 mm 529-ball CSP_BGA package in Figure 82 are shown in millimeters. A1 BALL CORNER 19.10 19.00 SQ 18.90 A1 BALL CORNER 22 20 18 16 14 12 10 8 6 4 2 23 21 19 17 15 13 11 9 7 5 3 1 A C 17.60 REF SQ 0.80 BSC TOP VIEW 1.50 1.36 1.21 B D E F G H J K L M N P R T U V W Y AA AB AC BOTTOM VIEW 0.70 REF DETAIL A DETAIL A 1.11 1.01 0.91 0.39 0.35 0.30 SEATING PLANE 0.50 COPLANARITY 0.2 0.45 0.40 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-275-RRAB-2. Figure 82. 529-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-529-1) Dimensions shown in millimeters SURFACE-MOUNT DESIGN Table 101 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 101. CSP_BGA Data for Use with Surface-Mount Design Package Ball Attach Type Solder Mask Defined Solder Mask Defined Package BC-349-1 BC-529-1 Rev. PrF | Page 166 of 168 | Package Solder Mask Opening 0.4 mm Diameter 0.4 mm Diameter February 2016 Package Ball Pad Size 0.5 mm Diameter 0.5 mm Diameter Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587 PRE RELEASE PRODUCTS Model1 ADSP-SC584-ENG ADSP-SC589-ENG ADSP-21583-ENG Max. Core Clock 450 MHz NA 450 MHz NA 450 MHz NA Temperature Range2, 3 Package Description 349-Ball CSP_BGA 529-Ball CSP_BGA 349-Ball CSP_BGA 1 Package Option BC-349-1 BC-529-1 BC-349-1 Z =RoHS compliant part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 80 for the junction temperature (TJ) specification which is the only temperature specification. 3 These are pre production parts. See ENG-Grade agreement for details. 2 Rev. PrF | Page 167 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR13317-0-2/16(PrF) Rev. PrF | Page 168 of 168 | February 2016 Preliminary Technical Data