M MCP6546/7/8/9 Open-Drain Output Sub-Microamp Comparators Features Description • • • • • • • • • • • The Microchip Technology Inc. MCP6546/7/8/9 family of comparators is offered in single (MCP6546), single with chip select (MCP6548), dual (MCP6547) and quad (MCP6549) configurations. The outputs are open-drain and are capable of driving heavy DC or capacitive loads. Low Quiescent Current: 600 nA/comparator (typ.) Rail-to-Rail Input: V SS - 0.3V to VDD + 0.3V Open-Drain Output: VOUT ≤10V Propagation Delay 4 µs (typ.) Wide Supply Voltage Range: 1.6V to 5.5V Single available in SOT-23-5, SC-70-5 packages Available in Single, Dual and Quad Chip Select (CS) with MCP6548 Low Switching Current Internal Hysteresis: 3.3 mV (typ.) Industrial Temperature: -40°C to +85°C Typical Applications • • • • • • • • Laptop Computers Mobile Phones Metering Systems Hand-held Electronics RC Timers Alarm and Monitoring Circuits Windowed Comparators Multi-vibrators These comparators are optimized for low power, single-supply application with greater than rail-to-rail input operation. The output limits supply current surges and dynamic power consumption while switching. The open-drain output of the MCP6546/7/8/9 family can be used as a level-shifter for up to 10V using a pull-up resistor. It can also be used as a wired-OR logic. The internal Input hysteresis eliminates output switching due to internal noise voltage, reducing current draw. These comparators operate with a single-supply voltage as low as 1.6V and draw less than 1 µA/ comparator of quiescent current. The related MCP6541/2/3/4 family of comparators from Microchip has a push-pull output that supports rail-torail output swing and interfaces with CMOS/TTL logic. Related Devices • CMOS/TTL-Compatible Output: MCP6541/2/3/4 Package Types 1 8 NC 2 - 3 + 7 VDD 6 OUT OUT 1 VDD 2 VIN+ 3 5 NC 4 MCP6546 SOT-23-5, SC-70-5 - VIN+ 3 5 VDD + OUT 1 VSS 2 4 VIN– 2003 Microchip Technology Inc. MCP6547 PDIP, SOIC, MSOP OUTA VINA– V INA+ 4 VIN– VSS 5 VSS + NC VIN– VIN+ VSS MCP6546-R SOT-23-5 - MCP6546 PDIP, SOIC, MSOP 2 OUTA 1 14 OUTD 7 OUTB VINA– 2 - + + - 13 VIND– 6 VINB– VINA+ 3 VDD 4 5 VINB+ 12 VIND+ 8 VDD 1 - + 3 + - 4 MCP6548 PDIP, SOIC, MSOP NC VIN– VIN+ VSS 8 CS 1 2 - 7 VDD 3 + 6 OUT 4 MCP6549 PDIP, SOIC, TSSOP 11 VSS VINB+ 5 VINB– 6 OUTB 7 10 VINC+ - + + - 9 VINC– 8 OUTC 5 NC DS21714C-page 1 MCP6546/7/8/9 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. VDD - VSS ..............................................................7.0V Open-Drain output..................................... VSS +10.5V PIN FUNCTION TABLE All inputs and outputs ........... VSS –0.3V to VDD +0.3V Difference Input voltage ............................ |VDD - VSS| NAME FUNCTION Output Short-Circuit Current .......................continuous VIN +, VINA+, VINB+, VINC +, VIND + Non-Inverting Inputs Current at Input Pins .........................................±2 mA VIN –, VINA–, VINB–, VINC–, VIND– Inverting Inputs VDD Positive Power Supply VSS Negative Power Supply Maximum Junction Temperature (TJ) ............... +150°C OUT, OUTA, OUTB, OUTC, OUTD Outputs ESD protection on all pins (HBM;MM)..........4 kV;200V CS Chip Select NC Not Connected Current at Output and Supply Pins .................. ±30 mA Storage temperature .......................... -65°C to +150°C DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V DD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = VSS, RPU = 2.74 kΩ to VPU = VDD (Refer to Figure 1-3). Parameters Sym Min Typ Max V DD IQ VCMR Units 1.6 — 5.5 V 0.3 0.6 1 µA VSS − 0.3 — V DD + 0.3 V Conditions Power Supply Supply Voltage Quiescent Current per comparator IOUT = 0 Input Input Voltage Range Common Mode Rejection Ratio CMRR 55 70 — dB V DD = 5V, VCM = -0.3V to 5.3V Common Mode Rejection Ratio CMRR 50 65 — dB V DD = 5V, VCM = 2.5V to 5.3V Common Mode Rejection Ratio CMRR 55 70 — dB V DD = 5V, VCM = -0.3V to 2.5V Power Supply Rejection Ratio PSRR 63 80 — dB V CM = VSS mV V CM = VSS (Note 1) Input Offset Voltage VOS -7.0 ±1.5 +7.0 ∆VOS/∆TA — ±3 — VHYST 1.5 3.3 6.5 Drift with Temperature ∆VHYST/∆TA — 10 — µV/°C TA = -40°C to +25°C, VCM = VSS Drift with Temperature ∆VHYST/∆TA — 5 — µV/°C TA = +25°C to +85°C, VCM = VSS IB — 1 — pA V CM = VSS IB — — 100 pA TA = -40°C to +85°C, VCM = VSS (Note 3) Input Offset Current IOS — ±1 — pA V CM = VSS Common Mode Input Impedance ZCM — 1013||4 — Ω||pF Differential Input Impedance ZDIFF — 1013||2 — Ω||pF Drift with Temperature Input Hysteresis Voltage Input Bias Current Over Temperature µV/°C TA = -40°C to +85°C, VCM = VSS mV V CM = VSS (Note 1) Open-Drain Output Output Pull-Up Voltage VPU VDD — 10 V High-Level Output Current IOH -100 — — nA Low-Level Output Voltage VOL VSS — VSS + 0.2 V ISC — ±50 — mA COUT — 8 — pF Short-Circuit Current Output Pin Capacitance Note 1: 2: 3: (Note 2) V DD = 1.6V to 5.5V, VPU = 10V (Note 2) IOUT = 2 mA, VPU = VDD = 5V V PU = VDD = 5.0V (Note 2) The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the input-referred trip points. Do not short the output above VSS + 10V. Limit the output current to Absolute Maximum Rating of 30 mA. The comparator does not function properly when VPU < VDD. Input bias current overtemperature is not tested for the SC-70-5 package. DS21714C-page 2 2003 Microchip Technology Inc. MCP6546/7/8/9 AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V DD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, Step = 200 mV, Overdrive = 100 mV, RPU = 2.74 kΩ to VPU = VDD, and CL = 36 pF (Refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units Conditions tF — 0.7 — µs Propagation Delay (High-to-Low) tPHL — 4.0 8.0 µs Propagation Delay (Low-to-High) tPLH — 3.0 8.0 µs Propagation Delay Skew tPDS — -1.0 — µs Maximum Toggle Frequency fMAX — 225 — kHz VDD = 1.6V fMAX — 165 — kHz VDD = 5.5V EN — 200 — µV P-P Fall Time Input Noise Voltage Note 1: 2: (Note 1) (Note 1) (Notes 1 and 2) 10 Hz to 100 kHz tR and tPLH depend on the load (RL and C L); these specifications are valid for the indicated load only. Propagation Delay Skew is defined as: tPDS = tPLH - tPHL. SPECIFICATIONS FOR MCP6548 CHIP SELECT Electrical Specifications: Unless otherwise indicated, V DD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN + = VDD /2, VIN– = VSS, RPU = 2.74 kΩ to VPU = VDD , and CL = 36 pF (Refer to Figures 1-1 and 1-3). Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low V IL VSS — 0.2VDD V CS Input Current, Low ICSL — 5 — pA CS Logic Threshold, High VIH 0.8V DD — VDD V CS Input Current, High ICSH — 1 — pA CS = VDD CS Input High, VDD Current IDD — 18 — pA CS = VDD CS Input High, GND Current ISS — -20 — pA CS = VDD Comparator Output Leakage IO(LEAK) — 1 — pA VOUT = VSS+10V CS Low to Comparator Output Low Turn-on Time tON — 2 50 ms CS = 0.2VDD to VOUT = VDD/2, VIN – = VDD CS High to Comparator Output High Z Turn-off Time tOFF — 10 — µs CS = 0.8VDD to VOUT = VDD/2, VIN – = VDD VCS_HYST — 0.6 — V VDD = 5V CS Low Specifications CS = VSS CS High Specifications CS Dynamic Specifications CS Hysteresis CS VIL VIH tON VOUT ISS ICS tOFF 100 mV VIN+ = VDD/2 Hi-Z Hi-Z -20 pA, typ. VIN– -0.6 µA, typ. 1 pA, typ. -20 pA, typ. 1 pA, typ. FIGURE 1-1: Timing Diagram for the CS pin on the MCP6548. 2003 Microchip Technology Inc. 100 mV tPLH VOUT VOL FIGURE 1-2: Diagram. tPHL VOH VOL Propagation Delay Timing DS21714C-page 3 MCP6546/7/8/9 TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5L-SC-70 θJA — 331 — °C/W Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W Thermal Resistance, 8L-PDIP θJA — 85 — °C/W Thermal Resistance, 8L-SOIC θJA — 163 — °C/W Thermal Resistance, 8L-MSOP θJA — 206 — °C/W Thermal Resistance, 14L-PDIP θJA — 70 — °C/W Thermal Resistance, 14L-SOIC θJA — 120 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Note Thermal Package Resistances Note: 1.2 The MCP6546/7/8/9 operates over this extended temperature range, but with reduced performance. In any case, the Junction Temperature (TJ) must not exceed the absolute maximum specification of +150°C. Test Circuit Configuration This test circuit configuration is used to determine the AC and DC specifications. VDD VPU = VDD 200 kΩ MCP654X 200 kΩ 100 kΩ VIN = V SS RPU 2.74 kΩ VOUT 36 pF VSS = 0V FIGURE 1-3: AC and DC Test circuit for the open- drain output comparators. DS21714C-page 4 2003 Microchip Technology Inc. MCP6546/7/8/9 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = +1.6V to +5.0V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, RPU = 2.74 kΩ to V PU = VDD, and CL = 36 pF. 12% 18% 1200 Samples VCM = VSS Percentage of Occurrences Percentage of Occurrences 14% 10% 8% 6% 4% 2% -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 Input Offset Voltage (mV) 5 6 10% 8% 6% 4% 2% 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 Input Hysteresis Voltage (mV) FIGURE 2-4: Input Hysteresis Voltage Histogram at VCM = VSS. 1200 Samples VCM = VSS Percentage of Occurrences Percentage of Occurrences 12% 7 FIGURE 2-1: Input Offset Voltage Histogram at VCM = VSS . 14% 14% 0% 0% 16% 12% 10% 8% 6% 4% 2% 0% 26% 24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 Input Offset Voltage Drift (µV/°C) 300 200 100 0 -100 -200 -300 -400 -500 VDD = 1.6V VDD = 5.5V -40 -20 0 20 40 60 Ambient Temperature (°C) 80 FIGURE 2-3: Input Offset Voltage vs. Ambient Temperature at VCM = VSS . 2003 Microchip Technology Inc. 5.5 1200 Samples VCM = VSS TA = -40°C to 25°C 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Input Hysteresis Voltage Drift (µV/°C) FIGURE 2-5: Drift Histogram. 6.0 VCM = VSS TA = 25°C to 85°C 2 Input Hysteresis Voltage (mV) Input Offset Voltage (µV) FIGURE 2-2: Input Offset Voltage Drift Histogram at VCM = VSS. 500 400 1200 Samples VCM = VSS 16% Input Hysteresis Voltage VCM = VSS 5.0 4.5 VDD = 1.6V 4.0 3.5 3.0 VDD = 5.5V 2.5 2.0 1.5 -40 -20 0 20 40 60 Ambient Temperature (°C) 80 FIGURE 2-6: Input Hysteresis Voltage vs. Ambient Temperature at VCM = VSS . DS21714C-page 5 MCP6546/7/8/9 2.0 TA = -40°C 2.0 90 85 PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V 75 70 60 CMRR, VIN + = -0.3V to 2.5V, VDD = 5.0V CMRR, VIN+ = -0.3V to 5.3V, VDD = 5.0V CMRR, VIN+ = 2.5V to 5.3V, VDD = 5.0V 55 -40 -20 0 20 40 60 80 Ambient Temperature (°C) FIGURE 2-9: CMRR, PSRR vs. Ambient Temperature at VCM = VSS. DS21714C-page 6 2.0 1.8 1.6 6.0 FIGURE 2-11: Input Hysteresis Voltage vs. Common Mode Input Voltage at VDD = 5.5V. Input Current (pA) CMRR, PSRR; Input Referred (dB) FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. 65 5.5 Common Mode Input Voltage (V) Common Mode Input Voltage (V) 80 5.0 1.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -2.0 TA = 25°C 2.5 4.5 TA = -40°C 3.0 4.0 -1.5 3.5 3.5 TA = 25°C TA = 85°C 4.0 3.0 -1.0 4.5 2.5 -0.5 5.0 2.0 0.0 VDD = 5.5V 1.5 TA = 85°C 5.5 0.0 1.0 6.0 -0.5 Input Offset Voltage (mV) VDD = 5.5V 0.5 FIGURE 2-10: Input Hysteresis Voltage vs. Common Mode Input Voltage at VDD = 1.6V. Input Hysteresis Voltage (mV) FIGURE 2-7: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.6V. 1.5 1.4 Common Mode Input Voltage (V) Common Mode Input Voltage (V) 2.0 1.2 TA = -40°C 1.5 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -2.0 2.5 1.0 -1.5 3.0 0.8 TA = -40°C 1.0 -1.0 3.5 0.6 TA = 25°C TA = 25°C 4.0 0.4 0.0 -0.5 TA = 85°C 4.5 0.2 0.5 5.0 0.0 1.0 VDD = 1.6V 5.5 -0.2 TA = 85°C 6.0 0.5 VDD = 1.6V 1.5 -0.4 Input Offset Voltage (mV) 2.0 Input Hysteresis Voltage (mV) Note: Unless otherwise indicated, VDD = +1.6V to +5.0V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, RPU = 2.74 kΩ to V PU = VDD, and CL = 36 pF. 24 22 20 18 16 14 12 10 8 6 4 2 0 TA = 85°C VDD = 5.5V Input Bias Current Input Offset Current 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-12: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage at +85°C. 2003 Microchip Technology Inc. MCP6546/7/8/9 0.7 VDD = 5.5V VCM = VDD TA = +85°C 0.6 Input Bias Current Input Offset Current TA = +25°C 0.5 TA = -40°C 0.4 0.3 0.2 0.1 0.0 25 35 45 55 65 75 85 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Power Supply Voltage (V) FIGURE 2-13: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-16: Quiescent Current vs. Power Supply Voltage. 0.7 0.7 VDD = 1.6 V 0.5 0.4 0.3 0.2 VDD = 5.5V IQ does not include pull-up resistor current 0.6 0.5 0.4 0.3 Sweep VIN+, VIN– = VDD/2 Sweep VIN–, VIN+ = VDD/2 0.2 0.1 0.1 Ambient Temperature (°C) 0.4 Sweep VIN+, VIN– = VDD/2 Sweep VIN–, VIN+ = VDD/2 0.2 0.1 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 0.0 Common Mode Input Voltage (V) FIGURE 2-15: Quiescent Current vs. Common Mode Input Voltage at VDD = 1.6V. 2003 Microchip Technology Inc. Output Short Circuit Current (mA) Quiescent Current (µA/comparator) 0.5 0.3 6.0 5.5 5.0 FIGURE 2-17: Quiescent Current vs. Common Mode Input Voltage at VDD = 5V. 50 VDD = 1.6V IQ does not include pull-up resistor current 0.6 4.5 Common Mode Input Voltage (V) FIGURE 2-14: Quiescent Current vs. Ambient Temperature vs. Power Supply Voltage. 0.7 4.0 80 3.5 60 3.0 40 2.5 20 2.0 0 1.5 -20 -0.5 -40 0.5 0.0 0.0 0.0 Quiescent Current (µA/comparator) 0.6 Quiescent Current (µA/comparator) VDD = 5.5 V 1.0 22 20 18 16 14 12 10 8 6 4 2 0 -2 Quiescent Current (µA/comparator) Input Current (pA) Note: Unless otherwise indicated, VDD = +1.6V to +5.0V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, RPU = 2.74 kΩ to V PU = VDD, and CL = 36 pF. 45 40 35 -IOSC , TA = -40°C 30 -I OSC, TA = +25°C 25 20 -IOSC, TA = +85°C 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Power Supply Voltage (V) 5.0 5.5 FIGURE 2-18: Output Short-Circuit Current vs. Power Supply Voltage. DS21714C-page 7 MCP6546/7/8/9 Output Voltage Headroom (V) 0.8 Output Voltage Headroom (V) Note: Unless otherwise indicated, VDD = +1.6V to +5.0V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, RPU = 2.74 kΩ to V PU = VDD, and CL = 36 pF. VDD = 1.6V 0.7 0.6 0.5 VOL-VSS, TA = -40°C 0.4 VOL-VSS, TA = +25°C VOL-VSS, TA = +85°C 0.3 0.2 0.1 0.0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDD = 5.5V VOL-VSS, TA = -40°C VOL-VSS, TA = 25°C VOL-VSS, TA = 85°C 0 2 4 6 Output Current (mA) 408 Samples 100 mV Overdrive VCM = VDD/2 VDD = 5.5V VDD = 1.6V 0 1 2 3 4 5 6 7 High-to-Low Propagation Delay (µs) Percentage of Occurrences FIGURE 2-20: Delay Histogram. 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% 65% 60% 55% 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% 408 Samples 100 mV Overdrive VCM = VDD/2 1 408 Samples 100 mV Overdrive VCM = VDD/2 FIGURE 2-23: Delay Histogram. 8 7 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Propagation Delay Skew (µs) FIGURE 2-21: Histogram. DS21714C-page 8 3 4 5 6 7 8 Propagation Delay Skew Low-to-High Propagation 100 mV Overdrive VCM = VDD/2 6 tPHL @ VDD = 5.5V tPHL @ VDD = 1.6V 5 4 3 2 tPLH @ VDD = 5.5V 1 0 -1.5 2 Low-to-High Propagation Delay (µs) VDD = 1.6V -2.0 VDD = 5.5V VDD = 1.6V 0 8 High-to-Low Propagation VDD = 5.5V Percentage of Occurrences 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% FIGURE 2-22: Output Voltage Headroom vs. Output Current at VDD = 5.5V. Propagation Delay (µs) Percentage of Occurrences FIGURE 2-19: Output Voltage Headroom vs. Output Current at VDD = 1.6V. 8 10 12 14 16 18 20 22 Output Current (mA) -40 -20 tPLH @ VDD = 1.6V 0 20 40 60 Ambient Temperature (°C) 80 FIGURE 2-24: Propagation Delay vs. Ambient Temperature. 2003 Microchip Technology Inc. MCP6546/7/8/9 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100 VCM = VDD/2 tPHL @ 10 mV Overdrive tPLH @ 10 mV Overdrive tPLH @ 100 mV Overdrive tPLH @ 100 mV Overdrive 2.0 2.5 3.0 3.5 4.0 4.5 Power Supply Voltage (V) 5.0 tPLH @ VDD = 1.6V 10 tPLH @ VDD = 5.5V tPHL @ VDD = 1.6V 1 8 VDD = 1.6V 100 mV Overdrive 6 5 4 tPHL 3 2 tPLH 1 10 100 Input Overdrive (mV) FIGURE 2-28: Overdrive. Propagation Delay (µs) Propagation Delay vs. Input 6 5 tPHL 4 3 2 tPLH 1 tPLH @ VDD = 5.5V tPLH @ VDD = 1.6V tPHL @ VDD = 5.5V tPHL @ VDD = 1.6V 0 10 FIGURE 2-27: Capacitance. 20 30 40 50 60 70 Load Capacitance (nF) 80 90 Propagation Delay vs. Load 2003 Microchip Technology Inc. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 FIGURE 2-29: Propagation Delay vs. Common Mode Input Voltage at VDD = 5.5V. Supply Current (µA/comparator) FIGURE 2-26: Propagation Delay vs. Common Mode Input Voltage at VDD = 1.6V. 100 mV Overdrive VCM = VDD/2 1.0 -0.5 2.0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 1.8 Common Mode Input Voltage (V) Common Mode Input Voltage (V) 200 180 160 140 120 100 80 60 40 20 0 0.5 0 0 Propagation Delay (µs) 1000 VDD = 5.5V 100 mV Overdrive 7 0.0 Propagation Delay (µs) tPHL @ VDD = 5.5V 5.5 FIGURE 2-25: Propagation Delay vs. Power Supply Voltage. 7 VCM = VDD/2 1 1.5 8 Propagation Delay (µs) Propagation Delay (µs) Note: Unless otherwise indicated, VDD = +1.6V to +5.0V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, RPU = 2.74 kΩ to V PU = VDD, and CL = 36 pF. 10 IDD does not include pull-up resistor current 100 mV Overdrive VCM = VDD/2 VDD = 5.5 V 1 VDD = 1.6 V 0.1 0.1 FIGURE 2-30: Frequency. 1 10 Toggle Frequency (kHz) 100 Supply Current vs. Toggle DS21714C-page 9 MCP6546/7/8/9 VIN– = 100 mV Overdrive tPLH @ VDD = 5.5V VCM = VDD/2 VIN+ = VCM tPLH @ VDD = 1.6V 7 6 5 4 3 2 1 tPHL @ VDD = 5.5V tPHL @ VDD = 1.6V 0 0 10 20 30 40 50 60 70 80 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 VDD = 5.5V VOUT CS 90 100 0 1 2 3 4 5 6 Time (ms) Pull-up Resistor, RPU (k ) Propagation Delay vs. Pull- 100µ Comparator Turns On Here 10µ 1.E-05 Comparator Shuts Off Here 1µ 1.E-06 CS Hysteresis 100n 1.E-07 CS Low-to-High 10n 1.E-08 CS High-to-Low 1n 1.E-09 100p 1.E-10 VDD = 1.6V 100µ Comparator 0.4 0.6 0.8 1.0 1.2 1.4 Chip Select (CS) Voltage (V) 1.6 1. E-05 1µ 1. E-06 CS High-to-Low 100n CS Low-to-High 1. E-07 CS Hysteresis 10n 1. E-08 1n 1. E-09 100p 1. E-10 VDD = 5.5V Chip Select (CS) Voltage (V) 1.6 VOUT 0.0 30 CS 25 -1.6 -3.3 20 VDD = 1.6V Start-up IDD 15 Output Voltage, CS Voltage (V) 35 -4.9 -6.6 10 5 -8.2 IDD 2 3 4 5 6 7 8 9 10 11 12 -9.8 Time (1 ms/div) FIGURE 2-33: Supply Current (charging current) vs. Chip Select (CS) pulse at VDD = 1.6V (MCP6548 only). DS21714C-page 10 FIGURE 2-35: Supply Current (shoot through current) vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6548 only). Supply Current (µA/comparator) 0.2 FIGURE 2-32: Supply Current (shoot through current) vs. Chip Select (CS) Voltage at VDD = 1.6V (MCP6548 only). 1 Comparator Shuts-Off Turns-On 10µ 10p 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.E-11 Supply Current (µA/comparator) 10 1. E-11 10p 0.0 0 9 1. E-04 1.E-04 0 8 FIGURE 2-34: Chip Select (CS) Step Response (MCP6548 only). Supply Current (A/Comparator) Supply Current (A/comparator) FIGURE 2-31: up Resistor. 7 5.5 350 VOUT 0.0 300 CS 250 -5.5 VDD = 5.5V -11.0 200 Start-up IDD 150 -16.5 Charging output capacitance 100 Output Voltage, CS Voltage (V) Propagation Delay (µs) 8 Chip Select, Output Voltage (V) Note: Unless otherwise indicated, VDD = +1.6V to +5.0V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, RPU = 2.74 kΩ to V PU = VDD, and CL = 36 pF. -22.0 -27.5 50 IDD 0 0 1 2 3 4 5 6 7 8 9 10 11 12 -33.0 Time (1 ms/div) FIGURE 2-36: Supply Current (charging current) vs. Chip Select (CS) pulse at VDD = 5.5V (MCP6548 only). 2003 Microchip Technology Inc. MCP6546/7/8/9 Note: Unless otherwise indicated, VDD = +1.6V to +5.0V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND, RPU = 2.74 kΩ to V PU = VDD, and CL = 36 pF. VDD = 5.5V 6 5 Output Leakage Current (pA) Inverting Input, Output Voltage (V) 7 VOUT 4 3 2 VIN– 1 0 -1 0 1 2 3 4 5 6 7 8 Time (1 ms/div) FIGURE 2-37: The MCP6546/7/8/9 comparators show no phase reversal. 2003 Microchip Technology Inc. 9 10 500 450 400 350 300 250 200 150 100 50 0 TA = +85°C CS = VDD VIN+ = VDD/2 VIN– = VSS VDD = 1.6V VDD = 5.5V 0 1 2 3 4 5 6 7 Output Voltage (V) 8 9 10 FIGURE 2-38: Output Leakage Current (CS = VDD ) vs. Output Voltage (MCP6548 only) DS21714C-page 11 MCP6546/7/8/9 The MCP6546/7/8/9 family of push-pull output comparators are fabricated on Microchip’s state-of-theart CMOS process. They are suitable for a wide range of applications requiring very low power consumption. 3.1 Comparator Inputs The MCP6546/7/8/9 comparator family uses CMOS transistors at the input. They are designed to prevent phase inversion when the input pins exceed the supply voltages. Figure 2-37 shows an input voltage exceeding both supplies with no resulting phase inversion. The input stage of this family of devices uses two differential input stages in parallel: one operates at low input voltages and the other at high input voltages. With this topology, the input voltage is 0.3V above VDD and 0.3V below VSS. Therefore, the input offset voltage is measured at both VSS - 0.3V and VDD + 0.3V to ensure proper operation. The maximum operating input voltages that can be applied are V SS - 0.3V and VDD + 0.3V. Voltages on the inputs that exceed this absolute maximum rating can cause excessive current to flow and permanently damage the device. In applications where the input pin exceeds the specified range, external resistors can be used to limit the current below ±2 mA, as shown in Figure 3-1. RIN MCP654X VOUT VIN ( Maximum expected V ) – V IN DDR ≥ --------------------------------------------------------------------------------IN 2 mA V SS – ( Minimum expected V IN ) R IN ≥ -----------------------------------------------------------------------------2 mA FIGURE 3-1: An input resistor (RIN) should be used to limit excessive input current if either of the inputs exceeds the absolute maximum specification. 3.2 Open-Drain Output The open-drain output is designed to make levelshifting and wired-OR logic easy to implement. The output can go as high as 10V for 9V battery-powered applications. The output stage minimizes switching current (shoot-through current from supply-to-supply) when the output changes state. See Figures 2-15, 2-17 and 2-32 through 2-36, for more information. DS21714C-page 12 3.3 MCP6548 Chip Select (CS) The MCP6548 is a single comparator with a chip select (CS) option. When CS is pulled high, the total current consumption drops to 20 pA (typ). 1 pA (typ) flows through the CS pin, 1 pA (typ) flows through the output pin and 18 pA (typ) flows through the VDD pin, as shown in Figure 1-1. When this happens, the comparator output is put into a high-impedance state. By pulling CS low, the comparator is enabled. If the CS pin is left floating, the comparator will not operate properly. Figure 1-1 shows the output voltage and supply current response to a CS pulse. The internal CS circuitry is designed to minimize glitches when cycling the CS pin. This helps conserve power, which is especially important in battery-powered applications. 3.4 Externally Set Hysteresis Greater flexibility in selecting hysteresis, or input trip points, is achieved by using external resistors. Input offset voltage (VOS) is the center (average) of the (input-referred) low-high and high-low trip points. Input hysteresis voltage (VHYST) is the difference between the same trip points. Hysteresis reduces output chattering when one input is slowly moving past the other, thus reducing dynamic supply current. It also helps in systems where it is best not to cycle between states too frequently (e.g., air conditioner thermostatic control). The MCP6546/7/8/9 family has internally-set hysteresis that is small enough to maintain input offset accuracy (<7 mV), and large enough to eliminate output chattering caused by the comparator’s own input noise voltage (200 µVp-p). 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 30 VDD = 5.0V VIN+ = 2.75V 25 20 VOUT 15 10 5 Hysteresis 0 -5 -10 -15 VIN– -20 Input Voltage (10 mV/div) APPLICATIONS INFORMATION Output Voltage (V) 3.0 -25 -30 0 100 200 300 400 500 600 700 800 900 1000 Time (100 ms/div) FIGURE 3-2: The MCP6546/7/8/9 comparators’ internal hysteresis eliminates output chatter caused by input noise voltage. 2003 Microchip Technology Inc. MCP6546/7/8/9 3.4.1 INVERTING CIRCUIT Where: Figure 3-3 shows an inverting circuit for a single-supply application using three resistors, besides the pull-up resistor. The resulting hysteresis diagram is shown in Figure 3-4. VDD VPU IPU VIN IRF R2 R3 × V DD V 23 = -----------------R2 + R 3 Using this simplified circuit, the trip voltage can be calculated using the following equation: RPU VOUT MCP654X VDD R2 R3 R 23 = -----------------R2 + R 3 IOL EQUATION R 23 R F + R PU V TH L = V PU --------------------------------------- + V 23 -------------------------------------- R 23 + R F + R PU R 23 + R F + R PU RF R3 R 23 RF - + V 23 --------------------V TLH = V OL ---------------------R + R R 23 + R F 23 F VTLH = trip voltage from low to high FIGURE 3-3: hysteresis. VTHL = trip voltage from high to low Inverting circuit with Figure 2-19 and Figure 2-22 can be used to determine typical values for VOL. This voltage is dependent on the output current IOL as shown in Figure 3-3. This current can be determined using the equation below: VOUT VPU VOH Low-to-High EQUATION High-to-Low I O L = I PU + I RF VIN VOL VSS VSS VTLH VTHL PU VDD VTHL = trip voltage from high to low In order to determine the trip voltages (V THL and VTLH) for the circuit shown in Figure 3-3, R2 and R 3 can be simplified to the Thevenin equivalent circuit with respect to VDD, as shown in Figure 3-5. VPU RPU MCP654X VOUT + R 23 + R F V O H = ( V PU – V 23 ) × ------------------------------------R + R + R 23 FIGURE 3-5: RF Thevenin Equivalent Circuit. 2003 Microchip Technology Inc. F PU As explained in Section 3.1, “Comparator Inputs”, it is important to keep the non-inverting input below VDD+0.3V when VPU > VDD. 3.5 Supply Bypass With this family of comparators, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good edge rate performance. 3.6 V23 R23 F EQUATION Hysteresis diagram for the - 23 VOH can be calculated using the equation below: VTLH = trip voltage from low to high FIGURE 3-4: inverting circuit. V PU – V O L V 23 – V OL I OL = ------------------------- + ------------------------ R R +R Capacitive Loads Reasonable capacitive loads (e.g., logic gates) have little impact on propagation delay (see Figure 2-27). The supply current increases with increasing toggle frequency (Figure 2-30), especially with higher capacitive loads. DS21714C-page 13 MCP6546/7/8/9 3.7 Battery Life 3.9 In order to maximize battery life in portable applications, use large resistors and small capacitive loads. Also, avoid toggling the output more than necessary and do not use chip select (CS) to conserve power for short periods of time. Capacitive loads will draw additional power at start-up. 3.8 Typical Applications 3.9.1 PRECISE COMPARATOR Some applications require higher DC precision. An easy way to solve this problem is to use an amplifier (such as the MCP6041) to gain-up the input signal before it reaches the comparator. Figure 3-7 shows an example of this approach. PCB Surface Leakage In applications where low input bias current is critical, PCB (Printed Circuit Board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low-humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5 pA. If current-to-flow, this is greater than the MCP6546/7/8/9 family’s bias current at 25°C (1 pA, typ). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 3-6. VIN- VIN+ VSS Guard Ring VDD VREF MCP6041 VDD RPU VIN R1 R2 VREF FIGURE 3-7: Comparator. 3.9.2 Inverting Configuration (Figures 3-3 and 3-6): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the comparator (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN–) to the input pad without touching the guard ring. DS21714C-page 14 VOUT MCP6546 Precise Inverting WINDOWED COMPARATOR Figure 3-8 shows one approach to designing a windowed comparator. The wired-OR connection produces a high output (logic 1) when the input voltage is between VRB and VRT (where VRT > VRB ). VRT 1/2 MCP6547 VPU FIGURE 3-6: Example Guard Ring Layout for Inverting Circuit. 1. VPU RPU VOUT VIN VRB FIGURE 3-8: 1/2 MCP6547 Windowed comparator. 2003 Microchip Technology Inc. MCP6546/7/8/9 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 5-Lead SC-70 (MCP6546) XNN YWW A25 307 5-Lead SOT-23 (MCP6546) XXNN XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) Example: MCP6546 I/P256 0307 Example: XXXXXXXX XXXXYYWW MCP6546 I/SN0307 NNN 256 Example: 8-Lead MSOP Legend: * Example: AB37 8-Lead PDIP (300 mil) Note: Example: XXXXXX 6546I YWWNNN 307256 XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 2003 Microchip Technology Inc. DS21714C-page 15 MCP6546/7/8/9 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6549) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6549) Example: MCP6549-I/P 0307256 Example: MCP6549ISL XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6549) 0307256 Example: XXXXXXXX YYWW MCP6549I 0307 NNN 256 DS21714C-page 16 2003 Microchip Technology Inc. MCP6546/7/8/9 5-Lead Plastic Package (LT) (SC-70) E E1 D p B n 1 Q1 A2 c A A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Top of Molded Pkg to Lead Shoulder Lead Thickness Lead Width A A2 A1 E E1 D L Q1 c B MIN .031 .031 .000 .071 .045 .071 .004 .004 .004 .006 INCHES NOM 5 .026 (BSC) MAX .043 .039 .004 .094 .053 .087 .012 .016 .007 .012 MILLIMETERS* NOM 5 0.65 (BSC) 0.80 0.80 0.00 1.80 1.15 1.80 0.10 0.10 0.10 0.15 MIN MAX 1.10 1.00 0.10 2.40 1.35 2.20 0.30 0.40 0.18 0.30 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEITA (EIAJ) Standard: SC-70 Drawing No. C04-061 2003 Microchip Technology Inc. DS21714C-page 17 MCP6546/7/8/9 5-Lead Plastic Small Outline Transistor (OT) (SOT23) E E1 p B p1 n D 1 α c A φ L β Units Dimension Limits n p Number of Pins Pitch Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic MIN p1 A A2 A1 E E1 D L φ c B α β .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 A2 A1 INCHES* NOM 5 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 MAX .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 MILLIMETERS NOM 5 0.95 1.90 0.90 1.18 0.90 1.10 0.00 0.08 2.60 2.80 1.50 1.63 2.80 2.95 0.35 0.45 0 5 0.09 0.15 0.35 0.43 0 5 0 5 MIN MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091 DS21714C-page 18 2003 Microchip Technology Inc. MCP6546/7/8/9 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic § A A2 A1 E E1 D L c B1 B eB a b MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2003 Microchip Technology Inc. DS21714C-page 19 MCP6546/7/8/9 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21714C-page 20 2003 Microchip Technology Inc. MCP6546/7/8/9 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A2 A c φ A1 (F) L β Units Dimension Limits n p MIN INCHES NOM MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0° 0.08 0.22 5° 5° - MIN 8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness A1 .006 .000 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF φ Foot Angle 0° 8° c Lead Thickness .003 .006 .009 B .009 .012 .016 Lead Width α 5° 15° Mold Draft Angle Top β 5° 15° Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.10 0.95 0.15 0.80 8° 0.23 0.40 15° 15° JEDEC Equivalent: MO-187 Drawing No. C04-111 2003 Microchip Technology Inc. DS21714C-page 21 MCP6546/7/8/9 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β eB B1 p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing § eB .310 .370 .430 α Mold Draft Angle Top 5 10 15 β Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21714C-page 22 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 2003 Microchip Technology Inc. MCP6546/7/8/9 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45× c A2 A φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 2003 Microchip Technology Inc. DS21714C-page 23 MCP6546/7/8/9 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B1 α β MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21714C-page 24 2003 Microchip Technology Inc. MCP6546/7/8/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Device Temperature Range Package Examples: a) b) Device: MCP6546: Single Comparator MCP6546T: Single Comparator (Tape and Reel) (SC-70, SOT-23, SOIC, MSOP) MCP6546RT: Single Comparator (Rotated - Tape and Reel) (SOT-23 only) MCP6547: Dual Comparator MCP6547T: Dual Comparator (Tape and Reel for SOIC and MSOP) MCP6548: Single Comparator with CS MCP6548T: Single Comparator with CS (Tape and Reel for SOIC and MSOP) MCP6549: Quad Comparator MCP6549T: Quad Comparator (Tape and Reel for SOIC and TSSOP) c) d) a) b) c) Temperature Range: I = -40°C to +85°C Package: LT OT MS P SN SL ST = = = = = = = Plastic Package (SC-70), 5-lead Plastic Small Outline Transistor (SOT-23), 5-lead Plastic MSOP, 8-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead (MCP6549) Plastic TSSOP (4.4mm Body), 14-lead (MCP6549) a) b) c) MCP6546T-I/LT: Tape and Reel, Industrial Temperature, 5LD SC-70. MCP6546T-I/OT: Tape and Reel, Industrial Temperature, 5LD SOT-23. MCP6546-I/P: Industrial Temperature, 8LD PDIP. MCP6546RT-I/OT: Tape and Reel, Industrial Temperature, 5LD SOT23. MCP6547-I/MS: Industrial Temperature, 8LD MSOP. MCP6547T-I/MS: Tape and Reel, Industrial Temperature, 8LD MSOP. MCP6547-I/P: Industrial Temperature, 8LD PDIP. MCP6548-I/SN: Industrial Temperature, 8LD SOIC. MCP6548T-I/SN: Tape and Reel, Industrial Temperature, 8LD SOIC. MCP6548-I/P: Industrial Temperature, 8LD PDIP. a) MCP6549T-I/SL: b) MCP6549T-I/SL: c) MCP6549-I/P: Tape and Reel, Industrial Temperature, 14LD SOIC. Tape and Reel, Industrial Temperature, 14LD SOIC. Industrial Temperature, 14LD PDIP. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. DS21714C-page 25 MCP6546/7/8/9 NOTES: DS21714C-page 26 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. Preliminary DS21714C-page 27 M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Atlanta Unit 915 Bei Hai Wan Tai Bldg. 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A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 2003 Microchip Technology Inc.