Mitsubishi M65664FP Picture-in-picture signal processing Datasheet

MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
DESCRIPTION
APPLICATION
The M65664FP is a PIP (Picture in Picture) signal
processing LSI, whose sub-picture input is composite
signal for NTSC, PAL-M, and PAL-N. The built-in field
memory (168k-bit RAM) , V-chip data slicer and analog
circuitries lead the high quality PIP system low cost and
small size.
FEATURES
NTSC, PAL-M, PAL-N color TV
RECOMMENDED OPERATING CONDITIONS
Supply voltage range ------------------------ 3.2 ~ 3.5 V
Operating frequency ----------------------- 14.32 MHz
Operating temperature ------------------------ 0 ~ 70 deg.
Input voltage (CMOS interface) "H" ----- VDD x 0.7 ~ VDD V
"L" ----- 0 ~ VDD x 0.3 V
Output current ( output buffer ) ------------ 4 mA ( MAX )
Output load capacitance ---------------------- 20 pF ( MAX ) *1
Circuit current ----------------------------------- mA
* Internal V-chip data slicer (for sub-picture)
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS pins.
* Vertical filter for sub-picture ( Y signal )
*1 : Include pin capacitance ( 7 pF )
* Single sub-picture ( selectable picture size : 1/9 , 1/16 )
* Sub-picture processing specification ( 1/9 , 1/16 size) :
Quantization bits
Y, B-Y, R-Y : 7 bits
Horizontal sampling 229 pixels (Y), 57 pixels (B-Y, R-Y)
Vertical lines
69/ 52 lines
* Frame ( sub-picture ) on/off
* Built-in analog circuits :
One 8-bit A/D converter (for sub-picture signal)
Three 8-bit D/A converters (for Y, U and V of sub-picture)
Sync-tip-clamp, VCXO ... etc..
* IIC BUS control ( parallel/serial control) :
PIP on/off , Frame on/off ( programmable luma level),
Sub-picture size ( 1/9, 1/16 ),
PIP position ( free position ), Picture freeze ,
Y delay adjustment, Chroma level, Tint, Black level,
Contrast
...etc..
PIN CONFIGURATION (TOP VIEW)
AVss(ana)
SWM
1
42
ACK
2
41
SDATA
3
40
ADJ_Usub
Vdd(da)
SCLK
4
39
YOUT
DVdd
DVss
5
38
ADJ_Ysub
6
37
BGPS
SCK
7
36
UOUT
ADJ_Vsub
8
35
VOUT
BGPM
9
34
TESTEN
FSC
TEST5
TEST6
10
33
11
32
VD
HD
12
31
AVss(vcxo)
SWMG
RESET
DVdd
13
30
X'tal(P-N)
14
29
X'tal(P-M)
15
28
DVss
16
27
X'tal(NT)
BIAS
MCK
17
26
CSYNCS
AVss(ad)
Vrb
18
25
19
24
AVdd(ad)
20
23
Vin(Sync sepa.)
Vrt
21
22
Vin(ad)
Filter
AVdd(vcxo)
Outline 0.8mm pitch 42 Pin SOP Package
1
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
BLOCK DIAGRAM
Y OUTPUT
U OUTPUT
V OUTPUT
PIP SW
Sub picture
Main HD
Main VD
SCL
SDA
2
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
ABSOLUTE MAXIMUM RATINGS
Symbol
(VSS=0V)
Limits
Parameter
Unit
Conditions
Min.
Max.
VDD3
Supply voltage (3.3V)
-0.3
4.2
V
VI
Input voltage(except 5V input)
-0.3
VDD3+0.3
V
VI
Input voltage(5V input)
-0.3
5.25
V
VO
Output voltage
-0.3
VDD3+0.3
V
IO
Output current (*1)
IOH = -4
IOL = 4
mA
PD
Power dissipation
-
1200
mW
Topr
Operating temperature
-10
70
deg.
Tstg
Storage temperature
-50
125
deg.
(*1) Output current per output terminal. But Pd limits all current.
TYPICAL CHARACTERISTICS
THERMAL DERATING (MAXIMUM RATING)
2000
1600
1200
800
400
0
0
25
50
7075
100
125
AMBIENT TEMPERATURE Ta (deg.)
3
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
DC CHARACTERISTICS
(VSS=0V)
(Ta = 25 deg. unless otherwise noted)
Symbol
Limits
Condition
Parameter
Unit
Min.
Typ.
Max.
VIL
Input voltage
L
VDD = 2.7V
0
-
0.81
VIH
(3.3V CMOS interface)
H
VDD = 3.6V
2.52
-
3.6
IIH
Input current
L
VDD = 3.6V, VI = 0V
-10
-
10
IIL
(3.3V CMOS interface)
H
VDD = 3.6V, VI = 3.6V
-10
-
10
0.8
-
1.65
1.4
-
2.7
0.3
-
1.2
-100
-
10
-10
-
10
-
-
0.05
VTVT+
Input voltage schmitt
-
(5.0V CMOS interface)
+
Hysteresis
VH
IIH
IIL
VOL
Input current
L
VDD = 3.6V, VI = 0V
(5.0V CMOS interface)
H
VDD = 3.6V, VI = 3.6V
L
CMOS output voltage
VDD = 3.3V, |IO| = 1µA
H
VOH
IOL
CMOS output current
IOH
IOZL
VDD = 3.3V
CI
Input pin capacitance
CO
Output pin capacitance
-
-
L
VDD = 3.0V, VOL = 0.4V
4
-
-
H
VDD = 3.0V, VOH = 2.6V
-
-
-4
L
VDD = 3.6V, VO = 0V
-10
-
10
H
VDD = 3.6V, VO = 3.6V
-10
-
10
-
7
15
-
7
15
15
Output leakage current
IOZH
3.25
f = 1MHz, VDD = 0V
CIO
Bidirectional pin capacitance
-
7
IDD
Operating current
-
140
3.3V supply
V
µA
V
µA
V
mA
-
µA
pF
mA
4
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Name
I/O
CMOS
output
SWM
CMOS output
ACK
CMOS I/O(5V)*1
SDATA
SCLK
CMOS input(5V)*1
DVdd1
Digital Vdd
DVss1
Digital Vss
BGPS
CMOS output
SCK
CMOS input
BGPM
CMOS output
FSC
CMOS input
CMOS input
TEST5
TEST6
CMOS input
SWMG
CMOS input
RESET
CMOS input
Digital Vdd
DVdd2
Digital Vss
DVss2
MCK
CMOS input
CSYNCS
CMOS input
Analog Vss
AVss (ADC)
Analog
VRB
VRT
Analog
Analog
VIN (ADC)
VIN (Sync Sep.) Analog
Analog Vdd
AVdd (ADC)
AVdd (VCXO) Analog Vdd
FILTER
Analog
Analog
BIAS
Analog
X'tal (NTSC)
X'tal (PAL-M) Analog
Analog
X'tal (PAL-N)
AVss (VCXO) Analog Vss
HD
CMOS input(5V)*1
CMOS input(5V)*1
VD
TESTEN
CMOS input
Analog
VOUT
Analog
ADJ_Vsub
Analog
UOUT
Analog
ADJ_Ysub
Analog
YOUT
Analog Vdd
AVdd (DAC)
Analog
ADJ_Usub
AVss (sub)
Analog Vss
Function
PIP switch output
I2C SDA output (for high load SDA line use only)
I2C SDA input/output
I2C SCL input
Vdd for digital part
Vss for digital part
Test output
Test input
Test output
Test input
Test input
Test input
Power on reset input
Vdd for digital part
Vss for digital part
Test input
Sub picture external C-sync input
Vss for internal ADC
Low level reference voltage output of ADC
High level reference voltage output of ADC
Sub picture input of ADC
Sub picture input of sync sep. for sub picture
Vdd for internal ADC
Vdd for VCXO
VCXO filter voltage connection
VXCO bias voltage connection
X'tal of NTSC connection
X'tal of PAL-M connection
X'tal of PAL-N connection
Vss for VCXO
Main picture HD input
MAIN picture VD input
Test input
Sub picture V or B output
Referece voltage connection of DAC of V
Sub picture U or G output
Referece voltage connection of DAC of Y
Sub picture Y or R output
Vdd for DAC
Referece voltage connection of DAC of U
Vss for substrate
Remarks
connect to GND
connect to GND
connect to GND
connect to GND
connect to Vdd
connect to GND
connect to GND
*1 ) (5V)means 5V I/F torelant
5
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
Dig.
BASIC APPLICATION EXAMPLE
Digital +3.3V power supply
< NTSC only application example >
0.1µ
Sub Composite video input
Digital GND
Analog +3.3V power supply
0.01µ
Ana
.
22
21
23
20
24
19
25
18
18 pin input when CSYNC of
sub picture is fed from external
3.3V
26
17
0V
27
16
28
15
29
14
30
13
31
12
Main HD input
32
11
Main VD input
33
10
34
9
35
8
36
7
37
6
38
5
39
4
40
3
41
2
42
1
0.01µ
0.66V(max) 1.0V(max)
0.22µ
12K 5M
0.033µ
0.22µ
Analog GND
0.01µ
X1
X1 : 14.31818MHz
12~36p
5V
(3.3V recommended)
0V
5V
(3.3V recommended)
0V
Ana.
360
PIP V or B output
Ana.
0.7V (typ)
PIP U or G output
360
0.01µ
Ana.
360
0.7V (typ)
10µ
0.01µ
PIP Y or R output
0.01µ
3.3V
10K
330
IIC BUS Clock input
IIC BUS DATA input /output
PIP SW output
0V
560p
< NTSC / PAL-M / PAL-N application example >
0.01µ
0.1µ
Sub Composite video input
0.66V(max)
1M
1.0V(max) 0.01µ
0.22µ
22
21
23
20
24
19
25
18
26
17
27
16
2K
12K 5M
0.033µ
0.22µ
0.01µ
18 pin input when CSYNC of
sub picture is fed from external
3.3V
0V
X1
X1 : 14.31818MHz
X2 : 14.30244MHz
X3 : 14.328MHz
5V
(3.3V recommended)
0V
5V
(3.3V recommended)
0V
28
15
29
14
30
13
31
12
Main HD input
32
11
Main VD input
33
10
34
9
35
8
36
7
37
6
38
5
39
4
40
3
41
2
42
1
12~36p
X2 330
12~36p
X3 330
12~36p
330
Ana.
360
PIP V or B output
10µ
Ana.
0.7V (typ)
360
PIP U or G output
PIP Y or R output
0.01µ
Ana.
360
0.7V (typ)
10K
0.01µ
IIC BUS Clock input
IIC BUS DATA input /output
0.01µ
3.3V
0V
PIP SW output
6
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
M65664FP TV SYSTEM BLOCK DIARGRAM
<BASIC >
Y
Y
Y/C
Separation C
Composite
Video Signal
C
R
Y
Video
Signal
Processing
U
Matrix
B
V
M65664FP
CV
Y
C
Y/C Separated
Video Signal
Y
PIP Signal U
Processing V
G
Deflection
Unit
HD
Yoke
VD
SWM
Y
Y/C
Separation C
Composite
Video Signal
Y
R
C
Video
Signal
Processing
G
B
M65664FP
Y/C Separated
Video Signal
Y
C
CV
R
PIP Signal G
Processing B
Deflection
Unit
HD
Yoke
VD
SWM
7
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
Internal register information
address bit
symbol
DISP
00h <7>
SIZE_V
<6>
SIZE_H
<5>
WEN
<4>
BGC
<3>
<2>
BGCS
<1>
FREE_RUN
RVS
<0>
01h <7:0> VXA<7:0>
02h <7:0> HXA<7:0>
03h <7> DECODE
<6:0> CONTRAST<6:0>
KILLER
04h <7>
<6:0> U_DAC<6:0>
GRC
05h <7>
YUVN_RGB_SEL
<6>
<5:0> TINT<5:0>
06h <7:6> EXT_SC_SEL<1:0>
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
<5>
<4>
<3:0>
<7:6>
<5:0>
<7:4>
<3:0>
<7:5>
<4:0>
<7>
<6:4>
<3:0>
<7:4>
<3:0>
<7>
<6>
<5:4>
<3>
<2>
<1>
<0>
<7:6>
<5:4>
<3>
<2>
<1>
<0>
<7>
<6>
<5:0>
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Reset val.1/9 ex.
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
20h
20h
0
0
32h
0
0
32h
1
0
0
00h 00h
0h
0h
0
HIMPRV
SUBINPUT
0
HT<3:0>
EXPORT<1:0>
BG_START<5:0>
ADJ<3:0>
YDL<3:0>
0h
BGBY<2:0>
Y_OFFSET<4:0>
0
VCHIP_ONLY
0h
BGRY<2:0>
BGY<3:0>
0h
PEDESTV<3:0>
0h
PEDESTU<3:0>
0
UV_FILTER_OFF
0
SET_ACC
SYSTEM_MODE<1:0>
0h
0
SET_SIZE
SET_VCHIP
0
0
INV_UV
CROSS_SEL
0
0h
SYNC_DELAY<1:0>
DCONT<1:0>
0h
C_GAIN_SEL
0
0h
AUTOAFC
0h
SUBINPUTB
0h
CVF
0
BITSEL
0
AFCBITSEL
ACC_LEVEL<5:0>
0
AUTO_ENABLE
BURST_CLOCK_MODE 0
PALN_ENABLE
0
INV_WFF
0
INV_RFF
0
ERRSEL
0
RFF_FIX
0
0
AUTO_RFF_FIX
0
0
Ah
2h
0Eh
2h
5h
0h
0Fh
0
0h
Ch
0h
0h
0
0
0h
0
0
0
0
0h
0h
0
0h
0h
0h
0
0
15h
0
0
0
0
0
0
0
1
remarks
Sub picture display : [0] off, [1] on
Sub picture vertical size : [0] 1/9, [1] 1/16
Sub picture horizontal size : [0] 1/9, [1] 1/16
Sub picture : [0] Still, [1] Moving
Back ground display : [0] off, [1] on
Sub picture mute : [0] off, [1] on
VCXO ocsilation : [0] Lock, [1] Free run
HD/VD input synchronous mode selection : [0] sync., [1] async.
Sub picture vertical position
Sub picture horizontal position
Sub picture color decoder reset : [1] reset
Sub picture Y or R DAC output amplitude control
Sub picture color killer : [0] enable, [1] disable
Sub picture U or G DAC output amplitude control
Frame display : [0] off, [1] on
PIP output mode selection : [0] YUV, [1] RGB
Sub picture tint control
Sub picture C-Sync sep. input selection :
[0] Digital, [1] 23 pin input, [2] external (18 pin), [3] Int. analog
H jitter improvement circuit : [0] off, [1] on
Sub picture input level : [0] 33% bigger : [0] same with M65669
Sub picture display timing adjust
Ext. port (7 pin) : [0or1] Sub BGP, [2]"0" output, [3]"1" output
Sub picture BGP position setting
Main/Sub switch delay control
Sub picture Y/C delay adjust
Back ground U level setting
Sub picture Y bright control
V-chip decode mode : [0] off, [1] on
Back ground V level setting
Back ground Y level setting
Sub picture V pedestal level (2's comp)
Sub picture U pedestal level (2's comp)
Sub picture U, V output filter : [0]on, [1]off
Address 0Dh, 0Eh setting mode : [0]default, [1] enable to set
System : [0]NTSC , [1]PAL-M, [2]PAL-N, [3] N.A.
Address 11h - 14h setting mode : [0]default, [1] enable to set
Address 15h - 17h setting mode : [0]default , [1] enable to set
Invert U, V output value : [0] normal, [1] invert
Sub picture read mode : [0] pixel based, [1] H based
Sub picture sync.delay control
Sub picture digital sync sep.threshold setting
Sub picture chroma : [0] x1, [1] x2
for test : 0 set only
for test : 0 set only
Internal chroma comb filter : [0] on : [0] off
Sub picture Y clamp time constant : [0] x2, [1] x1
Sub picture AFC time constant : [0] x2, [1] x1
Sub picture color decoder amplitude
System automatic judgment : [0] off, [1] on
VCXO mode selection : [0] 1H based, [1] 2H based
Main picture PAL-N : [0] enable, [1] disable
Invert sub picture field definition : [0] normal, [1] invert
Invert main picture field definition : [0] normal, [1] invert
for test : 0 set only
Main picture field fix : [0] not fix, [1]fix
Automatic 50/60Hz Judgement : [0] enable, [1] disable
8
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
Internal register information (continuing)
address
bit
10h <7>
<6>
<5:0>
11h <7>
<6:0>
12h <7:0>
13h <7:2>
<1:0>
14h <7:6>
symbol
INVDECODE
AVERAGE
PALRY<5:0>
WDOF_KILLER_ON
HYA<6:0>
VYA<7:0>
HX<5:0>
HP<1:0>
MVC<1:0>
<5:0>
15h <7>
<6>
<5>
<4:0>
16h <7:0>
VXS<5:0>
PLUS
LINE_NUM<4:0>
STB_DLY<7:0>
remarks
Sub picture decoder mode : [0] NTSC, [1] PAL
0
0
Sub picture decoder mode : [0] 1H based, [1] 2H based
0
0
00h 00h Threshold control of ident judgment of sub picture decoder
0
0 Sub picture killer on when its vert. sync lost : [0] on, [1] off
37h Sub picture horizontal display pixel
44h Sub picture vertical display line number
1Eh Sub picture horizontal capture position (coarse)
0h 0h Sub picture horizontal capture position (fine)
0h
0h Sub picture C-sync input mask period :
0] 48us, [1] 44us, [2] 53us, [3] off
29h Sub picture sample start line
0
0 for test : 0 set only
0
0 for test : 0 set only
0
0 for test : 0 set only
11h Data slicer line selection
Data slicer start bit detection parameter
40h
Reset val. 1/9 ex.
17h <7:0> L_LEVEL<7:0>
18h <7>
<6:4>
<3:0>
19h <7:5>
EDGE_ON
BGBY_EDGE<2:0>
BGY_EDGE<3:0>
BGRY_EDGE<2:0>
<4>
HPFOFF
<3:0> FREE_RUN_ADJ<3:0>
1Ah <7:0> SUB_PALM_JDGE<7:0>
1Bh <7:6> NO_BST_LEVEL
<5:4> BW_DET_LEVEL
<3:0> HADJ<3:0>
1Ch <7> PINOE
<6:0> V_DAC<6:0>
1Dh <7:0> PINOE<7:0>
1Eh <7:0> 1Fh <7:6>
<5>
<4>
<3>
<2>
<1>
<0>
20h <7:6>
<5>
<4>
<3>
<2>
<1>
<0>
21h <7:0>
22h <7:0>
23h <7:0>
SYSTEM_STATE<1:0>
MAIN_PALN
SUB_UNLOCK
SUB_PALN
RDOF
MAIN_BW
WDOF
NOISE<1:0>
WDOF
EDS_ACK2
EDS_ACK1
SIGNAL_OK
READ_REQB
READ_REQA
PDB<15:8>
PDB<7:0>
PDA<15:8>
24h <7:0> PDA<7:0>
82h
0
0h
0
0h
0h
0h
0
0h
0h
0
0h
0h
0h
0h
0h
0
0h
0h
0h
0h
0
0h
Data slicer data slice parameter
Frame data independent control : [0] disable, [1] enable
Frame data independent B-Y data setting
Frame data independent Y data setting
Frame data independent R-Y data setting
Sub picture Y output HPF : [0]on, [1]off
Frequency adjustment control when free run mode (2's comp)
Parameter setting for PAL-M judgment
for test
for test
Parameter setting for PAL-M judgment
for test
32h Sub picture V or B DAC output amplitude control
E6h for test
No assignment
Color state : [0] NTSC, [1] PAL-M, [2] PAL-N, [3]N.A.(Read only)
Main is : [0] not PAL-N, [1] PAL-N (Read only)
VCXO is : [0] Lock, [1] Unlock (Read only)
Sub is : [0] not PAL-N, [1] PAL-N (Read only)
Main picture V sync is : [0] present, [1] not present (Read only)
Test use (Read only)
Sub picture V sync is : [0] present, [1] not present (Read only)
Test use (Read only)
Sub
picture vertical sync detection (Read only)
EDS data flag of even field : [0] no EDS, [1] EDS (Read only)
EDS data flag of odd field : [0] no EDS, [1] EDS (Read only)
Test use (Read only)
Read request of even field : [0] no, [1] requesting (Read only)
Read request of odd field : [0] no, [1] requesting (Read only)
Even field Sliced data upper 8 bit (Read only)
Even field Sliced data lower 8 bit (Read only)
Odd field Sliced data upper 8 bit (Read only)
Odd field Sliced data lower 8 bit (Read only)
9
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
The relation of input signal 32-pin (Main-HD) and 33-pin (Main-VD) is shown below
prohibition time of
changing 33-pin signal
0
32-pin input
(Main-HD)
33-pin input
(Main-VD)
[Even to Odd]
-10usec
+10usec
33-pin input
(Main-VD)
[Odd to Even]
+21.75usec
+41.75usec
+53.5usec
20us
20us
20us
20us
20us
20us
VD input
4H
1H
end of vertical equalization pulse
37.5us
20us
20us
20us
20us
20us
20us
VD input
Driving Method and Operating Specification for Serial Interface Data
(1) Serial data transmission completion and start
A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial transmission and
makes the bus free.
A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and
DATA inputs.
(2) Serial data transmission
The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-byte data
transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In
reading state, ACK is 'H' under these two conditions ; 1) the coincidence of two address data for the address data transmission, 2) the
completion of 8-bit setting data transfer. In writing state, ACK is 'H' with the address coincidence and ACK is 'L' for detecting acknowledge
input from the master (micro processor) after sending 8-bit setting data.)
For address/data transmission, DATA must change while CLK is 'L'. (The data change while CLK is 'H' or the simultaneous change of
CLK and DATA, that will be a false operation because of undistinguished condition from the completion/start of serial data transfer).
After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited.
(3) The byte format of data transmission (The sequence of data transmission)
a. The byte format during data setting to M65664FP are shown as follows.
In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal
register address (1 byte) and setting data (by 1 byte unit) are transferred successively. Several bytes of setting data can be handled in the
one transmission. In this operation, the setting data are written into the address register whose address is increased one in initially
transferred internal register address.
b. The byte format during data reading from M65664FP are shown as follows.
Before data reading from M65664FP, whose internal address need to be set by the data reading/transmitting. After the data
reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the
slave address 25h (00100101b) is sent, and then the inverted read out data are available on ACK. Several bytes of writing data can be
handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is
increased one in initially transferred internal register address.
10
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
<The examples of serial byte transmission format>
(1) The writing operation of the setting data (AAh) into M65664FP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S 24h A 00h A AAh A D E
no
S : Operation of serial transmission start
A : Acknowledge detection
D : Dummy clock feed for the release of
acknowledge output state
E : Operation of serial transmission completion
is applied
on CLk for the
release of
output state
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65664FP internal address of
04h ~ 06h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S 24h A 04h A FFh A 80h A EEh A D E
no
is applied
on CLk for the
release of
output state
(3) The reading operation of the setting data from M65664FP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S 24h A 00h A D E S 25h A $$h A'
no
is applied
on CLk for the
release of
output state
A' : Bus free operation by the
master (micro processor)
11
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
(4) The reading operation of the setting data from M65664FP internal address of
04h ~ 06h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S 24h A 04h A D E S 25h A $$h A" $$h A" $$h A'
no
is applied
on CLk for the
release of
output state
A" : Output 'L' operation by the
master (micro processor)
<Timing Diagram>
1
2
3
4
5
6
7
8
9
1
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
ACK
Detec.
Bit7
(MSB)
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
Bit7
(MSB)
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
Bit7
(MSB)
SCL
(4 pin)
SDA
(3 pin)
SDA (Read data)
(3 pin)
ACK
(2 pin)
ACK (Read data)
(2 pin)
12
G
Z1
E
HE
e
1
42
z
EIAJ Package Code
SSOP42-P-450-0.80
Detail G
D
y
JEDEC Code
–
b
Weight(g)
0.63
21
22
Lead Material
Alloy 42/Cu Alloy
L1
MMP
Detail F
A2
A
A1
F
c
L
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
Symbol
e1
b2
e1
I2
b2
Dimension in Millimeters
Min
Nom
Max
2.4
–
–
–
–
0.05
–
2.0
–
0.5
0.4
0.35
0.2
0.15
0.13
17.7
17.5
17.3
8.6
8.4
8.2
–
0.8
–
12.23
11.93
11.63
0.7
0.5
0.3
–
1.765
–
–
0.75
–
–
–
0.9
0.15
–
–
0∞
–
10∞
–
0.5
–
–
11.43
–
–
–
1.27
Recommended Mount Pad
e
Plastic 42pin 450mil SSOP
I2
42P2R-A
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
DETAILED DIAGRAM OF PACKAGE OUTLINE
13
MITSUBISHI DIGITAL TV ICs
M65664FP
PICTURE-IN-PICTURE
SIGNAL PROCESSING
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reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may
lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your
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14