ON MT9V138 Inch color cmos ntsc/pal digital image soc with overlay processor Datasheet

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MT9V138:1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Features
1/4-Inch Color CMOS NTSC/PAL Digital Image SOC
with Overlay Processor
MT9V138 Datasheet, Rev. D
For the latest datasheet, please visit www.onsemi.com
Features
Table 1:
• Low-power CMOS image sensor with integrated
image flow processor (IFP) and video encoder
• 1/4-inch optical format, VGA resolution (640H x
480V)
• ±2.5% additional columns and rows to compensate
for lens alignment tolerances
• Overlay generator for dynamic bitmap overlay
• Integrated video encoder for NTSC/PAL with overlay
capability and 10-bit I-DAC
• Integrated microcontroller for flexibility
• On-chip image flow processor performs
sophisticated processing, such as color recovery and
correction, sharpening, gamma, lens shading
correction, on-the-fly defect correction, auto white
balancing, and auto exposure
• Auto black level calibration
• 10-bit, on-chip analog-to-digital converter (ADC)
• Internal master clock generated by on-chip phaselocked loop (PLL)
• Two-wire serial programming interface
• Interface to low-cost Flash through SPI bus
• High-level host command interface
• Stand alone operation support
• Comprehensive tool support for overlay generation
and lens correction setup
• Development system with DevWare
• Overlay generation and compilation tools
Key Parameters
Parameter
Typical Value
Pixel size
and type
5.6 m x 5.6 m active pinnedphotodiode with high-sensitivity mode
for low-light conditions
Sensor format
680H x 512V (includes ±2.5% of rows
and columns for lens alignment)
NTSC output
720H x 480V
PAL output
720H x 576V
Imaging area
Total array size: 3.584 mm x 2.688 mm
Optical format
¼-inch
Frame rate
50/60 fields/sec
Sensor scan mode
Progressive scan
Color filter array
RGB standard Bayer
Shutter type
Electronic rolling shutter (ERS)
Automatic
Functions
Exposure, white balance, black level
offset correction, flicker avoidance,
color saturation control, on-the-fly
defect correction, aperture correction
Programmable
Controls
Exposure, white balance, horizontal
and vertical blanking, color, sharpness,
gamma correction, lens shading
correction, horizontal and vertical
image flip, windowing, sampling rates,
GPIO control
Key parameters are continued on next page.
See details of new features on page 3.
Applications
See “Ordering Information” on page 3.
• Analog surveillance CCTV
• Surveillance network IP camera
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC 2015,
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Applications
Table 2:
Key Parameters (continued)
Parameter
Typical Value
Overlay Support1
Utilizes SPI interface to load overlay data from external flash/EEPROM memory with the
following features:
•Overlay Size 360 x 480 pixel rendered into 720 x 480 pixel display format
•Up to four (4) overlays may be blended simultaneously
•Selectable readout: Rotating order user selected
•Dynamic scenes by loading pre-rendered frames from external memory
•Palette of 32 colors out of 64,000
•8 colors per bitmap
•Blend factor dynamically programmable for smooth transitions
•Fast Update rate of up to 30 fps
•Every bitmap object has independent x/y position
•Statistic Engine to calibrate optical alignment
•Number Generator
Windowing
Programmable to any size
Max analog gain
0.5–16x
ADC
10-bit, on-chip
Output interface
Analog composite video out, single-ended or differential; 8-, 10-bit parallel digital
output
Output data formats1
Digital: Raw Bayer 8-,10-bit, CCIR656, 565RGB, 555RGB, 444RGB
Parallel: 27 MB/s
NTSC: 60 fields/sec
Data rate
PAL: 50 fields/sec
Control interface
Two-wire I/F for register interface plus high-level command exchange. SPI port to
interface to external memory to load overlay data, register settings, or firmware
extensions.
Input clock for PLL
27 MHz
SPI Clock Frequencies
4.5 - 9.0 - 18 MHz, programmable
Analog: 2.8 V ±5%
Core: 1.8 V ±5%
Supply voltage
IO: 2.8V ±5%
Full resolution at 60 fps: <350mW2
Power consumption
Package
48-pin Ceramic LCC, 11.43mm x 11.43mm, 0.8mm pitch
Operating: –30°C to 70°C
Ambient temperature
Storage: –50°C to +150°C
Dark Current
< 200e/s at 60°C with a gain of 1
Column
Fixed pattern noise
Row
< 2%
< 2%
Responsivity
15.8 V/lux-s at 550nm
Signal to noise ratio (S/N)
46 dB
Pixel dynamic range
74.8 dB
Notes:
MT9V138 DS Rev. D Pub. 5/15 EN
1. Graphical overlay is available only in CCIR656 output format.
2. Analog output enabled; parallel output disabled.
2
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
New Features
New Features
Integrated Video Encoder for PAL/NTSC with Overlay Capability
• Composite analog output (NTSC/PAL)
• 8-bit parallel digital output ITU-R BT.656 format
• Raw Bayer format
On-Chip Overlay Generator
•
•
•
•
•
•
Static and dynamic overlay graphics with four overlay planes plus number plane
Support for serial SPI memory up to 16 megabytes
Number generator
Overlay blending and x/y positioning
Overlay position adjustment and statistics engine to calibrate overlay
Overlay support utilizes SPI interface to load overlay data from external
Serial Flash/EEPROM to support the following features:
– Overlay size 360 x 480 pixel rendered into 720 x 480 pixel display format
– Up to four overlays may be blended simultaneously
– Selectable readout: rotating order user selected
– Dynamic scenes by loading pre-rendered frames from external memory
– Palette of 32 colors out of 64,000
– Eight colors per bitmap
– Blend factor dynamically programmable for smooth transitions
– Fast update rate of up to 30 fps
– Every bitmap object has independent x/y position
– Statistics engine to calibrate optical alignment
–
Ordering Information
Table 3:
Available Part Numbers
Part Number
Product Description
Orderable Product Attribute Description
MT9V138C12STC-DP
VGA 1/4" SOC
Dry Pack with Protective Film
MT9V138C12STC-DR
VGA 1/4" CIS SOC
Dry Pack without Protective Film
MT9V138D00STCK22BC1-200
VGA 1/4" SOC
Die Sales, 200m Thickness
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Descriptions and Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
SOC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Sensor Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Usage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
External Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Slave Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Overlay Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Serial Memory Partition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Overlay Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Overlay Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Figures
List of Figures
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Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Using a Crystal Instead of an External Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Image Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Sensor Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Pixel Color Pattern Detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Color Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Color Bar Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Gamma Correction Curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Auto-Config Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Flash Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Host Mode with Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
External Signal Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Power-Up Sequence – Configuration Options Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Interface Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Single Read from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Overlay Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Memory Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Overlay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Internal Block Diagram Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Example of Character Descriptor 0 Stored in ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Full Character Set for Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Single-Ended Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Differential Connection—Grounded Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems . . . . . . . . . . . . . . . . . . . .52
Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .53
Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .54
Primary Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Typical I/O Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
NTSC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Slew Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Reset to SPI Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Reset to Serial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Reset to AE/AWB Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SPI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Equivalent Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
V Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Figures
Figure 57:
48-Pin CLCC Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Tables
List of Tables
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Table 47:
Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Parameters (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reset/Default State of Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
EIA Color Bars (NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
EBU Color Bars (PAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
YCbCr Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
RGB Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2-Byte Bayer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SPI Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
SPI Commands Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
GPIO Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
System Manager Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Overlay Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
GPIO Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Flash Manager Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Sequencer Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
TX Manager Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Two-Wire Interface ID Address Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Transfer Time Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Character Generator Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Field, Vertical Blanking, EAV, and SAV States 525/60 Video System . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System . . . . . . . . . . . . . . . . . . . . . . . . .54
Output Data Ordering in DOUT RGB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Output Data Ordering in Sensor Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Parallel Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Slew Rate for PIXCLK and DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
RESET_BAR Delay Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SPI Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Video DAC Electrical Characteristics–Single-Ended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Video DAC Electrical Characteristics–Differential Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Digital I/O Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Power Consumption – Condition 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Power Consumption – Condition 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
NTSC Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Equivalent Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
V Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
General Description
General Description
The ON Semiconductor MT9V138 is a VGA-format, single-chip CMOS active-pixel
digital image sensor for surveillance applications. It captures high-quality color images
at VGA resolution and outputs NTSC or PAL interlaced composite video.
The VGA CMOS image sensor features ON Semiconductor’s breakthrough low-noise
CMOS imaging technology that achieves near-CCD image quality (based on signal-tonoise ratio and low-light sensitivity) while maintaining the inherent size, cost, low
power, and integration advantages of ON Semiconductor's advanced active pixel CMOS
process technology.
The MT9V138 is a complete camera-on-a-chip. It incorporates sophisticated camera
functions on-chip and is programmable through a simple two-wire serial interface or by
an attached SPI Flash memory that contains setup information that may be loaded automatically at startup.
The MT9V138 performs sophisticated processing functions including color recovery,
color correction, sharpening, programmable gamma correction, auto black reference
clamping, auto exposure, 50Hz/60Hz flicker avoidance, lens shading correction, auto
white balance (AWB), and on-the-fly defect identification and correction.
The MT9V138 outputs interlaced-scan images at 30 or 25 fps, supporting both NTSC and
PAL video formats. The image data can be output on one or two output ports:
• Composite analog video (single-ended and differential output support)
• Parallel 8-, 10-bit digital
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Architecture
Architecture
Internal Block Diagram
Figure 1:
Internal Block Diagram
SPI
2. 8 V
Two-Wire I/F
4
1. 8 V
2
Camera Control
SPI &2W I/F
Interface
AW B
AE
640 x 480
Active Array
¼ ” VG A R O I
@ 6 0 F r a m e/ss
C o lo r & G a m m a C o r r e ctio n
C o lo r Sp a ce C o n ve r sio n
Ed g e En h a n ce m e n t
Le ns S ha ding
C orrection
Image Flow Processor
10
O ve r la y
G r a p h ics
G e n e r a tio n
VideoEncoder
DAC
Note:
MT9V138 DS Rev. D Pub. 5/15 EN
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BT-656
N T SC/
PAL
The active array is smaller than the sensor array.
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
System Block Diagram
System Block Diagram
The system block diagram will depend on the application. The system block diagram in
Figure 2 shows all components; optional peripheral components are highlighted. The
optional microcontroller controls the MT9V138 sensor using the two-wire serial bus.
Optional components will vary by application. For further details, see the MT9V138
Register and Variable Reference.
Figure 2:
System Block Diagram
27 MHz
EXTCLK
XTAL
RESET_BAR
μC
Serial Data
Flash
10Kb - 16 MB
SPI
2WIRE I/F
LP Filter
DAC _POS
4.7 kΩ
DAC _REF
Composite
Video
PAL /NTSC
DAC _NEG
75Ω
VDD_DAC (2.8V)
VDD_PLL (2.8V)
Optional
VDD_IO (2.8V)
2.8V
VAA_PIX (2.8V)
VAA (2.8V )
LDO
VDD (1.8V )
DOUT [7:0]
DOUT_LSB0,1
CCIR 656/
GPO
PIXCLK
FRAME _VALID
LINE _VALID
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
System Block Diagram
Crystal Usage
As an alternative to using an external oscillator, a fundamental 27 MHz crystal may be
connected between EXTCLK and XTAL. Two small loading capacitors of 15–22pF of NPO
dielectric should be added as shown in Figure 3.
ON Semiconductor does not recommend using the crystal option for applications
above 85°C. A crystal oscillator with temperature compensation is recommended.
Figure 3:
Using a Crystal Instead of an External Oscillator
Sensor
18 pF - NPO
EXTCLK
27.000 MHz
XTAL
18pF - NPO
When using Xtal as the clock source, the internal inverter circuit has a 100K bias resistor
in parallel to Xtal, which can be connected or disconnected by register 0x0014 bit[14].
The clockin_bias_en bit is set to 1 by default.
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Pin Descriptions and Assignments
Table 4:
Pin Descriptions
Pin Number
Pin Name
Type
Description
Clock and Reset
9
EXTCLK
Input
10
XTAL
Output
12
RESET_BAR
Input
Master input clock (27MHz): This either can be a square-wave generated from
an oscillator (in which case the XTAL input must be left unconnected) or
connected directly to a crystal.
If EXTCLK is connected to one pin of a crystal, this signal is connected to the
other pin; otherwise this signal must be left unconnected.
Asynchronous active-low reset: When asserted, the device will return all
interfaces to their reset state. When released, the device will initiate the boot
sequence.
Register Interface
17
18
16
SCLK
SDATA
SADDR
Input
Input/OD
Input
These two signals implement serial communications protocol for access to
the internal register set and memory.
This signal controls the device ID that will respond to serial communication
commands.
Two-wire serial interface device ID selection:
0: 0x90
1: 0xBA
SPI Interface
22
SPI_SCLK
Output
Clock output for interfacing to an external SPI memory such as Flash/
EEPROM. Tristated when RESET_BAR is asserted.
21
SPI_SDI
Input
20
SPI_SDO
Output
Data in from SPI device. This signal has an internal pull-up resistor.
Data out to SPI device. Tristated when RESET_BAR is asserted.
19
SPI_CS_N
Output
Chip selects to SPI device. Tristated when RESET_BAR is asserted.
(Parallel) Pixel Data Output
32
31
33
39, 40, 41,
42, 43, 44,
45, 46
FRAME_VALID
LINE_VALID
PIXCLK
DOUT[7:0]
Input/Output
Input/Output
Output
Output
Pixel data from the MT9V138 can be routed out on this interface and
processed externally.
To save power, these signals are driven to a constant logic level unless the
parallel pixel data output or alternate (GPIO) function is enabled for these
pins.
This interface is disabled by default.
The slew rate of these outputs is programmable.
These signals can also be used as general purpose input/outputs.
38
37
DOUT_LSB1
DOUT_LSB0
Input/Output
Input/Output
When the sensor core is running in bypass mode, it will generate 10 bits of
output data per pixel. These two pins make the two LSB of pixel data
available externally. Leave DOUT_LSB1 unconnected if not used. To save
power, these signals are driven to a constant logic level unless the sensor core
is running in bypass mode or the alternate function is enabled for these pins.
The slew rate of these outputs is programmable. For analog output, the
DOUT_LSB0 cannot be left unconnected, and must be strapped to select either
NTSC or PAL mode. For more information, see Table 15, “GPIO Bit
Descriptions,” on page 33.
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Table 4:
Pin Descriptions (continued)
Pin Number
Pin Name
Type
Description
Composite Video Output
6
DAC_POS
Output
Positive video DAC output in differential mode.
Video DAC output in single-ended mode.
This interface is enabled by default using NTSC/PAL signaling. For
applications where composite video output is not required, the video DAC can
be placed in a power-down state under software control.
4
DAC_NEG
Output
Negative video DAC output in differential mode. Connect to AGND in singleended mode.
2
DAC_REF
Output
External reference resistor for the video DAC.
Manufacturing Test Interface
27
TDI
Input
JTAG Test pin (Reserved for Test Mode)
26
TDO
Output
JTAG Test pin (Reserved for Test Mode)
25
TMS
Input
JTAG Test pin (Reserved for Test Mode)
24
TCK
Input
JTAG Test pin (Reserved for Test Mode)
23
TRST_N
Input
Connect to GND
8, 14, 35, 48
DGND
Supply
Digital ground.
Video DAC GND
Power
3
GND_DAC
Supply
1, 7, 15, 34
VDD
Supply
Supply for VDD core: 1.8V nominal.
13, 36, 47
VDD_IO
Supply
Supply for digital IOs: 2.8V nominal.
Supply for video DAC: 2.8V nominal.
5
VDD_DAC
Supply
11
VDD_PLL
Supply
Supply for PLL: 2.8V nominal.
29
AGND
Supply
Analog ground.
28
VAA
Supply
Analog power: 2.8V nominal.
30
VAA_PIX
Supply
Analog pixel array power: 2.8V nominal. Must be at same voltage potential as
VAA.
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Pin Assignments
Table 5:
1
DOUT3
VDD
2
DOUT2
DAC_REF
3
DOUT1
GND_DAC
4
DOUT0
DAC_NEG
5
VDD-IO
VDD_DAC
6
GND
DAC_POS
Pin Assignments
48
47
46
45
44
43
10
39
DOUT7
VDD_PLL
11
38
DOUT_LSB1
RESET_BAR
12
37
DOUT_LSB0
VDD_IO
13
36
VDDIO
GND
14
35
GND
VDD
15
34
VDD
SADDR
16
33
PIXCLK
SCLK
17
32
FRAME_VALID
SDATA
18
31
LINE_VALID
20
21
22
23
24
25
26
27
28
29
30
VAA_PIX
19
VAA
XTAL
AGND
DOUT6
TDI
EXTCLK
TDO
DOUT5
40
TMS
41
9
TCK
GND
TRST_N
DOUT4
SPI_SDI
42
8
SPI_CLK
7
SPI_SD0
VDD
SPI_CS_N
Figure 4:
Reset/Default State of Interfaces
Name
Reset State
Default State
Notes
EXTCLK
Clock running or stopped
Clock running
Input
XTAL
N/A
N/A
Input
RESET_BAR
Asserted
De-asserted
Input
SCLK
N/A
N/A
SDATA
High impedance
High impedance
SADDR
N/A
N/A
Input. Must always be driven to a valid logic
level.
Input/Output. A valid logic level should be
established by pull-up resistor.
Input. Must always be driven to a valid logic
level. Must be permanently tied to VDD_IO or
GND.
SPI_SCLK
High impedance.
Driven, logic 0
Output. Output enable is R0x0032[9].
SPI_SDI
Internal pull-up enabled.
Internal pull-up enabled
Input. Internal pull-up is permanently
enabled.
SPI_SDO
High impedance
Driven, logic 0
Output enable is R0x0032[9].
SPI_CS_N
High impedance
Driven, logic 1
Output enable is R0x0032[9].
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Table 5:
Reset/Default State of Interfaces (continued)
Name
Reset State
Default State
FRAME_VALID
LINE_VALID
High impedance
High impedance
PIXCLK
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
DOUT_LSB1
DOUT_LSB0
High impedance
Driven, logic 0
Notes
Input/Output. This interface disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can
be left unconnected (floating). After reset,
these pins are powered up, sampled, then
powered down again as part of the autoconfiguration mechanism. See Note 2.
Output. This interface disabled by default.
See Note 1.
High impedance
High impedance
High impedance
Driven, logic 0
Input/Output. This interface disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can
be left unconnected (floating). After reset,
these pins are powered-up, sampled, then
powered down again as part of the autoconfiguration mechanism. For analog output,
the DOUT_LSB0 cannot be left unconnected,
and must be strapped to select either NTSC or
PAL mode
DAC_POS
DAC_NEG
DAC_REF
TDI
High impedance
Driven
Output. Interface disabled by hardware reset
and enabled by default when the device starts
streaming.
Internal pull-up enabled
Internal pull-up enabled
Input. Internal pull-up means that this pin can
be left unconnected (floating).
TDO
High impedance
High impedance
Output. Driven only during appropriate parts
of the JTAG shifter sequence.
TMS
Internal pull-up enabled
Internal pull-up enabled
Input. Internal pull-up means that this pin can
be left unconnected (floating).
TCK
Internal pull-up enabled
Internal pull-up enabled
Input. Internal pull-up means that this pin can
be left unconnected (floating).
TRST_N
N/A
N/A
Notes:
MT9V138 DS Rev. D Pub. 5/15 EN
Input. Must always be driven to a valid logic
level. Must be driven to GND for normal
operation.
1. The reason for defining the default state as logic 0 rather than high impedance is this: when wired
in a system (for example, on our demo boards), these outputs will be connected, and the inputs to
which they are connected will want to see a valid logic level. No current drain should result from
driving these to a valid logic level (unless there is a pull-up at the system level).
2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore,
they can be left floating but they will not drive a valid logic level to an attached device.
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
SOC Description
SOC Description
Detailed Architecture Overview
Sensor Core
The sensor consists of a pixel array, an analog readout chain, a 10-bit ADC with programmable
gain and black offset, and timing and control as illustrated in Figure 5.
Figure 5:
Sensor Core Block Diagram
Active Pixel
Sensor (APS)
Array
Control Register
Communication
Bus
to IFP
Timing and Control
Clock
Sync
Signals
Analog Processing
10-Bit Data
to IFP
ADC
Pixel Array Structure
The sensor core pixel array is configured as 744 columns by 512 rows, as shown in
Figure 6. This includes black rows and columns.
Figure 6:
Pixel Array Description
black rows
Pixel logical address = (0, 0)
black columns
Active pixel array
640 x 480
active border columns
black columns
Pixel logical address = (743, 511)
active border columns
active border rows
active border rows
black row
(not to scale)
The black row data are used internally for the automatic black level adjustment.
However, these black rows can also be read out by setting the sensor to raw data output
mode.
There are 744 columns by 512 rows of optically-active pixels that include a pixel
boundary around the VGA (640 x 480) image to avoid boundary effects during color
interpolation and correction.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
SOC Description
The one additional active column and two additional active rows are used to enable
horizontally and vertically mirrored readout to start on the same color pixel.
Figure 7 illustrates the process of capturing the image. The original scene is flipped and
mirrored by the sensor optics. Sensor readout starts at the lower right corner. The image
is presented in true orientation by the output display.
Figure 7:
Image Capture Example
SCENE
(Front view)
fI
so
es
oc
Pr
e
ag
m
in
er
th
Ga
OPTICS
g
d
an
e
IMAGE CAPTURE
ag
Im
IMAGE SENSOR
(Rear view)
isp
D
Row by Row
y
la
Start Rasterization
Start Readout
IMAGE RENDERING
DISPLAY
(Front view)
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Sensor Pixel Array
The active pixel array is 640 x 480 pixels. In addition, there are rows and columns for lens
alignment and demosaic.
Not shown in Figure 8 are pixels for black level calibration.
Figure 8:
Sensor Pixel Array
Lens Alignment Pixels - 12 Rows
Demosaic Pixels - 4 Columns
Active Pixels
640 Rows, 480 Columns
Lens Alignment Pixels - 16 Columns
Demosaic Pixels - 4 Columns
Lens Alignment Pixels - 16 Columns
Demosaic Pixels - 4 Rows
Demosaic Pixels - 4 Rows
Lens Alignment Pixels - 12 Rows
The range of adjustment is from Row 0 to 22 and Column 0 to 30. There are 4 rows/
columns needed to calculate the RGB values. The window should be moved only at even
numbers.
Figure 9:
Pixel Color Pattern Detail (top right corner)
Column Readout Direction
..
.
Row
Readout
Direction
MT9V138 DS Rev. D Pub. 5/15 EN
...
Black Pixels
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
18
First Active
Border
Pixel
(64, 0)
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Output Data Format
The sensor core image data are read out in progressive scan order. Valid image data are
surrounded by horizontal and vertical blanking, shown in Figure 10.
For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size
is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of
the image field.
For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical
size is 288 pixels per field.
Figure 10:
Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n
P2,0 P2,1 P2,2.....................................P2,n-1 P2,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Valid Image Odd Field
Horizontal
Blanking
Pm-2,0 Pm-2,1.....................................Pm-2,n-1 Pm-2,n 00 00 00 .................. 00 00 00
Pm,0 Pm,1.....................................Pm,n-1 Pm,n
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Vertical Even Blanking
Vertical/Horizontal
Blanking
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n
P3,0 P3,1 P3,2.....................................P3,n-1 P3,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Valid Image Even Field
Horizontal
Blanking
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00
Pm+1,0 Pm+1,1..................................Pm+1,n-1 Pm+1,n 00 00 00 .................. 00 00 00
MT9V138 DS Rev. D Pub. 5/15 EN
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Vertical Odd Blanking
Vertical/Horizontal
Blanking
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Image Flow Processor
Image and color processing in the MT9V138 are implemented as an image flow
processor (IFP) coded in hardware logic. During normal operation, the embedded
microcontroller will automatically adjust the operation parameters. The IFP is broken
down into different sections, as outlined in Figure 11.
Figure 11:
Color Pipeline
RAW 10
Pixel Array
ADC
Raw Data
IFP
Test Pattern
Generator
MUX
Black
Level
Subtraction
Digital Gain Control
Lens Shading
Correction
Defect Correction,
Noise Reduction,
Color Interpolation
Statistics
Engine
8-bit
RGB
RGB to YUV
10/12-Bit
RGB
8-bit
YUV
Color Correction
Color Kill
Aperture
Correction
Output
Formatting
YUV to RGB
Gamma
Correction
(12-to-8 Lookup)
Output
Interface
Analog Output Mux
NTSC/PAL
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Parallel Output Mux
Parallel
Output
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Test Patterns
During normal operation of the MT9V138, a stream of raw image data from the sensor
core is continuously fed into the color pipeline. For test purposes, this stream can be
replaced with a fixed image generated by a special test module in the pipeline. The
module provides a selection of test patterns sufficient for basic testing of the pipeline.
Test patterns are accessible by programming a register and are shown in Figure 12. ON
Semiconductor recommends disabling the MCU before enabling test patterns.
Figure 12:
Color Bar Test Pattern
Example
Test Pattern
Flat Field
Vertical Ramp
Color Bar
Vertical Stripes
Pseudo-Random
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
NTSC/PAL Test Pattern Generation
There is a built-in standard EIA (NTSC) and EBU (PAL) color bars to support hue and
color saturation characterization. Each pattern consists of seven color bars (white,
yellow, cyan, green, magenta, red, and blue). The Y, Cb and Cr values for each bar are
detailed in Tables 6 and 7.
The test pattern is invoked through a Host Command call to the TX Manager. See the
MT9V138 Host Command Specification.
Figure 13:
Color Bars
Table 6:
EIA Color Bars (NTSC)
Y
Cb
Cr
Table 7:
Y
Cb
Cr
Nominal Range
White
Yellow
Cyan
Green
Magenta
Red
Blue
16 to 235
16 to 240
16 to 240
180
128
128
162
44
142
131
156
44
112
72
58
84
184
198
65
100
212
35
212
114
EBU Color Bars (PAL)
Nominal Range
White
Yellow
Cyan
Green
Magenta
Red
Blue
16 to 235
16 to 240
16 to 240
235
128
128
162
44
142
131
156
44
112
72
58
84
184
198
65
100
212
35
212
114
CCIR-656 Format
The color bar data is encoded in 656 data streams. The duration of the blanking and
active video periods of the generated 656 data are summarized in the following tables.
Table 8:
NTSC
Line Numbers
Field
Description
1-3
2
Blanking
4-19
1
Blanking
20-263
1
Active video
264-265
1
Blanking
266-282
2
Blanking
283-525
2
Active Video
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Table 9:
PAL
Line Numbers
Field
1-22
1
Description
Blanking
23-310
1
Active video
311-312
1
Blanking
313-335
2
Blanking
336-623
2
Active video
624-625
2
Blanking
Black Level Subtraction and Digital Gain
Image stream processing starts with black level subtraction and multiplication of all
pixel values by a programmable digital gain. Both operations can be independently set
to separate values for each color channel (R, Gr, Gb, B). Independent color channel
digital gain can be adjusted with registers. Independent color channel black level adjustments can also be made. If the black level subtraction produces a negative result for a
particular pixel, the value of this pixel is set to 0.
Positional Gain Adjustments (PGA)
Lenses tend to produce images whose brightness is significantly attenuated near the
edges. There are also other factors causing fixed pattern signal gradients in images
captured by image sensors. The cumulative result of all these factors is known as image
shading. The MT9V138 has an embedded shading correction module that can be
programmed to counter the shading effects on each individual R, Gb, Gr, and B color
signal.
The Correction Function
The correction functions can then be applied to each pixel value to equalize the
response across the image as follows:
P corrected (row,col)=P sensor (row,col)*f(row,col)
(EQ 1)
where P are the pixel values and f is the color dependent correction functions for each
color channel.
Color Interpolation
In the raw data stream fed by the sensor core to the IFP, each pixel is represented by a
10-bit integer number, which can be considered proportional to the pixel's response to a
one-color light stimulus, red, green, or blue, depending on the pixel's position under the
color filter array. Initial data processing steps, up to and including the defect correction,
preserve the one-color-per-pixel nature of the data stream, but after the defect correction it must be converted to a three-colors-per-pixel stream appropriate for standard
color processing. The conversion is done by an edge-sensitive color interpolation
module. The module pads the incomplete color information available for each pixel
with information extracted from an appropriate set of neighboring pixels. The algorithm
used to select this set and extract the information seeks the best compromise between
preserving edges and filtering out high frequency noise in flat field areas. The edge
threshold can be set through register settings.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Color Correction and Aperture Correction
To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are
subjected to color correction. The IFP multiplies each vector of three pixel colors by a
3 x 3 color correction matrix. The three components of the resulting color vector are all
sums of three 10-bit numbers. Since such sums can have up to 12 significant bits, the bit
width of the image data stream is widened to 12 bits per color (36 bits per pixel). The
color correction matrix can be either programmed by the user or automatically selected
by the auto white balance (AWB) algorithm implemented in the IFP. Color correction
should ideally produce output colors that are corrected for the spectral sensitivity and
color crosstalk characteristics of the image sensor. The optimal values of the color
correction matrix elements depend on those sensor characteristics and on the spectrum
of light incident on the sensor. The color correction variables can be adjusted through
register settings.
To increase image sharpness, a programmable 2D aperture correction (sharpening filter)
is applied to color-corrected image data. The gain and threshold for 2D correction can
be defined through register settings.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Gamma Correction
The MT9V138 IFP includes a block for gamma correction that can adjust its shape based
on brightness to enhance the performance under certain lighting conditions. Two
custom gamma correction tables may be uploaded corresponding to a brighter lighting
condition and a darker lighting condition. At power-up, the IFP loads the two tables with
default values. The final gamma correction table used depends on the brightness of the
scene and takes the form of an interpolated version of the two tables.
The gamma correction curve (as shown in Figure 14) is implemented as a piecewise
linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit
output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280,
1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit ordinates
are programmable through IFP registers.
Figure 14:
Gamma Correction Curve
RGB to YUV Conversion
For further processing, the data is converted from RGB color space to YUV color space.
Color Kill
To remove high-or low-light color artifacts, a color kill circuit is included. It affects only
pixels whose luminance exceeds a certain preprogrammed threshold. The U and V
values of those pixels are attenuated proportionally to the difference between their luminance and the threshold.
YUV Color Filter
As an optional processing step, noise suppression by one-dimensional low-pass filtering
of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
YUV-to-RGB/YUV Conversion and Output Formatting
The YUV data stream emerging from the scaling module can either exit the color pipeline as-is or be converted before exit to an alternative YUV or RGB data format.
Output Format and Timing
YUV/RGB Data Ordering
The MT9V138 supports swapping YCbCr mode, as illustrated in Table 10.
Table 10:
YCbCr Output Data Ordering
Mode
Data Sequence
Default (no swap)
Swapped CbCr
Swapped YC
Swapped CbCr, YC
Yi
Yi
Cbi
Cri
Cbi
Cri
Yi
Yi
Cri
Cbi
Yi+1
Yi+1
Yi+1
Yi+1
Cri
Cbi
The RGB output data ordering in default mode is shown in Table 11. The odd and even
bytes are swapped when luma/chroma swap is enabled. R and B channels are bit-wise
swapped when chroma swap is enabled.
Table 11:
RGB Ordering in Default Mode
Mode (Swap Disabled)
Byte
D7D6D5D4D3D2D1D0
565RGB
Odd
Even
Odd
Even
Odd
Even
Odd
Even
R7R6R5R4R3G7G6G5
G4G3G2B7B6B5B4B3
0 R7R6R5R4R3G7G6
G5G4G3B7B6B5B4B3
R7R6R5R4G7G6G5G4
B7B6B5B4 0 0 0 0
0 0 0 0 R7R6R5R4
G7G6G5G4B7B6B5B4
555RGB
444xRGB
x444RGB
Uncompressed 10-Bit Bypass Output
Raw 10-bit Bayer data from the sensor core can be output in bypass mode in two ways:
• Using 8 data output signals (DOUT[7:0]) and GPIO[1:0]. The GPIO signals are the least
significant 2 bits of data.
• Using only 8 signals (DOUT[7:0]) and a special 8 + 2 data format, shown in Table 12.
Table 12:
2-Byte Bayer Format
Byte
Bits Used
Bit Sequence
Odd bytes
8 data bits
D9D8D7D6D5D4D3D2
Even bytes
2 data bits + 6 unused bits
0 0 0 0 0 0 D1D0
Readout Formats
Progressive format is used for raw Bayer output.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Output Formats
ITU-R BT.656 and RGB Output
The MT9V138 can output processed video as a standard ITU-R BT.656 (CCIR656) stream,
an RGB stream, or as unprocessed Bayer data. The ITU-R BT.656 stream contains YCbCr
4:2:2 data with fixed embedded synchronization codes. This output is typically suitable
for subsequent display by standard video equipment or JPEG/MPEG compression.
Colorpipe data (pre-lens correction and overlay) can also be output in YCbCr 4:2:2 and a
variety of RGB formats in 640 by 480 progressive format in conjunction with
LINE_VALID and FRAME_VALID.
The MT9V138 can be configured to output 16-bit RGB (565RGB), 15-bit RGB (555RGB),
and two types of 12-bit RGB (444RGB). Refer to Table 27 and Table 28 on page 56 for
details.
Bayer Output
Unprocessed Bayer data are generated when bypassing the IFP completely—that is, by
simply outputting the sensor Bayer stream as usual, using FRAME_VALID, LINE_VALID,
and PIXCLK to time the data. This mode is called sensor stand-alone mode.
Output Ports
Composite Video Output
The composite video output DAC is external-resistor-programmable and supports both
single-ended and differential output. The DAC is driven by the on-chip video encoder
output.
Parallel Output
Parallel output uses either 8-bit or 10-bit output. Eight-bit output is used for ITU-R
BT.656 and RGB output. Ten-bit output is used for raw Bayer output.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Usage Modes
Usage Modes
How a camera based on the MT9V138 will be configured depends on what features are
used. In the simplest case, only an MT9V138 plus an external flash memory, or an 8-bit
microcontroller (µC) might be sufficient. Flash sizes vary depending on the data for
registers, firmware, and overlay data—somewhere between 10Kb to 16MB. The two-wire
bus is adequate since only high-level commands are used to invoke overlays, load registers from memory, or set up lens correction parameters. Overlay data can alternatively
be issued by the external µC if the rate of refreshing data is deemed adequate. If there are
no commands in the Flash image the device can be in auto configuration mode by which
the sensor is set up according to the status of pins FRAME_VALID, LINE_VALID and
DOUT_LSB0. For further information, see “Auto-Configuration” on page 31.
In the simplest case no Flash memory or µC is required, as shown in Figure 15. This is
truly a single chip operation.
Note:
Figure 15:
Because mandatory patches must be loaded, the Auto-Config mode is not recommended.
Auto-Config Mode
MT9V138
Auto-Config Mode
Analog Out
Hi = PAL
LSB0
Digital Out
Lo = NTSC
The MT9V138 can be configured by a serial Flash through the SPI Interface.
Figure 16:
Flash Mode
MT9V138
Serial
Flash
Hi = PAL
LSB0
Lo = NTSC
MT9V138 DS Rev. D Pub. 5/15 EN
SPI
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Usage Modes
In some applications, button or user interface keypad can trigger overlay images being
called by the C as shown in Figure 17
Figure 17:
Host Mode with Flash
8/16bit μC
Button or
user interface
keypad
MT9V138
two-wire
Serial
Flash
SPI
LSB0
Hi = PAL
Lo = NTSC
Overlay information may also be passed by the µC without a need for a Flash memory.
However, because the data transfer rate is limited over the two-wire serial bus, the
update rate may be slower. However, if overlay images are preloaded into the four onchip buffers, they may be turned on and off or move location at the frame rate as shown
in Figure 18.
Figure 18:
Host Mode
8/16bit μC
Button
or user interface
keypad
MT9V138 DS Rev. D Pub. 5/15 EN
MT9V138
Hi = PAL
LSB0
two-wire
Lo = NTSC
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
External Signal Processing
An external signal processor can take data from ITU656 or raw Bayer output format and
post-process or compress the data in various formats.
Figure 19:
External Signal Processing Block Diagram
27 MHz
Serial data
Flash
10Kb to 16MB
EXTCLK
SPI
VIDEO_P
Hi = PAL
LSB0
Lo = NTSC
VIDEO_N
CVBS
PAL/NTSC
Signal processor
DOUT [7:0]
PIXCLK
Device Configuration
After power is applied and the device is out of reset by de-asserting the RESET_BAR pin,
it will enter a boot sequence to configure its operating mode. There are essentially four
modes, two when Flash is present and two when Flash is not present. Figure 20: “PowerUp Sequence – Configuration Options Flow Chart,” on page 32 contains more details on
the configuration options.
If Flash is present and:
• A valid Flash device identifier is detected AND the Flash device contains valid configuration records, then
– Disable Auto-Config
– Parse Flash Content
– Load Flash Configuration ->Flash Configuration Mode
• A valid Flash device identifier is detected BUT the Flash device DOES NOT contain
valid configuration records, then
– Enter Auto Configuration.
If Flash is not present and:
• SPI_SDI == 0, then
– Enter Host Configuration.
• SPI_SDI != 0, then
– Enter Auto Configuration
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Auto-Configuration
The device supports an auto-configuration feature. During system start-up, the device
first detects whether an SPI Flash device is attached to the MT9V138. If not, it will then
sample the state of a number of GPI inputs including FRAME_VALID, LINE_VALID and
DOUT_LSB0. For more information, see Table 15, “GPIO Bit Descriptions,” on page 33.
The state of these inputs then determines the configuration of a number of subsystems
of the device such as readout mode, pedestal and video format, respectively.
The auto-configuration feature can be disabled by grounding the SPI_DIN pin. The
device samples the state of this pin during the Flash device detection process. If no SPI
Flash device is detected (read device ID of 0x00 or 0xFF), OR the SPI_DIN pin is
grounded, then auto-configuration is disabled.
Flash Configuration Mode
If a valid Flash is detected (by reading device ID other than 0x00 or 0xFF) and the flash
device contains valid configuration records, then these configuration records are
processed.
Host Configuration
This mode is entered if the SPI_DIN pin is grounded. The SOC performs no configuration, and remains idle waiting for configuration and instruction from the host.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Power Sequence
In power-up, the core voltage (1.8V) must trail the IO (2.8V) by a positive number. All
2.8V rails can be turned on at the same time or follow the power-up sequence in Figure
46: “Power Up Sequence,” on page 62.
In power down, the sequence is reversed. The core voltage (1.8V) must be turned off
before any 2.8V. Refer to Figure 47: “Power Down Sequence,” on page 63 for details.
Figure 20:
Power-Up Sequence – Configuration Options Flow Chart
Power Up/ RESET
Host
Configuration :
yes
Flash
Header?
no
yes
Disable Auto -Config
SPI _SDI = 0?
Parse Flash Content
Flash
Configuration:
no
Disable Auto-Config
Auto Configuration:
FRAME_VALID,
LINE_VALID,
D OUT_LSB0
Wait for Host
Command
Host
Configuration:
Wait for Host
Command
Wait for Host
Command
FRAME_VALID
0: Normal
1: Horizontal Mirror
LINE_VALID
0 No Pedestal
1: Pedestal
DOUT_LSB0
0: NTSC
1: PAL
Supported SPI Devices
Table 13 lists supported Flash devices. Devices not compatible will require a firmware
patch. Contact ON Semiconductor for additional support.
Table 13:
SPI Flash Devices
Type
Density
Manufacturer
Device
Speed
(MHz)
Flash
8 MB
Atmel
AT26DF081A
70
Flash
1 MB
ST
M25P10-AVMB3
50
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32
Standard
JEDEC/Device
ID
Temp Range
(°F)
Supported
–20 to +85
Yes
–40 to +125
Yes
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Supported SPI Commands
The SPI commands shown in Table 14 are supported by the MT9V138.
Table 14:
Table 15:
SPI Commands Supported
Command
Value
Read Array
Block Erase
Chip Erase
Read Status
Write status
Byte Page Program
Write Enable
Write Disable
Read Manufacturer and Device
ID
(Fast) Read Array
0x03
0xD8
0xC7
0x05
0x01
0x02
0x06
0x04
0x9F
0x0B
GPIO Bit Descriptions
MT9V138 DS Rev. D Pub. 5/15 EN
GPI[2]
(DOUT_LSB0)
GPI[1]
(FRAME_VALID)
GPI[0]
(LINE_VALID)
Low (“0”)
NTSC
Normal
No pedestal
High (“1”)
PAL
Horizontal mirror
Pedestal
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Host Command Interface
ON Semiconductor’s sensors and SOCs contain numerous registers that are accessed
through a two-wire interface with speeds up to 400 kHz.
The MT9V138, in addition to writing or reading straight to/from registers or firmware
variables, has a mechanism to write higher level commands, the Host Command Interface (HCI). Once a command has been written through the HCI, it will be executed by on
chip firmware and the results are reported back. In general, registers shall not be
accessed with the exception of registers that are marked for “User Access.”
Flash memory is also available to store commands for later execution. Under DMA
control, a command is written into the SOC and executed.
For a complete spec on host commands, refer to the MT9V138 Host Command Interface
Specification.
Figure 21:
Interface Structure
bit
Addr 0x40
15
1
0
14
0
Host Command to FW
Response from FW
command register
door bell
bit
Addr 0xFC00
15
0
Parameter 0
cmd_handler_params_pool_0
`
Addr 0xFC02
cmd_handler_params_pool_1
`
cmd_handler_params_pool_2
Addr 0xFC04
`
cmd_handler_params_pool_3
Addr 0xFC06
```
cmd_handler_params_pool_4
Addr 0xFC08
`
cmd_handler_params_pool_5
Addr 0xFC0A
`
Addr 0xFC0C
cmd_handler_params_pool_6
`
Addr 0xFC0E
Parameter 7
cmd_handler_params_pool_7
`
MT9V138 DS Rev. D Pub. 5/15 EN
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Host Command Process Flow
Issu e
Comma n d
Wa it for a
resp on se?
Host cou ld in sert a n
op tion a l d ela y here
Yes
Rea d Comma n d
reg ister
Host cou ld in sert a n
op tion a l d ela y here
No
Rea d Comma n d
reg ister
No
Doorbell
bit clea r ?
Doorbell bit
clea r?
Yes
At this p oin t
Comma n d Reg ister
con ta in s resp on se cod e
Comma n d ha s
p a ra meters ?
Write p a ra meters
to
Pa ra meter Pool
No
Yes
Comma n d
ha s response
parameters ?
Yes
No
No
No
Yes
Rea d resp on se
p a ra meters from
Pa ra meter Pool
Write comma n d
to
Comma n d reg ister
Don e
Command Flow
The host issues a command by writing (through a two-wire interface bus) to the
command register. All commands are encoded with bit 15 set, which automatically
generates the host command (doorbell) interrupt to the microprocessor.
Assuming initial conditions, the host first writes the command parameters (if any) to the
parameters pool (in the command handler's logical page), then writes the command to
command register. The interrupt handler then signals the command handler task to
process the command.
If the host wishes to determine the outcome of the command, it must poll the command
register waiting for the doorbell bit to be cleared. This indicates that the firmware
completed processing the command. The contents of the command register indicate the
command's result status. If the command generated response parameters, the host can
now retrieve these from the parameters pool.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Note:
The host must not write to the parameters pool, nor issue another command, until
the previous command completes. This is true even if the host does not care about the
result of the previous command. Therefore, the host must always poll the command
register to determine the state of the doorbell bit, and ensure the bit is cleared before
issuing a command.
For a complete command list and further information consult the Host Command Interface Specification.
An example of how (using DevWare) a command may be initiated in the form of a
“Preset” follows.
Set Parallel Mode - Normal (Overlay i656)
All DevWare presets supplied by ON Semiconductor poll and test the doorbell bit after
issuing the command. Therefore there is no need to check if the doorbell bit is clear
before issuing the next command.
REG= 0xFC00, 0x1000
// CMD_HANDLER_PARAMS_POOL_0
REG= 0x0040, 0x8801 // issue command
//
POLL
COMMAND_REGISTER::DOORBELL =>
0x0
Summary of Host Commands
Table 16 on page 36 through Table 21 on page 38 show summaries of the host
commands. The commands are divided into the following sections:
– System Manager
– Overlay
– GPIO Host interface
– Flash Manager Host
– Patch Loader Interface
– TX Manager
Following is a summary of the Host Interface commands. The description gives a quick
orientation. The “Type” column shows if it is an asynchronous or synchronous
command. For a complete list of all commands including parameters, consult the Host
Command Interface Specification document.
Table 16:
System Manager Commands
System Manager
Host Command
Value
Type
Set State
0x8100
Asynchronous
Request the system enter a new state
Get State
0x8101
Synchronous
Get the current state of the system
Table 17:
Overlay Host Commands
Overlay Host Command
Description
Value
Type
Enable Overlay
0x8200
Synchronous
Enable or disable the overlay subsystem
Get Overlay State
0x8201
Synchronous
Retrieve the state of the overlay subsystem
Set Calibration
0x8202
Synchronous
Set the calibration offset
Set Bitmap Property
0x8203
Synchronous
Set a property of a bitmap
Get Bitmap Property
0x8204
Synchronous
Get a property of a bitmap
Set String Property
0x8205
Synchronous
Set a property of a character string
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Description
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Table 17:
Overlay Host Commands
Overlay Host Command
Value
Type
Load Buffer
0x8206
Asynchronous
Load an overlay buffer with a bitmap (from Flash)
Load Status
0x8207
Synchronous
Retrieve status of an active load buffer operation
Write Buffer
0x8208
Synchronous
Write directly to an overlay buffer
Read Buffer
0x8209
Synchronous
Read directly from an overlay buffer
Enable Layer
0x820A
Synchronous
Enable or disable an overlay layer
Get Layer Status
0x820B
Synchronous
Retrieve the status of an overlay layer
Set String
0x820C
Synchronous
Set the character string
Load String
0x820E
Asynchronous
Load a character string (from Flash)
Table 18:
Description
GPIO Host Commands
GPIO Host Command
Value
Type
Set GPIO Property
0x8400
Synchronous
Set a property of one or more GPIO pins
Get GPIO Property
0x8401
Synchronous
Retrieve a property of a GPIO pin
Set GPO State
0x8402
Synchronous
Set the state of a GPO pin or pins
Get GPIO State
0x8403
Synchronous
Get the state of a GPI pin or pins
Set GPI Association
0x8404
Synchronous
Associate a GPI pin state with a Command Sequence stored in SPI Flash
Table 19:
Description
Flash Manager Host Commands
Flash Manager
Host Command
Value
Type
Description
Get Lock
0x8500
Asynchronous Request the Flash Manager access lock
Lock Status
0x8501
Synchronous
Retrieve the status of the access lock request
Release Lock
0x8502
Synchronous
Release the Flash Manager access lock
Config
0x8503
Synchronous
Configure the Flash Manager and underlying SPI Flash subsystem
Read
0x8504
Asynchronous Read data from the SPI Flash
Write
0x8505
Asynchronous Write data to the SPI Flash
Erase Block
0x8506
Asynchronous Erase a block of data from the SPI Flash
Erase Device
0x8507
Asynchronous Erase the SPI Flash device
Query Device
0x8508
Asynchronous Query device-specific information
Status
0x8509
Synchronous
Table 20:
Obtain status of current asynchronous operation
Sequencer Host Commands
Sequencer Host
Command
Value
Type
Set Encoding Mode
0x8603
Synchronous
Set the encoding mode
Enable Horizontal Flip
0x8604
Synchronous
Enable or disable horizontal flip
Set Flicker Frequency
0x8605
Synchronous
Set the flicker frequency
Refresh Mode
0x8606
Synchronous
Refresh the Sequencer mode/context
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Description
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Table 21:
TX Manager Host Commands
TX Manager Host
Command
Value
Type
Config DAC
0x8800
Synchronous
Configure the Video DAC
Set Parallel Mode
0x8801
Synchronous
Configure the Parallel output port
MT9V138 DS Rev. D Pub. 5/15 EN
Description
38
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Slave Two-Wire Serial Interface
The two-wire serial interface bus enables read/write access to control and status registers within the MT9V138. This interface is designed to be compatible with the MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the electrical
characteristics and transfer protocols of the two-wire serial interface specification.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The sensor acts as a slave device. The master generates a clock
(SCLK) that is an input to the sensor and used to synchronize transfers.
Data is transferred between the master and the slave on a bidirectional signal (SDATA).
SDATA is pulled up to VDD_IO off-chip by a pull-up resistor in the range of 1.5 to 4.7k
resistor.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements, as follows:
• a start or restart condition
• a slave address/data direction byte
• a 16-bit register address
• an acknowledge or a no-acknowledge bit
• data bytes
• a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with
a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions.
The SADDR pin is used to select between two different addresses in case of conflict with
another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave
address is 0xBA. See Table 22 below.
Table 22:
Two-Wire Interface ID Address Switching
SADDR
Two-Wire Interface Address ID
0
1
0x90
0xBA
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is low and must be stable while SCLK is HIGH.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default
slave addresses used by the MT9V138 are 0x90 (write address) and 0x91 (read address).
Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be
selected by asserting the SADDR input signal.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data. The protocol used is outside the scope of the
two-wire serial interface specification.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver does not drive SDATA low during
the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Typical Operation
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”
indicates a WRITE and a “1” indicates a READ. If the address matches the address of the
slave device, the slave device acknowledges receipt of the address by generating an
acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master will then transfer the 16-bit data, as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master stops writing by generating a (re)start or stop condition. If the
request was a READ, the master sends the 8-bit write slave address/data direction byte
and 16-bit register address, just as in the write request. The master then generates a
(re)start condition and the 8-bit read slave address/data direction byte, and clocks out
the register data, 8 bits at a time. The master generates an acknowledge bit after each 8bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.
Single READ from Random Location
Figure 22 shows the typical READ cycle of the host to MT9V138. The first two bytes sent
by the host are an internal 16-bit register address. The following 2-byte READ cycle sends
the contents of the registers to host.
Figure 22:
Single READ from Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
A
M+1
Reg Address, M
Reg Address[7:0]
A Sr
Slave Address
1 A
Read Data
Read Data
A
A
[15:8]
[7:0]
P
slave to master
master toslave
Single READ from Current Location
Figure 23 shows the single READ cycle without writing the address. The internal address
will use the previous address value written to the register.
Figure 23:
Single Read from Current Location
Previous Reg Address, N
S
Slave Address
MT9V138 DS Rev. D Pub. 5/15 EN
1 A
Reg Address, N+1
Read Data
Read Data
A
A
[7:0]
[15:8]
P
S
41
Slave Address
N+2
1 A
Read Data
Read Data
A P
A
[15:8]
[7:0]
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Sequential READ, Start from Random Location
This sequence (Figure 24) starts in the same way as the single READ from random location (Figure 22 on page 41). Instead of generating a no-acknowledge bit after the first
byte of data has been transferred, the master generates an acknowledge bit and
continues to perform byte READs until “L” bytes have been read.
Figure 24:
Sequential READ, Start from Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Read Data
(15:8)
A
A
M+2
Read Data
(7:0)
A
Read Data
(15:8)
A
Reg Address, M
Reg Address[7:0]
Read Data
(15:8)
A
A
1 A
Slave Address
M+L-2
M+3
Read Data
(7:0)
A Sr
M+1
Read Data
M+L-1
Read Data
(7:0)
A
Read Data
(15:8)
A
A
M+L
Read Data
(7:0)
A P
Sequential READ, Start from Current Location
This sequence (Figure 25) starts in the same way as the single READ from current location (Figure 23). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte reads until “L” bytes have been read.
Figure 25:
Sequential READ, Start from Current Location
Previous Reg Address, N
S
Slave Address
1 A
N+1
Read Data
Read Data
(15:8)ReadAData
(7:0)
A
N+2
Read Data
Read Data
(15:8)ReadAData
(7:0)
A
Read Data
Read Data
ReadAData
(15:8)
(7:0)
N+L-1
Read Data
Read Data
Data
A Read
(15:8)
(7:0)
A
N+L
A P
Single Write to Random Location
Figure 26 shows the typical WRITE cycle from the host to the MT9V138. The first 2 bytes
indicate a 16-bit address of the internal registers with most-significant byte first. The
following 2 bytes indicate the 16-bit data.
Figure 26:
Single WRITE to Random Location
Previous Reg Address, N
S
MT9V138 DS Rev. D Pub. 5/15 EN
Slave Address
0 A Reg Address[15:8]
42
A Reg Address[7:0]
Reg Address, M
A
Write Data
M+1
A P
A
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Sequential WRITE, Start at Random Location
This sequence (Figure 27) starts in the same way as the single WRITE to random location
(Figure 26). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte writes until “L” bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 27:
Sequential WRITE, Start at Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Write Data
(15:8)
MT9V138 DS Rev. D Pub. 5/15 EN
A
M+2
Write Data
(7:0)
A
Write Data
Write Data
WriteAData
(15:8)
(7:0)
A
Reg Address, M
Reg Address[7:0]
A
Write Data
M+L-2
M+3
Write Data
Write Data
WriteAData
(15:8)
(7:0)
A
A
43
M+1
A
M+L-1
A
Write Data
Write Data
WriteAData
(15:8)
(7:0)
M+L
A
P
A
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Capability
Overlay Capability
Figure 28 highlights the graphical overlay data flow of the MT9V138. The images are
separated to fit into 2KB blocks of memory after compression.
• Up to four overlays may be blended simultaneously
• Overlay size 360 x 480 pixels rendered into a display area of 720 x 480 pixels
• Selectable readout: rotating order is user programmable
• Dynamic movement through predefined overlay images
• Palette of 32 colors out of 64,000 with eight colors per bitmap
• Blend factors may be changed dynamically to achieve smooth transitions
The host commands allow a bitmap to be written piecemeal to a memory buffer through
the I2C, and through the DMA direct from SPI Flash memory. Multiple encoding passes
may be required to fit an image into a 2KB block of memory; alternatively, the image can
be divided into two or more blocks to make the image fit. Every graphic image may be
positioned in an x/y direction and overlap with other graphic images.
The host may load an image at any time. Under control of DMA assist, data are transferred to the off-screen buffer in compressed form. This assures that no display data are
corrupted during the replenishment of the four active overlay buffers.
Figure 28:
Overlay Data Flow
Overlay buffers: 2KB each
Flash
Decompress
Blend and Overlay
Bitmaps - compressed
Note:
MT9V138 DS Rev. D Pub. 5/15 EN
Off-screen
buffer
These images are not actually rendered, but show conceptual objects and object blending.
44
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Serial Memory Partition
Serial Memory Partition
The contents of the Flash/EEPROM memory partition logically into three blocks (see
Figure 29):
• Memory for overlay data and descriptors
• Memory for register settings, which may be loaded at boot-up
• Firmware extensions or software patches; in addition to the on-chip firmware, extensions reside in this block of memory
These blocks are not necessarily contiguous.
Figure 29:
Memory Partitioning
Flash
Partitioning
Flash
Partitioning
Fixed-size
Fixed Size
Overlays
– RLE
Overlays-RLE
Fixed Size
Fixed-size
Overlays
– RLE
Overlays-RLE
12-byte
12Byte Header
Header
Overlay
DataData
Overlay
RLEEncoded
Encoded
RLE
Data
Data
2KB
2kByte
Lens Shading
Lens Correction
Correction
Parameter
Parameter
Alternate
Alternate
Reg.
Register
Setting
Setting
S/W Patch
Software
Patch
For a complete description of memory organization, refer to the MT9V138 SPI Flash
Contents Encoding Specification.
External Memory Speed Requirement
For a 2KB block of overlay to be transferred within a frame time to achieve maximum
update rate, the serial memory has to be a certain speed.
Table 23:
Transfer Time Estimate
MT9V138 DS Rev. D Pub. 5/15 EN
Frame Time
SPI Clock
Transfer Time to 2KB
33.3ms
4.5 MHz
1ms
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Adjustment
Overlay Adjustment
To ensure a correct position of the overlay to compensate for assembly deviation, the
overlay can be adjusted with assistance from the overlay statistics engine:
• The overlay statistics engine supports a windowed 8-bin luma histogram, either rowwise (vertical) or column-wise (horizontal).
• The example calibration statistics firmware patch can be used to perform an automatic successive-approximation search of a cross-hair target within the scene.
• On the first frame, the firmware performs a coarse horizontal search, followed by a
coarse vertical search in the second frame.
• In subsequent frames, the firmware reduces the region-of-interest of the search to the
histogram bins containing the greatest accumulator values, thereby refining the
search.
• The resultant X, Y location of the cross-hair target can be used to assign a calibration
value of offset selected overlay graphic image positions within the output image.
• The calibration statistics patch also supports a manual mode, which allows the host
to access the raw accumulator values directly.
Note:
MT9V138 DS Rev. D Pub. 5/15 EN
For the overlay calibration feature to work, load the appropriate patch. See Statistics
Engine document.
46
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Adjustment
Figure 30:
Overlay Calibration
The position of the target will be used to determine the calibration value that shifts the
X,Y position of adjustable overlay graphics.
The overlay calibration is intended to be applied on a device by device basis “in system,”
which means after the camera has been installed. ON Semiconductor provides basic
programming scripts that may reside in the SPI Flash memory to assist in this effort.
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Overlay Character Generator
In addition to the four overlay layers, a fifth layer exists for a character generator overlay
string.
There are a total of:
• 16 alphanumeric characters available
• 22 characters maximum per line
• 16 x 32 pixels with 1-bit color depth
Any update to the character generator string requires the string to be passed in its
entirety with the Host Command. Character strings have their own control properties
aside from the Overlay bitmap properties.
Figure 31:
Internal Block Diagram Overlay
B T 65 6
O verla y
L ayer3
R e giste r B u s
U ser R egiste rs
L ayer2
D a ta B u s
D M A /C P U
L ayer1
Tim in g co ntrol
L ayer0
N u m be r
G en era to r
ROM
B T 65 6
MT9V138 DS Rev. D Pub. 5/15 EN
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Character Generator
The character generator can be seen as the fifth top layer, but instead of getting the
source from RLE data in the memory buffers, it has a predefined 16 characters stored in
ROM.
All the characters are 1-bit depth color and are sharing the same YCbCr look up table.
Figure 32:
Example of Character Descriptor 0 Stored in ROM
ROM 15 14
0x00 0 0
0x02 0 0
0x04
0 0
0x06
0 0
0x08
0 0
0x0a
0 0
0x0c
0 0
0x0e
0 0
0x10
0 0
0x12
0 0
0x14
0 1
0x16
0 1
0x18
0 1
0x1a
0 1
0x1c
0 1
0x1e
0 1
0x20
0 1
0x22
0 1
0x24
0 1
0x26
0 1
0x28
0 0
0x2a
0 0
0x2c
0 0
0x2e
0 0
0x30
0 0
0x32
0 0
0x34
0 0
0x36
0 0
0x38
0 0
0x3a 0 0
0x3c 0 0
0x3e 0 0
…
13
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
12
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
11
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
10
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
9
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
8
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
7
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
6
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
5
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
4
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
3
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
It can show a row of up to 22 characters of 16 x 32 pixels resolution (32 x 32 pixels when
blended with the BT 656 data).
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Character Generator Details
Table 24 shows the characters that can be generated.
Table 24:
Character Generator Details
Item
Quantity
Description
16-bit character
22
Coder for one of these characters: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /, (space), :, –, (comma), (period)
1 bpp color
1
Depth of the bit map is 1 bpp
It is the responsibility of the user to set up proper values in the character positioning to
fit them in the same row (that is one of the reasons that 22 is the maximum number of
characters).
Note:
No error is generated if the character row overruns the horizontal or vertical limits of
the frame.
Full Character Set for Overlay
Figure 33 shows all of the characters that can be generated by the MT9V138.
Figure 33:
Full Character Set for Overlay
0x0 0x4 0x8 0xC
0x1 0x5 0x9 0xD
0x2 0x6 0xA 0xE
0x3 0x7 0xB 0xF
MT9V138 DS Rev. D Pub. 5/15 EN
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Modes and Timing
This section provides an overview of the typical usage modes and related timing information for the MT9V138.
Composite Video Output
The external pin DOUT_LSB0 must be used to configure the device for default NTSC or
PAL operation. This and other video configuration settings are available as register
settings accessible through the serial interface.
NTSC
Both differential and single-ended connections of the full NTSC format are supported.
The differential connection that uses two output lines is used for low noise or long
distance applications. The single-ended connection is used for PCB tracks and screened
cable where noise is not a concern. The NTSC format has three black lines at the bottom
of each image for padding (which most LCDs do not display).
PAL
The PAL format is supported with 576 active image rows.
Single-Ended and Differential Composite Output
The composite output can be operated in a single-ended or differential mode by simply
changing the external resistor configuration. For single-ended termination, see
Figure 34 on page 51. The differential schematic is shown in Figure 35 on page 52.
Figure 34:
Single-Ended Termination
V DD
i = IMINUS
i = IPLUS
Chip
Boundary
75Ω
Single-Ended
L0
L2
L1
L = 1uH
75Ω Terminated Receiver
75Ω
Single-ended
L = 1uH
C0
C1
C = 330 pF
C = 330 pF
R 1=75Ω
75Ω
L = 2.2μH
Single-ended
e.g. PCB Track
e .g. 75Ω COAX
Typical Values for LC
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 35:
Differential Connection—Grounded Termination
Parallel Output (DOUT)
The DOUT[7:0] port supports both progressive and Interlaced mode. Progressive mode
(with FV and LV signal) include raw bayer(8 or 10 bit), YCbCr, RGB. Interlaced mode is
CCIR656 compliant.
Figure 36 shows the data that is output on the parallel port for CCIR656. Both NTSC and
PAL formats are displayed. The blue values in Figure 36 represent NTSC (525/60). The
red values represent PAL (625/50).
Figure 36:
CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems
Start of digital line
Start of digital active line
EAV CODE
F
F
0
0
0
0
4
4
X
Y
BLANKING
8
0
1
0
8
0
SAV CODE
1
0
8
0
268
280
1
0
F
F
0
0
0
0
4
4
CO -SITED _
CO -SITED _
X C
Y B
Y
C
R
Next line
Y
C
B
Y
C
R
Y
C
R
Y
F
F
Digital
video
stream
1440
1440
1716
1728
Figure 37 on page 53 shows detailed vertical blanking information for NTSC timing. See
Table 25 on page 53 for data on field, vertical blanking, EAV, and SAV states.
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 37:
Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System
Line 4
Line 1 (V = 1)
Blanking
Field 1
(F = 0)
Odd
Line 20 (V = 0)
Field 1 Active Video
266
Line 264 (V = 1)
Blanking
Field 2
(F = 1)
Even
Line 283 (V = 0)
Field 2 Active Video
Line 525 (V = 0)
H=1
EAV
Table 25:
H=0
SAV
Field, Vertical Blanking, EAV, and SAV States 525/60 Video System
Line Number
F
V
H
(EAV)
H
(SAV)
1–3
4–9
20–263
264–265
266–282
283–525
1
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
Figure 38 shows detailed vertical blanking information for PAL timing. See Table 26 on
page 54 for data on field, vertical blanking, EAV, and SAV states.
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 38:
Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System
Line 1 (V = 1)
Blanking
Line 23 (V = 0)
Field 1
(F = 0)
Odd
Field 1 Active Video
Line 311 (V = 1)
Blanking
Line 336 (V = 0)
Field 2
(F = 1)
Even
Field 2 Active Video
Line 624 (V = 1)
Blanking
Line 625 (V = 1)
H =1
EAV
Table 26:
H= 0
SAV
Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System
MT9V138 DS Rev. D Pub. 5/15 EN
Line Number
F
V
H
(EAV)
H
(SAV)
1–22
23–310
311–312
313–335
336–623
624–625
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
54
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Reset and Clocks
Reset
Power-up reset is asserted or de-asserted with the RESET_BAR pin, which is active LOW.
In the reset state, all control registers are set to default values. See “Device Configuration” on page 30 for more details on Auto, Host, and Flash configurations.
Soft reset is asserted or de-asserted by the two-wire serial interface program. In softreset mode, the two-wire serial interface and the register bus are still running. All control
registers are reset using default values.
Clocks
The MT9V138 has two primary clocks:
• A master clock coming from the EXTCLK signal.
• In default mode, a pixel clock (PIXCLK) running at 2 * EXTCLK. In raw Bayer bypass
mode, PIXCLK runs at the same frequency as EXTCLK.
When the MT9V138 operates in sensor stand-alone mode, the image flow pipeline
clocks can be shut off to conserve power.
The sensor core is a master in the system. The sensor core frame rate defines the overall
image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced
by the sensor configuration, and are also a function of certain image flow pipeline functions. The relationship of the primary clocks is depicted in Figure 39.
The image flow pipeline typically generates up to 16 bits per pixel—for example, YCbCr
or 565RGB—but has only an 8-bit port through which to communicate this pixel data.
To generate NTSC or PAL format images, the sensor core requires a 27 MHz clock.
Figure 39:
Primary Clock Relationships
EXTCLK
Sensor
Master Clock
Sensor Core
Sensor
Pixel Clock
10 bits/pixel
1 pixel/clock
Colorpipe
16 bits/pixel
1 pixel/clock
Output Interface
16 bits/pixel (TYP)
0.5 pixel/clock
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Floating Inputs
The following MT9V138 pins cannot be floated:
• SDATA–This pin is bidirectional and should not be floated
• TRST_N
Output Data Ordering
Table 27:
Output Data Ordering in DOUT RGB Mode
Mode
(Swap Disabled)
565RGB
555RGB
444xRGB
x444RGB
Byte
D7
D6
D5
D4
D3
D2
D1
D0
First
Second
First
Second
First
Second
First
Second
R7
G4
0
G5
R7
B7
0
G7
R6
G3
R7
G4
R6
B6
0
G6
R5
G2
R6
G3
R5
B5
0
G5
R4
B7
R5
B7
R4
B4
0
G4
R3
B6
R4
B6
G7
0
R7
B7
G7
B5
R3
B5
G6
0
R6
B6
G6
B4
G7
B4
G5
0
R5
B5
G5
B3
G6
B3
G4
0
R4
B4
Note:
Table 28:
PIXCLK is 54 MHz when EXTCLK is 27 MHz.
Output Data Ordering in Sensor Stand-Alone Mode
Mode
D7
D6
D5
D4
D3
D2
D1
D0
DOUT_LSB1
DOUT_LSB0
10-bit Output
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Note:
MT9V138 DS Rev. D Pub. 5/15 EN
PIXCLK is 27 MHz when EXTCLK is 27 MHz.
56
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
I/O Circuitry
Figure 40 illustrates typical circuitry used for each input, output, or I/O pad.
Figure 40:
Typical I/O Equivalent Circuits
VDD_IO
Input Pad
Pad
Receiver
GND
VDD_IO
SPI_SDI and RESET_BAR
Input Pad
Pad
Receiver
GND
VDD_IO
Receiver
I/O Pad
Pad
Slew
Rate
Control
GND
VDD_IO
SCLK and XTAL_IN
Input Pad
Pad
Receiver
GND
Pad
VDD_IO
XTAL
Output Pad
GND
Note:
MT9V138 DS Rev. D Pub. 5/15 EN
All I/O circuitry shown above is for reference only. The actual implementation may be different.
57
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 41:
NTSC Block
NTSC Block
VDD_DAC
DAC_REF
Pad
ESD
Pad
DAC_POS
Pad
DAC_NEG
ESD
Resistor
4.7kΩ/2.35kΩ
ESD
GND
Note:
Figure 42:
All I/O circuitry shown above is for reference only. The actual implementation may be different.
Serial Interface
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
I/O Timing
Digital Output
By default, the MT9V138 launches pixel data, FV, and LV synchronously with the falling
edge of PIXCLK. The expectation is that the user captures data, FV, and LV using the
rising edge of PIXCLK. The timing diagram is shown in Figure 43.
As an option, the polarity of the PIXCLK can be inverted from the default by programming R0x0016[14].
Figure 43:
Digital Output I/O Timing
t
extclk_period
Input
EXT C LK
O utput
PIXC LK
t
t
pixclkf_dout
O utput
D OUT [7:0]
dout_ho
t
dout_su
t
fvlv_ho
t
pixclkf_fvlv
O utput F R AM E_VALID
LIN E _VALID
Table 29:
t
fvlv_su
Parallel Digital Output I/O Timing
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate
Signal
Parameter
fextclk
EXTCLK
Conditions
Min
Typ
Max
Unit
max ±100 ppm
–
27
–
MHz
t
extclk_period
–
37
–
ns
Duty cycle
45
50
55
%
f
pixclk
PIXCLK1
–
27
–
MHz
pixclk_period
–
37
–
ns
t
Duty cycle
45
50
55
%
t
–2
0
2
ns
t
dout_su
8
–
18.5
ns
tdout_ho
8
–
18.5
ns
pixclkf_dout
DATA[7:0]
t
pixclkf_fvlv
FV/LV
–2
0
2
ns
tfvlv_su
8
–
18.5
ns
tfvlv_ho
8
–
18.5
ns
Note:
MT9V138 DS Rev. D Pub. 5/15 EN
PIXCLK can be inverted from the default by programming R0x0016[14].
59
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Slew Rate
Table 30:
Slew Rate for PIXCLK and DOUT
f
EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; V_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; T = 25°C; CLOAD = 40 pF
PIXCLK
DOUT[7:0]
R0x30 [10:8]
Typical
Rise Time
Typical
Fall Time
R0x30 [2:0]
Typical
Rise Time
Typical
Fall Time
Unit
000
001
010
011
100
101
110
111
6.5
4.8
3.9
3.7
3.6
3.5
3.4
3.3
6.3
4.6
3.8
3.7
3.6
3.5
3.4
3.3
000
001
010
011
100
101
110
111
6.5
4.8
3.9
3.7
3.6
3.5
3.4
3.3
6.3
4.6
3.8
3.7
3.6
3.5
3.4
3.3
ns
ns
ns
ns
ns
ns
ns
ns
Figure 44:
Slew Rate Timing
90%
10%
PIXCLK
tr is e
tfa ll
90%
D OUT
10%
tr is e
MT9V138 DS Rev. D Pub. 5/15 EN
60
tfa ll
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Configuration Timing
During start-up, the Dout_LSB0, LV and FV are sampled. Setup and hold timing for the
RESET_BAR signal with respect to DOUT_LSB0, LV, and FV are shown in Figure 45 and
Table 31. These signals are sampled once by the on-chip firmware, which yields a long
tHold time.
Figure 45:
Configuration Timing
RESET_BAR
t
SETUP
DOUT_LSB0
FRAME_VALID
LINE_VALID
Table 31:
t
HOLD
Valid Data
Configuration Timing
Signal
DOUT_LSB0, FRAME_VALID, LINE_VALID
MT9V138 DS Rev. D Pub. 5/15 EN
Parameter
Min
Typ
Max
Unit
tSETUP
0
s
tHOLD
50
s
61
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 46:
Power Up Sequence
VDD_PLL
VDD_DAC (2.8)
t0
VAA_PIX
VAA (2.8)
t1
VDD_IO (2.8)
t2
VDD (1.8)
tx
EXTCLK
RESET_BAR
t3
Hard Reset
Notes:
Table 32:
t4
t5
Internal
(NTSC/PAL)
Initialization
Patch Config
SPI or Host
Streaming
1. RESET_BAR may not exceed VDD_IO + 0.3V.
2. The 2.8V plane (VAA, VAA_PIX, VDD_PLL, VDD_DAC, VDD_IO) must remain at a higher voltage than
the 1.8V core voltage at all times.
Power Up Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD_PLL to VAA/VAA_PIX
VAA/VAA_PIX to VDD_IO
VDD_IO to VDD
Xtal settle time
Hard Reset
Internal Initialization
Patch Load (SPI or I2C)
t0
t1
t2
tx
t3
t4
t5
0
0
0
–
102
50
–
–
–
–
301
–
–
4003
–
–
–
–
–
–
–
S
S
S
mS
Clock cycle
mS
mS
Notes:
MT9V138 DS Rev. D Pub. 5/15 EN
1. Xtal settling time is component-dependent (Xtal, Oscillator, etc) and usually takes about 10mS
~100mS.
2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are
required for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is
performed by the RC circuit, then the RC time must include the all power rail settle time and Xtal
3. This is required to load necessary patches via Flash mode (SPI) or Host mode (two-wire serial interface). Loading time varies depending on the number of patches and bus speed.
62
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MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 47:
Power Down Sequence
VDD (1.8)
t0
VDD_IO (2.8)
t1
VAA_PIX
VAA (2.8)
t2
VDD_PLL
VDD_DAC (2.8)
EXTCLK
t3
Power Down until next Power Up Cycle
Table 33:
Power Down Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD to VDD_IO
VDD_IO to VAA/VAA_PIX
VAA/VAA_PIX to VDD_PLL/DAC
Power Down until Next Power Up Time
t0
t1
t2
t3
0
0
0
1001
–
–
–
–
–
–
–
–
S
S
S
ms
(1) t3 is required between power down and next power up time, all decoupling caps from
regulators must completely discharged before next power up.
Figure 48:
Reset to SPI Access Delay
R ESET_BAR
t
RSTH_CSL
SPI_CS_N
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 49:
Reset to Serial Access Delay
RESET_BAR
tRSTH_SDATAL
SDATA
Figure 50:
Reset to AE/AWB Image
RESET_BAR
VIDEO
First Frame
t
Overlay from
Flash
RSTH_FVL
t
RSTH_OVL
t
Table 34:
AE/AWB settled
RSTH_AEAWB
RESET_BAR Delay Parameters
Parameter
Name
Power up delay 2.8V to 1.8V
RESET_BAR HIGH to SPI_CS_N LOW
RESET_BAR HIGH to SDATA LOW
RESET_BAR HIGH to FRAME_VALID
RESET_BAR HIGH to first Overlay
RESET_BAR HIGH to AE/AWB settled
tRSTH_CSL
tRSTH_SDATAL
tRSTH_FVL
tRSTH_OVL
tRSTH_AEAWB
MT9V138 DS Rev. D Pub. 5/15 EN
Condition
64
Min
Typ
Max
Unit
0.1
18
1.8
235
235
–
–
–
–
–
–
400
–
–
–
–
–
–
ms
ms
ms
ms
ms
ms
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Electrical Specifications
Figure 51:
SPI Output Timing
tCS_SCLK
SPI_CS_N
SPI_SCLK
SPI_SDI
tsu
tSCLK_SDO
SPI_SDO
Table 35:
SPI Data Setup and Hold Timing
Parameter
Description
Min
Typ
Max
Units
fSPI_SCLK
SPI_SCLK Frequency
Setup time
Hold time
Delay from falling edge of SPI_CS_N to rising edge of SPI_SCLK
1.6875
–
4.5
–
–
230
18
110
110
–
MHz
ns
ns
ns
tsu
tSCLK_SDO
tCS_SCLK
MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Caution
Table 36:
Stresses greater than those listed in Table 36 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings
Rating
Symbol
VDD
Parameter
Min
Max
Unit
Digital power (1.8V)
-0.3
2.4
V
I/O power (2.8v)
-0.3
4
V
VAA
VAA Analog power (2.8V)
-0.3
4
V
VAA_PIX
Pixel array power (2.8v)
-0.3
4
V
VDD_PLL
PLL power (2.8V)
-0.3
4
V
VDD_DAC
DAC power (2.8V)
-0.3
4
V
VDD_IO
DC Input Voltage
-0.3
VDD_IO+0.3
V
VOUT
DC Output Voltage
-0.3
VDD_IO+0.3
V
TSTG
Storage temperature
-50
150
°C
VIN
Table 37:
Electrical Characteristics and Operating Conditions
Parameter1
Core digital voltage (VDD)
Condition
Min
Typ
Max
Unit
–
1.7
1.8
1.9
V
IO digital voltage (VDD_IO)
–
2.66
2.8
2.94
V
Video DAC voltage (VDD_DAC)
–
2.66
2.8
2.94
V
PLL Voltage (VDD_PLL)
–
2.66
2.8
2.94
V
Analog voltage (VAA)
–
2.66
2.8
2.94
V
–
2.66
2.8
2.94
V
10
A
Pixel supply voltage (VAA_PIX)
Leakage current
EXTCLK: HIGH or LOW
Imager operating temperature
–
–30
+70
°C
Storage temperature
–
–50
+150
°C
Notes:
MT9V138 DS Rev. D Pub. 5/15 EN
1. VAA and VAA_PIX must all be at the same potential to avoid excessive current draw. Care must be
taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together.
66
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Table 38:
Video DAC Electrical Characteristics–Single-Ended Mode
f
EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter
Resolution
DNL
INL
Output local load
Output voltage
Output current
Supply current
DAC_REF
R DAC_REF
Table 39:
Condition
Min
Typ
Max
Unit
Output pad (DAC_POS)
Unused output (DAC_NEG)
Single-ended mode, code 000h
Single-ended mode, code 3FFh
Single-ended mode, code 000h
Single-ended mode, code 3FFh
Estimate
DAC Reference
DAC Reference
–
–
–
–
–
–
–
–
–
–
–
–
10
0.2
0.7
75
0
.02
1.30
0.26
17.33
1.15 +/-0.2
4.7
0.4
3.5
25.0
-
bits
bits
bits


V
V
mA
mA
mA
V
K
Video DAC Electrical Characteristics–Differential Mode
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter
DNL
INL
Output local load
Output voltage
Output current
Differential output,
midlevel
Supply current
DAC_REF
R DAC_REF
MT9V138 DS Rev. D Pub. 5/15 EN
Condition
Differential mode per pad
(DAC_POS and DAC_NEG)
Differential mode, code 000h, pad dacp
Differential mode, code 000h, pad dacn
Differential mode, code 3FFh, pad dacp
Differential mode, code 3FFH, pad dacn
Differential mode, code 000h, pad dacp
Differential mode, code 000h, pad dacn
Differential mode, code 3FFh, pad dacp
Differential mode, code 3FFH, pad dacn
Estimate
DAC Reference
DAC Reference
67
Min
Typ
Max
Unit
–
–
–
0.2
0.8
37.5
0.25
2.5
–
Bits
Bits

–
–
–
–
–
–
–
–
–
.02
1.30
1.30
.02
.53
34.7
34.7
.53
0.65
–
–
–
–
–
–
–
–
–
V
V
V
V
mA
mA
mA
mA
V
–
–
–
1.15 +/-0.2
2.35
50
mA
V
K
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Table 40:
Digital I/O Parameters
TA = Ambient = 25°C; All supplies at 2.8V
Signal
Parameter
All
Outputs
Definitions
Min
2.8V, 30pF load
2.8V, 5pF load
Load capacitance
Typ
Max
Unit
1
–
30
pF
–
–
VDD_IO
–
–
–
V/ns
V/ns
V
VOH
Output high voltage
–
–
–
VOL
Output low voltage
–0.3
–
–
V
–
–
8
mA
Output signal slew
IOH
VIH
Input high voltage
VDD = 2.8V, VOH
= 2.4V
VDD = 2.8V, VOL
= 0.4V
VDD = 2.8V
VIL
Input low voltage
VDD = 2.8V
IIN
Input leakage current
–2
–
2
A
Input signal
capacitance
–
3.5
–
pF
Output high current
IOL
All
Inputs
Condition
Output low current
Signal CAP
Notes:
MT9V138 DS Rev. D Pub. 5/15 EN
–
–
8
mA
0.7 * VDD_IO
–
VDD_IO + 0.3
V
–0.3
–
0.3 * VDD_IO
V
1. All inputs are protected and may be active when All supplies (2.8V and 1.8V) are turned off.
68
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Power Consumption, Operating Mode
Table 41:
Power Consumption – Condition 1
f
EXTCLK = 27 MHz; VDD = 1.8V; VDD _IO = 2.8V; VAA =2.8V;VAA_PIX=2.8V;
VDD _PLL = 2.8V; VDD _DAC = 2.8V
Power Plane
Supply
VDD
VDD_IO
VAA
VAA_PIX
VDD_DAC
VDD_PLL
1.8
2.8
2.8
2.8
2.8
2.8
Condition 1
Parallel off
Single 75(1)
Total
Typ Power
Max Power
Unit
140.4
4.2
89.6
1.96
39.2
13.44
288.8
162
8.4
112
5.04
44.8
16.8
349.04
mW
mW
mW
mW
mW
mW
mW
Analog output uses single-ended mode: DAC_Pos = 75, DAC_Neg = open, parallel
output is disabled.
Table 42:
Power Consumption – Condition 2
fEXTCLK = 27 MHz; VDD = 1.8V; VDD _IO = 2.8V; VAA =2.8V;VAA_PIX=2.8V;
VDD _PLL = 2.8V; VDD _DAC = 2.8V
Power Plane
Supply
VDD
VDD_IO
VAA
VAA_PIX
VDD_DAC
VDD_PLL
1.8
2.8
2.8
2.8
2.8
2.8
Condition 2
Parallel on
Single 75(1)
Total
Typ Power
Max Power
Unit
140.4
42
89.6
1.96
39.2
13.44
326.6
162
50.4
112
5.04
44.8
16.8
391.04
mW
mW
mW
mW
mW
mW
mW
Analog output uses single-ended mode: DAC_Pos = 75, DAC_Neg = open, parallel
output is enabled.
MT9V138 DS Rev. D Pub. 5/15 EN
69
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
NTSC Signal Parameters
Table 43:
NTSC Signal Parameters
f
EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter
Conditions
Min
Typ
Max
Units
Line Frequency
15734.25
15734.27
15734.28
Hz
Field Frequency
59.94
59.94
59.94
Hz
Sync Rise Time
148
148
148
ns
Sync Fall Time
148
148
148
ns
Sync Width
4.74
4.74
4.74
s
Sync Level
38
40
42
IRE
2, 4
2, 4
Burst Level
38
40
42
IRE
Sync to Setup
(with pedestal off)
9.44
9.44
9.44
s
Sync to Burst Start
5.33
5.33
5.33
s
Front Porch
1.33
1.33
1.33
Notes
s
Black Level
7.5
IRE
1, 2, 4
White Level
100
IRE
1, 2, 3, 4
Notes:
MT9V138 DS Rev. D Pub. 5/15 EN
1.
2.
3.
4.
Black and white levels are referenced to the blanking level.
NTSC convention standardized by the IRE (1 IRE = 7.14mV).
Encoder contrast setting R0x011 = R0x001 = 0.
DAC ref = 2.35k, load = 37.5
70
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Figure 52:
Video Timing
A
D
E
C
B
J
F
K
H
Table 44:
G
H
Video Timing
A
B
C
D
E
F
G
H
J
K
MT9V138 DS Rev. D Pub. 5/15 EN
Signal
NTSC
27 MHz
PAL
27 MHz
Units
H Period
Hsync to burst
burst
Hsync to Signal
Video Signal
Front
Hsync Period
Sync rising/falling edge
Back overscan (BOS)
Front overscan (FOS)
1716
144
63
255
1423
36
128
4
9
8
1728
153
66
279
1413
39
128
4
14
13
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
71
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Figure 53:
Equivalent Pulse
L
I
J
K
Table 45:
K
Equivalent Pulse
I
J
K
L
MT9V138 DS Rev. D Pub. 5/15 EN
Signal
NTSC
27 MHz
PAL
27 MHz
Units
H/2 Period
Pulse width
Pulse rising/falling edge
Signal to pulse
858
64
4
38
864
64
4
41
Clocks
Clocks
Clocks
Clocks
72
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Figure 54:
V Pulse
M
O
N
P
Table 46:
P
V Pulse
M
N
O
P
MT9V138 DS Rev. D Pub. 5/15 EN
Signal
NTSC
27 MHz
PAL
27 MHz
Units
H/2 Period
Pulse width
V pulse interval
Pulse rising/falling edge
858
730
128
4
864
736
128
4
Clocks
Clocks
Clocks
Clocks
73
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Two-Wire Serial Bus Timing
Figure 55 and Table 47 describe the timing for the two-wire serial interface.
Figure 55:
Two-Wire Serial Bus Timing Parameters
SDATA
tLOW
tf
tSU;DAT
tr
tf
tHD;STA
tr
tBUF
SCLK
tHD;STA
S
Table 47:
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Standard-Mode
Parameter
SCLK Clock Frequency
Fast-Mode
Symbol
Min
Max
Min
Max
Unit
fSCL
0
100
0
400
KHz
tHD;STA
4.0
-
0.6
-
S
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
LOW period of the SCLK clock
tLOW
4.7
-
1.3
-
S
HIGH period of the SCLK clock
tHIGH
4.0
-
0.6
-
S
Set-up time for a repeated START
condition
tSU;STA
4.7
-
0.6
-
S
Data hold time:
tHD;DAT
04
3.455
06
0.95
S
Data set-up time
tSU;DAT
-
1006
-
nS
300
nS
300
nS
250
Rise time of both SDATA and SCLK signals
tr
-
1000
20 + 0.1Cb7
Fall time of both SDATA and SCLK signals
t
f
-
300
20 + 0.1Cb7
tSU;STO
4.0
-
0.6
-
S
tBUF
4.7
-
1.3
-
S
Cb
-
400
-
400
pF
CIN_SI
-
3.3
-
3.3
pF
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull-up resistor
Notes:
MT9V138 DS Rev. D Pub. 5/15 EN
CLOAD_SD
-
30
-
30
pF
RSD
1.5
4.7
1.5
4.7
K
This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
Two-wire control is I2C-compatible.
All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
1.
2.
3.
4.
74
©Semiconductor Components Industries, LLC,2015.
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Spectral Characteristics
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
t
SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
Spectral Characteristics
Figure 56:
Quantum Efficiency
80
Quantum Efficiency (%)
70
B lue
G reen (B )
G reen (R )
R ed
60
50
40
30
20
10
0
350
450
550
650
750
850
950
1050
1150
Wavelength (nm)
MT9V138 DS Rev. D Pub. 5/15 EN
75
©Semiconductor Components Industries, LLC,2015.
48-Pin CLCC Package Outline Drawing
Figure 57:
MT9V138 DS Rev. D Pub. 5/15 EN
Package and Die Dimensions
©Semiconductor Components Industries, LLC,2015
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Spectral Characteristics
76
MT9V138: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Revision History
Revision History
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/29/15
• Converted to ON Semiconductor template
• Updated “Ordering Information” on page 3
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/22/10
• Updated capacitor value in “Crystal Usage” on page 11
• Updated Note 4 in Table 43, “NTSC Signal Parameters,” on page 70
• Updated Figure 55: “Two-Wire Serial Bus Timing Parameters,” on page 74
• Updated Table 47, “Two-Wire Serial Bus Characteristics,” on page 74
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/25/10
• Updated to Production
• Updated Package pitch number
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/5/10
• Initial release
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MT9V138 DS Rev. D Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015 .