STMicroelectronics M95040-W Compatible with spi bus serial interface Datasheet

M950x0-W M950x0-R M950x0-DF
4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM
with high-speed clock
Datasheet - production data
Features
• Compatible with SPI bus serial interface
(Positive clock SPI modes)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
• Single supply voltage:
– 2.5 V to 5.5 V for M950x0-W
– 1.8 V to 5.5 V for M950x0-R
– 1.7 V to 5.5 V for M95040-DF
• High-speed 20 MHz clock rate, 5 ms write time
• Memory array:
– 1/2/4 Kbit (128/256/512 bytes) of EEPROM
– Page size: 16 bytes
– Write protection by block: 1/4, 1/2 or whole
memory
– Additional Write lockable Page
(Identification page)
• Enhanced ESD protection
• More than 4 million write cycles
• More than 200-year data retention
• Packages RoHS-compliant and Halogen-free
(ECOPACK®)
Table 1. Device summary
UFDFPN8 (MC)
2 x 3 mm
Reference
Part number
M95040-W
M950x0-W
M95020-W
M95010-W
M95040-R
M950x0-R
M95020-R
M95010-R
M950x0-DF
August 2014
This is information on a product in full production.
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www.st.com
Contents
M950x0-W M950x0-R M950x0-DF
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8.2
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8.3
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
4
2.8.1
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/46
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.3
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Contents
6.4
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7
Read Identification Page (available only in M95040-D device) . . . . . . . . 25
6.8
Write Identification Page (available only in M95040-D device) . . . . . . . . 26
6.9
Read Lock Status (available only in M95040-D device) . . . . . . . . . . . . . . 27
6.10
Lock Identification Page (available only in M95040-D device) . . . . . . . . . 28
Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1
Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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3
List of tables
M950x0-W M950x0-R M950x0-DF
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
4/46
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Significant bits within the address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating conditions (M950x0-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating conditions (M950x0-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating conditions (M95040-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC characteristics (M950x0-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC characteristics (M950x0-R or M95040-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . 34
AC characteristics (M950x0-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AC characteristics (M950x0-R or M95040-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics (M950x0-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AC characteristics (M950x0-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SO8N 8-lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TSSOP8 8-lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . . . . 41
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC test measurement I/O waveform(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SO8N 8-lead plastic small outline 150 mils body width, package outline . . . . . . . . . . . . . . 40
TSSOP8 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 41
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Description
1
M950x0-W M950x0-R M950x0-DF
Description
The M95010/ M95020/M95040 devices (M950x0) are electrically erasable programmable
memories (EEPROMs) organized as 128/256/512 x 8 bits respectively, accessed through
the SPI bus.
The M950x0-W can operate with a supply voltage from 2.5 V to 5.5 V, the M950x0-R can
operate with a supply voltage from 1.8 V to 5.5 V, and the M950x0-DF can operate with a
supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
The M950x0-DF offers an additional page, named the Identification Page (16 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
6##
$
1
#
3
-XXX
7
(/,$
633
!)#
Figure 2. 8-pin package connections
-XXX
3 1 7 633 6##
(/,$
#
$
!)$
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
6/46
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Description
Table 2. Signal names
Signal name
Function
C
Serial Clock
D
Serial Data input
Q
Serial Data output
S
Chip Select
W
Write Protect
HOLD
Hold
VCC
Supply voltage
VSS
Ground
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Signal description
2
M950x0-W M950x0-R M950x0-DF
Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals can be held high or low (according to voltages of VIH, VOH,
VIL or VOL, as specified in Table 16: DC characteristics (M950x0-W, device grade 6) and
Table 17: DC characteristics (M950x0-R or M95040-DF, device grade 6). These signals are
described next.
2.1
Serial Data Output (Q)
This output signal transfers data serially out of the device. Data is shifted out on the falling
edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal transfers data serially into the device. It receives instructions, addresses,
and the data to be written. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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2.6
Signal description
Write Protect (W)
This input signal controls whether the memory is write protected. When Write Protect (W) is
held low, writes to the memory are disabled, but other operations remain enabled.
Write Protect (W) must either be driven high or low, but must not be left floating.
2.7
VSS ground
VSS is the reference for the VCC supply voltage.
2.8
Supply voltage (VCC)
2.8.1
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 9: Operating
conditions (M950x0-W), Table 10: Operating conditions (M950x0-R) and Table 11:
Operating conditions (M95040-DF, device grade 6)). This voltage must remain stable and
valid until the end of the transmission of the instruction and, for a Write instruction, until the
completion of the internal write cycle (tW).
In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line
with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS
package pins.
2.8.2
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches the internal reset threshold voltage (this threshold is defined in Table 9: Operating
conditions (M950x0-W), Table 10: Operating conditions (M950x0-R) and Table 11:
Operating conditions (M95040-DF, device grade 6) as VRES).
When VCC passes over the POR threshold, the device is reset and is in the following state:
•
Standby Power mode
•
Deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S))
•
Status register value:
–
Write Enable Latch (WEL) is reset to 0
–
Write In Progress (WIP) is reset to 0
–
SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When the device is in the above state, it must not be accessed until VCC reaches a valid and
stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 9:
Operating conditions (M950x0-W), Table 10: Operating conditions (M950x0-R) and
Table 11: Operating conditions (M95040-DF, device grade 6).
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Signal description
2.8.3
M950x0-W M950x0-R M950x0-DF
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 3: Bus master and memory devices on the SPI bus).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 9: Operating conditions (M950x0-W), Table 10: Operating conditions
(M950x0-R) and Table 11: Operating conditions (M95040-DF, device grade 6) and the rise
time must not vary faster than 1 V/µs.
2.8.4
Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in Table 9: Operating conditions (M950x0-W), Table 10:
Operating conditions (M950x0-R) and Table 11: Operating conditions (M95040-DF, device
grade 6)), the device must be:
10/46
•
Deselected (Chip Select S should be allowed to follow the voltage applied on VCC)
•
In Standby Power mode (there should not be any internal write cycle in progress).
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3
Connecting to the SPI bus
Connecting to the SPI bus
The device is fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 3: Bus master and memory devices on the SPI bus shows an example of three
memory devices connected to an MCU, on an SPI bus. Only one memory device is selected
at a time, so only one memory device drives the Serial Data output (Q) line at a time, the
other memory devices are high impedance.
The pull-up resistor R (represented in Figure 3: Bus master and memory devices on the SPI
bus) ensures that a device is not selected if the bus master leaves the S line in the high
impedance state.
In applications where the bus master might enter a state where all SPI bus inputs/outputs
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an Instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ..
Figure 3. Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
Bus master
SPI mmory
device
R
CS3
VCC
C Q D
VSS
VCC
C Q D
VSS
SPI memory
device
R
VSS
SPI memory
device
R
CS2 CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12304b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
DocID6512 Rev 13
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Connecting to the SPI bus
3.1
M950x0-W M950x0-R M950x0-DF
SPI modes
The device can be driven by a microcontroller with its SPI peripheral running in either of the
following modes:
•
CPOL=0, CPHA=0
•
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4: SPI modes supported, is the
clock polarity when the bus master is in Stand-by mode and not transferring data:
•
C remains at 0 for (CPOL=0, CPHA=0)
•
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. SPI modes supported
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M950x0-W M950x0-R M950x0-DF
Operating features
4
Operating features
4.1
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 5: Hold condition activation).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5: Hold condition activation also shows what happens if the rising and falling edges
are not timed to coincide with Serial Clock (C) being low.
Figure 5. Hold condition activation
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4.2
Status register
Figure 6 shows the position of the Status register in the control logic of the device. This
register contains a number of control bits and status bits, as shown in Table 6: Status
register format and as detailed in Section 6.3: Read Status Register (RDSR).
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Operating features
4.3
M950x0-W M950x0-R M950x0-DF
Data protection and protocol control
To help protect the device from data corruption in noisy or poorly controlled environments, a
number of safety features have been built in to the device. The main security measures can
be summarized as follows:
•
WEL bit is reset at power-up.
•
Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to
start a non-volatile Write cycle (in the memory array or in the Status register).
•
Accesses to the memory array are ignored during the non-volatile programming cycle,
and the programming cycle continues unaffected.
•
Invalid Chip Select (S) and Hold (HOLD) transitions are ignored.
For any instruction to be accepted and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) that latches the last bit of the instruction, and before the
next rising edge of Serial Clock (C).
For this, “the last bit of the instruction” can be the eighth bit of the instruction code, or the
eighth bit of a data byte, depending on the instruction (except in the case of RDSR and
READ instructions). Moreover, the “next rising edge of CLOCK” might (or might not) be the
next bus transaction for some other device on the bus.
When a Write cycle is in progress, the device protects it against external interruption by
ignoring any subsequent READ, WRITE or WRSR instruction until the present cycle is
complete.
Table 3. Write-protected block size
Status register bits
Protected array addresses
Protected block
14/46
BP1
BP0
M95040
M95020
M95010
0
0
none
none
none
none
0
1
Upper quarter
180h - 1FFh
C0h - FFh
60h - 7Fh
1
0
Upper half
100h - 1FFh
80h - FFh
40h - 7Fh
1
1
Whole memory
000h - 1FFh
00h - FFh
00h - 7Fh
DocID6512 Rev 13
M950x0-W M950x0-R M950x0-DF
Memory organization
The memory is organized as shown in Figure 6.
Figure 6. Block diagram
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DocID6512 Rev 13
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Instructions
6
M950x0-W M950x0-R M950x0-DF
Instructions
Each command is composed of bytes (MSBit transmitted first), initiated with the instruction
byte, as summarized in Table 4.
If an invalid instruction is sent (one not contained in Table 4), the device automatically enters
a Wait state until deselected.
Table 4. Instruction set
Instruction
Instruction
format
Description
WREN
Write Enable
0000 X110(1)
WRDI
Write Disable
0000 X100(1)
RDSR
Read Status Register
0000 X101(1)
WRSR
Write Status Register
0000 X001(1)
READ
Read from Memory Array
0000 A8011(2)
WRITE
Write to Memory Array
0000 A8010(2)
RDID(3)
Read Identification Page
1000 0011
(3)
Write Identification Page
1000 0010
RDLS(3)
Reads the Identification Page lock status.
1000 0011
LID(3)
Locks the Identification page in read-only mode.
1000 0010
WRID
1. X = Don’t Care.
2. For M95040, A8 = 1 for the upper half of the memory array and 0 for the lower half, while for M95010 and
M95020, A8 is Don’t Care.
3. Available only for the M95040-DF device.
Table 5. Significant bits within the address byte(1)(2)
Instructions
Bit b3 of the
instruction byte
Address byte
b7
b6
b5
b4
b3
b2
b1
b0
A8/x(3)
A7
A6
A5
A4
A3
A2
A1
A0
RDID or WRID
0
0
0
0
0
A3
A2
A1
A0
RDLS or LID
0
1
0
0
0
0
0
0
0
READ or WRITE
1. A: Significant address bit.
2. x: bit is Don’t Care.
3. For M95040, A8 = 1 for the upper half of the memory array and 0 for the lower half, while for M95010 and
M95020, A8 is Don’t Care.
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M950x0-W M950x0-R M950x0-DF
6.1
Instructions
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7: Write Enable (WREN) sequence, to send this instruction to the
device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on
Serial Data Input (D). The device then enters a wait state. It waits for a the device to be
deselected, by Chip Select (S) being driven high.
Figure 7. Write Enable (WREN) sequence
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DocID6512 Rev 13
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Instructions
6.2
M950x0-W M950x0-R M950x0-DF
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device. As shown in Figure 8: Write Disable (WRDI) sequence, to send this instruction
to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in,
on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be
deselected, by Chip Select (S) being driven high.
The Write Enable Latch (WEL) bit is reset by any of the following events:
•
Power-up
•
WRDI instruction execution
•
WRSR instruction completion
•
WRITE instruction completion
•
Write Protect (W) line being held low.
Figure 8. Write Disable (WRDI) sequence
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M950x0-W M950x0-R M950x0-DF
6.3
Instructions
Read Status Register (RDSR)
The Read Status Register instruction is used to read the Status Register.
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current
state of the bits in the Status register is shifted out, on Serial Data Out (Q). The Read Cycle
is terminated by driving Chip Select (S) high.
The Status Register is always readable, even if a Write or Write Status Register cycle is in
progress. During a Write Status Register cycle, the values of the non-volatile bits (BP0,
BP1) become available when a new RDSR instruction is executed, after completion of the
Write cycle. On the other hand, the two read-only bits (Write Enable Latch (WEL), Write In
Progress (WIP)) are dynamically updated during the ongoing Write cycle.
It is possible to read the Status Register contents continuously, as described in Figure 9.
Bits b7, b6, b5 and b4 are always read as 1. The status and control bits of the Status register
are as follows:
Table 6. Status register format
b7
1
b0
1
1
1
BP1
BP0
WEL
WIP
Block Protect bits
Write Enable Latch bit
Write In Progress bit
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
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Instructions
6.3.3
M950x0-W M950x0-R M950x0-DF
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 3: Write-protected block size) becomes
protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set.
Figure 9. Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
MSB
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI01444D
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M950x0-W M950x0-R M950x0-DF
6.4
Instructions
Write Status Register (WRSR)
A Write Status Register (WRSR) instruction allows new values to be written to the Status
register. Before it can be accepted, a Write Enable (WREN) instruction must previously have
been executed.
The WRSR instruction is entered by driving Chip Select (S) low, sending the instruction
code followed by the data byte on Serial Data input (D), and driving the Chip Select (S)
signal high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the WRSR instruction is not executed.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed write cycle that takes tW to complete (as specified in Table 16: DC characteristics
(M950x0-W, device grade 6) to Table 19: AC characteristics (M950x0-R or M95040-DF,
device grade 6)). The instruction sequence is shown in Figure 10: Write Status Register
(WRSR) sequence.
While the Write Status Register cycle is in progress, the Status register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also
reset at the end of the write cycle tW.
The WRSR instruction allows the user to change the values of the BP1, BP0 bits which
define the size of the area that is to be treated as read only, as defined in Table 3: Writeprotected block size. The contents of the BP1, BP0 bits are updated after the completion of
the WRSR instruction, including the tW write cycle.
The WRSR instruction has no effect on the b7, b6, b5, b4, b1 and b0 bits in the Status
register which are always read as 0.
Figure 10. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI01445B
The WRSR instruction is not accepted, and is not executed, under the following conditions:
•
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
•
if a write cycle is already in progress
•
if the device has not been deselected, by Chip Select (S) being driven high, after the
eighth bit, b0, of the data byte has been latched in
•
if Write Protect (W) is low during the WRSR command (instruction, address and data)
DocID6512 Rev 13
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Instructions
6.5
M950x0-W M950x0-R M950x0-DF
Read from Memory Array (READ)
As shown in Figure 11: Read from Memory Array (READ) sequence, to send this instruction
to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address
byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant
address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in Table 4:
Instruction set. The address is loaded into an internal address register, and the byte of data
at that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, an internal bit-pointer is automatically
incremented at each clock cycle, and the corresponding data bit is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Table 7. Address range bits
Device
M95040
M95020
M95010
Address Bits
A8-A0
A7-A0
A6-A0
Figure 11. Read from Memory Array (READ) sequence
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are Don’t Care.
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M950x0-W M950x0-R M950x0-DF
6.6
Instructions
Write to Memory Array (WRITE)
As shown in Figure 12: Byte Write (WRITE) sequence, to send this instruction to the device,
Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least
one data byte are then shifted in, on Serial Data input (D). The instruction is terminated by
driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle,
triggered by the rising edge of Chip Select (S), continues for a period tW (as specified in
Table 16: DC characteristics (M950x0-W, device grade 6) to Table 19: AC characteristics
(M950x0-R or M95040-DF, device grade 6)). After this time, the Write in Progress (WIP) bit
is reset to 0.
In the case of Figure 12: Byte Write (WRITE) sequence, Chip Select (S) is driven high after
the eighth bit of the data byte has been latched in, indicating that the instruction is being
used to write a single byte. If, though, Chip Select (S) continues to be driven low, as shown
in Figure 13: Page Write (WRITE) sequence, the next byte of input data is shifted in, so that
more than a single byte, starting from the given address towards the end of the same page,
can be written in a single internal Write cycle. If Chip Select (S) still continues to be driven
low, the next byte of input data is shifted in, and used to overwrite the byte at the start of the
current page.
The instruction is not accepted, and is not executed, under the following conditions:
Note:
•
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
•
if a Write cycle is already in progress
•
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and
before the next rising edge of Serial Clock (C) occurs anywhere on the bus)
•
if Write Protect (W) is low or if the addressed page is in the area protected by the Block
Protect (BP1 and BP0) bits
The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit
is read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
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are Don’t Care.
DocID6512 Rev 13
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45
Instructions
M950x0-W M950x0-R M950x0-DF
Figure 13. Page Write (WRITE) sequence
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24/46
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M950x0-W M950x0-R M950x0-DF
6.7
Instructions
Read Identification Page (available only in M95040-D device)
The Read Identification Page (RDID) instruction is used to read the Identification Page
(additional page of 16 bytes which can be written and later permanently locked in Read-only
mode).
The Chip Select (S) signal is first driven low, the bits of the instruction byte and address
bytes are then shifted in (MSB first) on Serial Data input (D). Address bit A7 must be 0 and
the other address bits are Don't Care except the lower address bits [A3:A0] (it might be
easier to define these bits as 0, as shown in Table 5). Data is then shifted/clocked out (MSB
first) on Serial Data output (Q).
The first byte addressed can be any byte within the identification page.
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented and the byte of data at the new address is shifted out.
Note that there is no roll over feature in the Identification Page. The address of bytes to read
must not exceed the page boundary.
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time when the data bits are shifted out.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 14. Read Identification Page sequence
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Instructions
6.8
M950x0-W M950x0-R M950x0-DF
Write Identification Page (available only in M95040-D device)
The Write Identification Page (WRID) instruction is used to write the Identification Page
(additional page of 16 bytes which can also be permanently locked in Read-only mode).
The Chip Select signal (S) is first driven low, and then the bits of the instruction byte,
address bytes, and at least one data byte are shifted in (MSB first) on Serial Data input (D).
Address bit A7 must be 0 and the other address bits are Don't Care except the lower
address bits [A3:A0] (it might be easier to define these bits as 0, as shown in Table 5).
The self-timed Write cycle starts from the rising edge of Chip Select (S), and continues for a
period tW (as specified in Chapter 9: DC and AC parameters).
Figure 15. Write Identification Page sequence
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The instruction is discarded, and is not executed if the Block Protect bits (BP1,BP0) = (1,1)
or one of the conditions defined in Section 4.3: Data protection and protocol control is not
satisfied.
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M950x0-W M950x0-R M950x0-DF
6.9
Instructions
Read Lock Status (available only in M95040-D device)
The Read Lock Status (RDLS) instruction is used to read the lock status.
To send this instruction to the device, Chip Select (S) first has to be driven low. The bits of
the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input
(D). Address bit A7 must be 1; all other address bits are Don't Care (it might be easier to
define these bits as 0, as shown in Table 5). The Lock bit is the LSB (Least Significant Bit) of
the byte read on Serial Data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the
lock is not active. If Chip Select (S) continues to be driven low, the same data byte is shifted
out.
The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is
shown in Figure 16.
The Read Lock Status instruction is not accepted and not executed if a Write cycle is
currently in progress.
Figure 16. Read Lock Status sequence
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Instructions
6.10
M950x0-W M950x0-R M950x0-DF
Lock Identification Page (available only in M95040-D device)
The Lock Identification Page (LID) command is used to permanently lock the Identification
Page in Read-only mode.
The LID instruction is issued by driving Chip Select (S) low, sending (MSB first) the
instruction code, the address and a data byte on Serial Data input (D), and driving Chip
Select (S) high. In the address sent, A7 must be equal to 1. All other address bits are Don't
Care (it might be easier to define these bits as 0, as shown in Table 5). The data byte sent
must be equal to the binary value xxxx xx1x, where x = Don't Care. The LID instruction is
terminated by driving Chip Select (S) high at a data byte boundary, otherwise, the instruction
is not executed.
Figure 17. Lock ID sequence
^
Ϭ
ϭ
Ϯ
ϯ
ϰ
ϱ
ϲ
ϳ
ϴ
ϵ
ϭϬ
ϭϯ ϭϰ ϭϱ ϭϲ ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ Ϯϰ Ϯϱ
/ŶƐƚƌƵĐƚŝŽŶ
ϴͲďŝƚĂĚĚƌĞƐƐ
ϳ
ϲ
ϱ
ϯ
ĂƚĂďLJƚĞ
Ϯ
ϭ
Ϭ
ϳ
ϲ
ϱ
ϰ
ϯ
Ϯ
ϭ
Ϭ
,ŝŐŚŝŵƉĞĚĂŶĐĞ
Y
D^ϯϭϲϯϮsϭ
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write
cycle which duration is tW (specified in Section 9: DC and AC parameters). The instruction
sequence is shown in Figure 17.
The instruction is discarded, and is not executed if the Block Protect bits (BP1,BP0) = (1,1)
or one of the conditions defined in Section 4.3: Data protection and protocol control is not
satisfied.
28/46
DocID6512 Rev 13
M950x0-W M950x0-R M950x0-DF
Power-up and delivery states
7
Power-up and delivery states
7.1
Power-up state
After Power-up, the device is in the following state:
•
Low power Standby Power mode
•
Deselected (after Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started)
•
Not in Hold Condition
•
Write Enable Latch (WEL) is reset to 0
•
Write In Progress (WIP) is reset to 0
The BP1 and BP0 bits of the Status register are unchanged from the previous power-down
(they are non-volatile bits).
7.2
Initial delivery state
The device is delivered with:
•
the memory array set to all 1s (each byte = FFh)
•
Status register: bit SRWD =0, BP1 =0 and BP0 =0
•
M95040-D only: the identification page bytes values are Don’t Care.
DocID6512 Rev 13
29/46
45
Maximum rating
8
M950x0-W M950x0-R M950x0-DF
Maximum rating
Stressing the device outside the ratings listed in Table 8: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 8. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
TAMR
Ambient operating temperature
–40
130
°C
TSTG
Storage temperature
–65
150
°C
(1)
°C
TLEAD
Lead temperature during soldering
see note
VO
Output voltage
–0.50
VCC+0.6
V
VI
Input voltage
–0.50
VCC+1.0
V
IOL
DC output current (Q = 0)
-
5
mA
IIH
DC output current (Q = 1)
-
5
mA
–0.50
6.5
V
-
4000
V
VCC
VESD
Supply voltage
Electrostatic pulse (Human Body Model)
voltage(2)
1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS
directive 2011/65/EU of July 2011).
2. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with JEDEC
Std JESD22-A114, C1=100pF, R1=1500 Ω, R2=500 Ω).
30/46
DocID6512 Rev 13
M950x0-W M950x0-R M950x0-DF
9
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 9. Operating conditions (M950x0-W)
Symbol
VCC
TA
Parameter
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Table 10. Operating conditions (M950x0-R)
Symbol
VCC
TA
Parameter
Table 11. Operating conditions (M95040-DF, device grade 6)
Symbol
Parameter
VCC
TA
Min.
Max.
Unit
Supply voltage
1.7
5.5
V
Ambient operating temperature
–40
85
°C
Max.
Unit
Table 12. AC test measurement conditions
Symbol
CL
Parameter
Min.
Load capacitance
30
pF
-
Input rise and fall times
-
50
ns
-
Input pulse voltages
0.2VCC to 0.8VCC
V
-
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
Figure 18. AC test measurement I/O waveform(1)
,QSXW/HYHOV
,QSXWDQG2XWSXW7LPLQJ
5HIHUHQFH/HYHOV
9&&
9&&
9&&
9&&
DLG
1. Output Hi-Z is defined as the point where data out is no longer driven.
DocID6512 Rev 13
31/46
45
DC and AC parameters
M950x0-W M950x0-R M950x0-DF
Table 13. Cycling performance(1)
Symbol
Ncycle
Parameter
Write cycle endurance
Test conditions
Min.
Max.
Unit
TA ≤ 25 °C,
VCC(min) < VCC < VCC(max)
-
4,000,000
TA = 85 °C,
VCC(min) < VCC < VCC(max)
-
Write cycle
1,200,000
1. Cycling performance for products identified by process letter K (previous products were specified with 1
million cycles at 25 °C).
Table 14. Memory cell data retention(1)
Parameter
Test conditions
Data retention
Min.
Unit
200
Year
TA = 55 °C
1. For products identified by process letter K (previous products were specified with a data retention of 40
years at 55°C). The data retention behavior is checked in production, while the 200-year limit is defined
from characterization and qualification results.
Table 15. Capacitance (1)
Symbol
COUT
CIN
Parameter
Test condition
Min.
Max.
Unit
VOUT = 0 V
-
8
pF
Input capacitance (D)
VIN = 0 V
-
8
pF
Input capacitance (other pins)
VIN = 0 V
-
6
pF
Output capacitance (Q)
1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 5 MHz.
32/46
DocID6512 Rev 13
M950x0-W M950x0-R M950x0-DF
DC and AC parameters
Table 16. DC characteristics (M950x0-W, device grade 6)
Symbol
Parameter
Test conditions in addition to those
defined in Table 9
Min.
Max.
Unit
ILI
Input leakage
current
VIN = VSS or VCC
-
±2
µA
ILO
Output leakage
current
S = VCC, VOUT = VSS or VCC
-
±2
µA
VCC = 2.5 V, fC = 5 MHz,
C = 0.1 VCC/0.9 VCC, Q = open
-
2
VCC = 2.5 V, fC = 10 MHz,
C = 0.1 VCC/0.9 VCC, Q = open
-
2
VCC = 5.5 V, fC = 20 MHz,
C = 0.1 VCC/0.9 VCC, Q = open
-
5 (1)
During tW, S = VCC, 2.5 V < VCC < 5.5 V
-
5
S = VCC, VCC = 5.5 V,
VIN = VSS or VCC,
-
3(3)
S = VCC, VCC = 2.5 V,
VIN = VSS or VCC,
-
2 (4)
ICC
ICC0(2)
ICC1
Supply current
(Read)
Supply current
(Write)
Supply current
(Standby)
mA
mA
µA
VIL
Input low voltage
-
–0.45
0.3 VCC
V
VIH
Input high voltage
-
0.7 VCC
VCC+1
V
VOL
Output low voltage
IOL = 1.5 mA, VCC = 2.5 V
-
0.4
V
VOH
Output high voltage
VCC = 2.5 V and IOH = 0.4 mA or
VCC = 5 V and IOH = 2 mA
0.8 VCC
-
V
1.0(5)
1.65(6)
V
VRES(2)
Internal reset
threshold voltage
-
1. Only for the devices identified by process letter K.
2. Characterized only, not tested in production.
3. 2 µA for the devices identified by process letter G or S.
4. 1 µA for the devices identified by process letter G or S.
5. 0.5 V with the device identified by process letter K.
6. 1.5 V with the device identified by process letter K.
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45
DC and AC parameters
M950x0-W M950x0-R M950x0-DF
Table 17. DC characteristics (M950x0-R or M95040-DF, device grade 6)
Symbol
Parameter
Test conditions in addition to those defined
in Table 10 or Table 11 and Table 12(1)
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
-
±2
µA
ILO
Output leakage current
S = VCC, voltage applied on Q = VSS or VCC
-
±2
µA
ICC
Supply current (Read)
VCC = 1.8 V or 1.7 V, fC = 5 MHz,
C = 0.1 VCC/0.9 VCC, Q = open
-
2
mA
ICC0(2)
Supply current (Write)
VCC = 1.8 V or 1.7 V, during tW, S = VCC
-
5
mA
ICC1
Supply current (Standby)
VCC = 1.8 V or 1.7 V, S = VCC, VIN = VSS or
VCC
-
1
µA
VIL
Input low voltage
VCC < 2.5 V
–0.45
0.25 VCC
V
VIH
Input high voltage
VCC < 2.5 V
0.75 VCC
VCC+1
V
VOL
Output low voltage
IOL = 0.15 mA, VCC = 1.8 V or 1.7 V
-
0.3
V
VOH
Output high voltage
IOH = –0.1 mA, VCC = 1.8 V or 1.7 V
0.8 VCC
-
V
1.0(3)
1.65(4)
V
VRES(2)
Internal reset threshold
voltage
-
1. If the application uses the M950x0-R or M95040-DF devices with 2.5 V ≤VCC ≤5.5 V and -40 °C ≤TA ≤+85 °C, please refer to
Table 16: DC characteristics (M950x0-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.
3. 0.5 V with the device identified by process letter K.
4. 1.5 V with the device identified by process letter K.
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M950x0-W M950x0-R M950x0-DF
DC and AC parameters
Table 18. AC characteristics (M950x0-W, device grade 6)(1)
Test conditions specified in Table 9 and Table 12
(2)
Symbol
Alt.
Parameter
VCC = 2.5 to 5.5 V VCC = 4.5 to 5.5 V
Unit
Min.
Max.
Min.
Max.
D.C.
10
D.C.
20
MHz
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
30
-
15
-
ns
tSHCH
tCSS2
S not active setup time
30
-
15
-
ns
tSHSL
tCS
S deselect time
40
-
20
-
ns
tCHSH
tCSH
S active hold time
30
-
15
-
ns
tCHSL
-
S not active hold time
30
-
15
-
ns
(3)
tCLH
Clock high time
40
-
20
-
ns
tCL(3)
tCLL
Clock low time
40
-
20
-
ns
tCLCH(4)
tRC
Clock rise time
-
2
-
2
µs
tCHCL(4)
tFC
Clock fall time
-
2
-
2
µs
tDVCH
tDSU
Data in setup time
10
-
5
-
ns
tCHDX
tDH
Data in hold time
10
-
10
-
ns
tHHCH
-
Clock low hold time after HOLD not active
30
-
15
-
ns
tHLCH
-
Clock low hold time after HOLD active
30
-
15
-
ns
tCLHL
-
Clock low set-up time before HOLD active
0
-
0
-
ns
tCLHH
-
Clock low set-up time before HOLD not active
0
-
0
Output disable time
-
40
-
20
ns
Clock low to output valid
-
40
-
20
ns
tCH
(4)
tDIS
(5)
tV
tSHQZ
tCLQV
ns
tCLQX
tHO
Output hold time
0
-
0
-
ns
tQLQH(4)
tRO
Output rise time
-
40
-
20
ns
tQHQL(4)
tFO
Output fall time
-
40
-
20
ns
tHHQV
tLZ
HOLD high to output valid
-
40
-
20
ns
tHLQZ(4)
tHZ
HOLD low to output high-Z
-
40
-
20
ns
tW
tWC
Write time
-
5
-
5
ms
1. The timing values described in this table are recommended for new designs.
2. Only for devices identified by process letter K.
3. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
4. Characterized only, not tested in production.
5. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.
DocID6512 Rev 13
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45
DC and AC parameters
M950x0-W M950x0-R M950x0-DF
Table 19. AC characteristics (M950x0-R or M95040-DF, device grade 6)(1)
Test conditions specified in Table 10 or Table 11 and Table 12(2)
Symbol
fC
Alt.
Parameter
fSCK Clock frequency
Min.
Max.
Unit
D.C.
5
MHz
tSLCH
tCSS1 S active setup time
60
-
ns
tSHCH
tCSS2 S not active setup time
60
-
ns
90
-
ns
60
-
ns
60
-
ns
tCLH Clock high time
80
-
ns
tCLL Clock low time
80
-
ns
tSHSL
tCS
tCHSH
tCSH S active hold time
tCHSL
tCH(3)
tCL
(3)
-
S deselect time
S not active hold time
tCLCH
(4)
tRC
Clock rise time
-
2
µs
tCHCL
(4)
tFC
Clock fall time
-
2
µs
tDVCH
tDSU Data in setup time
20
-
ns
tCHDX
tDH
Data in hold time
20
-
ns
tHHCH
-
Clock low hold time after HOLD not active
60
-
ns
tHLCH
-
Clock low hold time after HOLD active
60
-
ns
tCLHL
-
Clock low set-up time before HOLD active
0
-
ns
tCLHH
-
Clock low set-up time before HOLD not active
0
-
ns
Output disable time
-
80
ns
Clock low to output valid
-
80
ns
tSHQZ
(4)
tDIS
tCLQV
tV
tCLQX
tHO
Output hold time
0
-
ns
tQLQH(4)
tRO
Output rise time
-
80
ns
tQHQL(4)
tFO
Output fall time
-
80
ns
tHHQV
tLZ
HOLD high to output valid
-
80
ns
tHLQZ(4)
tHZ
HOLD low to output high-Z
-
80
ns
tW
tWC
Write time
-
5
ms
1. The timing values described in this table are recommended for new designs.
2. If the application uses the M950x0-R or M95040-DF devices at 2.5 V ≤VCC ≤5.5 V and -40 °C ≤TA ≤+85 °C,
please refer to Table 18: AC characteristics (M950x0-W, device grade 6), rather than to the above table.
3. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
4. Characterized only, not tested in production.
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M950x0-W M950x0-R M950x0-DF
DC and AC parameters
Table 20. AC characteristics (M950x0-W, device grade 6)(1)
Test conditions specified in Table 9 and Table 12
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK
Clock frequency
D.C.
10
MHz
tSLCH
tCSS1
S active setup time
15
-
ns
tSHCH
tCSS2
S not active setup time
15
-
ns
tSHSL
tCS
S deselect time
40
-
ns
tCHSH
tCSH
S active hold time
25
-
ns
tCHSL
-
S not active hold time
15
-
ns
tCH(2)
tCLH
Clock high time
40
-
ns
(2)
tCLL
Clock low time
40
-
ns
tCLCH(3)
tRC
Clock rise time
-
1
µs
tCHCL(3)
tFC
Clock fall time
-
1
µs
tDVCH
tDSU
Data in setup time
15
-
ns
tCHDX
tDH
Data in hold time
15
-
ns
tHHCH
-
Clock low hold time after HOLD not active
15
-
ns
tHLCH
-
Clock low hold time after HOLD active
20
-
ns
tCLHL
-
Clock low setup time before HOLD active
0
-
ns
tCLHH
-
Clock low setup time before HOLD not active
0
-
ns
Output disable time
-
25
ns
Clock low to output valid
-
35
ns
tCL
tSHQZ
(3)
tDIS
tCLQV
tV
tCLQX
tHO
Output hold time
0
-
ns
tQLQH(3)
tRO
Output rise time
-
20
ns
(3)
tFO
Output fall time
-
20
ns
tHHQV
tLZ
HOLD high to output valid
-
25
ns
tHLQZ(3)
tHZ
HOLD low to output high-Z
-
35
ns
tW
tWC
Write time
-
5
ms
tQHQL
1. Not recommended for new designs, for new designs refer to Table 18: AC characteristics (M950x0-W,
device grade 6)
2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
3. Value guaranteed by characterization, not 100% tested in production.
DocID6512 Rev 13
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45
DC and AC parameters
M950x0-W M950x0-R M950x0-DF
Table 21. AC characteristics (M950x0-R, device grade 6) (1)
Test conditions specified in Table 10 and Table 12 (2)
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK
Clock frequency
D.C.
5
MHz
tSLCH
tCSS1
S active setup time
90
-
ns
tSHCH
tCSS2
S not active setup time
90
-
ns
tSHSL
tCS
S deselect time
100
-
ns
tCHSH
tCSH
S active hold time
90
-
ns
tCHSL
-
S not active hold time
90
-
ns
tCH(3)
tCLH
Clock high time
90
-
ns
(2)
tCLL
Clock low time
90
-
ns
tCLCH(4)
tRC
Clock rise time
-
1
µs
tCHCL(3)
tFC
Clock fall time
-
1
µs
tDVCH
tDSU
Data in setup time
20
-
ns
tCHDX
tDH
Data in hold time
30
-
ns
tHHCH
-
Clock low hold time after HOLD not active
70
-
ns
tHLCH
-
Clock low hold time after HOLD active
40
-
ns
tCLHL
-
Clock low setup time before HOLD active
0
-
ns
tCLHH
-
Clock low setup time before HOLD not active
0
-
ns
Output disable time
-
100
ns
Clock low to output valid
-
80
ns
tCL
tSHQZ
(3)
tDIS
tCLQV
tV
tCLQX
tHO
Output hold time
0
-
ns
tQLQH(3)
tRO
Output rise time
-
50
ns
(3)
tFO
Output fall time
-
50
ns
tHHQV
tLZ
HOLD high to output valid
-
50
ns
tHLQZ(3)
tHZ
HOLD low to output high-Z
-
100
ns
tW
tWC
Write time
-
5
ms
tQHQL
1. Not recommended for new designs, for new designs refer to Table 19: AC characteristics (M950x0-R or
M95040-DF, device grade 6)
2. The test flow guarantees the AC parameter values defined in this table (when VCC = 1.8 V) and the AC
parameter values defined in Table 20: AC characteristics (M950x0-W, device grade 6) (when VCC = 2.5 or
when VCC = 5.0 V).
3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
4. Value guaranteed by characterization, not 100% tested in production.
38/46
DocID6512 Rev 13
M950x0-W M950x0-R M950x0-DF
DC and AC parameters
Figure 19. Serial input timing
T3(3,
3
T#(3,
T#(
T3,#(
T#(3(
T3(#(
#
T$6#(
T#,
T#(#,
T#,#(
T#($8
,3" ).
-3" ).
$
(IGH IMPEDANCE
1
!)D
Figure 20. Hold timing
3
T(,#(
T#,(,
T((#(
#
T#,((
T(,1:
T((16
1
!)C
Figure 21. Serial output timing
3
T#(
T3(3,
#
T#,16
T#,#(
T#(#,
T#,
T3(1:
T#,18
1
T1,1(
T1(1,
$
!$$2
,3" ).
!)F
DocID6512 Rev 13
39/46
45
Package mechanical data
10
M950x0-W M950x0-R M950x0-DF
Package mechanical data
In order to meet environmental requirements, ST offers the device in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 22. SO8N 8-lead plastic small outline 150 mils body width, package outline
K[ƒ
$
$
F
FFF
E
H
PP
*$8*(3/$1(
'
N
(
(
$
/
/
62$
1. Drawing is not to scale.
Table 22. SO8N 8-lead plastic small outline, 150 mils body width, package
mechanical data
Inches(1)
Millimeters
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
A
-
-
1.75
-
-
0.0689
A1
-
0.1
0.25
-
0.0039
0.0098
A2
-
1.25
-
-
0.0492
-
b
-
0.28
0.48
-
0.011
0.0189
c
-
0.17
0.23
-
0.0067
0.0091
ccc
-
-
0.1
-
-
0.0039
D
4.9
4.8
5
0.1929
0.189
0.1969
E
6
5.8
6.2
0.2362
0.2283
0.2441
E1
3.9
3.8
4
0.1535
0.1496
0.1575
e
1.27
-
-
0.05
-
-
h
-
0.25
0.5
-
0.0098
0.0197
k
-
0°
8°
-
0°
8°
L
-
0.4
1.27
-
0.0157
0.05
L1
1.04
-
-
0.0409
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
Figure 23. TSSOP8 8-lead thin shrink small outline, package outline
'
F
( (
D
$
&3
$
$
E
/
/
H
76623$0
1. Drawing is not to scale.
Table 23. TSSOP8 8-lead thin shrink small outline, package mechanical data
Inches(1)
Millimeters
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
A
-
-
1.2
-
-
0.0472
A1
-
0.05
0.15
-
0.002
0.0059
A2
1
0.8
1.05
0.0394
0.0315
0.0413
b
-
0.19
0.3
-
0.0075
0.0118
c
-
0.09
0.2
-
0.0035
0.0079
CP
-
-
0.1
-
-
0.0039
D
3
2.9
3.1
0.1181
0.1142
0.122
e
0.65
-
-
0.0256
-
-
E
6.4
6.2
6.6
0.252
0.2441
0.2598
E1
4.4
4.3
4.5
0.1732
0.1693
0.1772
L
0.6
0.45
0.75
0.0236
0.0177
0.0295
L1
1
-
-
0.0394
-
-
α
-
0°
8°
-
0°
8°
N (number of leads)
8
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M950x0-W M950x0-R M950x0-DF
Figure 24. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, outline
E
$
,
,
0IN %
B
%
+
,
!
$
EEE
!
:7?-%E6
1. Drawing is not to scale.
2. The central pad (area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed
to be connected to any other voltage or signal line on the PCB, for example during the soldering process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 24. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, data
Inches(1)
Millimeters
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
A
0.550
0.450
0.600
0.0217
0.0177
0.0236
A1
0.020
0.000
0.050
0.0008
0.0000
0.0020
b
0.250
0.200
0.300
0.0098
0.0079
0.0118
D
2.000
1.900
2.100
0.0787
0.0748
0.0827
D2 (rev MC)
-
1.200
1.600
-
0.0472
0.0630
E
3.000
2.900
3.100
0.1181
0.1142
0.1220
E2 (rev MC)
-
1.200
1.600
-
0.0472
0.0630
e
0.500
-
-
0.0197
-
-
K (rev MC)
-
0.300
-
-
0.0118
-
L
-
0.300
0.500
-
0.0118
0.0197
L1
-
-
0.150
-
-
0.0059
L3
-
0.300
-
-
0.0118
-
-
0.080
-
-
0.0031
-
eee
(2)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
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11
Part numbering
Part numbering
Table 25. Ordering information scheme
Example:
M95040-D
– W MN 6 T
P
Device type
M95 = SPI serial access EEPROM
Device function
040 = 4 Kbit (512 x 8)
040-D = 4 Kbit (512 x 8) plus identification page
020 = 2 Kbit (256 x 8)
010 = 1 Kbit (128 x 8)
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (MLP8) 2 × 3mm
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
T = Tape and reel packing
blank = tube packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
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Revision history
12
M950x0-W M950x0-R M950x0-DF
Revision history
Table 26. Document revision history
Date
02-Feb-2012
24-May-2013
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Version
Changes
10
Document renamed from “M95040 M95020 M95010” to “M950x0
M950x0-W M950x0-R”
Silhouette of UDFPN8 (MB or MC) on the cover page updated.
Section 6.3: Read Status Register (RDSR) updated.
Text modified in Section 6.3.1: WIP bit.
Table 8: Absolute maximum ratings updated.
Figure 24: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 × 3mm, outline modified.
Table 24: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package
no lead 2 × 3mm, data updated.
Removed tables of available products from Section 11: Part numbering.
11
Document renamed from “M95040 M95020 M95010” to “M950x0-W
M950x0-R”.
Silhouette of UDFPN8 (MB or MC) on the cover page updated.
Section 6.3: Read Status Register (RDSR) updated.
Text modified in Section 6.3.1: WIP bit.
Table 8 and Table 24 updated.
Tables 8, 13, 15, 17, 19 removed.
Figure 24 modified.
Removed tables of available products from Section 11: Part numbering.
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Revision history
Table 26. Document revision history (continued)
Date
17-Oct-2013
28-Aug-2014
Version
Changes
12
Added “M95040-DF” part number.
Updated:
– Features: Single supply voltage, high-speed clock frequency, memory
array, write cycles and data retention
– Section 1: Description
– Figure 6: Block diagram
– Section 6: Instructions: updated introduction and added Section 6.7 to
Section 6.10
– Section 7.2: Initial delivery state
– Note (1) under Table 8: Absolute maximum ratings.
– Table 16: DC characteristics (M950x0-W, device grade 6), Table 18: AC
characteristics (M950x0-W, device grade 6) and Table 25: Ordering
information scheme
Added Table 13: Cycling performance, Table 14: Memory cell data
retention, Table 17: DC characteristics (M950x0-R or M95040-DF, device
grade 6) and Table 19: AC characteristics (M950x0-R or M95040-DF,
device grade 6).
Renamed Table 20 and Table 21.
13
Updated footnotes:
– 1 in Table 13: Cycling performance;
– 1 in Table 14: Memory cell data retention;
– 2 in Table 19: AC characteristics (M950x0-R or M95040-DF, device
grade 6);
– 2 in Table 21: AC characteristics (M950x0-R, device grade 6).
Updated Table 20 with new title AC characteristics (M950x0-W, device
grade 6) and addition of footnote 1.
Updated Table 21 with new title AC characteristics (M950x0-R, device
grade 6) and addition of footnote 1.
Updated Table 25: Ordering information scheme.
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M950x0-W M950x0-R M950x0-DF
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