TI1 LM7372 High speed, high output current, dual operational amplifier Datasheet

LM7372
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SNOS926E – MAY 1999 – REVISED MARCH 2013
LM7372 High Speed, High Output Current, Dual Operational Amplifier
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FEATURES
DESCRIPTION
1
•
23
•
•
•
•
•
•
•
The LM7372 is a high speed dual voltage feedback
amplifier that has the slewing characteristic of current
feedback amplifiers; yet it can be used in all
traditional voltage feedback amplifier configurations.
−80dBc Highest Harmonic Distortion @1MHz,
2VPP
Very High Slew Rate: 3000V/µs
Wide Gain Bandwidth Product: 120MHz
−3dB Frequency @ AV = +2: 200MHz
Low Supply Current: 13mA (both amplifiers)
High Open Loop Gain: 85dB
High Output Current: 150mA
Differential Gain and Phase: 0.01%, 0.02°
The LM7372 is stable for gains as low as +2 or −1. It
provides a very high slew rate at 3000V/µs and a
wide gain bandwidth product of 120MHz, while
consuming only 6.5mA/per amplifier of supply current.
It is ideal for video and high speed signal processing
applications such as xDSL and pulse amplifiers. With
150mA output current, the LM7372 can be used for
video distribution, as a transformer driver or as a
laser diode driver.
APPLICATIONS
•
•
•
•
•
•
Operation on ±15V power supplies allows for large
signal swings and provides greater dynamic range
and signal-to-noise ratio. The LM7372 offers high
SFDR and low THD, ideal for ADC/DAC systems. In
addition, the LM7372 is specified for ±5V operation
for portable applications.
HDSL and ADSL Drivers
Multimedia Broadcast Systems
Professional Video Cameras
CATV/Fiber Optics Signal Processing
Pulse Amplifiers and Peak Detectors
HDTV Amplifiers
The LM7372 is built on TI's Advance VIP™ III
(Vertically integrated PNP) complementary bipolar
process.
Typical Application
VCC
+
C1
0.1uF
5
+ VIN
VCC
4
14
C6
0.1uF
+
1/2
LM7372
-
3
R9
50
R3
5.1k
R1
10.2k
C7
20uF
1:1
R5
2k
Twisted
Pair Line
R6
2k
+
C3
47uF
100
R7
2k
R2
10.2k
R4
5.1k
12
C2
0.1uF
11
- VIN
R8
50
1/2
LM7372
+
13
6
Figure 1. Single Supply Application (16-Pin SOIC)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VIP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
LM7372
SNOS926E – MAY 1999 – REVISED MARCH 2013
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Connection Diagrams
*
1
16
NC
2
15 NC
OUT A
3
14 V+
A
-
+
-IN 4
13
OUT B
12 -IN
5
+IN
*
B
V- 6
* Heatsink Pins.
11 +IN
-
+
NC
7
10 NC
*
8
9
*
(1)
Figure 2. 16-Pin SOIC, Top View
1
8
OUT A
+
V
A
2
-
+
7
-IN A
+IN A
3
6
B
+
-
V
4
OUT B
-IN B
5
+IN B
Figure 3. 8-Pin SO PowerPAD, Top View
NOTE
For SO PowerPAD package the exposed pad should be tied either to V− or left electrically
floating.
(Die attach material is conductive and is internally tied to V−)
(1)
The maximum power dissipation is a function of T(JMAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (T(JMAX) – TA)/θJA. All numbers apply for packages soldered directly into a PC board. The value for θJA is 106°C/W
for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, θJA for the 16-Pin SOIC is
decreased to 70°C/W. 8-Pin SO PowerPAD package θJA is with 2 in2 heatsink (top and bottom layer each) and 1 oz. copper (see
Table 2).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2) (3)
ESD Tolerance
+
Human Body Model
1.5kV (4)
Machine Model
200V (4)
−
Suppy Voltage (V −V )
36V
Differential Input Voltage (VS = ±15V)
±10V
Output Short Circuit to Ground (2)
Continuous
−65°C to 150°C
Storage Temp. Range
Soldering Information
Infrared or Convection Reflow (20 sec.)
235°C
Wave Soldering Lead Temperature (10 sec.)
260°C
V− to V+
Input Voltage
Maximum Junction Temperature (5)
(1)
(2)
(3)
(4)
(5)
150°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
For testing purposes, ESD was applied using human body model, 1.5kΩ in series with 100pF. Machine model, 0Ω in series with 200pF.
The maximum power dissipation is a function of T(JMAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (T(JMAX) – TA)/θJA. All numbers apply for packages soldered directly into a PC board. The value for θJA is 106°C/W
for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, θJA for the 16-Pin SOIC is
decreased to 70°C/W. 8-Pin SO PowerPAD package θJA is with 2 in2 heatsink (top and bottom layer each) and 1 oz. copper (see
Table 2).
Operating Ratings (1)
9V ≤ VS ≤ 36V
Supply Voltage
Junction Temperature Range (TJ)
LM7372
Thermal Resistance(θJA)
16-Pin SOIC (2)
8-Pin SO PowerPAD (2)
(see Application Information)
(1)
(2)
−40°C ≤ TJ ≤ 85°C
106°C/W
70°C/W
47°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
The maximum power dissipation is a function of T(JMAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (T(JMAX) – TA)/θJA. All numbers apply for packages soldered directly into a PC board. The value for θJA is 106°C/W
for the 16-Pin SOIC package. With a total area of 4sq. in of 1oz CU connected to pins 1,6,8,9 & 16, θJA for the 16-Pin SOIC is
decreased to 70°C/W. 8-Pin SO PowerPAD package θJA is with 2 in2 heatsink (top and bottom layer each) and 1 oz. copper (see
Table 2).
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±15V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = 0V and RL = 1kΩ. Boldface apply at the temperature
extremes.
Symbol
Parameter
Conditions
Min (1)
Typ (2)
Max (1)
Units
2.0
8.0
10.0
mV
VOS
Input Offset Voltage
TC VOS
Input Offset Voltage Average Drift
12
IB
Input Bias Current
2.7
10
12
µA
IOS
Input Offset Current
0.1
4.0
6.0
µA
RIN
Input Resistance
RO
Open Loop Output Resistance
CMRR
Common Mode Rejection Ratio
VCM = ±10V
PSRR
Power Supply Rejection Ratio
VS = ±15V to ±5V
VCM
Input Common-Mode Voltage Range
CMRR > 60dB
AV
VO
ISC
IS
(1)
(2)
(3)
4
Large Signal Voltage Gain
(3)
Output Swing
Output Short Circuit Current
µV/°C
Common Mode
40
MΩ
Differential Mode
3.3
MΩ
15
Ω
75
70
93
dB
75
70
90
dB
±13
V
RL = 1kΩ
75
70
85
dB
RL = 100Ω
70
66
81
dB
13
12.7
13.4
V
−13
−12.7
−13.3
V
IOUT = − 150mA
11.8
11.4
12.4
V
IOUT = 150mA
−11.2
−10.8
−11.9
V
Sourcing
260
mA
Sinking
250
RL = 1kΩ
Supply Current (both Amps)
13
mA
17
19
mA
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametic norm.
Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT = ±
10V. For VS = ±5V, VOUT = ±2V
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±15V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = 0V and RL = 1kΩ. Boldface apply at the temperature
extremes.
Symbol
SR
Parameter
Slew Rate
(3)
Conditions
Min (1)
Typ (2)
AV = +2, VIN 13VP-P
3000
AV = +2, VIN 10VP-P
2000
Unity Bandwidth Product
Max (1)
Units
V/µs
120
MHz
−3dB Frequency
AV = +2
220
MHz
φm
Phase Margin
AVOL = 6dB
70
deg
tS
Settling Time (0.1%)
AV = −1, AO = ±5V,
RL = 500Ω
50
ns
tP
Propagation Delay
AV = −2, VIN = ±5V,
RL = 500Ω
6.0
ns
AD
Differential Gain (4)
0.01
%
φD
Differential Phase (4)
0.02
deg
hd2
Second Harmonic Distortion
FIN = 1MHz, AV = +2
VOUT = 2VP-P, RL = 100Ω
−80
dBc
VOUT = 16.8VP-P, RL = 100Ω
−73
dBc
hd3
Third Harmonic Distortion
FIN = 1MHz, AV = +2
VOUT = 2VP-P, RL = 100Ω
−91
dBc
VOUT = 16.8VP-P, RL = 100Ω
−67
dBc
IMD
Intermodulation Distortion
Fin 1 = 75kHz,
Fin 2 = 85kHz
VOUT = 16.8VP-P, RL = 100Ω
−87
dBc
en
Input-Referred Voltage Noise
f = 10kHz
14
nV/√Hz
in
Input-Referred Current Noise
f = 10kHz
1.5
pA/√Hz
(1)
(2)
(3)
(4)
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametic norm.
Slew Rate is the average of the rising and falling slew rates.
Differential gain and phase are measured with AV = +2, VIN = 1VPP at 3.58 MHz and output is 150Ω terminated.
±5V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = 0V and RL = 1kΩ. Boldface apply at the temperature
extremes.
Symbol
Parameter
Conditions
Min (1)
Typ (2)
Max (1)
Units
2.2
8.0
10.0
mV
VOS
Input Offset Voltage
TC VOS
Input Offset Voltage Average Drift
12
IB
Input Bias Current
3.3
10
12
µA
IOS
Input Offset Current
0.1
4
6
µA
RIN
Input Resistance
RO
Open Loop Output Resistance
CMRR
Common Mode Rejection Ratio
VCM = ±2.5V
PSRR
Power Supply Rejection Ratio
VS = ±15V to ±5V
VCM
Input Common-Mode Voltage Range
CMRR > 60dB
(1)
(2)
µV/°C
Common Mode
40
MΩ
Differential Mode
3.3
MΩ
15
Ω
70
65
90
dB
75
70
90
dB
±3
V
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametic norm.
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±5V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = 0V and RL = 1kΩ. Boldface apply at the temperature
extremes.
Symbol
AV
Large Signal Voltage Gain
VO
Output Short Circuit Current
IS
(3)
(3)
Output Swing
ISC
Min (1)
Typ (2)
RL = 1kΩ
70
65
78
dB
RL = 100Ω
64
60
72
dB
RL = 1kΩ
3.2
3.0
3.4
V
−3.2
−3.0
−3.4
V
IOUT = − 80mA
2.5
2.2
2.8
V
IOUT = 80mA
−2.5
−2.2
−2.7
V
Sourcing
150
mA
Sinking
150
Parameter
Conditions
Supply Current (both Amps)
12.4
Max (1)
Units
mA
16
18
mA
Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT = ±
10V. For VS = ±5V, VOUT = ±2V
±5V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = 0V and RL = 1kΩ. Boldface apply at the temperature
extremes.
Symbol
SR
Parameter
Slew Rate
(3)
Min (1)
Conditions
AV = +2, VIN 3VP-P
Unity Bandwidth Product
−3dB Frequency
AV = +2
Typ (2)
Max (1)
Units
700
V/µs
100
MHz
125
MHz
70
deg
φm
Phase Margin
tS
Settling Time (0.1%)
AV = −1, VO = ±1V, RL = 500Ω
70
ns
tP
Propagation Delay
AV = +2, VIN = ±1V, RL = 500Ω
7
ns
AD
Differential Gain (4)
0.02
%
(4)
φD
Differential Phase
0.03
deg
hd2
Second Harmonic Distortion
FIN = 1MHz, AV = +2
VOUT = 2VP-P, RL = 100Ω
−84
dBc
hd3
Third Harmonic Distortion
FIN = 1MHz, AV = +2
VOUT = 2VP-P, RL = 100Ω
−94
dBc
en
Input-Referred Voltage Noise
f = 10kHz
14
nV/√Hz
in
Input-Referred Current Noise
f = 10kHz
1.8
pA/√Hz
(1)
(2)
(3)
(4)
6
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametic norm.
Slew Rate is the average of the rising and falling slew rates.
Differential gain and phase are measured with AV = +2, VIN = 1VPP at 3.58 MHz and output is 150Ω terminated.
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Typical Performance Characteristics
Harmonic Distortion vs
Frequency
Harmonic Distortion vs
Frequency
-30
-50
VS = ±12V
AV = 2
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
VS = ±12V
VO = 2VP-P
-70
HD2
RL = 100
HD3
-90
-110
AV = 2
-50
RL = 100
HD2
-70
-90
-110
1M
100k
1M
100k
10M
Figure 4.
Figure 5.
Harmonic Distortion vs
Frequency
Harmonic Distortion vs
Frequency
-30
-30
VS = ±12V
VS = ±12V
HARMONIC DISTORTION (dBc)
AV = 8
HARMONIC DISTORTION (dBc)
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
VO = 2VP-P
-50
HD2
RL = 100
-70
HD3
-90
HD3
AV = 8
VO = 16.8VP-P
-50
RL = 100
HD2
-70
-90
-110
1M
100k
100M
1M
100k
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6.
Figure 7.
Harmonic Distortion vs
Harmonic Distortion vs
Output Level
-50
-40
VS = ±12V
VS = ±12V
AV = 8
AV = 8
RL = 100
f = 1MHz
RL = 100
f = 100kHz
-70
DISTORTION (dBc)
DISTORTION (dBc)
HD3
VO = 16.8VP-P
HD2
-90
HD3
-110
-60
HD2
-80
HD3
-100
1
10
20
OUTPUT VOLTAGE (VP-P)
1
10
20
OUTPUT VOLTAGE (VP-P)
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
Harmonic Distortion vs
Output Level
Harmonic Distortion vs
Output Level
-50
VS = ±12V
VS = ±12V
AV = 2
AV = 2
RL = 100
f = 100kHZ
-80
DISTORTION (dBc)
DISTORTION (dBc)
-60
HD2
-100
RL = 100
f = 1MHZ
-70
HD2
-90
HD3
HD3
-120
-110
1
10
1
20
OUTPUT VOLTAGE (VP-P)
10
OUTPUT VOLTAGE (VP-P)
Figure 10.
Figure 11.
Harmonic Distortion vs
Load Resistance
Harmonic Distortion vs
Load Resistance
-40
-60
VS = ±12V
VS = ±12v
AV = 2
AV = 2
VO = 2VP-P
f = 100kHz
-80
-60
DISTORTION (dBc)
DISTORTION (dBc)
20
HD2
-100
VO = 2VP-P
f = 1MHz
-80
HD2
HD3
-100
HD3
-120
-120
10
100
1000
10
100
1000
LOAD RESISTANCE (:)
LOAD RESISTANCE (:)
Figure 12.
Figure 13.
Harmonic Distortion vs
Load Resistance
Harmonic Distortion vs
Load Resistance
-40
-40
VS = ±12V
VS = ±12V
AV = 8
-80
HD2
-100
VO = 2VP-P
f = 100kHz
-60
DISTORTION (dBc)
DISTORTION (dBc)
AV = 8
VO = 2VP-P
f = 1MHz
-60
-80
HD2
-100
HD3
HD3
-120
-120
10
100
1000
LOAD RESISTANCE (:)
100
1000
LOAD RESISTANCE (:)
Figure 14.
8
10
Figure 15.
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Typical Performance Characteristics (continued)
Frequency Response
Frequency Response
2
2
VS = ±12V
1
1
RL = 100
GAIN = +2
-1
0
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
-2
GAIN = +8
-3
-4
-1
GAIN = +2
-2
GAIN = +8
-3
-4
-5
-5
-6
-6
VS = ±15V
RL = 100
1
10
100
1
1000
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 16.
Figure 17.
Frequency Response
Small Signal Pulse Response
2
VS = ±5V
VS = ±12V
RL = 100
AV = 2
OUTPUT VOLTAGE (100mV/div)
1
NORMALIZED GAIN (dB)
0
-1
GAIN = +2
-2
GAIN = +8
-3
-4
RL = 100
-5
-6
1
10
100
1000
TIME (100ns/div)
FREQUENCY (MHz)
Figure 18.
Figure 19.
Large Signal Pulse Response
Thermal Performance of 8ld-SO PowerPAD
100
AV = 2
90
RL = 100
80
TJA (°C/W)
OUTPUT VOLTAGE (2V/div)
VS = ±12V
70
0.5 oz
60
1.0 oz
50
2.0 oz
40
30
20
0
TIME (100ns/div)
0.5
1.0
1.5
2.0
2.5
2
COPPER AREA (in )
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
Harmonic Distortion vs
Frequency
Input Bias Current (µA) vs
Temperature
-50
3
VS = ±5V
VS = ±15V
2.5
VO = 2VP-P
-70
INPUT BIAS CURRENT (µA)
HARMONIC DISTORTION (dBc)
AV = 2
RL = 100
HD2
-90
HD3
2
1.5
1
0.5
0
-40
-110
100k
1M
10M
25
85
125
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 22.
Figure 23.
Output Voltage vs
Output Current
20
VS = ±15V
OUTPUT VOLTAGE (V)
POSITIVE OUTPUT
10
0
NEGATIVE OUTPUT
-10
-20
-200
-100
0
100
200
OUTPUT CURRENT (mA)
Figure 24.
10
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Typical Performance Characteristics (continued)
M1
Q1
Q4
RE
IN
-
V
-
IN
+
OUTPUT
BUFFER
+
A
V
Q3
Q2
M2
Figure 25. Simplified Schematic Diagram
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APPLICATION INFORMATION
The LM7372 is a high speed dual operational amplifier with a very high slew rate and very low distortion, yet like
many other op amps, it is used in conventional voltage feedback amplifier applications. Also, again like many op
amps, it has a class AB output stage in order to be able to deliver high currents to low impedance loads, yet
draw a low quiescent supply current in most situations (the supply current increases when necessary to keep up
with large output swing and/or high frequency. See HIGH FREQUENCY/LARGE SIGNAL SWING
CONSIDERATIONS section below). For most op amps in typical applications, this topology means that internal
power dissipation is rarely an issue, even with the trend to smaller surface mount packages. However, the
LM7372 has been designed for applications where significant levels of power dissipation will be encountered,
and an effective means of removing the internal heat generated by this power dissipation is needed to maintain
the semiconductor junction temperature at acceptable levels, particularly in environments with elevated ambient
temperatures.
Several factors contribute to power dissipation and consequently higher semiconductor junction temperatures,
and these factors need to be well understood if the LM7372 is to perform to the desired specifications in a given
application. Since different applications will have different dissipation levels and different compromises can be
made between the ways these factors will contribute to the total junction temperature, this section will examine
the typical application shown on the front page of this data sheet as an example, and offer suggestions for
solutions where excessive junction temperatures are encountered.
There are two major contributors to the internal power dissipation; the product of the supply voltage and the
LM7372 quiescent current when no signal is being delivered to the external load, and the additional power
dissipated while delivering power to the external load. For low frequency (<1MHz) applications, the LM7372
supply current specification will suffice to come up with the quiescent power dissipation (see HIGH
FREQUENCY/LARGE SIGNAL SWING CONSIDERATIONS section for cases where the frequency range
exceeds 1MHz and the LM7372 supply current increases) . The LM7372 quiescent supply current is given as
6.5mA per amplifier, so with a 24Volt supply the power dissipation is
PQ = VS x 2Iq
-3
= 24 x 2 x (6.5 x 10 )
= 312mW
where
(1)
(VS = V+ - V−)
This is already a high level of internal power dissipation, and in a small surface mount package with a thermal
resistance (θJA = 140°C/Watt (a not unreasonable value for an 8-Pin SOIC package) would result in a junction
temperature 140°C/W x 0.312W = 43.7°C above the ambient temperature. A similar calculation using the worst
case maximum supply current specification of 8.5mA per amplifier at an 85°C ambient will yield a power
dissipation of 456mW with a junction temperature of 149°C, perilously close to the maximum permitted junction
temperature of 150°C!
The second contributor to high junction temperature is the additional power dissipated internally when power is
being delivered to the external load. This cause of temperature rise can be less amenable to calculation, even
when the actual operating conditions are known.
For a Class B output stage, one transistor of the output pair will conduct the load current as the output voltage
swings positive, with the other transistor drawing no current, and hence dissipating no power. During the other
half of the signal swing this situation is reversed, with the lower transistor sinking the load current and the upper
transistor is cut off. The current in each transistor will be a half wave rectified version of the total load current.
Ideally neither transistor will dissipate power when there is no signal swing, but will dissipate increasing power as
the output current increases. However, as the signal voltage across the load increases with load current, the
voltage across the output transistor (which is the difference voltage between the supply voltage and the
instantaneous voltage across the load) will decrease and a point will be reached where the dissipation in the
transistor will begin to decrease again. If the signal is driven into a square wave, ideally the transistor dissipation
will fall all the way back to zero.
For each amplifier then, with an effective load each of RL and a sine wave source, integration over the half cycle
with a supply voltage VS and a load voltage VL yields the average power dissipation
PD = VSVL/πRL - VL2/2RL
(2)
where VS is the supply voltage and VL is the peak signal swing across the load RL.
12
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For the package, the power dissipation will be doubled since there are two amplifiers in the package, each
contributing half the swing across the load.
The circuit in Figure 1 is using the LM7372 as the upstream driver in an ADSL application with Discrete
MultiTone modulation. With DMT the upstream signal is spread into 32 adjacent channels each 4kHz wide. For
transmission over POTS, the regular telephone service, this upstream signal from the CPE (Customer Premise
Equipment) occupies a frequency band from around 20kHz up to a maximum frequency of 135kHz. At first sight,
these relatively low transmission frequencies certainly do not seem to require the use of very high speed
amplifiers with GBW products in the range of hundreds of megahertz. However, the close spacing of multiple
channels places stringent requirements on the linearity of the amplifier, since non-linearities in the presence of
multiple tones will cause harmonic products to be generated that can easily interfere with the higher frequency
down stream signals also present on the line. The need to deliver 3rd Harmonic distortion terms lower than
−75dBc is the reason for the LM7372 quiescent current levels. Each amplifier is running over 3mA in the output
stage alone in order to minimize crossover distortion.
xDSL signal levels are adjusted to provide a given power level on the line, and in the case of ADSL this is an
average power of 13dBm. For a line with a characteristic impedance of 100Ω this is only 20mW (= 1mW x
10(13/10)). Because the transformer shown in Figure 1 is part of a transceiver circuit, two back-termination
resistors are connected in series with each amplifier output. Therefore the equivalent RL for each amplifier is also
100Ω, and each amplifier is required to deliver 20mW to this load.
Since VL2/2RL = 20mW then VL = 2V(peak).
(3)
Using Equation 2 with this value for signal swing and a 24V supply, the internal power dissipation per amplifier is
132.8mW. Adding the quiescent power dissipation to the amplifier dissipation gives the total package internal
power dissipation as
PD(TOTAL) = 312mW + (2 x 132.8mW) = 578mW
(4)
This result is actually quite pessimistic because it assumes that the dissipation as a result of load current is
simply added to the dissipation as a result of quiescent current. This is not correct since the AB bias current in
the output stage is diverted to load current as the signal swing amplitude increases from zero. In fact with load
currents in excess of 3.3mA, all the bias current is flowing in the load, consequently reducing the quiescent
component of power dissipation. Also, it assumes a sine wave signal waveform when the actual waveform is
composed of many tones of different phases and amplitudes which may demonstrate lower average power
dissipation levels.
The average current for a load power of 20mW is 14.1mA (= √(20mW/100)). Neglecting the AB bias current, this
appears as a full-wave rectified current waveform in the supply current with a peak value of 19.9mA. The peak to
average ratio for a waveform of this shape is 1.57, so the total average load current is 12.7mA (= 19.9mA/1.57).
Adding this to the quiescent current, and subtracting the power dissipated in the load (20mV x 2 = 40mW) gives
the same package power dissipation level calculated above (= (12.7 + 13) mA x 24V –40mV = 576 mW).
Nevertheless, when the supply current peak swing is measured, it is found to be significantly lower because the
AB bias current is contributing to the load current. The supply current has a peak swing of only 14mA (compared
to 19.9mA) superimposed on the quiescent current, with a total average value of only 21mA. Therefore the total
package power dissipation in this application is
PD(TOTAL) = (VS x Iavg) - Power in Load
= (24 x 21)mW - 40mW
= 464mW
(5)
This level of power dissipation would not take the junction temperature in the 8-Pin SO PowerPAD package over
the absolute maximum rating at elevated ambient temperatures (barely), but there is no margin to allow for
component tolerances or signal variances.
To develop 20mW in a 100Ω requires each amplifier to deliver a peak voltage of only 2V, or 4V(P-P). This level of
signal swing does not require a high supply voltage but the application uses a 24V supply. This is because the
modulation technique uses a large number of tones to transmit the data. While the average power level is held to
20mW, at any time the phase and amplitude of individual tones will be such as to generate a combined signal
with a higher peak value than 2V. For DMT this crest factor is taken to be around 5.33 so each amplifier has to
be able to handle a peak voltage swing of
VLpeak = 1.4 x 5.33 = 7.5V or 15V(P-P)
(6)
If other factors, such as transformer loss or even higher peak to average ratios are allowed for, this means the
amplifiers must each swing between 16 to 18V(P-P).
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The required signal swing can be reduced by using a step-up transformer to drive the line. For example a 1:2
ratio will reduce the peak swing requirement by half, and this would allow the supply to be reduced by a
corresponding amount. This is not recommended for the LM7372 in this particular application for two reasons.
Although the quiescent power contribution to the overall dissipation is reduced by about 150mW, the internal
power dissipation to drive the load remains the same, since the load for each amplifier is now 25Ω instead of
100Ω. Furthermore, this is a transceiver application where downstream signals are simultaneously appearing at
the transformer secondary. The down stream signals appear differentially across the back termination resistors
and are now stepped down by the transformer turns ratio with a consequent loss in receiver sensitivity compared
to using a 1:1 transformer. Any trade-off to reduce the supply voltage by an increase in turns ratio should bear
these factors in mind, as well as the increased signal current levels required with lower impedance loads.
At an elevated ambient temperature of 85°C and with an average power dissipation of 464mW, a package
thermal resistance between 60°C/W and 80°C/W will be needed to keep the maximum junction temperature in
the range 110°C to 120°C. The SO PowerPAD package would be the package of choice here with ample board
copper area to aid in heat dissipation (see Table 2).
For most standard surface mount packages, 8-Pin SOIC, 14-Pin SOIC, 16-Pin SOIC etc, the only means of heat
removal from the die is through the bond wires to external copper connecting to the leads. Usually it will be
difficult to reduce the thermal resistance of these packages below 100°C/W by these methods and several
manufacturers, including Texas Instruments, offer package modifications to enhance the thermal characteristics.
L*
H*
16-PIN SURFACE
MOUNT
Figure 26. Copper Heatsink Patterns
The LM7372 is available in the 16-Pin SOIC package. Since only 8 pins are needed for the two operational
amplifiers, the remaining pins are used for heat sink purposes. Each of the end pins, 1,8,9 & 16 are internally
bonded to the lead frame and form an effective means of transferring heat to external copper. This external
copper can be either electrically isolated or be part of the topside ground plane in a single supply application.
Figure 26 shows a copper pattern which can be used to dissipate internal heat from the LM7372. Table 1 gives
some values of θJA for different values of L and H with 1oz copper.
Table 1. 16-Pin SOIC Thermal Resistance with Area of Cu
14
L (in)
H (in)
θJA (°C/W)
1
0.5
83
2
1
70
3
1.5
67
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From Table 1 it is apparent that two areas of 1oz copper at each end of the package, each 2 in2 in area (for a
total of 2600mm2) will be sufficient to hold the maximum junction temperature under 120°C with an 85°C ambient
temperature.
An even better package for removing internally generated heat is a package with an exposed die attach paddle.
Improved removal of internal heat can be achieved by directly connecting bond wires to the lead frame inside the
package. Since this lead frame supports the die attach paddle, heat is transferred directly from the substrate to
the outside copper by these bond wires. The LM7372 is also available in the 8-Pin SO PowerPAD package. For
this package the entire lower surface of the paddle is not covered with plastic, which would otherwise act as a
thermal barrier to heat transfer. Heat is transferred directly from the die through the paddle rather than through
the small diameter bonding wires. Values of θJA in °C/W for the SO PowerPAD package with various areas and
weights of copper are tabulated below.
Table 2. Thermal Resistance of SO PowerPAD Package
Copper
Area
0.5 in2
(each side)
1.0 in2
(each side)
2.0 in2
(each side)
0.5 oz
1.0 oz
2.0 oz
Top
Layer
Only
115
91
74
105
79
60
102
72
52
0.5 oz
1.0 oz
2.0 oz
Bottom
Layer
Only
102
92
85
88
75
66
81
65
54
0.5 oz
1.0 oz
2.0 oz
Top And Bottom
83
71
63
70
57
48
63
47
37
Table 2 clearly demonstrates the superior thermal qualities of the exposed pad package. For example, using the
topside copper only in the same way as shown for the SOIC package (Figure 26), the SO PowerPAD requires
half the area of 1 oz copper (2 in2, total or 1300mm2), for a comparable thermal resistance of 72°C/Watt. This
gives considerably more flexibility in the pcb layout aside from using less copper.
The shape of the heat sink shown in Figure 26 is necessary to allow external components to be connected to the
package pins. If thermal vias are used beneath the SO PowerPAD to the bottom side ground plane, then a
square pattern heat sink can be used and there is no restriction on component placement on the top side of the
board. Even better thermal characteristics are obtained with bottom layer heat sinking. A 2 inch square of 0.5oz
copper gives the same thermal resistance (81°C/W) as a competitive thermally enhanced 8-Pin SOIC package
which needs two layers of 2 oz copper, each 4 in2 (for a total of 5000 mm2). With heavier copper, thermal
resistances as low as 54°C/W are possible with bottom side heat sinking only, substantially improving the long
term reliability since the maximum junction temperature is held to less than 110°C, even with an ambient
temperature of 85°C. If both top and bottom copper planes are used, the thermal resistance can be brought to
under 40°C/W.
HIGH FREQUENCY/LARGE SIGNAL SWING CONSIDERATIONS
The LM7372 employs a unique input stage in order to support large slew rate and high output current capability
with large output swings, with a relatively low quiescent current. This input architecture boosts the device supply
current when the application demands it. The result is a supply current which increases at high enough
frequencies when the output swing is large enough with added power dissipation as a consequence.
Figure 27 shows the amount of increase in supply current as a function of frequency for various sinusoidal output
swing amplitudes:
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1000
10V supply (1 amplifier)
10V supply (2 amplifiers)
TJ = 140°C
100
30V supply
(1 amplifier)
10 30V supply
10
V
6V
PP
PP
(2 amplifiers)
PP
PP
2V
3V
PP
PP
V
1V
1
15
20
V
PP
24
V
PP
IS INCREASE (mA)
8-Pin SO PowerPAD
qJA = 47°C/W
TA = 85°C
1
10
100
FREQUENCY (MHz)
Figure 27. Power Supply Current Increase
Figure 27 shows that there could be 1mA or more excess supply current per amplifier with close to full output
swing (24VPP) when frequency is just above 1MHz (or at higher frequencies when the output swing is less). This
boost in supply current enables the output to “keep up” with high frequency/large signal output swing, but in turn,
increases the total package power dissipation and therefore raises the device junction temperature. As a
consequence, these demanding applications, especially ones which run at higher supply voltages, need special
attention to the package heatsink design. For that reason, Figure 27 has the safe operating limits for the 8-Pin
SO PowerPAD package (e.g. “30V supply (2 amplifiers)” horizontal line) superimposed on top of it (with TJ limit of
140°C when operated at 85°C ambient), so that the designer can readily decide whether or not there is need for
additional heat sinking.
For example, if the LM7372 is operating similarly to Figure 1 schematic with a single power supply of 10V,
Figure 27 shows that it is safe to have up to 10VPP output swing at up to 40MHz with no additional heat sinking.
This determination is from inspection of Figure 27 where the “10V supply (2 amplifiers)” safe operating limit
intercepts the 10VPP swing graph at around 40MHz. Use the “10V supply (1 amplifier)” safe operating limit line in
cases where the second amplifier in the LM7372 package does not experience high frequency/high output swing
conditions.
At any given “IS increase” value (y axis), the product of frequency and output swing remains essentially constant
for all output swing plots. This holds true for the lower frequency range before the plots experience a slope
increase. Therefore, if the application example just discussed operates up to 60MHz instead, it is possible to
calculate the junction-temperature-limited maximum output swing of 6.7VPP(= 40MHz x 10VPP/60MHz) instead.
Please note that Figure 27 precludes any additional amplifier power dissipation related to load (this topic is
discussed below in detail). This load current, if large enough, will reduce the operating frequency/output swing
further. It is important to note that the LM7372 can be destroyed if it is allowed to dissipate enough power that
compromises its maximum junction temperature limit of 150°C.
With the op amp tied to a load, the device power dissipation consists of the quiescent power due to the supply
current flow into the device, in addition to power dissipation due to the load current. The load portion of the
power itself could include an average value (due to a DC load current) and an AC component. DC load current
would flow if there is an output voltage offset, or the output AC average current is non-zero, or if the op amp
operates in a single supply application where the output is maintained somewhere in the range of linear
operation. Therefore:
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PD(TOTAL) = PQ + PDC + PAC
PQ = |IS • VS|
Op Amp Quiescent Power Dissipation
PDC = |IO • (VR - VO)|
DC Load Power
PAC = See Table 3
AC Load Power
where:
IS
Supply Current
VS
Total Supply Voltage (V+ - V−)
IO
Average Load Current
VO
Average Output Voltage
VR
Reference Voltage (V+ for sourcing and V− for sinking current)
Table 3 below shows the maximum AC component of the load power dissipated by the op amp for standard
Sinusoidal, Triangular, and Square Waveforms:
Table 3. Normalized maximum AC Power Dissipated in the Output Stage for Standard Waveforms
PAC (W.Ω/V2)
Sinusoidal
Triangular
Square
50.7 x 10−3
46.9 x 10−3
62.5 x 10−3
The table entries are normalized to VS2/RL. These entries are computed at the output swing point where the
amplifier dissipation is the highest for each waveform type. To figure out the AC load current component of
power dissipation, simply multiply the table entry corresponding to the output waveform by the factor VS2/RL. For
example, with ±5V supplies, a 100Ω load and triangular output waveform, power dissipation in the output stage is
calculated as: PAC = 46.9 x 10−3 x 102/100 = 46.9mW which contributes another 2.2°C (= 46.9mW x 47°C/W) rise
to the LM7372 junction temperature in the 8-Pin SO PowerPAD package.
POWER SUPPLIES
The LM7372 is fabricated on a high voltage, high speed process. Using high supply voltages ensures adequate
headroom to give low distortion with large signal swings. In Figure 1, a single 24V supply is used. To maximize
the output dynamic range the non-inverting inputs are biased to half supply voltage by the resistive divider R1,
R2. The input signals are AC coupled and the coupling capacitors (C1, C2) can be scaled with the bias resistors
(R3, R4) to form a high pass filter if unwanted coupling from the POTS signal occurs.
Supply decoupling is important at both low and high frequencies. The 10µF Tantalum and 0.1µF Ceramic
capacitors should be connected close to the supply Pin 14. Note that the V− pin (pin 6), and the PCB area
associated with the heatsink (Pins 1,8,9 & 16) are at the same potential. Any layout should avoid running input
signal leads close to this ground plane, or unwanted coupling of high frequency supply currents may generate
distortion products.
Although this application shows a single supply, conversion to a split supply is straightforward. The half supply
resistive divider network is eliminated and the bias resistors at the non-inverting inputs are returned to ground,
see Figure 28 (the pin numbers in Figure 28 are given for SO PowerPAD package, those in Figure 1 are for the
SOIC package). With a split supply, note that the ground plane and the heatsink copper must be separate and
are at different potentials, with the heatsink (pin 4 of the SO PowerPAD, pins 6,1,8,9 &16 of the SOIC) now at a
negative potential (V−).
In either configuration, the area under the input pins should be kept clear of copper (whether ground plane
copper or heatsink copper) to avoid parasitic coupling to the inputs.
The LM7372 is stable with non inverting closed loop gains as low as +2. Typical of any voltage feedback
operational amplifier, as the closed loop gain of the LM7372 is increased, there is a corresponding reduction in
the closed loop signal bandwidth. For low distortion performance it is recommended to keep the closed loop
bandwidth at least 10X the highest signal frequency. This is because there is less loop gain (the difference
between the open loop gain and the closed loop gain) available at higher frequencies to reduce harmonic
distortion terms.
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V+
+
0.1uF
3
+ VIN
20uF
+
1/2
LM7372
-
2
5.1k
0.1uF
8
1
50
1:1
2k
Twisted
Pair Line
2k
100
2k
50
6
1/2
LM7372
0.1uF
5
- VIN
+
7
4
5.1k
V0.1uF
+
20uF
Figure 28. Split Supply Application (SO PowerPAD)
PRINTED CIRCUIT BOARD LAYOUT and EVALUATION BOARDS
Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitance on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15 (SNOA367) for more information). Texas Instruments
suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and
characterization:
Device
Package
Evaluation Board PN
LM7372MA
16-Pin SOIC
None
LM7372MR
8-Pin SO PowerPAD
CLC730121
The DAP (die attach paddle) on the 8-Pin SO PowerPAD should be tied to V−. It should not be tied to ground.
See the respective Evaluation Board documentation.
18
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM7372IMA
NRND
SOIC
D
16
48
TBD
Call TI
Call TI
-40 to 85
LM7372IMA
LM7372IMA/NOPB
ACTIVE
SOIC
D
16
48
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM7372IMA
LM7372IMAX/NOPB
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LM7372IMA
LM7372MR
NRND
SO PowerPAD
DDA
8
95
TBD
Call TI
Call TI
-40 to 85
LM73
72MR
ACTIVE SO PowerPAD
DDA
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LM73
72MR
SO PowerPAD
DDA
8
2500
TBD
Call TI
Call TI
-40 to 85
LM73
72MR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
LM73
72MR
LM7372MR/NOPB
LM7372MRX
LM7372MRX/NOPB
NRND
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2014
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM7372IMAX/NOPB
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.3
8.0
16.0
Q1
LM7372MRX
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM7372MRX/NOPB
SO
Power
PAD
DDA
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM7372IMAX/NOPB
SOIC
D
16
2500
367.0
367.0
35.0
LM7372MRX
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
LM7372MRX/NOPB
SO PowerPAD
DDA
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DDA0008B
MRA08B (Rev B)
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