IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL CLOCK DRIVER IDT5T9891 FEATURES: DESCRIPTION: • 2.5 VDD • 6 pairs of programmable skew outputs • Low skew: 100ps all outputs at same interface level, 250ps all outputs at different interface levels • Selectable positive or negative edge synchronization • Tolerant of spread spectrum input clock • Synchronous output enable • Selectable inputs • Input frequency: 4.17MHz to 250MHz • Output frequency: 12.5MHz to 250MHz • Internal non-volatile EEPROM • JTAG or I2C bus serial interface for programming • Hot insertable and over-voltage tolerant inputs • Feedback divide selection with multiply ratios of (1-6, 8, 10, 12) • Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input interface • Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for each output bank • Selectable differential or single-ended inputs and six differential outputs • PLL bypass for DC testing • External differential feedback, internal loop filter • Low Jitter: <75ps cycle-to-cycle, all outputs at same interface level: <100ps cycle-to-cycle all outputs at different interface levels • Power-down mode • Lock indicator • Available in VFQFPN package The IDT5T9891 is a 2.5V PLL differential clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5T9891 has six differential programmable skew outputs in six banks, including a dedicated differential feedback through the use of JTAG or I2C programming. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. The clock driver can be configured through the use of JTAG/I2C programming. An internal EEPROM will allow the user to save and restore the configuration of the device. The feedback bank allows divide-by-functionality from 1 to 12 through the use of JTAG or I2C programming. This provides the user with frequency multiplication 1 to 12 without using divided outputs for feedback. Each output bank also allows for a divide-by functionality of 2 or 4. The IDT5T9891 features a user-selectable, single-ended or differential input to six differential outputs. The differential clock driver also acts as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Each output bank can be individually configured to be either HSTL, eHSTL, 2.5V LVTTL, or 1.8V LVTTL, including the feedback bank. Also, each clock input can be individually configured to accept 2.5V LVTTL, 1.8V LVTTL, or differential signals. The outputs can be synchronously enabled/disabled.The differential outputs can be synchronously enabled/disabled. Furthermore, all the outputs can be synchronized with the positive edge of the REF clock input or the negative edge of REF. The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE NOVEMBER 2004 1 c 2004 Integrated Device Technology, Inc. DSC - 6505/19 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM TDO/ADDR1 (TDO) (ADDR1) TMS/ADDR0 JTAG/I2C PROGRAMMING SELECTION AND CONTROL LOGIC TCLK/SCLK TDI/SDA TRST/SEL 1sOE VDDQ1 Skew Select 1Q 1Q 2sOE EEPROM VDDQ2 Skew Select 2Q 2Q PD 3sOE OMODE VDDQ3 FB /N FB/VREF2 0 PLL Skew Select 3Q REF0 REF0/VREF0 3Q 0 4sOE VDDQ4 1 REF1 REF1/VREF1 Skew Select 1 4Q 4Q 5sOE VDDQ5 REF_SEL PLL_EN Skew Select 5Q 5Q LOCK(φ) VDDQFB Skew Select QFB QFB 2 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE VDD VDD VDD VDD 2Q 60 59 58 57 56 2sOE 1Q 61 52 1Q 62 VDDQ2 VDDQ1 63 53 VDDQ1 64 VDDQ2 1sOE 65 54 LOCK 66 2Q TDO/ADDR1 67 55 TMS/ADDR0 68 PIN CONFIGURATION VDD 1 51 TRST/SEL TDI/SDA 2 50 OMODE TCLK/SCLK 3 49 3sOE VDD 4 48 VDDQ3 REF_SEL 5 47 VDDQ3 REF1 6 46 3Q REF1/VREF1 7 45 3Q REF0 8 44 VDD REF0/VREF0 9 43 VDD GND VFQFPN TOP VIEW 3 33 34 5sOE 5Q VDDQ5 VDD 32 35 VDDQ5 17 31 NC 30 4sOE 5Q 36 29 16 VDD NC 28 VDDQ4 VDD 37 27 15 VDD NC VDD VDDQ4 26 14 25 NC 38 QFB 39 24 13 QFB VDD 23 4Q VDDQFB 40 22 12 VDDQFB VDD 21 VDD PLL_EN 41 PD 11 20 FB/VREF2 19 VDD VDD 42 18 10 VDD FB 4Q IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL ABSOLUTE MAXIMUM RATINGS(1) Symbol Description INDUSTRIAL TEMPERATURE RANGE CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V) Max Unit VDDQN, VDD Power Supply Voltage(2) –0.5 to +3.6 V VI Input Voltage –0.5 to +3.6 V VO Output Voltage –0.5 to VDDQ +0.5 V VREF Reference Voltage(3) –0.5 to +3.6 V TJ Junction Temperature 150 °C TSTG Storage Temperature –65 to +165 °C Parameter Description Min. Typ. Max. Unit CIN Input Capacitance COUT Output Capacitance 2.5 3 3.5 pF — 6.3 7 pF NOTE: 1. Capacitance applies to all inputs except JTAG/I2C signals, SEL, ADDR0, and ADDR1. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQN and VDD internally operate independently. No power sequencing requirements need to be met. 3. Not to exceed 3.6V. RECOMMENDED OPERATING RANGE Symbol TA VDD(1) Description Ambient Operating Temperature Internal Power Supply Voltage HSTL Output Power Supply Voltage Extended HSTL and 1.8V LVTTL Output Power Supply Voltage 2.5V LVTTL Output Power Supply Voltage Termination Voltage VDDQN(1) VT Min. –40 2.3 1.4 1.65 Typ. +25 2.5 1.5 1.8 VDD VDDQN / 2 Max. +85 2.7 1.6 1.95 Unit °C V V V V V NOTE: 1. All power supplies should operate in tandem. If VDD or VDDQN is at maximum, then VDDQN or VDD (respectively) should be at maximum, and vice-versa. PIN DESCRIPTION Symbol REF[1:0] REF[1:0]/ VREF[1:0] I/O I I Type Adjustable(1) Adjustable(1) FB FB/VREF2 I I Adjustable(1) Adjustable(1) Description Clock input. REF[1:0] is the "true" side of the differential clock input. If operating in single-ended mode, REF[1:0] is the clock input. Complementary clock input. REF[1:0]/VREF[1:0] is the "complementary" side of REF[1:0] if the input is in differential mode. If operating in single-ended mode, REF[1:0]/VREF[1:0] is left floating. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] should be set to the desired toggle voltage for REF[1:0]: 2.5V LVTTL VREF = 1250mV (SSTL2 compatible) 1.8V LVTTL, eHSTL VREF = 900mV HSTL VREF = 750mV LVEPECL VREF = 1082mV Clock input. FB is the "true" side of the differential feedback clock input. If operating in single-ended mode, FB is the feedback clock input. Complementary feedback clock input. FB/VREF2 is the "complementary" side of FB if the input is in differential mode. If operating in singleended mode, FB/VREF2 is left floating. For single-ended operation in differential mode, FB/VREF2 should be set to the desired toggle voltage for FB: 2.5V LVTTL VREF = 1250mV (SSTL2 compatible) 1.8V LVTTL, eHSTL VREF = 900mV HSTL VREF = 750mV LVEPECL VREF = 1082mV NOTE: 1. Inputs are capable of translating the following interface standards. User can select between: Single-ended 2.5V LVTTL levels Single-ended 1.8V LVTTL levels or Differential 2.5V/1.8V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL levels 4 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION, CONTINUED Symbol I/O Type REF_SEL I LVTTL(1) Description Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1. nsOE I LVTTL(1) Synchronous output enable/disable. Each outputs's enable/disable state can be controlled either with the nsOE pin or through JTAG or I2C programming, corresponding bits 52 - 56. When the nsOE is HIGH or the corresponding Bit (52 - 56) is 1, the output will be synchronously disabled. When the nsOE is LOW and the corresponding Bit (52 - 56) is 0, the output will be enabled. (See JTAG/I2C Serial Configuration table.) QFB O Adjustable(2) Feedback clock output QFB nQ nQ O O O Adjustable(2) Adjustable(2) Adjustable(2) Complementary feedback clock output Clock outputs Complementary clock outputs PLL_EN I LVTTL(1) PLL enable/disable control. The PLL's enable/disable state can be controlled either with the PLL_EN pin or through JTAG or I2C programming, corresponding Bit 57. When PLL_EN is HIGH or the corresponding Bit 57 is 1, the PLL is disabled and REF[1:0] goes to all outputs. When PLL_EN is LOW and the corresponding Bit 57 is 0, the PLL will be active. PD I LVTTL(1) Power down control. When PD is LOW, the inputs are disabled and internal switching is stopped. The OMODE pin in conjunction with the corresponding Bit 59 selects whether the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH or Bit 59 is 1, Bit 58 determines the level at which the outputs stop. When Bit 58 is 0/1, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and Bit 59 is 0, the outputs are tri-stated. Set PD HIGH for normal operation. (See JTAG/I2C Serial Configuration table.) LOCK O LVTTL PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to OMODE I LVTTL(1) Output disable control. Used in conjunction with nsOE and PD. The outputs' disable state can be controlled either with the OMODE pin or through JTAG or I2C programming, corresponding Bit 59. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs' disable state will be gated and Bit 58 will determine the level at which the outputs stop. When Bit 58 is 0/1, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding bit 59 is 0, the outputs disable state will be the tri-state. (See JTAG/I2C Serial Configurations tables.) TRST/SEL I/I LVTTL/ TRST- Active LOW input to asynchronously reset the JTAG boundary-scan circuit. the inputs. The output will be 2.5V LVTTL. (For more information on application specific use of the LOCK pin, please see AN237.) LVTTL(4,5) 3-Level(3,4,5) TDO/ADDR1 TMS/ADDR0 TCLK/SCLK TDI/SDA O/I I/I I/I I/I SEL - Select programming interface control for the dual-function pins. When HIGH, the dual-function pins are set for JTAG programming. When LOW, the dual-function pins are set for I2C programming and the JTAG interface is asynchronously placed in the Test Logic Reset state. LVTTL/ TDO - Serial data output pin for instructions as well as test and programming data. Data is shifted in on the falling edge of TCLK. The pin is tri-stated if data is not being shifted out of the device. 3-Level(3,4,5) ADDR1 - Used to define a unique I2C address for this device. Only for I2C programming. (See JTAG/I2C Serial Interface Description.) LVTTL/ TMS - Input pin that provides the control signal to determine the transitions of the JTAG TAP controller state machine. Transitions within the state machine occur at the rising edge of TCLK. Therefore, TMS must be set up before the rising edge of TCLK. TMS is evaluated on the rising edge of TCLK. LVTTL(4,5) ADDR0 - Used to define a unique I2C address for this device. Only for I2C programming. (See JTAG/I2C Serial Interface Description.) LVTTL/ LVTTL(4,5) TCLK - The clock input to the JTAG BST circuitry. LVTTL/ SCLK - Serial clock for I2C programming TDI - Serial input pin for instructions as well as test and programming data. Data is shifted in on the rising edge of TCLK. SDA - Serial data (see JTAG/I2C Serial Description table) VDDQN PWR Power supply for each pair of outputs. When using 2.5V LVTTL, 1.8V LVTTL, HSTL, or eHSTL outputs, VDDQN should be set to its corresponding outputs (see Front Block Diagram). When using 2.5V LVTTL outputs, VDDQN should be connected to VDD. VDD PWR Power supply for phase locked loop, lock output, inputs, and other internal circuitry GND PWR Ground NOTES: 1. Pins listed as LVTTL inputs can be configured to accept 1.8V or 2.5V signals through the use of the I2C/JTAG programming, bit 61. (See JTAG/I2C Serial Description.) 2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQN voltage. 3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant. 4. The JTAG (TDO, TMS, TCLK, and TDI) and I2C (ADDR1, ADDR0, SCLK, and SDA) signals share the same pins (dual-function pins) for which the TRST/SEL pin will select between the two programming interfaces. 5. JTAG and I2C pins accept 2.5V signals. The JTAG input pins (TMS, TCLK, TDI, TRST) will also accept 1.8V signals. 5 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE JTAG/ I2C SERIAL DESCRIPTION Bit 95:62 Description Reserved Bits. Set bits 95:62 to '0'. 61 Input interface selection for control pins (REF_SEL, PD, PLL_EN, OMODE, nSOE). When bit 61 is ‘1’, the control pins are 2.5V LVTTL. When bit 61 is ‘0’, the control pins are 1.8V LVTTL. 60 VCO frequency range. When ‘0’, range is 50MHz-125MHz. When ‘1’, range is 100MHz-250MHz. 59 Output’s disable state. See corresponding external pin OMODE for Pin Description table. 58 Positive/Negative edge control. When ‘0’/’1’, the outputs are synchronized with the negative/positive edge of the reference clock. 57 PLL enable/disable. See corresponding external pin PLL_EN in Pin Description table.(1) 56 Output disable/enable for 1Q[1:0] outputs. See corresponding external pin 1SOE in Pin Description table. 55 Output disable/enable for 2Q[1:0] outputs. See corresponding external pin 2SOE in Pin Description table. 54 Output disable/enable for 3Q[1:0] outputs. See corresponding external pin 3SOE in Pin Description table. 53 Output disable/enable for 4Q[1:0] outputs. See corresponding external pin 4SOE in Pin Description table. 52 Output disable/enable for 5Q[1:0] outputs. See corresponding external pin 5SOE in Pin Description table. 51 FB Divide-by-N selection 50 FB Divide-by-N selection 49 FB Divide-by-N selection 48 FB Divide-by-N selection 47 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 1 46 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 1 45 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 2 44 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 2 43 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 3 42 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 3 41 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 4 40 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 4 39 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 5 38 Output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on bank 5 37 FB output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on FB bank 36 FB output drive strength selection for 2.5V LVTTL, 1.8V LVTTL, or HSTL/eHSTL on FB bank 35 REF0 Input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential 34 REF0 Input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential 33 REF1 input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential 32 REF1 input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential 31 FB input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential 30 FB input interface selection for 2.5V LVTTL, 1.8V LVTTL, or Differential 29 Skew or frequency selection for bank 1 28 Skew or frequency selection for bank 1 27 Skew or frequency selection for bank 1 26 Skew or frequency selection for bank 1 25 Skew or frequency selection for bank 1 24 Skew or frequency selection for bank 2 23 Skew or frequency selection for bank 2 22 Skew or frequency selection for bank 2 NOTE: 1. Only for EEPROM operation; bit 57 must be set to 0 to enable the PLL for proper EEPROM operation. The EEPROM access times are based on the VCO frequency of the PLL (refer to the EEPROM Operation section). 6 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE JTAG/ I2C SERIAL DESCRIPTION, CONT. Bit Description 21 Skew or frequency selection for bank 2 20 Skew or frequency selection for bank 2 19 Skew or frequency selection for bank 3 18 Skew or frequency selection for bank 3 17 Skew or frequency selection for bank 3 16 Skew or frequency selection for bank 3 15 Skew or frequency selection for bank 3 14 Skew or frequency selection for bank 4 13 Skew or frequency selection for bank 4 12 Skew or frequency selection for bank 4 11 Skew or frequency selection for bank 4 10 Skew or frequency selection for bank 4 9 Skew or frequency selection for bank 5 8 Skew or frequency selection for bank 5 7 Skew or frequency selection for bank 5 6 Skew or frequency selection for bank 5 5 Skew or frequency selection for bank 5 4 Skew or frequency selection for FB bank 3 Skew or frequency selection for FB bank 2 Skew or frequency selection for FB bank 1 Skew or frequency selection for FB bank 0 Skew or frequency selection for FB bank JTAG/ I2C SERIAL CONFIGURATIONS: POWERDOWN JTAG/ I2C SERIAL CONFIGURATIONS: OUTPUT ENABLE/DISABLE Bit 59 (OMODE) Bit 56-52 (nsOE) Output PD Bit 59 (OMODE) Output X (X) Normal Operation X (X) 0 and (L) Normal Operation H 0 and (L) 1 or (H) Tri-Sate L 0 and (L) Tri-Sate 1 or (H) Gated(1) L 1 or (H) Gated(1) 1 or (H) NOTE: 1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/ HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs' disable state will be gated. Bit 58 determines the level at which the outputs stop. When Bit 58 is 0/ 1, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding Bit 59 is 0, the outputs' disable state will be the tri-state. NOTE: 1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/ HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs' disable state will be gated. Bit 58 determines the level at which the outputs stop. When Bit 58 is 0/ 1, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding Bit 59 is 0, the outputs' disable state will be the tri-state. JTAG/ I2C SERIAL CONFIGURATIONS: CLOCK INPUT INTERFACE SELECTION(1) JTAG/ I2C SERIAL CONFIGURATIONS: OUTPUT DRIVE STRENGTH SELECTION(1) Bit 31, 33, 35 Bit 30, 32, 34 Interface Bit 37, 39, 41, Bit 36, 38, 40, 0 0 Differential(2) 43, 45, 47 42, 44, 46 Interface 0 2.5V LVTTL 0 1 2.5V LVTTL 0 1 1 1.8V LVTTL 0 1 1.8V LVTTL 1 0 HSTL/eHSTL NOTES: 1. All other states that are undefined in the table will be reserved. 2. Differential input interface for HSTL/eHSTL, LVEPECL (2.5V), and 2.5V/1.8V LVTTL. NOTE: 1. All other states that are undefined in the table will be reserved. 7 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE JTAG/ I2C SERIAL CONFIGURATIONS: SKEW OR FREQUENCY SELECT(1) Bit 4, 9, 14, 19, 24, 29 Bit 3, 8, 13, 18, 23, 28 Bit 2, 7, 12, 17, 22, 27 Bit 1, 6, 11, 16, 21, 26 Bit 0, 5, 10, 15, 20, 25 Output Skew 0 0 0 0 1 +7tu 0 0 0 1 0 +6tu 0 0 0 1 1 +5tu 0 0 1 0 0 +4tu 0 0 1 0 1 +3tu 0 0 1 1 0 +2tu 0 0 1 1 1 +1tu 0 0 0 0 0 Zero Skew 0 1 0 0 1 -1tu 0 1 0 1 0 -2tu 0 1 0 1 1 -3tu 0 1 1 0 0 -4tu 0 1 1 0 1 -5tu 0 1 1 1 0 -6tu 0 1 1 1 1 -7tu 1 0 0 0 0 Inverted 1 0 0 0 1 Divide-by-2 1 0 0 1 0 Divide-by-4 NOTE: 1. All other states that are undefined in the table will result in zero skew. JTAG/ I2C SERIAL CONFIGURATIONS: FB DIVIDE-BY-N(1) Bit 51 Bit 50 Bit 49 Bit 48 Divide-by-N Permitted Output Divide-by-N connected to FB and FB/VREF2 (2) 0 0 0 0 1 1, 2, 4 0 0 0 1 2 1, 2 0 0 1 0 3 1 0 0 1 1 4 1, 2 0 1 0 0 5 1, 2 0 1 0 1 6 1, 2 0 1 1 0 8 1 0 1 1 1 10 1 1 0 0 0 12 1 NOTES: 1. All other states that are undefined in the table will be reserved. 2. Permissible output division ratios connected to FB and FB/VREF2. The frequencies of the REF[1:0] and REF [1:0]/VREF[1:0] inputs will be Fvco/N when the parts are configured for frequency multiplication by using an undivided output for FB and FB/VREF2 and setting N (N = 1-6, 8, 10, 12). JTAG/ I2C SERIAL CONFIGURATIONS: VCO FREQUENCY SELECT Bit 60 Min. Max. 0 50Mhz 125MHz 1 100MHz 250Mhz 8 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE PROGRAMMABLE SKEW Output skew with respect to the REF[1:0] and REF[1:0]/VREF[1:0] input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit (tU) which ranges from 250ps to 1.25ns (see Programmable Skew Range and Resolution Table). There are 18 skew/divide configurations available for each output pair. These configurations are chosen through JTAG/I2C programming. PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE Bit 60 = 0 Bit 60 = 1 Timing Unit Calculation (tU) 1/(16 x FNOM) 1/(16 x FNOM) VCO Frequency Range (FNOM)(1,2) 50 to 125MHz 100 to 250MHz ±8.75ns ±4.375ns Comments Skew Adjustment Range(3) Max Adjustment: ns ±157.5° ±157.5° Phase Degrees ±43.75% ±43.75% % of Cycle Time Example 1, FNOM = 50MHz tU = 1.25ns — Example 2, FNOM = 75MHz tU = 0.833ns — Example 3, FNOM = 100MHz tU = 0.625ns tU = 0.625ns Example 4, FNOM = 150MHz — tU = 0.417ns Example 5, FNOM = 200MHz — tU = 0.313ns Example 6, FNOM = 250MHz — tU = 0.25ns NOTES: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. 2. The VCO frequency always appears at nQ and nQ outputs when they are operated in their undivided modes. The frequency appearing at the REF[1:0] and REF[1:0]/VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and QFB are undivided and FB divide-by-1. The frequency of the REF[1:0] and REF[1:0]/VREF[1:0] and FB and FB/VREF2 inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided QFB and QFB and setting FB divide-by-1. Using the FB divideby-N configuration inputs allows a different method for frequency multiplication (see JTAG/I2C Serial Configurations: FB Divide-by-N). 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed QFB and QFB output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to all output pairs where ±7tU skew adjustment is possible and at the lowest FNOM value. INPUT/OUTPUT SELECTION(1) EXTERNAL DIFFERENTIAL FEEDBACK By providing a dedicated external differential feedback, the IDT5T9891 gives users flexibility with regard to divide selection. The FB and FB/ VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0] signals at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. Input Output(2) 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL, 1.8V LVTTL, 2.5V LVTTL DSE 1.8V LVTTL DSE HSTL, eHSTL LVEPECL DSE eHSTL DSE An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF MASTER RESET FUNCTIONALITY eHSTL DIF HSTL DIF The IDT5T9891 performs a reset of the internal output divide circuitry when all five output banks are disabled by toggling the nSOE pins HIGH. When one or more banks of outputs are enabled by toggling the nSOE LOW (if the corresponding nSOE programming bits are also set LOW), the divide circuitry starts again from a known state. In the case that the FB output is selected for divide-by-2 or divide-by-4, the FB output will stop toggling while all five nSOE pins and bits are LOW, and loss of lock will occur. NOTES: 1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the REF[1:0] /VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring VREF[1:0] and VREF2. Differential (DIF) inputs are used only in differential mode. 2. For each output bank. 9 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol VIHH VIMM VILL I3 IPU Parameter Input HIGH Voltage Level(1) Input MID Voltage Level(1) Input LOW Voltage Level(1) 3-Level Input DC Current (ADDR0, ADDR1) Input Pull-Up Current Test Conditions 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only HIGH Level VIN = VDD VIN = VDD/2 MID Level VIN = GND LOW Level VDD = Max., VIN = GND Min. VDD – 0.4 VDD/2 – 0.2 — — –50 –200 –100 Max — VDD/2 + 0.2 0.4 200 +50 — — Unit V V V µA µA NOTE: 1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and the PLL may require additional tLOCK time before all datasheet limits are achieved. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current IIL Input LOW Current VIK Clamp Diode Voltage VIN DC Input Voltage VDIF DC Differential Voltage(2,8) VCM DC Common Mode Input Voltage(3,8) VIH DC Input HIGH(4,5,8) VIL DC Input LOW(4,6,8) Single-Ended Reference Voltage(4,8) VREF Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage VOX nQ/nQ and FB/FB Output Crossing Point Test Conditions VDD = 2.7V VI = VDDQN/GND VDD = 2.7V VI = GND/VDDQN VDD = 2.3V, IIN = -18mA IOH = -8mA IOH = -100µA IOL = 8mA IOL = 100µA Min. Typ.(7) Max Unit — — — - 0.3 0.2 680 VREF + 100 — — — — - 0.7 µA 750 ±5 ±5 - 1.2 +3.6 — 900 — VREF - 100 — VDDQN/2 — — 0.4 0.1 VDDQN/2 + 150 VDDQN - 0.4 VDDQN - 0.1 — — VDDQN/2 - 150 750 V V V mV mV mV mV V V mV NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQN = 1.5V, +25°C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.) 10 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS FOR HSTL OUTPUTS(1) Symbol IDDQ Parameter Quiescent VDD Power Supply Current(3) IDDQQ Quiescent VDDQN Power Supply Current(3) IDDPD IDDD ITOT Power Down Current Dynamic VDD Power Supply Current per Output Dynamic VDDQN Power Supply Current per Output Total Power VDD Supply Current(4,5) ITOTQ Total Power VDDQN Supply Current(4,5) IDDDQ Test Conditions(2) VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW, PLL_EN = HIGH, Outputs enabled, All outputs unloaded VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW, PLL_EN = HIGH, Outputs enabled, All outputs unloaded VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH VDD = Max., VDDQN = Max., CL = 0pF Typ. 112 Max 150 Unit mA 2 75 µA 0.3 22 3 30 mA µA/MHz VDD = Max., VDDQN = Max., CL = 0pF 19 30 µA/MHz VDDQN = 1.5V, FVCO = 100MHz, CL = 15pF VDDQN = 1.5V, FVCO = 250MHz, CL = 15pF VDDQN = 1.5V, FVCO = 100MHz, CL = 15pF VDDQN = 1.5V, FVCO = 250MHz, CL = 15pF 280 320 130 220 400 450 200 330 mA NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH. 4. Bit 60 = 1. 5. All outputs are at the same interface level. 11 mA IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL Symbol Parameter VDIF Input Signal Swing(1) VX Differential Input Signal Crossing Point VTHI Input Timing Measurement Reference Level(3) tR, tF Input Signal Edge Rate (2) Value Units 1 V 750 mV Crossing Point V 1 V/ns (4) NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR eHSTL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current IIL Input LOW Current VIK Clamp Diode Voltage VIN DC Input Voltage VDIF DC Differential Voltage(2,8) VCM DC Common Mode Input Voltage(3,8) VIH DC Input HIGH(4,5,8) VIL DC Input LOW(4,6,8) Single-Ended Reference Voltage(4,8) VREF Output Characteristics Output HIGH Voltage VOH VOL Output LOW Voltage VOX nQ/nQ and FB/FB Output Crossing Point Test Conditions VDD = 2.7V VI = VDDQN/GND VDD = 2.7V VI = GND/VDDQN VDD = 2.3V, IIN = -18mA IOH = -8mA IOH = -100µA IOL = 8mA IOL = 100µA Min. Typ.(7) Max Unit — — — - 0.3 0.2 800 VREF + 100 — — — — - 0.7 µA 900 ±5 ±5 - 1.2 +3.6 — 1000 — VREF - 100 — V V V mV mV mV mV VDDQN/2 — — 0.4 0.1 VDDQN/2 + 150 V V V V mV VDDQN - 0.4 VDDQN - 0.1 — — VDDQN/2 - 150 900 NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in a differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQN = 1.8V, +25°C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.) 12 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS FOR eHSTL OUTPUTS(1) Symbol IDDQ Parameter Quiescent VDD Power Supply Current(3) IDDQQ Quiescent VDDQN Power Supply Current(3) IDDPD IDDD ITOT Power Down Current Dynamic VDD Power Supply Current per Output Dynamic VDDQN Power Supply Current per Output Total Power VDD Supply Current(4,5) ITOTQ Total Power VDDQN Supply Current(4,5) IDDDQ Test Conditions(2) VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW, PLL_EN = HIGH, Outputs enabled, All outputs unloaded VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW, PLL_EN = HIGH, Outputs enabled, All outputs unloaded VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH VDD = Max., VDDQN = Max., CL = 0pF Typ. 112 Max 150 Unit mA 2 75 µA 0.3 22 3 30 mA µA/MHz VDD = Max., VDDQN = Max., CL = 0pF 22 30 µA/MHz VDDQN = 1.8V, FVCO = 100MHz, CL = 15pF VDDQN = 1.8V, FVCO = 250MHz, CL = 15pF VDDQN = 1.8V, FVCO = 100MHz, CL = 15pF VDDQN = 1.8V, FVCO = 250MHz, CL = 15pF 280 330 160 270 400 450 250 400 mA mA NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH. 4. Bit 60 = 1. 5. All outputs are at the same interface level. DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL Symbol Parameter VDIF Input Signal Swing(1) VX Differential Input Signal Crossing Point VTHI Input Timing Measurement Reference Level(3) tR, tF Input Signal Edge Rate (2) (4) Value Units 1 V 900 mV Crossing Point V 1 V/ns NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. 13 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVEPECL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current IIL Input LOW Current VIK Clamp Diode Voltage VIN DC Input Voltage VCM DC Common Mode Input Voltage(3,5) VREF Single-Ended Reference Voltage(4,5) VIH DC Input HIGH VIL DC Input LOW Test Conditions VDD = 2.7V VI = VDDQN/GND VDD = 2.7V VI = GND/VDDQN VDD = 2.3V, IIN = -18mA Min. Typ.(2) Max Unit — — — - 0.3 915 — 1275 555 — — - 0.7 — 1082 1082 — — ±5 ±5 - 1.2 3.6 1248 — 1620 875 µA V V mV mV mV mV NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Typical values are at VDD = 2.5V, +25°C ambient. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation while in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. 5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.) DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL Symbol Parameter Value Units VDIF (1) Input Signal Swing 732 mV VX Differential Input Signal Crossing Point(2) 1082 mV VTHI Input Timing Measurement Reference Level(3) tR, tF Input Signal Edge Rate(4) Crossing Point V 1 V/ns NOTES: 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. 14 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 2.5V LVTTL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current IIL Input LOW Current VIK Clamp Diode Voltage DC Input Voltage VIN Single-Ended Inputs(2) VIH DC Input HIGH DC Input LOW VIL Differential Inputs VDIF DC Differential Voltage(3,9) VCM DC Common Mode Input Voltage(4,9) VIH DC Input HIGH(5,6,9) VIL DC Input LOW(5,7,9) Single-Ended Reference Voltage(5,9) VREF Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.7V VI = VDDQN/GND VDD = 2.7V VI = GND/VDDQN VDD = 2.3V, IIN = -18mA Min. Typ.(8) Max Unit — — — - 0.3 — — - 0.7 ±5 ±5 - 1.2 +3.6 µA — 0.7 V V — 1350 — VREF - 100 — V mV mV mV mV — — 0.4 0.1 V V V V 1.7 — 0.2 1150 VREF + 100 — — IOH = -12mA IOH = -100µA IOL = 12mA IOL = 100µA VDDQN - 0.4 VDDQN - 0.1 — — 1250 1250 V V NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 2.5V LVTTL single-ended operation, Bits 35/34, 33/32, 31/30 = 0/1 or 1/0, and REF[1:0]/VREF[1:0] is left floating. If Bits 47 - 36 = 0, FB/VREF2 should be left floating. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQN = VDD, +25°C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.) 15 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS FOR 2.5V LVTTL OUTPUTS(1) Symbol IDDQ Parameter Quiescent VDD Power Supply Current(3) IDDQQ Quiescent VDDQN Power Supply Current(3) IDDPD IDDD ITOT Power Down Current Dynamic VDD Power Supply Current per Output Dynamic VDDQN Power Supply Current per Output Total Power VDD Supply Current(4,5) ITOTQ Total Power VDDQN Supply Current(4,5) IDDDQ Test Conditions(2) VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW, PLL_EN = HIGH, Outputs enabled, All outputs unloaded VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW, PLL_EN = HIGH, Outputs enabled, All outputs unloaded VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH VDD = Max., VDDQN = Max., CL = 0pF Typ. 112 Max 150 Unit mA 15 75 µA 0.3 21 3 30 mA µA/MHz VDD = Max., VDDQN = Max., CL = 0pF 33 40 µA/MHz VDDQN = 2.5V., FVCO = 100MHz, CL = 15pF VDDQN = 2.5V., FVCO = 250MHz, CL = 15pF VDDQN = 2.5V., FVCO = 100MHz, CL = 15pF VDDQN = 2.5V., FVCO = 250MHz, CL = 15pF 280 320 210 345 400 450 320 530 mA mA NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH. 4. Bit 60 = 1. 5. All outputs are at the same interface level. DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL Symbol Parameter VDIF Input Signal Swing(1) VX Differential Input Signal Crossing Point VTHI Input Timing Measurement Reference Level(3) tR, tF Input Signal Edge Rate(4) (2) Value Units VDD V VDD/2 V Crossing Point V 2.5 V/ns NOTES: 1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VTHI Input Timing Measurement Reference Level tR, tF Input Signal Edge Rate(2) (1) Value Units VDD V 0 V VDD/2 V 2 V/ns NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform. 16 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V LVTTL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current IIL Input LOW Current VIK Clamp Diode Voltage DC Input Voltage VIN Single-Ended Inputs(2) VIH DC Input HIGH DC Input LOW VIL Differential Inputs VDIF DC Differential Voltage(3,9) VCM DC Common Mode Input Voltage(4,9) VIH DC Input HIGH(5,6,9) VIL DC Input LOW(5,7,9) Single-Ended Reference Voltage(5,9) VREF Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.7V VI = VDDQN/GND VDD = 2.7V VI = GND/VDDQN VDD = 2.3V, IIN = -18mA IOH = -6mA IOH = -100µA IOL = 6mA IOL = 100µA Min. Typ.(8) Max Unit — — — - 0.3 — — - 0.7 ±5 ±5 - 1.2 VDDQN + 0.3 µA 1.073(10) — — 0.683(11) V V 0.2 825 VREF + 100 — — — 975 — VREF - 100 — V mV mV mV mV — — 0.4 0.1 V V V V VDDQN - 0.4 VDDQN - 0.1 — — 900 900 V V NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 1.8V LVTTL single-ended operation, Bits 35 - 30 = 0 and REF[1:0]/VREF[1:0] is left floating. If Bits 47/46, 45/44, 43/42, 41/40, 39/38, 37/36 = 0/1, FB/VREF2 should be left floating. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. The input is guaranteed to toggle within ±200mV of VREF[1:0] when VREF[1:0] is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the REF[1:0] input. To guarantee switching in voltage range specified in the JEDEC 1.8V LVTTL interface specification, VREF[1:0] must be maintained at 900mV with appropriate tolerances. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQN = 1.8V, +25°C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.) 10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply. 11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply. 17 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS(1) Symbol IDDQ Parameter Quiescent VDD Power Supply Current(3) IDDQQ Quiescent VDDQN Power Supply Current(3) IDDPD IDDD ITOT Power Down Current Dynamic VDD Power Supply Current per Output Dynamic VDDQN Power Supply Current per Output Total Power VDD Supply Current(4,5) ITOTQ Total Power VDDQN Supply Current(4,5) IDDDQ Test Conditions(2) VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW, PLL_EN = HIGH, Outputs enabled, All outputs unloaded VDDQN = Max., REF = LOW, PD = HIGH, nSOE = LOW, PLL_EN = HIGH, Outputs enabled, All outputs unloaded VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH VDD = Max., VDDQN = Max., CL = 0pF Typ. 112 Max 150 Unit mA 2 75 µA 0.3 19 3 30 mA µA/MHz VDD = Max., VDDQN = Max., CL = 0pF 22 30 µA/MHz VDDQN = 1.8V., FVCO = 100MHz, CL = 15pF VDDQN = 1.8V., FVCO = 250MHz, CL = 15pF VDDQN = 1.8V., FVCO = 100MHz, CL = 15pF VDDQN = 1.8V., FVCO = 250MHz, CL = 15pF 275 310 135 200 400 450 200 300 mA mA NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH. 4. Bit 60 = 1. 5. All outputs are at the same interface level. DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL Symbol Parameter Value Units VDIF Input Signal Swing (1) VDDI V VX Differential Input Signal Crossing Point(2) VDDI/2 mV VTHI Input Timing Measurement Reference Level(3) tR, tF Input Signal Edge Rate(4) Crossing Point V 1.8 V/ns NOTES: 1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL Symbol Parameter Value VIH Input HIGH Voltage VIL Input LOW Voltage VTHI Input Timing Measurement Reference Level(2) tR, tF Input Signal Edge Rate(3) (1) VDDI V 0 V VDDI/2 mV 2 V/ns NOTES: 1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. 2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform. 18 Units IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE All outputs at the same interface level Symbol FNOM tRPW tFPW tU tSK(O) tSK1(ω) tSK2(ω) tSK1(INV) tSK2(INV) tSK(PR) t(φ) tODCV tORISE tOFALL tL tL(ω) tL(PD) tL(REFSEL1) tL(REFSEL2) tJIT(CC) Parameter Min. Typ. Max Unit VCO Frequency Range see JTAG/I2C Serial Configurations: VCO Frequency Range table Reference Clock Pulse Width HIGH or LOW 1 — — ns Feedback Input Pulse Width HIGH or LOW 1 — — ns Programmable Skew Time Unit see Control Summary Table Output Skew (Rise-Rise, Fall-Fall, Nominal)(1,2) — — 100 ps Multiple Frequency Skew (Rise-Rise, Fall-Fall, Nominal-Divided, Divided-Divided)(1,2,3) — — 100 ps Multiple Frequency Skew (Rise-Fall, Nominal-Divided, Divided-Divided)(1,2,3) — — 300 ps Inverting Skew (Nominal-Inverted)(1,2) — — 300 ps Inverting Skew (Rise-Rise, Fall-Fall, Rise-Fall, Inverted-Divided)(1,2,3) — — 300 ps Process Skew(1,2,4) — — 300 ps REF Input to FB Static Phase Offset(5) -100 — 100 ps Output Duty Cycle Variation from 50%(11,12) 1.8V LVTTL -375 — 375 ps 2.5V LVTTL -275 — 275 Output Rise Time(6) HSTL / eHSTL / 1.8V LVTTL — — 1.2 ns 2.5V LVTTL — — 1 Output Fall Time(6) HSTL / eHSTL / 1.8V LVTTL — — 1.2 ns 2.5V LVTTL — — 1 Power-up PLL Lock Time(7) — — 4 ms (7) PLL Lock Time After Input Frequency Change — — 1 ms PLL Lock Time After Asserting PD Pin(7) — — 1 ms PLL Lock Time After Change in REF_SEL(7,9) — — 100 µs PLL Lock Time After Change in REF_SEL (REF1 and REF0 are different frequency)(7) — — 1 ms Cycle-to-Cycle Output Jitter (peak-to-peak)(2,8) — 50 75 ps tJIT(PER) Period Jitter (peak-to-peak)(2,8) — — 75 ps tJIT(HP) Half Period Jitter (peak-to-peak)(2,8,10) — — 125 ps tJIT(DUTY) VOX Duty Cycle Jitter (peak-to-peak)(2,8) HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level — — 100 VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150 ps mV NOTES: 1. Skew is the time between the earliest and latest output transition among all outputs for which the same tU delay has been selected, when all outputs are loaded with the specified load. 2. For differential LVTTL outputs, the measurement is made at VDDQN/2, where the true outputs are only compared with other true outputs and the complementary outputs are only compared to other complementary outputs. For differential HSTL/eHSTL outputs, the measurement is made at the crossing point (VOX) of the true and complementary signals. 3. There are three classes of outputs: nominal (multiple of tU delay), inverted, and divided (divide-by-2 or divide-by-4 mode). 4. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQN, ambient temperature, air flow, etc.). 5. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For 1.8V / 2.5V LVTTL input and output, the measurement is taken from VTHI on REF to VTHI on FB. For HSTL / eHSTL input and output, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to 0tU, FB input divider is set to divide-by-one, and Bit 60 = 1. 6. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing. 7. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQN is stable and within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified limits. 8. The jitter parameters are measured with all outputs selected for 0tU, FB input divider is set to divide-by-one, and Bit 60 = 1. 9. Both REF inputs must be the same frequency, but up to ±180° out of phase. 10. For HSTL/eHSTL outputs only. 11. For LVTTL outputs only. 12. tODCV is measured with all outputs selected for zero delay. 19 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE All outputs at the different interface levels Symbol FNOM tRPW tFPW tU tSK(O) tSK1(ω) tSK2(ω) tSK1(INV) tSK2(INV) tSK(PR) t(φ) tODCV tORISE tOFALL tL tL(ω) tL(PD) tL(REFSEL1) tL(REFSEL2) tJIT(CC) Parameter Min. Typ. Max Unit VCO Frequency Range see JTAG/I2C Serial Configurations: VCO Frequency Range table Reference Clock Pulse Width HIGH or LOW 1 — — ns Feedback Input Pulse Width HIGH or LOW 1 — — ns Programmable Skew Time Unit see Control Summary Table Output Skew (Rise-Rise, Fall-Fall, Nominal)(1,2) — — 250 ps Multiple Frequency Skew (Rise-Rise, Fall-Fall, Nominal-Divided, Divided-Divided)(1,2,3) — — 500 ps Multiple Frequency Skew (Rise-Fall, Nominal-Divided, Divided-Divided)(1,2,3) — — 500 ps Inverting Skew (Nominal-Inverted)(1,2) — — 500 ps Inverting Skew (Rise-Rise, Fall-Fall, Rise-Fall, Inverted-Divided)(1,2,3) — — 500 ps (1,2,4) Process Skew — — 400 ps REF Input to FB Static Phase Offset(5) -200 — 200 ps Output Duty Cycle Variation from 50%(11,12) 1.8V LVTTL -475 — 475 ps 2.5V LVTTL -375 — 375 Output Rise Time(6) HSTL / eHSTL / 1.8V LVTTL — — 1.2 ns 2.5V LVTTL — — 1 Output Fall Time(6) HSTL / eHSTL / 1.8V LVTTL — — 1.2 ns 2.5V LVTTL — — 1 Power-up PLL Lock Time(7) — — 4 ms PLL Lock Time After Input Frequency Change(7) — — 1 ms (7) PLL Lock Time After Asserting PD Pin — — 1 ms PLL Lock Time After Change in REF_SEL(7,9) — — 100 µs PLL Lock Time After Change in REF_SEL (REF1 and REF0 are different frequency)(7) — — 1 ms Cycle-to-Cycle Output Jitter (peak-to-peak)(2,8) — — 100 ps tJIT(PER) Period Jitter (peak-to-peak)(2,8) — — 150 ps tJIT(HP) Half Period Jitter (peak-to-peak)(2,8,10) — — 200 ps tJIT(DUTY) VOX Duty Cycle Jitter (peak-to-peak)(2,8) HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level — — 150 VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150 ps mV NOTES: 1. Skew is the time between the earliest and latest output transition among all outputs for which the same tU delay has been selected, when all outputs are loaded with the specified load. 2. For differential LVTTL outputs, the measurement is made at VDDQN/2, where the true outputs are only compared with other true outputs and the complementary outputs are only compared to other complementary outputs. For differential HSTL/eHSTL outputs, the measurement is made at the crossing point (VOX) of the true and complementary signals. 3. There are three classes of outputs: nominal (multiple of tU delay), inverted, and divided (divide-by-2 or divide-by-4 mode). 4. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQN, ambient temperature, air flow, etc.). 5. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For 1.8V / 2.5V LVTTL input and output, the measurement is taken from VTHI on REF to VTHI on FB. For HSTL / eHSTL input and output, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to 0tU, FB input divider is set to divide-by-one, and Bit 60 = 1. 6. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing. 7. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQN is stable and within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified limits. 8. The jitter parameters are measured with all outputs selected for 0tU, FB input divider is set to divide-by-one, and Bit 60 = 1. 9. Both REF inputs must be the same frequency, but up to ±180° out of phase. 10. For HSTL/eHSTL outputs only. 11. For LVTTL outputs only. 12. tODCV is measured with all outputs selected for zero delay. 20 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE AC DIFFERENTIAL INPUT SPECIFICATIONS(1) Symbol tW Parameter Reference/Feedback Input Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)(2) Reference/Feedback Input Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2) HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL VDIF AC Differential Voltage(3) VIH AC Input HIGH VIL LVEPECL (4,5) AC Input LOW (4,6) Min. 1 1 Typ. — — Max — — Unit ns 400 — — mV Vx + 200 — — mV — — Vx - 200 mV — mV VDIF AC Differential Voltage(3) 400 — VIH AC Input HIGH 1275 — — mV VIL AC Input LOW(4) — — 875 mV (4) NOTES: 1. For differential input mode, Bits 35 - 30 = 1. 2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined by VDIF has been met or exceeded. 3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state. 4. For single-ended operation, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. Refer to each input interface's DC specification for the correct VREF[1:0] range. 5. Voltage required to switch to a logic HIGH, single-ended operation only. 6. Voltage required to switch to a logic LOW, single-ended operation only. 21 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM(1) tRPWL REF tRPWH REF tFPWH tFPWL FB FB tODCV tODCV Q Q tSK(O) tSK(O) OTHER Q OTHER Q tSK1(INV) tSK1(INV) INVERTED Q INVERTED Q tSK2(ω), tSK2(INV) tSK2(INV) tSK2(ω) Q DIVIDED BY 2 Q DIVIDED BY 2 tSK1(ω), tSK2(INV) tSK1(ω) Q DIVIDED BY 4 Q DIVIDED BY 4 NOTE: 1. The AC TIMING DIAGRAM applies to Bit 58 = 1. For Bit 58 = 0, the negative edge of FB aligns with the negative edge of REF[1:0], divided outputs change on the negative edge of REF[1:0], and the positive edges of the divide-by-2 and divide-by-4 signals align. 22 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE JITTER AND OFFSET TIMING WAVEFORMS nQ, QFB nQ, QFB tcycle n tcycle n + 1 tjit(cc) = tcycle n tcycle n+1 Cycle-to-Cycle jitter REF[1:0] REF[1:0] FB FB t(Ø)n + 1 t(Ø)n ∑ t(Ø) = n=N 1 t(Ø)n N Static Phase Offset NOTE: 1. Diagram for Bit 58 = 1 and HSTL / eHSTL input and output. nQ, QFB nQ, QFB tW(MIN) tW(MAX) tJIT(DUTY) = tW(MAX) - tW(MIN) Duty-Cycle Jitter 23 (N is a large number of samples) IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE nQ, QFB nQ, QFB tcycle n nQ, QFB nQ, QFB 1 fo tjit(per) = tcycle n 1 fo Period jitter nQ, QFB nQ, QFB thalf period n+1 thalf period n nQ, QFB nQ, QFB 1 fo tjit(hper) = thalf period n Half-Period jitter 24 1 2*f o IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND CONDITIONS VDDI R1 VIN 3 inch, ~50Ω Transmission Line VDD VDDQN R2 VDDI REF[1:0] D.U.T. Pulse Generator R1 VIN REF[1:0] 3 inch, ~50Ω Transmission Line R2 Test Circuit for Differential Input(1) DIFFERENTIAL INPUT TEST CONDITIONS Symbol VDD = 2.5V ± 0.2V Unit R1 100 Ω R2 100 Ω VDDI VCM*2 V HSTL: Crossing of REF[1:0] and REF[1:0] eHSTL: Crossing of REF[1:0] and REF[1:0] VTHI LVEPECL: Crossing of REF[1:0] and REF[1:0] V 1.8V LVTTL: VDDI/2 2.5V LVTTL: VDD/2 NOTE: 1. This input configuration is used for all input interfaces. For single-ended testing, the REF[1:0] must be left floating. For testing single-ended in differential input mode, the VIN should be floating. 25 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE VDDQN VDDQN VDD R1 VDDQN REF[1:0] R1 VDDQN VDDQN VDD nQ CL D.U.T. REF[1:0] R1 D.U.T. R1 FB QFB FB QFB VDDQN QFB nQ FB R2 CL R2 QFB FB CL R2 CL R2 SW1 SW1 Test Circuit for Differential Outputs Test Circuit for Differential Feedback DIFFERENTIAL OUTPUT TEST CONDITIONS DIFFERENTIAL FEEDBACK TEST CONDITIONS Symbol VDD = 2.5V ± 0.2V Symbol Unit VDD = 2.5V ± 0.2V Unit VDDQN = Interface Specified VDDQN = Interface Specified CL 15 pF CL 15 pF R1 100 Ω R1 100 Ω R2 100 Ω R2 100 Ω VOX HSTL: Crossing of nQ and nQ V VOX HSTL: Crossing of QFB and QFB V V VTHO 1.8V/2.5V LVTTL Open SW1 HSTL/eHSTL Closed eHSTL: Crossing of QFB and QFB eHSTL: Crossing of nQ and nQ VTHO 1.8V LVTTL: VDDQN/2 V 2.5V LVTTL: VDDQN/2 2.5V LVTTL: VDDQN/2 SW1 1.8V LVTTL: VDDQN/2 26 1.8V/2.5V LVTTL Open HSTL/eHSTL Closed IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL I2C SERIAL INTERFACE CONTROL INDUSTRIAL TEMPERATURE RANGE I2C ADDRESS The I C interface permits the configuration of the IDT5T9891. The IDT5T9891 is a read/write slave device meeting Philips I2C bus specifications. The I2C bus is controlled by a master device that generates the serial clock SCLK, controls bus access, and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter and receiver but the master device determines which mode is activated. 2 A7 1 A6 1 A5 0 A4 1 A3 X A2 X A1 X Address A0 is the read/write bit and is set to ‘0’ for writes and ‘1’ for reads. The ADDR0 and ADDR1 tri-level pins allow the last three bits of the 7-bit address to be defined by the user. BUS CONDITIONS Data transfer on the bus can only be initiated when the bus is not busy. During data transfer, the data line (SDA) must remain stable whenever the clock line (SCLK) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined by the I2C bus protocol and are illustrated in figure 1. ADDR1 LOW LOW LOW MID MID MID HIGH HIGH HIGH NOT BUSY Both the data (SDA) and clock (SCLK) lines remain high to indicate the bus is not busy. START DATA TRANSFER A high to low transition of the SDA line while the SCLK input is high indicates a START condition. All commands to the device must be preceded by a START condition. ADDR0 LOW MID HIGH LOW MID HIGH LOW MID HIGH A3 0 0 0 0 1 1 1 1 1 A2 0 0 1 1 0 0 1 1 1 A1 0 1 0 1 0 1 0 1 0 WRITE OPERATION (see I2C Interface Definition for ProgWrite) To initiate a write operation (ProgWrite), the read/write bit is set to ‘0’. During the write operation, the first two bytes transferred must be the Device Address followed by the Command Code. The internal programming registers of the device ignore these first two bytes. The subsequent bytes are the Data Bytes, which total twelve. All twelve Data Bytes must be written into the device during the write operation in order for the internal programming registers to be updated. If a STOP condition is generated before the 12th Data Byte, the internal programming registers will remain unchanged to prevent an invalid PLL configuration. An Acknowledge by the device between each byte must occur before the next byte is sent. After the transfer of the 12th Data Byte, an Acknowledge signal will be sent to the bus master after which it will generate a STOP condition. Once the STOP condition has occurred, the internal programming registers of the device will be updated. STOP DATA TRANSFER A low to high transition of the SDA line while SCLK is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition. DATA VALID The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCLK line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCLK signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and terminated with a STOP condition. ACKNOWLEDGE When addressed, the receiving device is required to generate an Acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the Acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. READ OPERATION (see I2C Interface Definition for ProgRead) To initiate a read operation (ProgRead), the read/write bit is set to ‘1’. During the read operation, there will be a total of fourteen data bytes returned following an Acknowledge of the device address. The first two data bytes are the ID Byte and a Reserved Byte, in that order. The subsequent bytes are the same twelve Data Bytes that were written during the write operation. The read back can be terminated at any time by issuing a STOP condition. I2C BUS OPERATION The IDT5T9891 I2C interface supports Standard-Mode (100kHz) and FastMode (400kHz) data transfer rates. Data is transferred in bytes in sequential order from the lowest to highest byte. After generating a START condition, the bus master broadcasts a 7-bit slave address followed by a read/write bit. I2C ID BYTE ID7 0 27 ID6 0 ID5 0 ID4 0 ID3 0 ID2 1 ID1 1 ID0 1 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE EEPROM OPERATION (see I2C Interface Definition for the EEPROM instructions) The IDT5T9891 can also store its configuration in internal EEPROM. The contents of the device’s internal programming registers can be saved to the EEPROM by issuing a save instruction (ProgSave) and can be loaded back to the internal programming registers by issuing a restore instruction (ProgRestore). To initiate a save or restore, only two bytes are transferred. The Device Address is issued with the read/write bit set to ‘0’ followed by the appropriate Command Code. The save or restore instruction executes after the STOP condition is received, during which time the IDT5T9891 will not generate Acknowledge bits. The device is ready to accept a new programming instruction once it Acknowledges its 7-bit address. The time it takes for the save and restore instructions to complete depends on the PLL oscillator frequency, FVCO. The restore time, TRESTORE, and the save time, TSAVE, can be calculated as follows: TRESTORE = 1.23X109/FVCO TSAVE = 3.09X109/FVCO + 52 (mS) (mS) In order for the save and restore instructions to function properly, the IDT5T9891 must not be in power-down mode (PD must be HIGH), and the PLL must be enabled (PLL_EN must be LOW and Bit 57 = 0). On power-up of the IDT5T9891, an automatic restore is performed to load the EEPROM contents into the internal programming registers. The auto-restore will not function properly if the device is in power-down mode (PD must be HIGH). The device’s auto-restore feature will function regardless of the state of the PLL_EN pin or Bit 57. The IDT5T9891 will be ready to accept a programming instruction once it acknowledges its 7-bit I2C address. The time it takes for the device to complete the auto-restore is approximately 3ms. PROGRAMMING NOTES Once the IDT5T9891 has been programmed either with a ProgWrite or ProgRestore instruction, the device will attempt to achieve phase lock using the new PLL configuration. If there is a valid REF and FB input clock connected to the device and it does not achieve lock, the user should issue a ProgRead instruction to confirm that the PLL configuration data is valid. On power-up and before the automatic ProgRestore instruction has completed, the internal programming registers will contain the value of ‘0’ for all bits 95:0. The PLL will remain at the minimum frequency and will not achieve phase lock until after the automatic restore is completed. If the outputs are enabled by the nSOE pins, the outputs will toggle at the minimum frequency. If the outputs are disabled by the nSOE pins and the OMODE pin is set HIGH, the nQ and QFB are stopped HIGH, while nQ and QFB are stopped LOW. SCLK tSU:START tSU:STOP tHD:START SDA Address or data valid START Data can change STOP tR tHIGH tF tLOW SCLK tHD:START tHD:DATA tSU:START tSU:DATA tSU:STOP SDA IN tBUF tOVD tOVD SDA OUT Figure 1: I2C Timing Data 28 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE I2C INTERFACE DEFINITION ProgWrite S Device Address W 7'b1101xxx 0 Part # 5T9891 ProgRead ProgSave ProgRestore S S S A 8'bxxxxxx00 A Data Byte 1 (Bits 95 - 88) A ... Data Byte 2 A ... Data Byte 3 A ... Data Byte 4 A ... Data Byte 5 A ... Data Byte 6 A ... Data Byte 7 A ... Data Byte 8 A ... Data Byte 9 A ... Data Byte 10 A ... Data Byte 11 A ... Data Byte 12 (Bits 7 - 0) A P L S B M S B L S B M S B Data Command Code ID Byte: ID 00000111 Device Address R 7'b1101xxx 1 Device Address W 7'b1101xxx 0 Device Address W 7'b1101xxx 0 ID Byte A 8'b00000111 A Reserved Byte A Data Byte 1 (Bits 95 - 88) A ... ... ... Data Byte 2 A ... Data Byte 3 A ... Data Byte 4 A ... Data Byte 5 A ... Data Byte 6 A ... Data Byte 7 A ... Data Byte 8 A ... Data Byte 9 A ... Data Byte 10 A ... Data Byte 11 A ... Data Byte 12 (Bits 7 - 0) A P Command Code A 8'bxxxxxx01 A P A P Command Code A 8'bxxxxxx10 29 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE I2C BUS DC CHARACTERISTICS Symbol VIH VIL VHYS IIN VOL Parameter Input HIGH Level Input LOW Level Hysteresis of Inputs Input Leakage Current Output LOW Voltage Conditions Min 0.7 * VDD Typ Max ±1.0 0.4 Unit V V V µA V Max Unit 100 KHz 0.3 * VDD 0.05 * VDD IOL = 3 mA I2C BUS AC CHARACTERISTICS FOR STANDARD MODE Symbol FSCLK tBUF Parameter Min Serial Clock Frequency (SCLK) Typ 0 Bus free time between STOP and START 4.7 µs tSU:START Setup Time, START 4.7 µs tHD:START Hold Time, START 4 µs tSU:DATA Setup Time, data input (SDA) 250 ns tHD:DATA Hold Time, data input (SDA)(1) 0 tOVD CB µs µs pF Output data valid from clock Capacitive Load for Each Bus Line 3.45 400 tR Rise Time, data and clock (SDA, SCLK) 1000 ns tF Fall Time, data and clock (SDA, SCLK) 300 ns tHIGH HIGH Time, clock (SCLK) 4 µs tLOW LOW Time, clock (SCLK) 4.7 µs 4 µs tSU:STOP Setup Time, STOP NOTE: 1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge of SCLK. I2C BUS AC CHARACTERISTICS FOR FAST MODE Symbol FSCLK Parameter Min Serial Clock Frequency (SCLK) 0 Typ Max Unit 400 KHz Bus free time between STOP and START 1.3 µs tSU:START Setup Time, START 0.6 µs tHD:START Hold Time, START 0.6 µs tSU:DATA Setup Time, data input (SDA) 100 ns tHD:DATA Hold Time, data input (SDA)(1) 0 tBUF tOVD CB Output data valid from clock Capacitive Load for Each Bus Line µs 0.9 400 µs pF ns tR Rise Time, data and clock (SDA, SCLK) 20 + 0.1 * CB 300 tF Fall Time, data and clock (SDA, SCLK) 20 + 0.1 * CB 300 ns tHIGH HIGH Time, clock (SCLK) 0.6 µs tLOW LOW Time, clock (SCLK) 1.3 µs Setup Time, STOP 0.6 µs tSU:STOP NOTE: 1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge of SCLK. 30 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE JTAG INTERFACE The Standard JTAG interface consists of four basic elements: • Test Access Port (TAP) • TAP controller • Instruction Register (IR) • Data Register Port (DR) The following sections provide a brief description of each element. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). Five additional pins (TDI, TDO, TMS, TCLK and TRST) are provided to support the JTAG boundary scan interface. The IDT5T9891 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices. Device ID Reg. MUX Boundary Scan Reg. Bypass Reg. TDO TDI TAP TMS TCLK TAP Controller clkDR, ShiftDR UpdateDR TRST Instruction Decode clkLR, ShiftLR UpdateLR Instruction Register Control Signals Boundary Scan Architecture TEST ACCESS PORT (TAP) The Tap interface is a general-purpose port that provides access to the internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST) and one output port (TDO). THE TAP CONTROLLER The Tap controller is a synchronous finite state machine that responds to TMS and TCLK signals to generate clock and control signals to the Instruction and Data Registers for capture and update of data. 31 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE 1 Test-Logic Reset 0 1 0 Run-Test/ Idle 1 1 SelectDR-Scan SelectIR-Scan 0 0 1 1 Capture-DR 0 Capture-IR 0 0 Shift-DR 0 Shift-IR 1 1 1 Exit1-DR 0 0 0 Pause-DR 1 Exit2-DR 0 Exit2-IR 1 1 Update-DR 1 0 Pause-IR 1 0 1 Exit1-IR Update-IR 1 0 0 TAP Controller State Diagram NOTES: 1. Five consecutive TCLK cycles with TMS = 1 will reset the TAP. 2. TAP controller must be reset before normal PLL operations can begin. Refer to the IEEE Standard Test Access Port Specification (IEEE Std.1149.1) for the full state diagram All state transitions within the TAP controller occur at the rising edge of theTCLK pulse. The TMS signal level (0 or 1) determines the state progression that occurs on each TCLK rising edge. The TAP controller takes precedence over the PLL and must be reset after power up of the device. See TRST description for more details on TAP controller reset. Test-Logic-Reset All test logic is disabled in this controller state enabling the normal operation of the IC. The TAP controller state machine is designed in such a way that, no matter what the initial state of the controller is, the TestLogic-Reset state can be entered by holding TMS at high and pulsing TCLK five times. This is the reason why the Test Reset (TRST) pin is optional. Run-Test-Idle In this controller state, the test logic in the IC is active only if certain instructions are present. For example, if an instruction activates the self test, then it will be executed when the controller enters this state. The test logic in the IC is idles otherwise. Select-DR-Scan This is a controller state where the decision to enter the Data Path or the Select-IR-Scan state is made. Select-IR-Scan This is a controller state where the decision to enter the Instruction Path is made. The Controller can return to the Test-Logic-Reset state otherwise. Capture-IR In this controller state, the shift register bank in the Instruction Register parallel loads a pattern of fixed values on the rising edge of TCLK. The last two significant bits are always required to be “01”. Shift-IR In this controller state, the instruction register gets connected between TDI and TDO, and the captured pattern gets shifted on each rising edge of TCLK. The instruction available on the TDI pin is also shifted in to the instruction register. Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made. Pause-IR This state is provided in order to allow the shifting of instruction register to be temporarily halted. Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made. Update-IR In this controller state, the instruction in the instruction register is latched in to the latch bank of the Instruction Register on every falling edge of TCLK. This instruction also becomes the current instruction once it is latched. Capture-DR In this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of TCLK. Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR states in the Instruction path. 32 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction is used to select the test to be performed, or the test data register to be accessed, or both. The instruction shifted into the register is latched at the completion of the shifting process when the TAP controller is at Update- IR state. The instruction register must contain 4 bit instruction register-based cells which can hold instruction data. These mandatory cells are located nearest the serial outputs they are the least significant bits. INDUSTRIAL TEMPERATURE RANGE path. When the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of TCLK when the TAP controller is in the Capture-DR state. The operation of the bypass register should not have any effect on the operation of the device in response to the BYPASS instruction. THE BOUNDARY-SCAN REGISTER The Boundary Scan Register allows serial data TDI be loaded in to or read out of the processor input/output ports. The Boundary Scan Register is a part of the IEEE 1149.1-1990 Standard JTAG Implementation. TEST DATA REGISTER The Test Data register contains three test data registers: the Bypass, the Boundary Scan register and Device ID register. These registers are connected in parallel between a common serial input and a common serial data output. The following sections provide a brief description of each element. For a complete description, refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). THE DEVICE IDENTIFICATION REGISTER The Device Identification Register is a Read Only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT5T9891, the Part Number field is 0X3A9. TEST BYPASS REGISTER The register is used to allow test data to flow through the device from TDI to TDO. It contains a single stage shift register for a minimum length in serial JTAG DEVICE IDENTIFICATION REGISTER 31 (MSB) Version (4 bits) 0X0 28 27 Part number (16-bit) 12 11 Manufacturer ID (11-bit) 0X33 1 0(LSB) 1 JTAG INSTRUCTION REGISTER The Instruction register allows instruction to be serially input into the device when the TAP controller is in the Shift-IR state. The instruction is decoded to perform the following: • Select test data registers that may operate while the instruction is current. The other test data registers should not interfere with chip operation and the selected data register. • Define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. The Instruction Register is a 4-bit field (i.e.IR3, IR2, IR1, IR0) to decode sixteen different possible instructions. Instructions are decoded as follows. JTAG INSTRUCTION REGISTER DECODING IR (3) IR (2) IR (1) IR (0) Instruction Function 0 0 0 0 EXTEST Select boundary scan register 0 0 0 1 SAMPLE/PRELOAD Select boundary scan register 0 0 1 0 IDCODE Select chip identification data register 0 0 1 1 0 1 0 0 PROGWRITE Writing to the volatile programming registers Reserved 0 1 0 1 PROGREAD Reading from the volatile programming registers 0 1 1 0 PROGSAVE Saving the contents of the volatile programming registers to the EEPROM 0 1 1 1 PROGRESTORE Loading the EEPROM contents into the volatile programming registers 1 0 0 0 CLAMP JTAG 1 0 0 1 HIGHZ JTAG 1 0 1 X BYPASS Select bypass register 1 1 X X BYPASS Select bypass register 33 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL The following sections provide a brief description of each instruction. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). INDUSTRIAL TEMPERATURE RANGE The PROGRESTORE instruction is for loading the IDT5T9891 configuration data from the EEPROM to the device’s volatile programming registers. This instruction selects the BYPASS register path for shifting data from TDI to TDO during data register scanning. EXTEST The required EXTEST instruction places the IC into an external boundarytest mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register is accessed to drive test data off-chip through the boundary outputs, and recieve test data off-chip through the boundary inputs. As such, the EXTEST instruction is the workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. During the execution of a PROGSAVE or PROGRESTORE instruction, the IDT5T9891 will not accept a new programming instruction (read, write, save, or restore). All non-programming JTAG instructions will function properly, but the user should wait until the save or restore is complete before issuing a new programming instruction. The time it takes for the save and restore instructions to complete depends on the PLL oscillator frequency, FVCO. The restore time, TRESTORE, and the save time, TSAVE, can be calculated as follows: SAMPLE/PRELOAD The required SAMPLE/PRELOAD instruction allows the IC to remain in a normal functional mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register can be accessed via a data scan operation, to take a sample of the functional data entering and leaving the IC. TRESTORE = 1.23X109/FVCO TSAVE = 3.09X109/FVCO + 52 (mS) (mS) If a new programming instruction is issued before the save or restore completes, the new instruction is ignored, and the BYPASS register path remains in effect for shifting data from TDI to TDO during data register scanning. IDCODE The optional IDCODE instruction allows the IC to remain in its functional mode and selects the optional device identification register to be connected between TDI and TDO. The device identification register is a 32-bit shift register containing information regarding the IC manufacturer, device type, and version code. Accessing the device identification register does not interfere with the operation of the IC. Also, access to the device identification register should be immediately available, via a TAP data-scan operation, after powerup of the IC or after the TAP has been reset using the optional TRST pin or by otherwise moving to the Test-Logic-Reset state. PROGWRITE The PROGWRITE instruction is for writing the IDT5T9891 configuration data to the device’s volatile programming registers. This instruction selects the programming register path for shifting data from TDI to TDO during data register scanning. The programming register path has 112 registers (14 bytes) between TDI and TDO. The 12 configuration data bytes are scanned in through TDI first, starting with Bit 0. After scanning in the last configuration bit, Bit 95, sixteen additional bits must be scanned in to place the configuration data in the proper location. The last sixteen registers in the programming path are reserved, read-only registers. In order for the ProgSave and ProgRestore instructions to function properly, the IDT5T9891 must not be in power-down mode (PD must be HIGH), and the PLL must be enabled (PLL_EN = LOW and Bit 57 = 0). On power-up of the IDT5T9891, an automatic restore is performed to load the EEPROM contents into the internal programming registers. The autorestore will not function properly if the device is in power-down mode (PD must be HIGH). The device's auto-restore feature will function regardless of the state of the PLL_EN pin or Bit 57. The time it takes for the device to complete the auto-restore is approximately 3ms. CLAMP The optional CLAMP instruction loads the contents from the boundary-scan register onto the outputs of the IC, and selects the one-bit bypass register to be connected between TDI and TDO. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the IC outputs. PROGREAD The PROGREAD instruction is for reading out the IDT5T9891 configuration data from the device’s volatile programming registers. This instruction selects the programming register path for shifting data from TDI to TDO during data register scanning. The programming register path has 112 registers between TDI and TDO, and the first bit scanned out through TDO will be Bit 0 of the configuration data. PROGSAVE and PROGRESTORE (EEPROM OPERATION) The PROGSAVE instruction is for copying the IDT5T9891 configuration data from the device’s volatile programming registers to the EEPROM. This instruction selects the BYPASS register path for shifting data from TDI to TDO during data register scanning. HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types) of an IC to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the IC outputs. BYPASS The required BYPASS instruction allows the IC to remain in a normal functional mode and selects the one-bit bypass register to be connected between TDI and TDO. The BYPASS instruction allows serial data to be transferred through the IC from TDI to TDO without affecting the operation of the IC. 34 IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE PROGRAMMING NOTES Once the IDT5T9891 has been programmed either with a ProgWrite or ProgRestore instruction, the device will attempt to achieve phase lock using the new PLL configuration. If there is a valif REF and FB input clock connected to the device, and it does not achieve lock, the user should issue a ProgRead instruction to confirm that the PLL configuration data is valid. On power-up and before the automatic ProgRestore instruction has completed, the internal programming registers will contain the value of '0' for all bits 95:0. The PLL will remain at the minimum frequency and will not achieve phase lock until after the automatic restore is completed. If the outputs are enabled by the nSOE pins, the outputs will toggle at the minimum frequency. If the outputs are disabled by the nSOE pins, and the OMODE pin is set high, the nQ[1:0] and QFB are stopped HIGH, while QFB is stopped LOW. tTCLK t4 t2 t1 TCLK t3 TDI/TMS tDS tDH TDO TDO tDO t6 TRST t5 Standard JTAG Timing NOTE: t1 = tTCLKLOW t2 = tTCLKHIGH t3 = tTCLKFALL t4 = tTCLKRISE t5 = tRST (reset pulse width) t6 = tRSR (reset recovery) JTAG AC ELECTRICAL CHARACTERISTICS Symbol tTCLK tTCLKHIGH tTCLKLOW tTCLKRISE tTCLKFALL tRST tRSR Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery Min. 100 40 40 — — 50 50 Max. — — — 5(1) 5(1) — — SYSTEM INTERFACE PARAMETERS Units ns ns ns ns ns ns ns Symbol tDO tDOH tDS tDH Parameter Data Output(1) Data Output Hold(1) Data Input, tRISE = 3ns Data Input, tFALL = 3ns NOTE: 1. 50pF loading on external output signals. NOTE: 1. Guaranteed by design. 35 Min. — 0 10 10 Max. 20 — — — Units ns ns ns ns IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL RECOMMENDED LANDING PATTERN NL 68 pin NOTE: All dimensions are in millimeters. 36 INDUSTRIAL TEMPERATURE RANGE IDT5T9891 EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL DIFFERENTIAL INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package X Package I -40°C to +85°C (Industrial) NL Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package VFQFPN - Green NLG 5T9891 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 EEPROM Programmable 2.5V Programmable Skew PLL Differential Clock Driver for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 37 for Tech Support: [email protected]