IDT IDT71B74 Bicmos static ram 64k (8k x 8-bit) cache-tag ram Datasheet

IDT71B74
BiCMOS STATIC RAM
64K (8K x 8-BIT)
CACHE-TAG RAM
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed address to MATCH comparison time
— Commercial: 8/10/12/15/20ns (max.)
• High-speed address access time
— Commercial: 8/10/12/15/20ns (max.)
• High-speed chip select access time
— Commercial: 6/7/8/10ns (max.)
• Power-ON Reset Capability
• Low power consumption
— 830mW (typ.) for 12ns parts
— 880mW (typ.) for 10ns parts
— 920mW (typ.) for 8ns parts
• Produced with advanced BiCMOS high-performance
technology
• Input and output directly TTL-compatible
• Standard 28-pin plastic DIP and 28-pin SOJ (300 mil)
The IDT71B74 is a high-speed cache address comparator
subsystem consisting of a 65,536-bit static RAM organized as
8K x 8 and an 8-bit comparator. A single IDT71B74 can map
8K cache words into a 2 megabyte address space by using the
21 bits of address organized with the 13 LSBs for the cache
address bits and the 8 higher bits for cache data bits. Two
IDT71B74s can be combined to provide 29 bits of address
comparison, etc. The IDT71B74 also provides a single RAM
clear control, which clears all words in the internal RAM to zero
when activated. This allows the tag bits for all locations to be
cleared at power-on or system-reset, a requirement for cache
comparator systems. The IDT71B74 can also be used as a
resettable 8K x 8 high-speed static RAM.
The IDT71B74 is fabricated using IDT’s high-performance,
high-reliability BiCMOS technology. Address access times as
fast as 8ns, chip select times of 6ns and address-to-match
times of 8ns are available.
The MATCH pin of several IDT71B74s can be wired-ORed
together to provide enabling or acknowledging signals to the
data cache or processor, thus eliminating logic delays and
increasing system throughput.
FUNCTIONAL BLOCK DIAGRAM
VCC
A0
ADDRESS
DECODER
65,536-BIT
MEMORY ARRAY
GND
A12
RESET
I/O0 - 7
WE
OE
CS
8
I/O CONTROL
CONTROL
LOGIC
EQUAL
MATCH (OPEN DRAIN)
3013 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-3013/4
14.1
1
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
RESET
1
28
V CC
A 12
A7
A6
A5
A4
A3
A2
A1
A0
I/O 0
I/O 1
I/O 2
GND
2
27
WE
3
26
4
25
MATCH
A8
A9
A 11
5
24
P28-2
SO28-5
6
23
7
22
8
21
9
20
CS
10
19
11
18
12
17
13
16
14
15
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
OE
A 10
3013 drw 02
DIP/SOJ
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
TRUTH TABLE(1, 2)
WE
CS
OE
RESET
MATCH
I/O
Function
Symbol
X
X
X
L
HIGH
—
Reset all bits to LOW
VTERM(2)
X
H
X
H
HIGH
Hi-Z
Deselect chip
Terminal Voltage with
Respect to GND
H
L
H
H
LOW
DIN
No MATCH
TA
H
L
H
H
HIGH
DIN
MATCH
H
L
L
H
HIGH
DOUT
Read
L
L
X
H
HIGH
DIN
Write
NOTES:
3013 tbl 01
1. H = VIH, L = VIL, X = DON'T CARE
2. HIGH = High-Z (pulled up by an external resistor), and LOW = VOL.
PIN DESCRIPTIONS
Pin Names
Description
Rating
Com’l.
Unit
–0.5 to +7.0
V
Operating Temperature
0 to +70
°C
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–55 to +125
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
NOTES:
3013 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
A0–12
Address
I/O0-7
Data Input/Output
CS
Chip Select
RESET
Memory Reset
MATCH
Data/Memory Match (Open Drain)
CIN
Input Capacitance
WE
Write Enable
COUT
Output Capacitance
OE
Output Enable
GND
Ground
VCC
Power
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ Package)
Symbol
Parameter(1)
Conditions
Max. Unit
VIN = 3dV
6
pF
VOUT = 3dV
7
pF
NOTE:
3013 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
3013 tbl 02
14.1
2
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Parameter
Min.
Typ.
VCC
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
VIHR
VIL
Input HIGH Voltage
RESET
(1)
2.2
(2)
Input Voltage
Input LOW Voltage
2.5
–0.5
(3)
Max. Unit
(4)
—
6.0
Grade
Ambient Temperature
GND
VCC
Commercial
0°C to +70°C
0V
5V ± 10%
3013 tbl 06
V
—
6.0
V
—
0.8
V
NOTES:
3013 tbl 05
1. All inputs except RESET.
2. When using bipolar devices to drive the RESET input, a pullup resistor of
1kΩ–10kΩ is usually required to assure this voltage.
3. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
4. VTERM must not exceed VCC + 0.5V.
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V)
Symbol
ICC
Parameter
Dynamic Operating Current
Outputs Open, VCC = Max., f = fMAX(2)
WE
WE
71B74S8
71B74S10
71B74S12
71B74S15
71B74S20
Unit
230
210
210
200
200
170
190
160
180
150
mA
mA
= VLC
= VHC
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only input addresses are cycling at fMAX.
3013 tbl 07
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE (VCC = 5.0V ± 10%)
IDT71B74S
Symbol
Parameter
Test Condition
Min.
Max.
Unit
|ILI|
Input Leakage Current
VCC = Max., VIN = GND to VCC
—
5
µA
|ILO|
Output Leakage Current
VCC = Max., CS = VIH,
VOUT = GND to VCC
—
5
µA
Output LOW Voltage
IOL = 22mA MATCH
—
0.5
V
IOL = 18mA MATCH
—
0.4
VOL
VOH
Output HIGH Voltage
IOL = 10mA, VCC = Min. (Except MATCH)
—
0.5
IOL = 8mA, VCC = Min. (Except MATCH)
—
0.4
IOH = –4mA, VCC = Min. (Except MATCH)
2.4
—
V
3013 tbl 08
AC TEST CONDITIONS
Input Pulse Levels
1.5V
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
50Ω
DATA OUT
See Figures 1, 2, and 3
3013 drw 03
3013 tbl 09
Figure 1. AC Test Load
14.1
3
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
7
5V
•
6
∆TADM
(Typical, ns) 5
480Ω
DATA OUT
4
3
•
2
1
•
•
•
255Ω
•
5pF*
•
3013 drw 05
*Includes scope and jig.
8 20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
3013 drw 04
Figure 1A. Lumped Capacitive Load
Typical Derating Curve
7
•
6
∆TAA
(Typical, ns) 5
5V
4
RL
•
3
MATCH
•
2
1
•
R L = 200Ω (COM’L.)
= 270Ω (MIL.)
•
•
•
3013 drw 06
8 20 40 60 80 100 120 140 160 180 200
Figure 3. AC Test Load for MATCH
CAPACITANCE (pF)
3013 drw 07
Figure 3A. Lumped Capacitive Load
Typical Derating Curve
DATA
ADDR
32
D0-D 31
32
A0-A31
13
8
7
A17 -A24
5V
80486
32-BIT
MICROPROCESSOR
R L(2)
A4-A16
DATA
ADDR
LOGIC 1
8
9
8
8
9
8
IDT71256
CACHEDATA
RAM
256
256
256
A25-A31
IDT71B74
CACHETAG
RAM
IDT71B74
CACHETAG
RAM
MATCH
MATCH
MAIN
MEMORY
CLEAR
RDY
MEMORY READ/WRITE
CONTROL LOGIC
CACHE READ/WRITE
MAIN MEMORY READ/WRITE
3013 drw 08
NOTES:
1. For more information refer to IDT Application Notes AN-07 and AN-78 and Technical Notes TN-11 and TN-13.
2. RL = 200Ω.
Figure 4. Example of Cache Memory System Block Diagram
14.1
4
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8
Symbol
Parameter
71B74S10
71B74S12
71B74S15
71B74S20
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
8
—
10
—
12
—
15
—
20
—
ns
tAA
Address Access Time
—
8
—
10
—
12
—
15
—
20
ns
Chip Select Access Time
—
6
—
7
—
8
—
8
—
10
ns
Chip Select to Output in Low-Z
2
—
2
—
2
—
3
—
3
—
ns
tACS
tCLZ
(1)
tOE
tOLZ
Output Enable to Output Valid
—
5
—
6
—
6
—
8
—
9
ns
(1)
Output Enable to Output in Low-Z
2
—
2
—
2
—
2
—
2
—
ns
(1)
Chip Select to Output in High-Z
—
4
—
5
—
5
—
7
—
8
ns
(1)
Output Disable to Output in High-Z
—
4
—
4
—
5
—
5
—
8
ns
Output Hold from Address Change
3
—
3
—
3
—
3
—
3
—
tCHZ
tOHZ
tOH
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
ns
3013 tbl 10
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t RC
ADDRESS
t AA
t OH
OE
t OE
t OLZ (5)
t OHZ (5)
CS
t ACS (3)
t CHZ (5)
t CLZ (5)
DATAOUT
DATAOUT VALID
3013 drw 09
TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4)
t RC
ADDRESS
t AA
t OH
t OH
DATAOUT
DATAOUT VALID
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is continuously active, OE is LOW.
5. Transition is measured ±200mV from steady state.
14.1
3013 drw 10
5
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8
Symbol
Parameter
71B74S10
71B74S12
71B74S15
71B74S20
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle
tWC
Write Cycle Time
8
—
10
—
12
—
15
—
20
—
ns
tCW
Chip Select to End of Write
7
—
8
—
9
—
10
—
15
—
ns
tAW
Address Valid to End of Write
7
—
8
—
9
—
10
—
15
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
0
—
0
—
ns
tWP
Write Pulse Width
7
—
8
—
9
—
10
—
15
—
ns
tWR
Write Recovery Time (CS, WE)
0
—
0
—
0
—
0
—
0
—
ns
tWHZ(1)
Write Enable to Output in High-Z
—
5
—
5
—
5
—
5
—
5
ns
tDW
Data Valid to End of Write
5
—
5
—
6
—
8
—
10
—
ns
tDH
Data Hold from Write Time
0
—
0
—
0
—
0
—
0
—
ns
tOW(1)
Output Active from End of Write
2
—
2
—
2
—
2
—
2
—
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
ns
3013 tbl 11
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Controlled Timing, OE HIGH During Write)(1, 6)
t WC
ADDRESS
OE
CS
t WR (3)
t AW
t AS
WE
t WP (2)
t WHZ (8,9)
t OW (9)
DATAOUT
t OHZ
t DW
(4,9)
t DH
DATA VALID
DATAIN
3013 drw 11
NOTES:
1. WE, CS must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW WE and a LOW CS.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. OE is continuously HIGH, OE ≥ VIH. If during the WE controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and the data to be placed on the bus for the required tDW. If OE is HIGH during the WE controlled write cycle, this requirement does not
apply and the minimum write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW timing.
7. DATAOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. tWHZ is not included if OE remains HIGH during the write cycle. If OE is LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW.
9. Transition is measured ±200mV from steady state.
14.1
6
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS Controlled Timing)(1, 6)
t WC
ADDRESS
OE
t CW
(5)
CS
t WR (3)
(2)
t AW
t AS
WE
t OW (9)
t WHZ (8,9)
(7)
DATAOUT
t DW
t DH
DATA VALID
DATA IN
3013 drw 12
NOTES:
1. WE, CS must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW WE and a LOW CS.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. OE is continuously HIGH, OE ≥ VIH. If during the WE controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and the data to be placed on the bus for the required tDW. If OE is HIGH during the WE controlled write cycle, this requirement does not
apply and the minimum write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW timing.
7. DATAOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. tWHZ is not included if OE remains HIGH during the write cycle. If OE is LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW.
9. Transition is measured ±200mV from steady state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8
Symbol
Parameter
71B74S10
71B74S12
71B74S15
71B74S20
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Address to MATCH Valid
—
8
—
10
—
12
—
15
—
20
ns
Chip Select to MATCH Valid
—
7
—
7
—
8
—
10
—
10
ns
Chip Select to MATCH HIGH
—
7
—
8
—
8
—
8
—
8
ns
Data Input to MATCH Valid
—
7
—
8
—
10
—
12
—
12
ns
Match Cycle
tADM
tCSM
(1)
tCSMHI
tDAM
tOEMHI
(1)
tWEMHI
(1)
(1)
OE
LOW to MATCH HIGH
—
7
—
8
—
10
—
10
—
10
ns
WE
LOW to MATCH HIGH
—
7
—
8
—
10
—
10
—
10
ns
—
8
—
10
—
10
—
12
—
15
ns
tRSMHI
RESET
LOW to MATCH HIGH
tMHA
MATCH Valid Hold From Address
2
—
2
—
2
—
2
—
2
—
ns
tMHD
MATCH Valid Hold From Data
2
—
2
—
2
—
2
—
2
—
ns
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
14.1
3013 tbl 12
7
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
MATCH TIMING(1)
ADDRESS
t MHA
t ADM
t CSM
CS
t CSMHI
(2)
OE
t OEMHI
(2)
WE
t WEMHI
(2)
RESET
t RSMHI
VALID MATCH
DATA
VALID READ DATA
DATA
(2)
t DAM
t MHD
MATCH
MATCH VALID
MATCH
NO MATCH
3013 drw 13
NOTES:
1. It is not recommended to float data and address input pins while the MATCH pin is active.
2. Transition is measured at ±200mV from steady state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
71B74S8
Symbol
Parameter
71B74S10
71B74S12
71B74S15
71B74S20
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
30
—
35
—
35
—
40
—
45
—
ns
Reset Cycle
tRSPW(1)
Reset Pulse Width
tWERS
WE
HIGH to Reset HIGH
5
—
5
—
5
—
5
—
5
—
ns
tRSRC
Reset HIGH to WE LOW
25
—
25
—
25
—
30
—
30
—
ns
tPORS(2)
Power On Reset
100
—
100
—
100
—
120
—
120
—
ns
NOTES:
1. Recommended duty cycle = 10% maximum.
2. This parameter is guaranteed with the AC Load (Figure 1) by device characterization, but is not production tested.
3013 tbl 13
RESET TIMING
t RSPW
RESET
t RSRC
WE
t WERS
3013 drw 14
14.1
8
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
POWER ON RESET TIMING
t PORS
VCC
RESET
t RSRC
WE
t WERS
3013 drw 15
5V
IDT71B74
IDT71B74
1KΩ – 10KΩ
RESET
CMOS GATE
RESET
BIPOLAR GATE
3013 drw 16
Driving the RESET pin with CMOS logic.
3013 drw 17
Driving the RESET pin with bipolar logic.
Figure 5.
ORDERING INFORMATION
IDT
71B74
S
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
14.1
Blank
Commercial (0°C to +70°C)
TP
Y
Plastic DIP (300 mil) (P28–2)
SOJ (Small Outline IC, J-bend) (SO28–5)
8
10
12
15
20
Commercial Only, SOJ Only
Commercial Only
Commercial Only
Commercial Only
Commercial Only
Speed in ns
3013 drw 18
9
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