TI1 DS90UR907QSQX 24-bit color fpd-link to fpd-link ii converter Datasheet

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DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
DS90UR907Q-Q1 5 to 65-MHz, 24-Bit Color FPD-Link to FPD-Link II Converter
1 Features
3 Description
•
The DS90UR907Q-Q1 converts FPD-Link to FPDLink II. It translates four LVDS data/control streams
and one LVDS clock pair (FPD-Link) into a highspeed serialized interface (FPD-Link II) over a single
pair. This serial bus scheme greatly eases system
design by eliminating skew problems between clock
and data, reduces the number of connector pins,
reduces the interconnect size, weight, and cost, and
overall eases PCB layout. In addition, internal DC
balanced encoding is used to support AC-coupled
interconnects.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5-MHz to 65-MHz Support (140-Mbps to 1.82Gbps Serial Link)
5-Channel (4 data + 1 clock) FPD-Link Receiver
Inputs
AC-Coupled STP Interconnect up to 10 Meters in
Length
Integrated Output Termination
At Speed Link BIST Mode
Optional I2C Compatible Serial Control Bus
RGB888 + VS, HS, DE support
Power-Down Mode Minimizes Power Dissipation
Randomizer/Scrambler – DC-Balanced Data
Stream
Low EMI FPD-Link Input
Selectable Output VOD and Adjustable DeEmphasis
1.8-V or 3.3-V Compatible Control Bus Interface
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
>8-kV HBM and ISO 10605 ESD Rating
Backward Compatible Mode for Operation With
Older Generation Devices
The DS90UR907Q-Q1 converts, balances and level
shifts four LVDS data/control streams, and embeds
one LVDS clock pair (FPD-Link) to a serial stream
(FPD-Link II). Up to 24 bits of RGB in the FPD-Link
are serialized along with the three video control
signals.
Serial transmission is optimized by a user selectable
de-emphasis and differential output level select
features. EMI is minimized by the use of low voltage
differential signaling and spread spectrum clocking
compatibility.
With fewer wires to the physical interface of the host,
FPD-Link input with LVDS technology is ideal for high
speed, low power and low EMI data transfer.
The device is offered in a 36-pin WQFN package and
is specified over the automotive AEC-Q100 Grade 2
temperature range of –40˚C to 105˚C.
2 Applications
•
•
Automotive Display for Navigation
Automotive Display for Entertainment
Device Information(1)
PART NUMBER
PACKAGE
DS90UR907Q-Q1
WQFN (36)
BODY SIZE (NOM)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Applications Diagram
FPD-Link
FPD-Link II
HOST
Graphics
Processor
RGB Style Display Interface
VDDIO
(1.8V or 3.3V)
RxCLKIN+/-
PDB
MAPSEL
CONFIG[1:0]
Optional
SCL
SDA
ID[x]
TxOUT3+/-
High-Speed Serial Link
1 Pair/AC Coupled
RxIN2+/-
RxIN0+/-
VDDIO
1.8V 3.3V (1.8V or 3.3V)
1.8V
RxIN3+/-
RxIN1+/-
FPD-Link
TxOUT2+/-
DOUT+
RIN+
DOUT-
RIN100 ohm STP Cable
DS90UR907Q
Converter
CMF
BISTEN
VODSEL
De-Emph
SSC[2:0]
LFMODE
CONFIG[1:0]
MAPSEL
Optional
SCL
SDA
ID[x]
DS90UR908Q
Converter
TxOUT1+/TxOUT0+/-
RGB Display
QVGA to XGA
24-bit Color Depth
TxCLKOUT+/-
LOCK
PASS
PDB
BISTEN
OEN
OSSEL
VODSEL
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UR907Q-Q1
SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings—JEDEC .............................................. 5
ESD Ratings—IEC and ISO...................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
DC Electrical Characteristics .................................... 6
Recommended Timing for the Serial Control Bus .... 7
Switching Characteristics .......................................... 8
DC and AC Serial Control Bus Characteristics......... 8
Typical Characteristics .......................................... 12
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2
7.3
7.4
7.5
8
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
13
13
18
18
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 24
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (April 2013) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted table note from Pin Functions .................................................................................................................................. 3
•
Deleted 36L WQFN Package row from Absolute Maximum Ratings .................................................................................... 5
Changes from Revision E (April 2013) to Revision F
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 27
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SNLS316G – SEPTEMBER 2009 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
RxIN0-
28
RxIN0+
29
RxIN1-
30
RxIN1+
31
RES4
MAPSEL
RES7
VDDRX
PDB
VDDIO
BISTEN
VODSEL
De-Emph
27
26
25
24
23
22
21
20
19
NJK Package
36-Pin WQFN
Top View
DAP = GND
DS90UR907Q
(Top View)
18
RES3
17
VDDTX
16
DOUT+
15
DOUT-
14
VDDHS
9
CONFIG[1]
CONFIG[0]
10
8
36
RES0
RES5
7
VDDP
SDA
11
6
35
SCL
RxCLKIN+
5
RES1
VDDL
12
4
34
ID[x]
RxCLKIN-
3
RES2
RES6
13
2
33
RxIN3+
RxIN2+
1
32
RxIN3-
RxIN2-
Pin Functions
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
FPD-LINK INPUT INTERFACE
RxIN[3:0]+
2, 33, 31, 29
I, LVDS
True LVDS Data Input
This pair requires an external 100 Ω termination for standard LVDS levels.
RxIN[3:0]-
1, 34, 32, 30,
28
I, LVDS
Inverting LVDS Data Input
This pair requires an external 100 Ω termination for standard LVDS levels.
RxCLKIN+
35
I, LVDS
True LVDS Clock Input
This pair requires an external 100 Ω termination for standard LVDS levels.
RxCLKIN-
34
I, LVDS
Inverting LVDS Clock Input
This pair requires an external 100 Ω termination for standard LVDS levels.
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Pin Functions (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
CONTROL AND CONFIGURATION
PDB
23
I, LVCMOS
w/ pulldown
Power-down Mode Input
PDB = 1, Device is enabled (normal operation).
Refer to Power-Up Requirements and PDB Pin in the Applications Information Section.
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL
20
I, LVCMOS
w/ pulldown
Differential Driver Output Voltage Select — Pin or Register Control
VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typical) — Long Cable / De-E
Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typical)
De-Emph
19
I, Analog
w/ pullup
MAPSEL
26
I, LVCMOS
w/ pulldown
FPD-Link Map Select — Pin or Register Control
MAPSEL = 1, MSB on RxIN3+/-. Figure 17
MAPSEL = 0, LSB on RxIN3+/-. Figure 16
10, 9
I, LVCMOS
w/ pulldown
Operating Modes
Determine the device operating mode and interfacing device. Table 1
CONFIG[1:0] = 00: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR906 or DS90UR908, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
ID[x]
4
I, Analog
SCL
6
I, LVCMOS
SDA
7
BISTEN
21
I, LVCMOS
w/ pulldown
BIST Mode — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[7:0]
25, 3, 36, 27,
18, 13, 12, 8
I, LVCMOS
w/ pulldown
Reserved - tie LOW
CONFIG[1:0]
De-Emphasis Control — Pin or Register Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control through register.
See Table 3
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10-kΩ pullup to 1.8-V rail. See Table 5.
Serial Control Bus Clock Input - Optional
SCL requires an external pullup resistor to VDDIO.
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pullup resistor VDDIO.
FPD-LINK II SERIAL INTERFACE
DOUT+
16
O, LVDS
True Output.
The output must be AC Coupled with a 100 nF capacitor.
DOUT-
15
O, LVDS
Inverting Output.
The output must be AC Coupled with a 100 nF capacitor.
POWER AND GROUND
VDDL
5
Power
Logic Power, 1.8 V ±5%
VDDP
11
Power
PLL Power, 1.8 V ±5%
VDDHS
14
Power
TX High Speed Logic Power, 1.8 V ±5%
VDDTX
17
Power
Output Driver Power, 1.8 V ±5%
VDDRX
24
Power
RX Power, 1.8 V ±5%
VDDIO
22
Power
LVCMOS I/O Power and FPD-Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Supply voltage – VDDn (1.8 V)
–0.3
2.5
V
Supply voltage – VDDIO
−0.3
4
V
LVCMOS I/O voltage
−0.3
VDDIO + 0.3
V
LVDS input voltage
−0.3
VDDIO + 0.3
V
Driver output voltage
−0.3
VDDn + 0.3
V
150
°C
150
°C
Junction temperature
−65
Storage temperature
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings—JEDEC
VALUE
Human-body model (HBM), per AEC Q100-002
(1)
V(ESD)
(1)
Electrostatic discharge
UNIT
±8000
Charged-device model (CDM), per AEC Q100-011
±1250
Machine model
±250
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC and ISO
VALUE
RD = 330 Ω, CS = 150 pF
V(ESD)
Electrostatic discharge
RD = 330 Ω, CS = 150 and 330 pF
RD = 2 kΩ, CS = 150 and 330 pF
IEC, powered-up only contact discharge
(RIN+, RIN−)
≥±6000
IEC, powered-up only air-gap discharge
(RIN+, RIN−)
≥±30000
UNIT
V
ISO10605 contact discharge (RIN+, RIN−)
≥±8000
ISO10605 air-gap discharge (RIN+, RIN−)
≥±15000
ISO10605 contact discharge (RIN+, RIN−)
≥±8000
ISO10605 air-gap discharge (RIN+, RIN−)
≥±15000
V
V
6.4 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
1.71
1.8
1.89
V
3
3.3
3.6
V
−40
25
105
°C
OR
LVCMOS Supply Voltage (VDDIO)
Operating Free Air Temperature (TA)
RxCLKIN Frequency
5
Supply Noise (1)
(1)
65
MHz
100
mVP-P
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8 V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
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6.5 Thermal Information
DS90UR907Q-Q1
THERMAL METRIC (1)
NJK (WQFN)
UNIT
36 PINS
RθJA
Junction-to-ambient thermal resistance
33.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
15.8
°C/W
RθJB
Junction-to-board thermal resistance
7.2
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
LVCMOS INPUT DC SPECIFICATIONS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VDDIO = 3 to 3.6 V
VDDIO = 1.71 to 1.89 V
VDDIO = 3 to 3.6 V
IIN
Input Current
VDDIO = 1.71 to 1.89 V
VIN = 0 V or VDDIO
VDDIO = 3
to 3.6 V
PDB,
VODSEL,
MAPSEL,
CONFIG[1:0],
BISTEN
2.2
VDDIO
0.65* VDDIO
VDDIO
GND
0.8
GND
0.35*
VDDIO
–15
±1
15
–15
±1
15
V
V
μA
VDDIO = 1.7
to 1.89 V
FPD-LINK LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Threshold High
Voltage
VTL
Differential Threshold Low
Voltage
|VID|
Differential Input Voltage
Swing
VCM
Common Mode Voltage
IIN
Input Current
(1)
(2)
(3)
6
100
mV
VCM = 1.2 V, Figure 1
–100
RxIN[3:0]+/-,
RxCLKIN+/-,
200
600
VDDIO = 3.3 V
0
1.2
2.4
VDDIO = 1.8 V
0
1.2
1.55
−15
±1
15
mV
V
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD = 3.3 V, Ta = 25°C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
±225
±300
±375
±350
±450
±550
UNIT
FPD-LINK II LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
VODp-p
Differential Output Voltage
(DOUT+) – (DOUT-)
VODSEL = 0
RL = 100 Ω,
VODSEL = 1
De-Emph = disabled,
VODSEL = 0
Figure 3
VODSEL = 1
ΔVOD
Output Voltage Unbalance
RL = 100 Ω, De-Emph = disabled,
VODSEL = L
VOS
Offset Voltage – Singleended
At TP A and B, Figure 2
RL = 100 Ω,
De-Emph = disabled
ΔVOS
Offset Voltage Unbalance
Single-ended
At TP A and B, Figure 2
RL = 100 Ω, De-Emph = disabled
IOS
Output Short-Circuit Current
DOUT± = 0 V,
De-Emph = disabled
RT
Internal Termination
Resistor
VODSEL = 0
VODSEL = 1
600
mVp-p
900
mVp-p
1
DOUT+,
DOUT-
VODSEL = 0
mV
50
mV
1.65
V
1.575
V
1
mV
–35
mA
80
120
Ω
80
90
mA
3
5
mA
10
13
mA
75
85
mA
3
5
mA
10
13
mA
60
1000
µA
0.5
10
µA
1
30
µA
NOM
MAX
SUPPLY CURRENT
IDDT1
IDDIOT1
IDDT2
Supply Current
(includes load current)
RL = 100 Ω, f = 65 MHz
IDDIOT2
IDDZ
IDDIOZ
Supply Current Power
Down
Checker Board
Pattern,
De-Emph = 3 kΩ,
VODSEL = H,
Figure 10
VDD= 1.89 V
Checker Board
Pattern,
De-Emph = 6 kΩ,
VODSEL = L,
Figure 10
VDD= 1.89 V
PDB = 0 V , (All
other LVCMOS
Inputs = 0 V)
All VDD pins
VDDIO= 1.89 V
VDDIO = 3.6 V
VDDIO
All VDD pins
VDDIO= 1.89 V
VDDIO = 3.6 V
VDD= 1.89 V
VDDIO= 1.89 V
VDDIO = 3.6 V
VDDIO
All VDD pins
VDDIO
6.7 Recommended Timing for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN
fSCL
tLOW
tHIGH
tHD;STA
tSU:STA
tHD;DAT
tSU;DAT
SCL Clock Frequency
SCL Low Period
SCL High Period
Standard Mode
0
100
Fast Mode
0
400
Standard Mode
4.7
Fast Mode
1.3
Standard Mode
Fast Mode
4
us
0.6
Standard Mode
Fast Mode
0.6
Set Up time for a start or a
repeated start condition,
Figure 12
Standard Mode
4.7
Fast Mode
0.6
Data Hold Time,
Figure 12
Standard Mode
0
3.45
Fast Mode
0
0.9
Data Set Up Time,
Figure 12
Standard Mode
250
Fast Mode
100
4
us
us
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kHz
us
Hold time for a start or a
repeated start condition,
Figure 12
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Units
us
ns
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Recommended Timing for the Serial Control Bus (continued)
Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN
tSU;STO
tBUF
tr
tf
NOM
MAX
Set Up Time for STOP
Condition, Figure 12
Standard Mode
Fast Mode
0.6
4
Bus Free Time
Between STOP and START,
Figure 12
Standard Mode
4.7
Fast Mode
1.3
SCL and SDA Rise Time,
Figure 12
Standard Mode
Fast Mode
300
SCL and SDA Fall Time,
Figure 12
Standard Mode
300
Fast mode
300
Units
us
us
1000
ns
ns
6.8 Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FPD-LINK LVDS INPUT
tRSP0
Receiver Strobe Position-bit 0
0.66
1.1
1.54
ns
tRSP1
Receiver Strobe Position-bit 1
2.86
3.3
3.74
ns
tRSP2
Receiver Strobe Position-bit 2
5.05
5.5
5.93
ns
tRSP3
Receiver Strobe Position-bit 3
7.25
7.7
8.13
ns
tRSP4
Receiver Strobe Position-bit 4
9.45
9.90
10.33
ns
tRSP5
Receiver Strobe Position-bit 5
11.65
12.1
12.53
ns
tRSP6
Receiver Strobe Position-bit 6
13.85
14.30
14.73
ns
RxCLKIN = 65 MHz,
RxIN[3:0]
Figure 5
FPD-LINK II LVDS OUTPUT
tHLT
tHLT
tXZD
Output Low-to-High Transition
Time, Figure 4
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 0
200
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 1
200
Output High-to-Low Transition
Time, Figure 4
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 0
200
RL = 100 Ω, De-Emphasis = disabled, VODSEL = 1
200
Ouput Active to OFF Delay,
Figure 7
(1)
tPLD
PLL Lock Time, Figure 6
RL = 100 Ω
tSD
Delay - Latency, Figure 8
RL = 100 Ω
tDJIT
Output Total Jitter,
Figure 9
RL = 100 Ω, De-Emphasis = disabled,
RANDOM pattern, RxCLKIN = 43 and 65 MHz (2)
λSTXBW
Jitter Transfer
Function –3-dB Bandwidth (3)
δSTX
(1)
(2)
(3)
(4)
(4)
Jitter Transfer
Function Peaking (3) (4)
ps
ps
5
15
ns
1.5
10
ms
140*T
145*T
ns
0.26
RxCLKIN = 43 MHz
2.2
RxCLKIN = 65 MHz
3
RxCLKIN = 43 MHz
1
RxCLKIN = 65 MHz
1
UI
MHz
dB
tPLD is the time required by the device to obtain lock when exiting power-down state with an active RxCLKIN.
UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*RxCLKIN). The UI scales with RxCLKIN frequency.
Specification is ensured by characterization and is not tested in production.
Specification is ensured by design and is not tested in production.
6.9 DC and AC Serial Control Bus Characteristics
Over 3.3-V supply and temperature ranges unless otherwise specified.
PARAMETER
VIH
Input High Level
TEST CONDITIONS
SDA and SCL
MIN
TYP
0.7*
VDDIO
VIL
Input Low Level Voltage
VHY
Input Hysteresis
8
SDA and SCL
GND
>50
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UNIT
VDDIO
V
0.3*
VDDIO
V
mV
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DC and AC Serial Control Bus Characteristics (continued)
Over 3.3-V supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
VOL
SDA, IOL = 1.25 mA
Iin
SDA or SCL, Vin = VDDIO or GND
MIN
TYP
MAX
UNIT
0
0.36
V
–10
10
µA
tR
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time — READ
See Figure 12
tHD;DAT
Hold Up Time — READ
See Figure 12
615
ns
tSP
Input Filter
50
ns
Cin
Input Capacitance
<5
pF
SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 12
SDA or SCL
430
ns
20
ns
560
ns
RxIN[3:0]+
RxCLKIN+
VTL
VCM=1.2V
VTH
RxIN[3:0]RxClkIN-
GND
Figure 1. FPD-Link DC VTH/VTL Definition
A
TPA
CA
Scope
50:
50:
B
CB
TPB
50:
50:
Single-Ended
Figure 2. Output Test Circuit
DOUT+
VOD-
VOD+
DOUT-
VOS
VOD+
(DOUT+) - (DOUT+)
VODp-p
0V
VOD-
Differential
GND
Figure 3. Output Waveforms
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+VOD
80%
(DOUT+) - (DOUT-)
0V
20%
-VOD
tLHT
tHLT
Figure 4. Output Transition Times
Figure 5. RSP (Receiver Strobe Position)
10
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PDB
VIHMIN
RxCLKIN
"X"
active
tPLD
DOUT
(Diff.)
Driver On
Driver OFF, VOD = 0V
Figure 6. Lock Time
VILMAX
PDB
active
RxCLKIN
"X"
tXZD
DOUT
(Diff.)
active
Driver OFF, VOD = 0V
RxIN[3:0]
N-1
N
N+1
| |
Figure 7. Disable Time
N+2
|
tSD
RxCLKIN
2
23
0
1
2
23
0
1
2
23
0
1
2
23
0
1
2
| |
1
| |
0
| |
DCA, DCB
| |
DOUT0-23
STOP START
STOP START
STOP START
STOP START
STOP
BIT BIT SYMBOL N-3 BIT BIT SYMBOL N-2 BIT BIT SYMBOL N-1 BIT BIT
BIT
SYMBOL N
| |
SYMBOL N-4
23
Figure 8. Latency Delay
tDJIT
tDJIT
VOD (+)
DOUT
(Diff.)
TxOUT_E_O
0V
VOD (-)
tBIT (1 UI)
Figure 9. Output Jitter
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+VOD
RxCLKIN
-VOD
+VOD
RxIN[odd]
-VOD
+VOD
RxIN[even]
-VOD
Cycle N
Cycle N+1
Figure 10. Checkerboard Data Pattern
VILMAX
BISTEN
tPASS
PASS
(w/ errors)
VOLMAX
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 11. BIST Pass Waveform
SDA
tf
tHD;STA
tLOW
tf
tr
tr
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tSU;STO
tSU;DAT
tHD;DAT
START
STOP
REPEATED
START
START
Figure 12. Serial Control Bus Timing Diagram
6.10 Typical Characteristics
85
IDDT @ 1.8V (mA)
80
75
70
VODSEL = H
65
60
VODSEL = L
55
50
45
40
0
10
20
30
40
50
60
70
RxCLK (MHz)
Figure 13. Typical IDDT (1.8-V Supply) Current as a Function of RxCLK
12
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7 Detailed Description
7.1 Overview
The DS90UR907Q converter transmits an FPD-Link interface (4 LVDS data channels + 1 LVDS clock) with total
of 27–bits of data (24–high speed bits and 3 low speed video control signals) over a single serial FPD-Link II
pair. The serial stream also contains an embedded clock and the DC-balance information which enhances signal
quality and supports AC coupling. The device is intended for use with DS90UR908Q or DS90UR906Q, but is
backward compatible with previous generations of FPD-Link II as well.
The DS90UR907Q can operate in 24-bit color mode (with VS,HS,DE encoded in the serial stream) or in 18-bit
color mode.
The DS90UR907Q can be configured through external pins or through the optional serial control bus. It features
enhanced signal quality on the link by supporting: selectable VOD level, selectable deemphasis signal
conditioning and also the FPD-Link II data coding that provides randomization, scrambling, and DC Balancing of
the video data. It also includes multiple features to reduce EMI associated with display data transmission. This
includes the randomization and scrambling of the data and also the system spread spectrum PCLK support. The
DS90UR907Q features power saving with a power-down mode, and auto stop clock feature.
See also Built In Self Test (BIST) and Optional Serial Bus Control for more information.
7.2 Functional Block Diagram
RxIN1+/RxIN0+/RxCLKIN+/-
PLL
CONFIG[1:0]
MAPSEL
PDB
SCL
SDA
ID[x]
Parallel to Serial
RxIN2+/-
Serial to Parallel
RxIN3+/-
DC Balance Encoder
VODSEL
De-Emph
DOUT+
DOUT-
Pattern
Generator
Timing and
Control
BISTEN
FPD-Link to FPD-Link II Convertor
7.3 Feature Description
7.3.1 Data Transfer
The DS90UR907Q transmits a pixel of data in the following format: C1 and C0 represent the embedded clock in
the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled RGB data. DCB is
the DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This
bit determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data
stream and can also contain encoded control (VS,HS,DE). Both DCA and DCB coding schemes are generated
by the DS90UR907Q and decoded by the paring deserializer automatically reference to FPD-Link II Serial
Stream. Figure 14 illustrates the serial stream per PCLK cycle.
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Feature Description (continued)
NOTE
The figure only illustrates the bits but does not actually represent the bit location as the
bits are scrambled and balanced continuously.
C
1
b
0
b
1
D
C
B
b
2
b
1
2
b
3
b
1
3
b
4
b
1
4
b
5
b
1
5
b
6
b
1
6
b
7
b
1
7
b
8
b
9
b
1
8
b
1
9
b
1
0
b
2
0
b
1
1
b
2
1
D
C
A
b
2
2
b
2
3
C
0
Figure 14. FPD-Link II Serial Stream
7.3.2 Operating Modes And Backward Compatibility - Config[1:0]
The DS90UR907Q is backward compatible with previous generations of FPD-Link II deserializers. Configuration
modes are provided for backwards compatibility with the DS90C124 FPD-Link II Generation 1, and also the
DS90UR124 FPD-Link II Generation 2 deserializers by setting the respective mode with the CONFIG[1:0] pins as
shown in Table 1. The selection also determine whether the Video Control Signal filter feature is enabled or
disabled in Normal mode.
Table 1. DS90UR907Q Configuration Modes
CON
FIG1
CON
FIG0
MODE
DES DEVICE
L
L
Normal Mode, Control Signal Filter disabled
DS90UR908Q, DS90UR906Q
L
H
Normal Mode, Control Signal Filter enabled
DS90UR908Q, DS90UR906Q
H
L
Backwards Compatible GEN2
DS90UR124, DS99R124
H
H
Backwards Compatible GEN1
DS90C124
7.3.3 Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low-frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high-frequency
noise on the control signals. See Figure 15.
14
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PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filtered OUT
Figure 15. Video Control Signal Filter Waveform
7.3.4 Color Bit Mapping Select
The DS90UR907Q can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs
on RxIN[3] shown in Figure 16 or MSBs on RxIN[3] shown in Figure 17. The mapping scheme is controlled by
MAPSEL pin or by Register.
RxCLKIN +/Previous cycle
Current cycle
RxIN3 +/-
DE
(bit 20)
RxIN2 +/-
R[1]
(bit 22)
R[0]
(bit 21)
B[6]
(bit 16)
B[5]
(bit 15)
B[4]
(bit 14)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
VS
(bit 19)
HS
(bit 18)
B[7]
(bit 17)
G[7]
(bit 11)
R[6]
(bit 4)
RxIN1 +/-
B[3]
(bit 13)
B[2]
(bit 12)
RxIN0 +/-
G[2]
(bit 6)
R[7]
(bit 5)
G[0]
(bit 23)
Figure 16. 8–Bit FPD-Link Mapping: LSB's on Rxin3
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RxCLKIN +/Previous cycle
Current cycle
B[7]
(bit 26)
RxIN3 +/-
DE
(bit 20)
RxIN2 +/-
RxIN1 +/-
RxIN0 +/-
VS
(bit 19)
B[1]
(bit 13)
B[0]
(bit 12)
G[0]
(bit 6)
R[5]
(bit 5)
R[7]
(bit 22)
R[6]
(bit 21)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
B[6]
(bit 25)
G[7]
(bit 24)
HS
(bit 18)
B[5]
(bit 17)
G[5]
(bit 11)
R[4]
(bit 4)
G[6]
(bit 23)
Figure 17. 8–Bit FPD-Link Mapping: MSB's on Rxin3
7.3.5 EMI Reduction Features
7.3.5.1 Spread Spectrum Compatibility
The RxCLKIN of the FPD-Link input is capable of tracking spread spectrum clocking (SSC) from a host source.
The RxCLKIN will accept spread spectrum, tracking up to 35-kHz modulation and ±0.5, ±1 or ±2% deviations
(center spread). The maximum conditions for the RxCLKIN input are: a modulation frequency of 35 kHz and
amplitude deviations of ±2% (4% total).
7.3.6 Signal Quality Enhancers
7.3.6.1 VOD Select (VODSEL)
The DS90UR907Q differential output voltage may be increased by setting the VODSEL pin High. When VODSEL
is Low, the DC VOD is at the standard (default) level. When VODSEL is High, the DC VOD is increased in level.
The increased VOD is useful in extremely high noise environments and also on extra long cable length
applications. When using de-emphasis, TI recommends setting VODSEL = H to avoid excessive signal
attenuation especially with the larger de-emphasis settings. This feature may be controlled by the external pin or
by register.
Table 2. Differential Output Voltage
INPUT
EFFECT
VODSEL
VOD (mV)
VOD (mVp-p)
H
±450
900
L
±300
600
7.3.6.2 De-Emphasis (De-Emph)
The De-Emph pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the
device drives. It is the signal conditioning function for use in compensating against cable transmission loss. This
pin should be left open for standard switching currents (no de-emphasis) or if controlled by register. De-emphasis
is selected by connecting a resistor on this pin to ground, with R value from 0.5 kΩ to 1 MΩ, or by register
setting. When using De-Emphasis, TI recommends setting VODSEL = H.
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Table 3. De-Emphasis Resistor Value
RESISTOR VALUE (kΩ)
DE-EMPHASIS SETTING
Open
Disabled
0.6
–12 dB
1
–9 dB
2
–6 dB
5
–3 dB
0.00
VDD = 1.8V,
-2.00
TA = 25oC
DE-EMPH (dB)
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
R VALUE - LOG SCALE (:)
Figure 18. De-Emph vs R Value
7.3.7 Power Saving Features
7.3.7.1 Power-Down Feature (PDB)
The DS90UR907Q has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the
host and is used to save power, disabling the link when the display is not needed. In the POWER DOWN mode,
the high-speed driver outputs present a 0V VOD state. Note – in POWER DOWN, the optional Serial Bus Control
Registers are RESET.
7.3.7.2 Stop Clock Feature
The DS90UR907Q enters a low power SLEEP state when the RxCLKIN is stopped. A STOP condition is
detected when the input clock frequency is less than 3 MHz. The clock should be held at a static Low or high
state. When the RxCLKIN starts again, the device will then lock to the valid input RxCLKIN and then transmits
the RGB data to the deserializer. Note – in STOP CLOCK SLEEP, the optional Serial Bus Control Registers
values are RETAINED.
7.3.7.3 1.8-V or 3.3-V VDDIO Operation
The DS90UR907Q parallel control bus operate with 1.8-V or 3.3-V levels (VDDIO) for host compatibility. The 1.8-V
levels will offer a system power savings.
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7.4 Device Functional Modes
7.4.1 Operating Modes and Backward Compatibility (Config[1:0])
The DS90UR907Q is backward compatible with previous generations of FPD-Link II deserializers. Configuration
modes are provided for backwards compatibility with the DS90C124 FPD-LinkII Generation 1, and also the
DS90UR124 FPD-Link II Generation 2 deserializers by setting the respective mode with the CONFIG[1:0] pins as
shown in Table 4. The selection also determines whether the Video Control Signal filter feature is enabled or
disabled in Normal mode.
Table 4. DS90UR907Q
CONFIG 1
CONFIG 0
MODE
DES DEVICE
L
L
Normal Mode, Control Signal
Filter disabled
DS90UR908Q, DS90UR906Q
L
H
Normal Mode, Control Signal
Filter enabled
DS90UR908Q, DS90UR906Q
H
L
Backwards compatible GEN2
DS90UR124, DS99R124
H
H
Backwards compatible GEN1
DS90C124
7.5 Programming
7.5.1 Optional Serial Bus Control
See the following section on the Optional Serial Bus Control Interface.
7.5.2 Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the DS90UR907Q and deserializer BISTEN input pins.
The DS90UR907Q outputs a test pattern (PRBS7) and drives the link at speed. The deserializer detects the
PRBS7 pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with
1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST
test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or
more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer
BISTEN pin.
Inter-operability is supported between this FPD-Link II device and all FPD-Link II generations (Gen 1/2/3) — see
respective data sheets for details on entering BIST mode and control.
Sample BIST Sequence
See Figure 19 for the BIST mode flow diagram.
Step 1: Place the DS90UR907Q in BIST Mode by setting Ser BISTEN = H. The BIST Mode is enabled through
the BISTEN pin. An RxCLKIN is required for all the Ser options. When the deserializer detects the BIST mode
pattern and command (DCA and DCB code) the RGB and control signal outputs are shut off.
Step 2: Place the pairing deserializer in BIST mode by setting the BISTEN = H. The Des is now in the BIST
mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the
PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be
monitored and counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the
data and the final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If
there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new
BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the
BISTEN signal.
Step 4: To return the link to normal operation, the DS90UR907Q BISTEN input is set Low. The Link returns to
normal operation.
18
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Programming (continued)
Figure 20 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission and so forth), thus they may be introduced by greatly extending the cable length,
faulting the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or deserializer
Equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
Start
Step 3: DES in Normal
Mode - check PASS
BIST
Stop
Step 4: SER in Normal
Figure 19. BIST Mode Flow Diagram
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Programming (continued)
BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
• Pixel Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the RxCLKIN rate times the test duration. If we
assume a 65-MHz RxCLKIN, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.07 × 10E-12
The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and
performance monitoring.
Deserializer Outputs Case 1 - Pass
BISTEN
(DS90UR907Q)
BISTEN
(Deserializer)
TxCLKOUT
(Diff.)
TxOUT[3:0]
(Diff.)
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
X
FAIL
Prior Result
Normal
PRBS
Case 2 - Fail
X = bit error(s)
DATA
(internal)
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 20. BIST Waveforms
7.5.3 Optional Serial Bus Control
The DS90UR907Q may be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus because multiple addresses are supported. See Figure 21.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pullup resistor to VDDIO. For most
applications a 4.7-k pullup resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
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Programming (continued)
1.8V
VDDIO
10k
ID[X]
4.7k
HOST
4.7k
RID
DS90UR907Q
SCL
SCL
SDA
SDA
To other
Devices
Figure 21. Serial Control Bus Connection
The third pin is the ID[x] pin. This pin sets one of four possible device addresses. Two different connections are
possible. The pin may be pulled to VDD (1.8 V, NOT VDDIO)) with a 10-kΩ resistor. Or a 10-kΩ pullup resistor (to
VDD1.8 V, NOT VDDIO)) and a pulldown resistor of the recommended value to set other three possible addresses
may be used. See Table 5.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 22.
SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
Figure 22. Start and Stop Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 23 and a WRITE is shown in Figure 24.
If the Serial Bus is not required, the three pins may be left open (NC).
Table 5. ID[x] Resistor Value – DS90UR907Q
Resistor
RID kΩ
Address 7'b
Address 8'b
0 appended (WRITE)
0.47
7b' 110 1001 (h'69)
8b' 1101 0010 (h'D2)
2.7
7b' 110 1010 (h'6A)
8b' 1101 0100 (h'D4)
8.2
7b' 110 1011 (h'6B)
8b' 1101 0110 (h'D6)
Open
7b' 110 1110 (h'6E)
8b' 1101 1100 (h'DC)
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Programming (continued)
Register Address
Slave Address
A
2
S
A
1
A
0
Slave Address
a
c
k
a
0 ck
A
2
S
A
1
A
0
Data
1
a
c
k
a
c
k
P
Figure 23. Serial Control Bus — Read
Register Address
Slave Address
A
2
S
A
1
A
0
0
Data
a
c
k
a
c
k
a
c
k
P
Figure 24. Serial Control Bus — Write
Table 6. Serial Bus Control Registers
ADD ADD
(dec) (hex)
0
1
2
22
0
1
2
REGISTER
NAME
BIT(S)
R/W
DEFAULT
(bin)
Ser Config 1
7
R/W
6
R/W
5
R/W
Device ID
De-Emphasis
Control
FUNCTION
DESCRIPTION
0
Reserved
Reserved
0
MAPSEL
0: LSB on RxIN3
1: MSB on RxIN3
0
VODSEL
0: Low
1: High
4
R/W
0
Reserved
Reserved
3:2
R/W
00
CONFIG
00: Normal Mode, Control Signal Filter
DISABLED
01: Normal Mode, Control Signal Filter
ENABLED
10: Backwards Compatible (DS90UR124,
DS99R124)
11: Backwards Compatible (DS90C124)
1
R/W
0
SLEEP
Note – not the same function as
PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings
retained.
0
R/W
0
REG
0: Configurations set from control pins
1: Configuration set from registers (except
I2C_ID)
7
R/W
0
REG ID
0: Address from ID[x] Pin
1: Address from Register
6:0
R/W
1101000
ID[x]
Serial Bus Device ID, Five IDs are:
7b '1101 000 (h'68)
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are Reserved.
7:5
R/W
000
De-Emph Setting
000: set by external Resistor
001: –1 dB
010: –2 dB
011: –3.3 dB
100: –5 dB
101: –6.7 dB
110: –9 dB
111: –12 dB
4
R/W
0
De-Emph EN
0: De-Emphasis Enabled
1: De-Emphasis Disabled
3:0
R/W
000
Reserved
Reserved
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90UR907Q and DS90UR908Q chipset is intended for interface between a host (graphics processor) and
a Display. It supports an 24-bit color depth (RGB888) and up to 1024 × 768 display formats. In a RGB888
application, 24 color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are
supported across the serial link with PCLK rates from 5 to 65 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general purpose signals may also be sent from host to display.
8.1.1 Power-Up Requirements and PDB Pin
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and a
22-uF capacitor to GND to delay the PDB input signal.
8.1.2 Transmission Media
The DS90UR907Q and the companion deserializer chipset is intended to be used in a point-to-point
configuration, through a PCB trace, or through twisted pair cable. The DS90UR907Q provide internal
terminations providing a clean signaling environment. The interconnect for LVDS should present a differential
impedance of 100 Ω. Use cables and connectors that have matched differential impedance to minimize
impedance discontinuities. Shielded or unshielded cables may be used depending upon the noise environment
and application requirements.
8.1.3 Alternate Color / Data Mapping
Color Mapped data pin names are provided to specify a recommended mapping for 24-bit and 18-bit
Applications. When connecting to earlier generations of FPD-Link II deserializer devices, a color mapping review
is recommended to ensure the correct connectivity is obtained. Table 7 provides examples for interfacing
between DS90UR907Q and different deserializers.
Table 7. Alternate Color / Data Mapping
FPD-Link
Bit Number
RGB (LSB
Example)
DS90UR906Q
RxIN3
Bit 26
B1
B1
Bit 25
B0
B0
Bit 24
G1
G1
Bit 23
G0
G0
Bit 22
R1
R1
Bit 21
R0
R0
DS90UR124
DS99R124Q
DS90C124
N/A
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Application Information (continued)
Table 7. Alternate Color / Data Mapping (continued)
FPD-Link
Bit Number
RGB (LSB
Example)
DS90UR906Q
DS90UR124
DS99R124Q
DS90C124
RxIN2
Bit 20
DE
DE
ROUT20
TxOUT2
ROUT20
RxIN1
RxIN0
Bit 19
VS
VS
ROUT19
ROUT19
Bit 18
HS
HS
ROUT18
ROUT18
Bit 17
B7
B7
ROUT17
ROUT17
Bit 16
B6
B6
ROUT16
ROUT16
Bit 15
B5
B5
ROUT15
ROUT15
Bit 14
B4
B4
ROUT14
ROUT14
Bit 13
B3
B3
ROUT13
Bit 12
B2
B2
ROUT12
ROUT12
Bit 11
G7
G7
ROUT11
ROUT11
Bit 10
G6
G6
ROUT10
ROUT10
Bit 9
G5
G5
ROUT9
ROUT9
Bit 8
G4
G4
ROUT8
ROUT8
Bit 7
G3
G3
ROUT7
ROUT7
Bit 6
G2
G2
ROUT6
Bit 5
R7
R7
ROUT5
ROUT5
Bit 4
R6
R6
ROUT4
ROUT4
Bit 3
R5
R5
ROUT3
ROUT3
Bit 2
R4
R4
ROUT2
ROUT2
Bit 1
R3
R3
ROUT1
ROUT1
Bit 0
R2
R2
ROUT0
ROUT0
N/A
* These bits are not supported by DS90UR907Q
DS90UR907Q
Settings
MAPSEL = 0
N/A
CONFIG [1:0]
= 00
TxOUT1
TxOUT0
ROUT13
ROUT6
ROUT23*
OS2*
ROUT23*
ROUT22*
OS1*
ROUT22*
ROUT21*
OS0*
ROUT21*
CONFIG [1:0] = 10
CONFIG [1:0]
= 11
8.2 Typical Application
Figure 25 shows a typical application of the DS90UR907Q for a 65-MHz 24-bit Color Display Application. The
LVDS inputs of the FPD-Link interface require external 100-Ω terminations. The LVDS outputs of FPD-Link II
require 100-nF AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors
are placed near the power supply pins. At a minimum, four 0.1-µF capacitors and a 4.7-µF capacitor should be
used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN
pins. The application assumes the companion deserializer (DS90UR908Q); therefore, the configuration pins are
also both tied Low. In this example the cable is long; therefore, the VODSEL pin is tied High and a De-Emphasis
value is selected by the resistor R1. The interface to the host is with 1.8-V LVCMOS levels, thus the VDDIO pin
is connected also to the 1.8-V rail. The Optional Serial Bus Control is not used in this example, thus the SCL,
SDA and ID[x] pins are left open. A delay capacitor and resistor is placed on the PDB signal to delay the
enabling of the device until power is stable. Bypass capacitors are placed near the power supply pins. Ferrite
beads are placed on the power lines for effective noise suppression.
24
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Typical Application (continued)
DS90UR907Q
VDDIO
VDDIO
C10
C8
FB1
1.8V
VDDTX
VDDHS
C3
C4
FB2
C5
FB3
C6
FB4
C7
FB5
C9
C11
VDDP
C12
RxCLKIN100:
RxCLKIN+
VDDL
RxIN3100:
RxIN3+
RxIN2100:
VDDRX
RxIN2+
FPD-Link
Interface
RxIN1100:
DOUT+
DOUT-
RxIN1+
RxIN0-
100:
RxIN0+
C1
Serial
FPD-Link II
Interface
1.8V
C2
10k
ID[X]
SCL
SDA
RID
VDDIO
VODSEL
De-Emph
R1
Host
Control
BISTEN
PDB
R
C13
CONFIG1
CONFIG0
MAPSEL
NOTE:
C1-C2 = 0.1 PF (50 WV)
C3-C9 = 0.1 PF
C10-C12 = 4.7 PF
C13 = >10 PF
R = 10 k:
R1 (cable insertion loss specific)
RID (see ID[x] Resistor Value Table)
FB1-FB5: Impedance = 1 k:,
low DC resistance (<1:)
RES7
RES6
RES5
RES4
RES3
RES2
RES1
RES0
DAP (GND)
Figure 25. Typical Connection Diagram
8.2.1 Design Requirements
Table 8 shows the input parameters for the typical design application.
Table 8. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VDDIO
1.8 V or 3.3 V
VDDL, VDDP, VDDHS, VDDTX,
VDDRX
1.8 V
AC Coupling Capacitor for DOUT±
100 nF
8.2.2 Detailed Design Procedure
The DOUT± outputs require 100-nF AC coupling capacitors to the line. FPD-Link data input pair required an
external 100-Ω termination for standard LVDS levels. The power supply filter capacitors are placed near the
power supply pins. A smaller capacitance capacitor should be located closer to the power supply pins. Adding a
ferrite bead is optional. Recommend to use 1-kΩ impedance and low DC resistance such as less than 1 Ω. The
VODSEL pin is tied to VDDIO for the long cable application. The De-Emph pin may connect a resistor to ground.
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Refer to the Table 3. The PDB and BISTEN pins are assumed controlling by a microprocessor. The PDB must
be low state until all power supply voltages reach the final voltage. The CONFIG[1:0] pins are set depending on
operating modes and interfacing device. See the Table 1. MAPSEL pin is set the mapping scheme. Refer to the
Figure 16 and Figure 17. The SCL, SDA, and ID[x] pins are left open when these Serial Bus Control pins are
unused. The RES[7:0] pins and DAP should be tied to ground.
8.2.3 Application Curves
Serializer CML Output Stream with Input PCLK = 65 MHz, VODSEL = L
Figure 26. Serializer CML Output Stream With Input PCLK
= 65 MHz, VODSEL = L
Serializer CML Output Stream with Input PCLK = 65 MHz, VODSEL = H
Figure 27. Serializer CML Output Stream With Input
PÄCLK = 65 MHz, VODSEL = H
9 Power Supply Recommendations
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower than 1.5
ms, then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and a
>10-μF capacitor to GND to delay the PDB input signal.
All inputs must not be driven until all supply voltages have reached their steady-state value.
26
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10 Layout
10.1 Layout Guidelines
10.1.1 PCB Layout and Power System Considerations
Design the circuit board layout and stack-up for the LVDS devices to provide low-noise power feed to the device.
Good layout practice will also separate high-frequency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback, and interference. Power system performance may be greatly improved by using
thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the
PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and
makes the value and placement of external bypass capacitors less critical. The capacitors may use values in the
range of 0.01 uF to 0.1 uF.
TI recommends surface mount capacitors due to their smaller parasitics. When using multiple capacitors per
supply pin, place the smaller value closer to the pin. TI recommends a large bulk capacitor at the point of power
entry. This is typically in the 50-uF to 100-uF range and will smooth low-frequency switching noise. TI
recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with the via on both ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the path.
TI recommends a small body size X7R chip capacitor, such as the 0603, for external bypass. The X7R chip
capacitor's small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the
resonance frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide
effective bypassing, use multiple capacitors to achieve low impedance between the supply rails over the
frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins
to the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. The table typically provides guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Place LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ω
are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise
will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate
less.
10.1.2 LVDS Interconnect Guidelines
See SNLA008 and SNLA035 for full details.
• Use 100-Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500-megabits per second line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI
website at: www.ti.com/lvds
10.2 Layout Example
Figure 28 and Figure 29 show the PCB layout example derived from the layout design of the DS90UR907Q-Q1
Evaluation Board. The graphic and layout description are used to determine both proper routing and proper
solder techniques for designing the board.
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Layout Example (continued)
AC Capacitors
Length-Matched
Differential Signals.
Length-Matched
Differential Signals.
High-Speed Traces
Figure 28. Top Layer
28
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Layout Example (continued)
Figure 29. Bottom Layer
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines, SNLA008
• Application Note AN-1187, Leadless Leadframe Package (LLP), SNOA401
• Application Note 905 Transmission Line RAPIDESIGNER Operation and Applications Guide, SNLA035
• LVDS Owner’s Manual Design Guide, 4th Edition, SNLA187
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
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5-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90UR907QSQ/NOPB
ACTIVE
WQFN
NJK
36
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UR907QSQ
DS90UR907QSQE/NOPB
ACTIVE
WQFN
NJK
36
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UR907QSQ
DS90UR907QSQX/NOPB
ACTIVE
WQFN
NJK
36
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UR907QSQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Aug-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DS90UR907QSQ/NOPB
Package Package Pins
Type Drawing
WQFN
NJK
36
DS90UR907QSQE/NOPB WQFN
NJK
DS90UR907QSQX/NOPB WQFN
NJK
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
36
250
178.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
36
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UR907QSQ/NOPB
WQFN
NJK
36
1000
367.0
367.0
38.0
DS90UR907QSQE/NOPB
WQFN
NJK
36
250
213.0
191.0
55.0
DS90UR907QSQX/NOPB
WQFN
NJK
36
2500
367.0
367.0
38.0
Pack Materials-Page 2
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help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
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Copyright © 2016, Texas Instruments Incorporated

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