DATA SHEET MOS FIELD EFFECT TRANSISTOR NP80N03EDE, NP80N03KDE NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION These products are N-channel MOS Field Effect Transistors designed for high current switching applications. <R> ORDERING INFORMATION PART NUMBER NP80N03EDE-E1-AY Note1, 2 NP80N03EDE-E2-AY Note1, 2 NP80N03KDE-E1-AY Note1 NP80N03KDE-E2-AY Note1 NP80N03CDE-S12-AZ Note1, 2 NP80N03DDE-S12-AY Note1, 2 NP80N03MDE-S18-AY Note1 NP80N03NDE-S18-AY Note1 LEAD PLATING PACKING PACKAGE TO-263 (MP-25ZJ) typ. 1.4 g Pure Sn (Tin) Tape 800 p/reel TO-263 (MP-25ZK) typ. 1.5 g Sn-Ag-Cu Pure Sn (Tin) TO-220 (MP-25) typ. 1.9 g Tube 50 p/tube Notes 1. Pb-free (This product does not contain Pb in the external electrode.) 2. Not for new design TO-262 (MP-25 Fin Cut) typ. 1.8 g TO-220 (MP-25K) typ. 1.9 g TO-262 (MP-25SK) typ. 1.8 g (TO-220) FEATURES • Channel Temperature 175 degree rated • Super Low on-state Resistance RDS(on)1 = 7.0 mΩ MAX. (VGS = 10 V, ID = 40 A) RDS(on)2 = 9.0 mΩ MAX. (VGS = 5 V, ID = 40 A) (TO-262) RDS(on)3 = 11 mΩ MAX. (VGS = 4.5 V, ID = 40 A) • Low input capacitance Ciss = 2600 pF TYP. (TO-263) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. D15310EJ3V0DS00 (3rd edition) Date Published October 2007 NS Printed in Japan 2001, 2007 The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" NP80N03EDE, NP80N03KDE, NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 30 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V ID(DC) ±80 A ID(pulse) ±320 A Total Power Dissipation (TC = 25°C) PT1 120 W Total Power Dissipation (TA = 25°C) PT2 1.8 W Channel Temperature Tch 175 °C Drain Current (DC) (TC = 25°C) Drain Current (pulse) Note1 Note2 Tstg −55 to +175 °C Single Avalanche Current Note3 IAS 50/40/9 A Single Avalanche Energy Note3 EAS 2.5/160/400 mJ Storage Temperature Notes 1. Calculated constant current according to MAX. allowable channel temperature. 2. PW ≤ 10 μs, Duty cycle ≤ 1% 3. Starting Tch = 25°C, RG = 25 Ω, VGS = 20 → 0 V (See Figure 4.) THERMAL RESISTANCE Channel to Case Thermal Resistance Rth(ch-C) 1.25 °C/W Channel to Ambient Thermal Resistance Rth(ch-A) 83.3 °C/W 2 Data Sheet D15310EJ3V0DS NP80N03EDE, NP80N03KDE, NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 30 V, VGS = 0 V 10 μA Gate Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±100 nA Gate to Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 1.5 2.0 2.5 V Forward Transfer Admittance | yfs | VDS = 10 V, ID = 40 A 20 41 Drain to Source On-state Resistance RDS(on)1 VGS = 10 V, ID = 40 A 5.3 7.0 mΩ RDS(on)2 VGS = 5 V, ID = 40 A 6.8 9.0 mΩ RDS(on)3 VGS = 4.5 V, ID = 40 A 7.5 11 mΩ Input Capacitance Ciss VDS = 25 V, 2600 3900 pF Output Capacitance Coss VGS = 0 V, 590 890 pF Reverse Transfer Capacitance Crss f = 1 MHz 270 490 pF Turn-on Delay Time td(on) VDD = 15 V, ID = 40 A, 20 44 ns Rise Time tr VGS = 10 V, 12 31 ns Turn-off Delay Time td(off) RG = 1 Ω 60 120 ns Fall Time tf 14 35 ns Total Gate Charge QG1 ID = 80 A, VDD = 24 V, VGS = 10 V 48 72 nC QG2 VDD = 24 V, 28 42 nC Gate to Source Charge QGS VGS = 5 V, 10 nC Gate to Drain Charge QGD ID = 80 A 14 nC Body Diode Forward Voltage VF(S-D) IF = 80 A, VGS = 0 V 1.0 V Reverse Recovery Time trr IF = 80 A, VGS = 0 V, 34 ns Reverse Recovery Charge Qrr di/dt = 100 A/μs 22 nC TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω S VGS RL Wave Form RG PG. VDD VGS 0 VGS 10% 90% VDD VDS 90% IAS 90% VDS VGS 0 BVDSS VDS 10% 0 10% Wave Form VDS ID τ VDD Starting Tch τ = 1 μs Duty Cycle ≤ 1% td(on) tr ton td(off) tf toff TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = 2 mA PG. 50 Ω RL VDD Data Sheet D15310EJ3V0DS 3 NP80N03EDE, NP80N03KDE, NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE TYPICAL CHARACTERISTICS (TA = 25°C) Figure2. TOTAL POWER DISSIPATION vs. CASE TEMPERATURE Figure1. DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA PT - Total Power Dissipation - W dT - Percentage of Rated Power - % 140 100 80 60 40 20 0 0 25 50 75 120 100 80 60 40 20 0 100 125 150 175 200 0 25 TC - Case Temperature - °C Figure3. FORWARD BIAS SAFE OPERATING AREA 75 100 125 150 175 200 Figure4. SINGLE AVALANCHE ENERGY DERATING FACTOR 450 ID(pulse) =1 0μ 10 d ite im ) )L 0V 1 (on S RDVGS = ( 100 PW s 0μ ID(DC) EAS - Single Avalanche Energy - mJ 1000 ID - Drain Current - A 50 TC - Case Temperature - °C s 1m DC Po Lim wer ite Dis sip d s ati on 10 1 TC = 25°C Single pulse 0.1 0.1 1 10 VDS - Drain to Source Voltage - V 400 mJ 400 350 300 IAS = 9 A 40 A 50 A 250 200 160 mJ 150 100 50 2.5 mJ 0 25 100 50 75 100 125 150 175 Starting Tch - Starting Channel Temperature - °C Figure5. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(t) - Transient Thermal Resistance - °C/W 1000 100 Rth(ch-A) = 83.3°C/W 10 Rth(ch-C) = 1.25°C/W 1 0.1 Single pulse 0.01 10 μ 100 μ 1m 10 m 100 m 1 PW - Pulse Width - s 4 Data Sheet D15310EJ3V0DS 10 100 1000 NP80N03EDE, NP80N03KDE, NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE Figure6. FORWARD TRANSFER CHARACTERISTICS 1000 Figure7. DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE 400 Pulsed Pulsed ID - Drain Current - A ID - Drain Current - A 350 100 TA = −50°C 25°C 75°C 150°C 175°C 10 1 VGS = 10 V 300 250 5V 200 150 100 4.5 V 50 0.1 0 1 2 3 5 4 6 TA = 175°C 75°C 25°C −50°C 0.1 0.1 1 10 100 RDS(on) - Drain to Source On-state Resistance - mΩ ID - Drain Current - A Figure10. DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT Pulsed 30 20 VGS = 4.5 V 5V 10 V 10 0 1 10 100 1000 RDS(on) - Drain to Source On-state Resistance - mΩ 10 VGS(th) - Gate to Source Threshold Voltage - V | yfs | - Forward Transfer Admittance - S Figure8. FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 100 VDS = 10 V Pulsed 0.01 0.01 4.0 3.0 VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V 1 2.0 1.0 0 Figure9. DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 50 Pulsed 40 30 20 10 0 ID = 40 A 0 2 4 6 8 10 12 14 16 18 VGS - Gate to Source Voltage - V Figure11. GATE TO SOURCE THRESHOLD VOLTAGE vs. CHANNEL TEMPERATURE 3.0 VDS = VGS ID = 250 μA 2.5 2.0 1.5 1.0 0.5 0 −50 0 50 100 150 Tch - Channel Temperature - °C ID - Drain Current - A Data Sheet D15310EJ3V0DS 5 NP80N03EDE, NP80N03KDE, NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE Figure13. SOURCE TO DRAIN DIODE FORWARD VOLTAGE 1000 IF - Diode Forward Current - A 10 VGS = 4.5 V 5V 10 V 8 6 4 2 Pulsed 100 VGS = 10 V 10 0V 1 ID = 40 A 0 −50 50 0 100 0.1 0 150 Tch - Channel Temperature - °C VF(S-D) - Source to Drain Voltage - V Figure15. SWITCHING CHARACTERISTICS Figure14. CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 1000 VGS = 0 V f = 1 MHz td(on), tr, td(off), tf - Switching Time - ns Ciss, Coss, Crss - Capacitance - pF 10000 Ciss 1000 Coss Crss 100 10 0.1 1 10 100 tf 100 td(off) td(on) 10 tr VDD = 15 V VGS = 10 V 1 RG = 1 Ω 0.1 trr - Reverse Recovery Time - ns 100 di/dt = 100 A/μs VGS = 0 V 100 10 Figure17. DYNAMIC INPUT/OUTPUT CHARACTERISTICS 16 40 VDS - Drain to Source Voltage - V Figure16. REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 14 35 VGS 30 VDD = 24 V 15 V 6V 25 20 12 10 8 6 15 4 10 VDS 5 2 ID = 80 A 1 0.1 0 1 10 100 0 10 20 30 40 50 60 QG - Gate Charge - nC IF - Diode Forward Current - A 6 10 1 ID - Drain Current - A VDS - Drain to Source Voltage - V 1000 1.5 1.0 0.5 Data Sheet D15310EJ3V0DS 70 80 0 VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ Figure12. DRAIN TO SOURCE ON-STATE RESISTANCE vs CHANNEL TEMPERATURE 12 Pulsed NP80N03EDE, NP80N03KDE, NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE PACKAGE DRAWINGS (Unit: mm) Note 1.3 ± 0.2 10.0 ± 0.3 No plating 7.88 MIN. 4 2 3 1.4 ± 0.2 0.7 ± 0.2 2.54 TYP. 9.15 ± 0.3 8.0 TYP. 8.5 ± 0.2 1 5.7 ± 0.4 1.0 ± 0.5 4 4.45 ± 0.2 0.025 to 0.25 P. .5R 0 TY R 0.8 2.54 TYP. P. TY 0.5 ± 0.2 0.75 ± 0.2 0.5 ± 2.8 ± 0.2 1.Gate 2.Drain 3.Source 4.Fin (Drain) 1 2 1.Gate 2.Drain 2.5 3.Source 15.5 MAX. 5.9 MIN. 4 1 0.75 ± 0.1 2.54 TYP. 1.3 ± 0.2 12.7 MIN. 6.0 MAX. 1 2 3 0.5 ± 0.2 2.8 ± 0.2 0.75 ± 0.3 2.54 TYP. 2 3 1.0 ± 0.5 10 TYP. Note 4.8 MAX. 1.3 ± 0.2 8.5 ± 0.2 1.3 ± 0.2 4.Fin (Drain) 12.7 MIN. 4.8 MAX. φ 3.6 ± 0.2 10.0 TYP. 1.3 ± 0.2 3 4)TO-262 (MP-25 Fin Cut) 4 8ο 0.25 Note 10.6 MAX. 0.2 0 to 2.54 3)TO-220 (MP-25) 1.3 ± 0.2 2.54 ± 0.25 4.8 MAX. 10 TYP. 1.35 ± 0.3 2)TO-263 (MP-25ZK) 15.25 ± 0.5 1)TO-263 (MP-25ZJ) 3.0 ± 0.3 <R> 0.5 ± 0.2 2.8 ± 0.2 2.54 TYP. 1.Gate 2.Drain 3.Source 4.Fin (Drain) 2.54 TYP. 1.Gate 2.Drain 3.Source 4.Fin (Drain) Note Not for new design Data Sheet D15310EJ3V0DS 7 NP80N03EDE, NP80N03KDE, NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE 0.8 ± 0.1 0.5 ± 0.2 2.54 TYP. 2.5 ± 0.2 2.54 TYP. 1.Gate 2.Drain 3.Source 4.Fin (Drain) 1.3 ± 0.2 1.27 ± 0.2 3.1 ± 0.3 1 2 3 4.45 ± 0.2 10.1 ± 0.3 15.9 MAX. 1.27 ± 0.2 4 8.9 ± 0.2 3 10.0 ± 0.2 13.7 ± 0.3 13.7 ± 0.3 1 2 4.45 ± 0.2 1.3 ± 0.2 3.1 ± 0.2 4 φ 3.8 ± 0.2 6.3 ± 0.3 2.8 ± 0.3 10.0 ± 0.2 1.2 ± 0.3 6)TO-262 (MP-25SK) 5)TO-220 (MP-25K) 0.8 ± 0.1 0.5 ± 0.2 2.54 TYP. 2.54 TYP. 2.5 ± 0.2 1.Gate 2.Drain 3.Source 4.Fin (Drain) EQUIVALENT CIRCUIT Drain Body Diode Gate Source Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. 8 Data Sheet D15310EJ3V0DS NP80N03EDE, NP80N03KDE, NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE <R> TAPE INFORMATION There are two types (-E1, -E2) of taping depending on the direction of the device. Draw-out side <R> Reel side MARKING INFORMATION NEC 80N03 DE <R> Pb-free plating marking Abbreviation of part number Lot code RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Soldering Method Soldering Conditions Infrared reflow Maximum temperature (Package's surface temperature): 260°C or below MP-25ZJ, MP-25ZK Time at maximum temperature: 10 seconds or less Time of temperature higher than 220°C: 60 seconds or less Preheating time at 160 to 180°C: 60 to 120 seconds Recommended Condition Symbol IR60-00-3 Maximum number of reflow processes: 3 times Maximum chlorine content of rosin flux (percentage mass): 0.2% or less Wave soldering Maximum temperature (Solder temperature): 260°C or below MP-25, MP-25K, MP-25SK, Time: 10 seconds or less MP-25 Fin Cut Maximum chlorine content of rosin flux: 0.2% (wt.) or less Partial heating Maximum temperature (Pin temperature): 350°C or below MP-25ZJ, MP-25ZK, Time (per side of the device): 3 seconds or less MP-25K, MP-25SK Maximum chlorine content of rosin flux: 0.2% (wt.) or less Partial heating Maximum temperature (Pin temperature): 300°C or below MP-25, MP-25 Fin Cut Time (per side of the device): 3 seconds or less THDWS P350 P300 Maximum chlorine content of rosin flux: 0.2% (wt.) or less Caution Do not use different soldering methods together (except for partial heating). Data Sheet D15310EJ3V0DS 9 NP80N03EDE, NP80N03KDE, NP80N03CDE, NP80N03DDE, NP80N03MDE, NP80N03NDE • The information in this document is current as of October, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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